[libcxx-commits] [PATCH] D136264: [libunwind][RISCV] Support reading of VLENB CSR register

[Craig Topper via Phabricator via libcxx-commits]

craig.topper added a comment.

In D136264#3939348 <https://reviews.llvm.org/D136264#3939348>, @MaskRay wrote:

>> Support read of VLENB (vector byte length) control register (CSR number: 0xC22, DWARF register number: 0x1C22 according to RISC-V DWARF specification: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc). This support is needed for correct unwinding of RVV objects on stack.
>
> I don't find 0x1C22 on https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc
>
> No, please don't share false information.

The DWARF spec generically says CSRs are assigned their CSR address plus 4096.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136264/new/

https://reviews.llvm.org/D136264