[flang-commits] [clang] [flang] [lld] [llvm] AMDGPU: Introduce amdgpu triple arch (PR #206480)
Matt Arsenault via flang-commits
flang-commits at lists.llvm.org
Mon Jun 29 06:15:04 PDT 2026
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/206480
Move towards using the triple for representing incompatible
ISA changes. Use the subarch field to represent the various
incompatible cases. Previously we pretended a single triple arch
was universally compatible, and only distinguished by function
level subtargets. Move towards using distinct triples to enable
more sophisticated toolchain handling in the future, like proper
runtime library linking.
Introduce a new subarch per unique ISA, but also introduce
"major subarches" which are compatible by a set of covered
minor ISA versions. These map to the existing generic targets.
There are a few placeholder subarch entries, which currently
have missing backing generic arches for codegen.
This should be the preferred triple arch name going forward,
but is treated as an alias of amdgcn. This does not yet change
clang to emit the new triples.
Part of #154925
>From 38392142f8f8ce4d0573e4355de13f0a0c3f80c5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Mon, 1 Sep 2025 14:51:44 +0900
Subject: [PATCH] AMDGPU: Introduce amdgpu triple arch
Move towards using the triple for representing incompatible
ISA changes. Use the subarch field to represent the various
incompatible cases. Previously we pretended a single triple arch
was universally compatible, and only distinguished by function
level subtargets. Move towards using distinct triples to enable
more sophisticated toolchain handling in the future, like proper
runtime library linking.
Introduce a new subarch per unique ISA, but also introduce
"major subarches" which are compatible by a set of covered
minor ISA versions. These map to the existing generic targets.
There are a few placeholder subarch entries, which currently
have missing backing generic arches for codegen.
This should be the preferred triple arch name going forward,
but is treated as an alias of amdgcn. This does not yet change
clang to emit the new triples.
Part of #154925
---
clang/include/clang/Basic/Attr.td | 4 +-
clang/lib/Basic/OffloadArch.cpp | 3 +-
clang/lib/Basic/Targets.cpp | 2 +-
clang/lib/Basic/Targets/SPIR.cpp | 2 +-
clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp | 2 +-
clang/lib/CIR/CodeGen/CIRGenModule.cpp | 2 +-
.../Transforms/TargetLowering/LowerModule.cpp | 2 +-
clang/lib/CodeGen/CGBuiltin.cpp | 2 +-
clang/lib/CodeGen/CodeGenModule.cpp | 6 +-
clang/lib/Driver/Driver.cpp | 11 +-
clang/lib/Driver/ToolChain.cpp | 2 +-
clang/lib/Driver/ToolChains/CommonArgs.cpp | 6 +-
clang/lib/Driver/ToolChains/Darwin.cpp | 2 +-
clang/lib/Driver/ToolChains/Flang.cpp | 3 +-
clang/lib/Driver/ToolChains/Gnu.cpp | 2 +-
clang/lib/Sema/SemaAMDGPU.cpp | 2 +-
clang/lib/Sema/SemaChecking.cpp | 6 +-
clang/test/Driver/amdgpu-toolchain.c | 8 +
.../ClangLinkerWrapper.cpp | 2 +-
flang/include/flang/Tools/TargetSetup.h | 2 +-
flang/lib/Optimizer/CodeGen/Target.cpp | 2 +-
lld/ELF/InputFiles.cpp | 2 +-
llvm/docs/AMDGPUUsage.rst | 1036 +++++++++--------
llvm/docs/ReleaseNotes.md | 3 +
llvm/include/llvm/Object/ELFObjectFile.h | 2 +-
.../llvm/TargetParser/AMDGPUTargetParser.def | 124 +-
.../llvm/TargetParser/AMDGPUTargetParser.h | 50 +-
llvm/include/llvm/TargetParser/Triple.h | 95 +-
llvm/lib/Frontend/OpenMP/OMPContext.cpp | 4 +-
llvm/lib/Object/RelocationResolver.cpp | 2 +-
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 2 +
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 46 +
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 32 +-
.../Disassembler/AMDGPUDisassembler.cpp | 4 +
llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 43 +-
.../AMDGPU/MCA/AMDGPUCustomBehaviour.cpp | 5 +
.../MCTargetDesc/AMDGPUMCTargetDesc.cpp | 32 +-
.../MCTargetDesc/AMDGPUTargetStreamer.cpp | 2 +-
.../AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp | 20 +-
.../AMDGPU/TargetInfo/AMDGPUTargetInfo.h | 4 +
llvm/lib/TargetParser/AMDGPUTargetParser.cpp | 252 +++-
llvm/lib/TargetParser/TargetDataLayout.cpp | 2 +-
llvm/lib/TargetParser/Triple.cpp | 163 ++-
llvm/lib/Transforms/IPO/ExpandVariadics.cpp | 4 +-
llvm/lib/Transforms/IPO/OpenMPOpt.cpp | 2 +-
llvm/lib/Transforms/Utils/CodeExtractor.cpp | 2 +-
llvm/test/CodeGen/AMDGPU/amdgpu-triple.ll | 72 ++
.../CodeGen/AMDGPU/elf-header-flags-mach.ll | 2 +-
llvm/test/CodeGen/AMDGPU/loop-prefetch.ll | 2 +-
.../AMDGPU/march-amdgcn-legacy-arch-name.ll | 10 +
.../CodeGen/AMDGPU/target-id-from-triple.ll | 177 +++
...validate-subtarget-subarch-empty-module.ll | 10 +
.../AMDGPU/validate-subtarget-subarch.ll | 47 +
.../CodeGen/MIR/AMDGPU/init-whole.wave.ll | 4 +-
.../Linker/Inputs/amdgpu-amdpal-no-subarch.ll | 5 +
llvm/test/Linker/Inputs/amdgpu-no-subarch.ll | 5 +
llvm/test/Linker/Inputs/amdgpu10-subarch.ll | 5 +
llvm/test/Linker/Inputs/amdgpu9.00-subarch.ll | 5 +
llvm/test/Linker/amdgpu-triple-os-mismatch.ll | 19 +
llvm/test/Linker/amdgpu-triple-subarch.ll | 42 +
.../amd-amdgpu-isa-malformed-target-id.s | 2 +-
...mdgcn-target-directive-subarch-cpu-field.s | 58 +
.../amdgcn-target-malformed-target-id.s | 2 +-
.../amdgcn_target_directive_from_eflags.s | 28 +-
.../MC/AMDGPU/arch-amdgcn-legacy-arch-name.s | 7 +
.../Object/AMDGPU/elf-header-flags-mach.yaml | 2 +-
llvm/test/Object/AMDGPU/objdump.s | 2 +-
.../AMDGPU/arch-amdgcn-legacy-arch-name.s | 8 +
.../llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx10.s | 2 +-
.../llvm-objdump/ELF/AMDGPU/subarch-triple.s | 37 +
.../llvm-objdump/ELF/AMDGPU/subtarget.ll | 96 +-
.../llvm-readobj/ELF/AMDGPU/elf-headers.test | 2 +-
llvm/tools/llvm-objdump/llvm-objdump.cpp | 4 +-
llvm/unittests/Object/ELFObjectFileTest.cpp | 2 +-
.../TargetParser/TargetParserTest.cpp | 417 +++++++
llvm/unittests/TargetParser/TripleTest.cpp | 150 ++-
llvm/utils/UpdateTestChecks/asm.py | 1 +
offload/plugins-nextgen/amdgpu/src/rtl.cpp | 2 +-
78 files changed, 2528 insertions(+), 705 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/amdgpu-triple.ll
create mode 100644 llvm/test/CodeGen/AMDGPU/march-amdgcn-legacy-arch-name.ll
create mode 100644 llvm/test/CodeGen/AMDGPU/target-id-from-triple.ll
create mode 100644 llvm/test/CodeGen/AMDGPU/validate-subtarget-subarch-empty-module.ll
create mode 100644 llvm/test/CodeGen/AMDGPU/validate-subtarget-subarch.ll
create mode 100644 llvm/test/Linker/Inputs/amdgpu-amdpal-no-subarch.ll
create mode 100644 llvm/test/Linker/Inputs/amdgpu-no-subarch.ll
create mode 100644 llvm/test/Linker/Inputs/amdgpu10-subarch.ll
create mode 100644 llvm/test/Linker/Inputs/amdgpu9.00-subarch.ll
create mode 100644 llvm/test/Linker/amdgpu-triple-os-mismatch.ll
create mode 100644 llvm/test/Linker/amdgpu-triple-subarch.ll
create mode 100644 llvm/test/MC/AMDGPU/amdgcn-target-directive-subarch-cpu-field.s
create mode 100644 llvm/test/MC/AMDGPU/arch-amdgcn-legacy-arch-name.s
create mode 100644 llvm/test/tools/llvm-objdump/AMDGPU/arch-amdgcn-legacy-arch-name.s
create mode 100644 llvm/test/tools/llvm-objdump/ELF/AMDGPU/subarch-triple.s
diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td
index 3f57104d474a7..de3e0f7b563a7 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -477,7 +477,7 @@ class TargetArch<list<string> arches> : TargetSpec {
}
def TargetARM : TargetArch<["arm", "thumb", "armeb", "thumbeb"]>;
def TargetAArch64 : TargetArch<["aarch64", "aarch64_be", "aarch64_32"]>;
-def TargetAMDGPU : TargetArch<["amdgcn", "r600"]>;
+def TargetAMDGPU : TargetArch<["amdgpu", "r600"]>;
def TargetAnyArm : TargetArch<!listconcat(TargetARM.Arches, TargetAArch64.Arches)>;
def TargetAVR : TargetArch<["avr"]>;
def TargetBPF : TargetArch<["bpfel", "bpfeb"]>;
@@ -512,7 +512,7 @@ def TargetMicrosoftCXXABI : TargetArch<["x86", "x86_64", "arm", "thumb", "aarch6
// environment on Windows 2. an offloading target e.g. amdgcn or nvptx with
// a host target in MSVC environment on Windows.
def TargetMicrosoftRecordLayout : TargetArch<["x86", "x86_64", "arm", "thumb",
- "aarch64", "amdgcn", "nvptx",
+ "aarch64", "amdgpu", "nvptx",
"nvptx64", "spirv", "spirv32",
"spirv64"]> {
let CustomCode = [{ Target.hasMicrosoftRecordLayout() }];
diff --git a/clang/lib/Basic/OffloadArch.cpp b/clang/lib/Basic/OffloadArch.cpp
index 2a333662455e4..5d12f257f3680 100644
--- a/clang/lib/Basic/OffloadArch.cpp
+++ b/clang/lib/Basic/OffloadArch.cpp
@@ -173,8 +173,7 @@ llvm::Triple OffloadArchToTriple(const llvm::Triple &DefaultToolchainTriple,
}
if (IsAMDOffloadArch(ID))
- return llvm::Triple(llvm::Triple::amdgcn, llvm::Triple::NoSubArch,
- llvm::Triple::AMD, llvm::Triple::AMDHSA);
+ return llvm::Triple("amdgcn-amd-amdhsa");
return {};
}
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index ed88ae7173bad..8c01cfca8ccb4 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -434,7 +434,7 @@ std::unique_ptr<TargetInfo> AllocateTarget(const llvm::Triple &Triple,
return std::make_unique<NVPTXTargetInfo>(Triple, Opts,
/*TargetPointerWidth=*/64);
- case llvm::Triple::amdgcn:
+ case llvm::Triple::amdgpu:
case llvm::Triple::r600:
return std::make_unique<AMDGPUTargetInfo>(Triple, Opts);
diff --git a/clang/lib/Basic/Targets/SPIR.cpp b/clang/lib/Basic/Targets/SPIR.cpp
index 8fdb45acf381f..3eb62c9051b58 100644
--- a/clang/lib/Basic/Targets/SPIR.cpp
+++ b/clang/lib/Basic/Targets/SPIR.cpp
@@ -111,7 +111,7 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions &Opts,
}
static const AMDGPUTargetInfo
- AMDGPUTI(llvm::Triple(llvm::Triple::amdgcn, llvm::Triple::NoSubArch,
+ AMDGPUTI(llvm::Triple(llvm::Triple::amdgpu, llvm::Triple::NoSubArch,
llvm::Triple::AMD, llvm::Triple::AMDHSA),
{});
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
index 3b8149411e7c4..0dc686cbb3f99 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
@@ -2769,7 +2769,7 @@ emitTargetArchBuiltinExpr(CIRGenFunction *cgf, unsigned builtinID,
// These are actually NYI, but that will be reported by emitBuiltinExpr.
// At this point, we don't even know that the builtin is target-specific.
return std::nullopt;
- case llvm::Triple::amdgcn:
+ case llvm::Triple::amdgpu:
return cgf->emitAMDGPUBuiltinExpr(builtinID, e);
case llvm::Triple::systemz:
return std::nullopt;
diff --git a/clang/lib/CIR/CodeGen/CIRGenModule.cpp b/clang/lib/CIR/CodeGen/CIRGenModule.cpp
index 69dfadf58aa49..796e7aaaff884 100644
--- a/clang/lib/CIR/CodeGen/CIRGenModule.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenModule.cpp
@@ -310,7 +310,7 @@ const TargetCIRGenInfo &CIRGenModule::getTargetCIRGenInfo() {
case llvm::Triple::nvptx64:
theTargetCIRGenInfo = createNVPTXTargetCIRGenInfo(genTypes);
return *theTargetCIRGenInfo;
- case llvm::Triple::amdgcn: {
+ case llvm::Triple::amdgpu: {
theTargetCIRGenInfo = createAMDGPUTargetCIRGenInfo(genTypes);
return *theTargetCIRGenInfo;
}
diff --git a/clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp b/clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp
index cccbfdde3bfdf..4061d3b2e58c7 100644
--- a/clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp
+++ b/clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp
@@ -48,7 +48,7 @@ createTargetLoweringInfo(LowerModule &lm) {
const llvm::Triple &triple = lm.getTarget().getTriple();
switch (triple.getArch()) {
- case llvm::Triple::amdgcn:
+ case llvm::Triple::amdgpu:
return createAMDGPUTargetLoweringInfo();
case llvm::Triple::nvptx:
case llvm::Triple::nvptx64:
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 475bfec6199fc..91080c2f5ec37 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -108,8 +108,8 @@ static Value *EmitTargetArchBuiltinExpr(CodeGenFunction *CGF,
case llvm::Triple::ppc64:
case llvm::Triple::ppc64le:
return CGF->EmitPPCBuiltinExpr(BuiltinID, E);
+ case llvm::Triple::amdgpu:
case llvm::Triple::r600:
- case llvm::Triple::amdgcn:
return CGF->EmitAMDGPUBuiltinExpr(BuiltinID, E);
case llvm::Triple::systemz:
return CGF->EmitSystemZBuiltinExpr(BuiltinID, E);
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp
index fec18acd46998..35fb3815fa18c 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -291,7 +291,7 @@ createTargetCodeGenInfo(CodeGenModule &CGM) {
return createLanaiTargetCodeGenInfo(CGM);
case llvm::Triple::r600:
return createAMDGPUTargetCodeGenInfo(CGM);
- case llvm::Triple::amdgcn:
+ case llvm::Triple::amdgpu:
return createAMDGPUTargetCodeGenInfo(CGM);
case llvm::Triple::sparc:
return createSparcV8TargetCodeGenInfo(CGM);
@@ -629,7 +629,7 @@ void CodeGenModule::createOpenMPRuntime() {
switch (getTriple().getArch()) {
case llvm::Triple::nvptx:
case llvm::Triple::nvptx64:
- case llvm::Triple::amdgcn:
+ case llvm::Triple::amdgpu:
case llvm::Triple::spirv64:
assert(
getLangOpts().OpenMPIsTargetDevice &&
@@ -6208,7 +6208,7 @@ LangAS CodeGenModule::GetGlobalConstantAddressSpace() const {
}
// In address space agnostic languages, string literals are in default address
-// space in AST. However, certain targets (e.g. amdgcn) request them to be
+// space in AST. However, certain targets (e.g. amdgpu) request them to be
// emitted in constant address space in LLVM IR. To be consistent with other
// parts of AST, string literal global variables in constant address space
// need to be casted to default address space before being put into address
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 0b04a68417bbe..1d4e6ab50152c 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -941,10 +941,8 @@ static TripleSet inferOffloadToolchains(Compilation &C,
for (llvm::StringRef Arch : Archs) {
OffloadArch ID = StringToOffloadArch(Arch);
if (ID == OffloadArch::Unknown)
- ID = StringToOffloadArch(getProcessorFromTargetID(
- llvm::Triple(llvm::Triple::amdgcn, llvm::Triple::NoSubArch,
- llvm::Triple::AMD, llvm::Triple::AMDHSA),
- Arch));
+ ID = StringToOffloadArch(
+ getProcessorFromTargetID(llvm::Triple("amdgcn-amd-amdhsa"), Arch));
if (Kind == Action::OFK_HIP && !IsAMDOffloadArch(ID)) {
C.getDriver().Diag(clang::diag::err_drv_offload_bad_gpu_arch)
@@ -990,8 +988,7 @@ static TripleSet inferOffloadToolchains(Compilation &C,
// Infer the default target triple if no specific architectures are given.
if (Archs.empty() && Kind == Action::OFK_HIP)
- Triples.insert(llvm::Triple(llvm::Triple::amdgcn, llvm::Triple::NoSubArch,
- llvm::Triple::AMD, llvm::Triple::AMDHSA));
+ Triples.insert(llvm::Triple("amdgcn-amd-amdhsa"));
else if (Archs.empty() && Kind == Action::OFK_Cuda) {
llvm::Triple::ArchType Arch =
C.getDefaultToolChain().getTriple().isArch64Bit()
@@ -7238,7 +7235,7 @@ const ToolChain &Driver::getToolChain(const ArgList &Args,
case llvm::Triple::csky:
TC = std::make_unique<toolchains::CSKYToolChain>(*this, Target, Args);
break;
- case llvm::Triple::amdgcn:
+ case llvm::Triple::amdgpu:
case llvm::Triple::r600:
TC = std::make_unique<toolchains::AMDGPUToolChain>(*this, Target, Args);
break;
diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp
index 726c8a6ad229a..3f6049d83423f 100644
--- a/clang/lib/Driver/ToolChain.cpp
+++ b/clang/lib/Driver/ToolChain.cpp
@@ -1482,7 +1482,7 @@ std::string ToolChain::ComputeLLVMTriple(const ArgList &Args, BoundArch BA,
}
case llvm::Triple::aarch64_32:
return getTripleString().str();
- case llvm::Triple::amdgcn: {
+ case llvm::Triple::amdgpu: {
llvm::Triple Triple = getTriple();
tools::AMDGPU::setArchNameInTriple(getDriver(), Args, InputType, Triple);
return Triple.getTriple();
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index ba4341ed41f1a..65591a52e25fb 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -95,7 +95,7 @@ static bool useFramePointerForTargetByDefault(const llvm::opt::ArgList &Args,
case llvm::Triple::sparc:
case llvm::Triple::sparcel:
case llvm::Triple::sparcv9:
- case llvm::Triple::amdgcn:
+ case llvm::Triple::amdgpu:
case llvm::Triple::r600:
case llvm::Triple::csky:
case llvm::Triple::loongarch32:
@@ -817,8 +817,8 @@ std::string tools::getCPUName(const Driver &D, const ArgList &Args,
case llvm::Triple::systemz:
return systemz::getSystemZTargetCPU(Args, T);
+ case llvm::Triple::amdgpu:
case llvm::Triple::r600:
- case llvm::Triple::amdgcn:
return getAMDGPUTargetGPU(T, Args);
case llvm::Triple::wasm32:
@@ -899,8 +899,8 @@ void tools::getTargetFeatures(const Driver &D, const llvm::Triple &Triple,
case llvm::Triple::sparcv9:
sparc::getSparcTargetFeatures(D, Triple, Args, Features);
break;
+ case llvm::Triple::amdgpu:
case llvm::Triple::r600:
- case llvm::Triple::amdgcn:
amdgpu::getAMDGPUTargetFeatures(D, Triple, Args, Features);
break;
case llvm::Triple::nvptx:
diff --git a/clang/lib/Driver/ToolChains/Darwin.cpp b/clang/lib/Driver/ToolChains/Darwin.cpp
index 64bc96a900f30..a729fb4fc1a4f 100644
--- a/clang/lib/Driver/ToolChains/Darwin.cpp
+++ b/clang/lib/Driver/ToolChains/Darwin.cpp
@@ -66,8 +66,8 @@ llvm::Triple::ArchType darwin::getArchTypeForMachOArchName(StringRef Str) {
.Cases({"armv8m.base", "armv8m.main", "armv8.1m.main"}, llvm::Triple::arm)
.Cases({"arm64", "arm64e"}, llvm::Triple::aarch64)
.Case("arm64_32", llvm::Triple::aarch64_32)
+ .Cases({"amdgpu", "amdgcn"}, llvm::Triple::amdgpu)
.Case("r600", llvm::Triple::r600)
- .Case("amdgcn", llvm::Triple::amdgcn)
.Case("nvptx", llvm::Triple::nvptx)
.Case("nvptx64", llvm::Triple::nvptx64)
.Case("amdil", llvm::Triple::amdil)
diff --git a/clang/lib/Driver/ToolChains/Flang.cpp b/clang/lib/Driver/ToolChains/Flang.cpp
index ea4df1db38ec8..49330f7d4bd6a 100644
--- a/clang/lib/Driver/ToolChains/Flang.cpp
+++ b/clang/lib/Driver/ToolChains/Flang.cpp
@@ -603,9 +603,8 @@ void Flang::addTargetOptions(const ArgList &Args, ArgStringList &CmdArgs,
getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
AddAArch64TargetArgs(Args, CmdArgs);
break;
-
+ case llvm::Triple::amdgpu:
case llvm::Triple::r600:
- case llvm::Triple::amdgcn:
getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
AddAMDGPUTargetArgs(Args, CmdArgs, BA, DeviceOffloadKind);
break;
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp
index b58c10145e7f3..24076d8814322 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -3067,7 +3067,7 @@ Generic_GCC::getDefaultUnwindTableLevel(const ArgList &Args) const {
switch (getArch()) {
case llvm::Triple::aarch64:
case llvm::Triple::aarch64_be:
- case llvm::Triple::amdgcn:
+ case llvm::Triple::amdgpu:
case llvm::Triple::ppc:
case llvm::Triple::ppcle:
case llvm::Triple::ppc64:
diff --git a/clang/lib/Sema/SemaAMDGPU.cpp b/clang/lib/Sema/SemaAMDGPU.cpp
index bd9e7e7b71ed6..f1de44e3d2ed7 100644
--- a/clang/lib/Sema/SemaAMDGPU.cpp
+++ b/clang/lib/Sema/SemaAMDGPU.cpp
@@ -1034,7 +1034,7 @@ bool DiagnoseUnguardedBuiltins::VisitCallExpr(CallExpr *CE) {
for (auto &&F : llvm::split(BInfo.getRequiredFeatures(GID), ','))
FeatureMap[F] = true;
} else {
- static const llvm::Triple AMDGCN(llvm::Triple::amdgcn,
+ static const llvm::Triple AMDGCN(llvm::Triple::amdgpu,
llvm::Triple::NoSubArch, llvm::Triple::AMD,
llvm::Triple::AMDHSA);
llvm::AMDGPU::fillAMDGPUFeatureMap(CurrentGFXIP.back().second, AMDGCN,
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 2bbd880c0e068..df5e6586bc1b0 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -2242,7 +2242,7 @@ bool Sema::CheckTSBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
case llvm::Triple::ppc64:
case llvm::Triple::ppc64le:
return PPC().CheckPPCBuiltinFunctionCall(TI, BuiltinID, TheCall);
- case llvm::Triple::amdgcn:
+ case llvm::Triple::amdgpu:
return AMDGPU().CheckAMDGCNBuiltinFunctionCall(BuiltinID, TheCall);
case llvm::Triple::riscv32:
case llvm::Triple::riscv64:
@@ -3088,7 +3088,7 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID,
if (CheckBuiltinTargetInSupported(
*this, TheCall,
{llvm::Triple::x86_64, llvm::Triple::arm, llvm::Triple::thumb,
- llvm::Triple::aarch64, llvm::Triple::amdgcn}))
+ llvm::Triple::aarch64, llvm::Triple::amdgpu}))
return ExprError();
break;
@@ -3107,7 +3107,7 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID,
if (CheckBuiltinTargetInSupported(
*this, TheCall,
{llvm::Triple::x86, llvm::Triple::x86_64, llvm::Triple::arm,
- llvm::Triple::thumb, llvm::Triple::aarch64, llvm::Triple::amdgcn,
+ llvm::Triple::thumb, llvm::Triple::aarch64, llvm::Triple::amdgpu,
llvm::Triple::ppc, llvm::Triple::ppc64, llvm::Triple::ppcle,
llvm::Triple::ppc64le}))
return ExprError();
diff --git a/clang/test/Driver/amdgpu-toolchain.c b/clang/test/Driver/amdgpu-toolchain.c
index 135129b739603..78b76aa8bc8c5 100644
--- a/clang/test/Driver/amdgpu-toolchain.c
+++ b/clang/test/Driver/amdgpu-toolchain.c
@@ -1,5 +1,9 @@
// RUN: %clang -### --target=amdgcn--amdhsa -x assembler -mcpu=kaveri %s 2>&1 | FileCheck -check-prefix=AS_LINK %s
// RUN: %clang -### -g --target=amdgcn--amdhsa -mcpu=kaveri -nogpulib %s 2>&1 | FileCheck -check-prefix=DWARF_VER %s
+
+// RUN: %clang -### --target=amdgpu7--amdhsa -x assembler -mcpu=kaveri %s 2>&1 | FileCheck -check-prefix=AS_LINK %s
+// RUN: %clang -### -g --target=amdgpu7--amdhsa -mcpu=kaveri -nogpulib %s 2>&1 | FileCheck -check-prefix=DWARF_VER %s
+
// RUN: %clang -### --target=amdgcn-amd-amdpal -x assembler -mcpu=kaveri %s 2>&1 | FileCheck -check-prefix=AS_LINK %s
// RUN: %clang -### -g --target=amdgcn-amd-amdpal -mcpu=kaveri %s 2>&1 | FileCheck -check-prefix=DWARF_VER %s
// RUN: %clang -### --target=amdgcn-mesa-mesa3d -x assembler -mcpu=kaveri %s 2>&1 | FileCheck -check-prefix=AS_LINK %s
@@ -29,6 +33,10 @@
// RUN: %clang -### --target=amdgcn-amd-amdhsa -mcpu=gfx90a:xnack+:sramecc- -nogpulib \
// RUN: -L. -fconvergent-functions %s 2>&1 | FileCheck -check-prefix=MCPU %s
+
+// RUN: %clang -### --target=amdgpu9.0a-amd-amdhsa -mcpu=gfx90a:xnack+:sramecc- -nogpulib \
+// RUN: -L. -fconvergent-functions %s 2>&1 | FileCheck -check-prefix=MCPU %s
+
// MCPU: ld.lld{{.*}}"-plugin-opt=mcpu=gfx90a"{{.*}}"-plugin-opt=-mattr=+xnack,-sramecc"{{.*}}
// RUN: %clang -### --target=amdgcn-amd-amdhsa -mcpu=gfx906 -nogpulib \
diff --git a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
index a4a67eed7d47f..75e92861ef4f7 100644
--- a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
+++ b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
@@ -632,7 +632,7 @@ Expected<StringRef> linkDevice(ArrayRef<StringRef> InputFiles,
switch (Triple.getArch()) {
case Triple::nvptx:
case Triple::nvptx64:
- case Triple::amdgcn:
+ case Triple::amdgpu:
case Triple::x86:
case Triple::x86_64:
case Triple::aarch64:
diff --git a/flang/include/flang/Tools/TargetSetup.h b/flang/include/flang/Tools/TargetSetup.h
index 002e82aa72484..3fc08ec5ae870 100644
--- a/flang/include/flang/Tools/TargetSetup.h
+++ b/flang/include/flang/Tools/TargetSetup.h
@@ -47,7 +47,7 @@ namespace Fortran::tools {
}
switch (targetTriple.getArch()) {
- case llvm::Triple::ArchType::amdgcn:
+ case llvm::Triple::ArchType::amdgpu:
case llvm::Triple::ArchType::x86_64:
break;
default:
diff --git a/flang/lib/Optimizer/CodeGen/Target.cpp b/flang/lib/Optimizer/CodeGen/Target.cpp
index 45311850e38df..2042b8b0c06fe 100644
--- a/flang/lib/Optimizer/CodeGen/Target.cpp
+++ b/flang/lib/Optimizer/CodeGen/Target.cpp
@@ -1950,7 +1950,7 @@ std::unique_ptr<fir::CodeGenSpecifics> fir::CodeGenSpecifics::get(
return std::make_unique<TargetRISCV64>(ctx, std::move(trp),
std::move(kindMap), targetCPU,
targetFeatures, targetABI, dl);
- case llvm::Triple::ArchType::amdgcn:
+ case llvm::Triple::ArchType::amdgpu:
return std::make_unique<TargetAMDGPU>(ctx, std::move(trp),
std::move(kindMap), targetCPU,
targetFeatures, targetABI, dl);
diff --git a/lld/ELF/InputFiles.cpp b/lld/ELF/InputFiles.cpp
index 2f544f0fe0958..fede7cbbdd3a8 100644
--- a/lld/ELF/InputFiles.cpp
+++ b/lld/ELF/InputFiles.cpp
@@ -1744,7 +1744,7 @@ static uint16_t getBitcodeMachineKind(Ctx &ctx, StringRef path,
case Triple::aarch64:
case Triple::aarch64_be:
return EM_AARCH64;
- case Triple::amdgcn:
+ case Triple::amdgpu:
case Triple::r600:
return EM_AMDGPU;
case Triple::arm:
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 2b522395ee892..f78ffd295ecac 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -49,8 +49,10 @@ LLVM
Target Triples
--------------
-Use the Clang option ``--target=<Architecture>-<Vendor>-<OS>-<Environment>``
-to specify the target triple:
+Use the Clang option ``--target=<Architecture><SubArch>-<Vendor>-<OS>-<Environment>``
+to specify the target triple. Historically, the single top-level
+``amdgcn`` architecture was used for all devices and specific devices
+by the subtarget. Currently a subarch should be specified.
.. table:: AMDGPU Architectures
:name: amdgpu-architecture-table
@@ -59,7 +61,8 @@ to specify the target triple:
Architecture Description
============ ==============================================================
``r600`` AMD GPUs HD2XXX-HD6XXX for graphics and compute shaders.
- ``amdgcn`` AMD GPUs GCN GFX6 onwards for graphics and compute shaders.
+ ``amdgpu`` AMD GPUs GCN GFX6 onwards for graphics and compute shaders.
+ ``amdgcn`` Legacy alias for ``amdgpu``.
============ ==============================================================
.. table:: AMDGPU Vendors
@@ -105,6 +108,113 @@ to specify the target triple:
*<empty>* Default.
============ ==============================================================
+.. _amdgpu-subarch-compatibility:
+
+Subarchitecture Compatibility
+-----------------------------
+
+For the ``amdgpu`` architecture the ISA version is encoded in the
+triple's *SubArch* component. Every unique ISA has its own *minor
+subarch* (for example ``amdgpu9.00`` for ``gfx900``). ``amdgcn`` is a
+legacy alias of ``amdgpu`` (see :ref:`amdgpu-architecture-table`)
+which does not support subarches.
+
+Minor subarches are grouped into *major subarches* that name a family
+of largely compatible ISA versions (for example ``amdgpu9``). A major
+subarch corresponds to a :ref:`generic processor
+<amdgpu-generic-processor-table>` when one exists for that family; the
+remaining major subarches are placeholders for families that do not
+yet have a generic target for code generation.
+
+Two subarches are considered *compatible* when:
+
+* they are identical, or
+* one of them is the major subarch of the family that the other belongs to.
+
+In particular, two distinct *minor* subarches are never compatible
+with each other, even within the same family (for example
+``amdgpu9.00`` and ``amdgpu9.06`` are not compatible). A minor subarch
+is only compatible with its own major subarch, and a major subarch is
+compatible with itself and every minor subarch it covers. A triple
+with no subarch (``amdgpu``) is treated as compatible with anything,
+as a backwards-compatibility allowance. When linking modules with
+compatible-but-unequal subarches, the more specific (minor) subarch is
+selected for the merged module.
+
+The following table lists each major subarch and the minor subarches it covers.
+The *Default Generic Processor* column gives the generic processor that a major
+subarch selects by default for code generation; this is the corresponding
+generic processor for families that have one (see
+:ref:`amdgpu-generic-processor-table`). Major subarches listed as *(none)* are
+placeholders for families that do not yet have a generic target.
+
+ .. list-table:: AMDGPU Major SubArchitecture Coverage
+ :name: amdgpu-major-subarch-table
+ :header-rows: 1
+
+ * - Major SubArch
+ - Default Processor
+ - Covered SubArches (Processor)
+ * - ``amdgpu6``
+ - *(none)*
+ - ``amdgpu6.00`` (``gfx600``), ``amdgpu6.01`` (``gfx601``),
+ ``amdgpu6.02`` (``gfx602``)
+ * - ``amdgpu7``
+ - *(none)*
+ - ``amdgpu7.00`` (``gfx700``), ``amdgpu7.01`` (``gfx701``),
+ ``amdgpu7.02`` (``gfx702``), ``amdgpu7.03`` (``gfx703``),
+ ``amdgpu7.04`` (``gfx704``), ``amdgpu7.05`` (``gfx705``)
+ * - ``amdgpu8``
+ - *(none)*
+ - ``amdgpu8.01`` (``gfx801``), ``amdgpu8.02`` (``gfx802``),
+ ``amdgpu8.03`` (``gfx803``), ``amdgpu8.05`` (``gfx805``)
+ * - ``amdgpu8.10``
+ - *(none)*
+ - ``amdgpu8.10`` (``gfx810``)
+ * - ``amdgpu9``
+ - ``gfx9-generic``
+ - ``amdgpu9.00`` (``gfx900``), ``amdgpu9.02`` (``gfx902``),
+ ``amdgpu9.04`` (``gfx904``), ``amdgpu9.06`` (``gfx906``),
+ ``amdgpu9.09`` (``gfx909``), ``amdgpu9.0c`` (``gfx90c``)
+ * - ``amdgpu9.08``
+ - *(none)*
+ - ``amdgpu9.08`` (``gfx908``)
+ * - ``amdgpu9.0a``
+ - *(none)*
+ - ``amdgpu9.0a`` (``gfx90a``)
+ * - ``amdgpu9.4``
+ - ``gfx9-4-generic``
+ - ``amdgpu9.42`` (``gfx942``), ``amdgpu9.50`` (``gfx950``)
+ * - ``amdgpu10.1``
+ - ``gfx10-1-generic``
+ - ``amdgpu10.10`` (``gfx1010``), ``amdgpu10.11`` (``gfx1011``),
+ ``amdgpu10.12`` (``gfx1012``), ``amdgpu10.13`` (``gfx1013``)
+ * - ``amdgpu10.3``
+ - ``gfx10-3-generic``
+ - ``amdgpu10.30`` (``gfx1030``), ``amdgpu10.31`` (``gfx1031``),
+ ``amdgpu10.32`` (``gfx1032``), ``amdgpu10.33`` (``gfx1033``),
+ ``amdgpu10.34`` (``gfx1034``), ``amdgpu10.35`` (``gfx1035``),
+ ``amdgpu10.36`` (``gfx1036``)
+ * - ``amdgpu11``
+ - ``gfx11-generic``
+ - ``amdgpu11.00`` (``gfx1100``), ``amdgpu11.01`` (``gfx1101``),
+ ``amdgpu11.02`` (``gfx1102``), ``amdgpu11.03`` (``gfx1103``),
+ ``amdgpu11.50`` (``gfx1150``), ``amdgpu11.51`` (``gfx1151``),
+ ``amdgpu11.52`` (``gfx1152``), ``amdgpu11.53`` (``gfx1153``)
+ * - ``amdgpu11.7``
+ - *(none)*
+ - ``amdgpu11.70`` (``gfx1170``), ``amdgpu11.71`` (``gfx1171``),
+ ``amdgpu11.72`` (``gfx1172``)
+ * - ``amdgpu12``
+ - ``gfx12-generic``
+ - ``amdgpu12.00`` (``gfx1200``), ``amdgpu12.01`` (``gfx1201``)
+ * - ``amdgpu12.5``
+ - ``gfx12-5-generic``
+ - ``amdgpu12.50`` (``gfx1250``), ``amdgpu12.51`` (``gfx1251``)
+ * - ``amdgpu13``
+ - *(none)*
+ - ``amdgpu13.10`` (``gfx1310``)
+
.. _amdgpu-processors:
Processors
@@ -123,404 +233,406 @@ Every processor supports every OS ABI (see :ref:`amdgpu-os`) with the following
.. table:: AMDGPU Processors
:name: amdgpu-processor-table
- =========== =============== ============ ===== ================= =============== =============== ======================
- Processor Alternative Target dGPU/ Target Target OS Support Example
- Processor Triple APU Features Properties *(see* Products
- Architecture Supported `amdgpu-os`_
- *and
- corresponding
- runtime release
- notes for
- current
- information and
- level of
- support)*
- =========== =============== ============ ===== ================= =============== =============== ======================
+ =========== =============== =============== ===== ================= =============== =============== ======================
+ Processor Alternative Target dGPU/ Target Target OS Support Example
+ Processor Triple APU Features Properties *(see* Products
+ Architecture Supported `amdgpu-os`_
+ *and
+ corresponding
+ runtime
+ release
+ notes for
+ current
+ information
+ and
+ level
+ of
+ support)*
+ =========== =============== =============== ===== ================= =============== =============== ======================
**Radeon HD 2000/3000 Series (R600)** [AMD-RADEON-HD-2000-3000]_
- -----------------------------------------------------------------------------------------------------------------------
- ``r600`` ``r600`` dGPU - Does not
- support
- generic
- address
- space
- ``r630`` ``r600`` dGPU - Does not
- support
- generic
- address
- space
- ``rs880`` ``r600`` dGPU - Does not
- support
- generic
- address
- space
- ``rv670`` ``r600`` dGPU - Does not
- support
- generic
- address
- space
+ --------------------------------------------------------------------------------------------------------------------------
+ ``r600`` ``r600`` dGPU - Does not
+ support
+ generic
+ address
+ space
+ ``r630`` ``r600`` dGPU - Does not
+ support
+ generic
+ address
+ space
+ ``rs880`` ``r600`` dGPU - Does not
+ support
+ generic
+ address
+ space
+ ``rv670`` ``r600`` dGPU - Does not
+ support
+ generic
+ address
+ space
**Radeon HD 4000 Series (R700)** [AMD-RADEON-HD-4000]_
- -----------------------------------------------------------------------------------------------------------------------
- ``rv710`` ``r600`` dGPU - Does not
- support
- generic
- address
- space
- ``rv730`` ``r600`` dGPU - Does not
- support
- generic
- address
- space
- ``rv770`` ``r600`` dGPU - Does not
- support
- generic
- address
- space
+ --------------------------------------------------------------------------------------------------------------------------
+ ``rv710`` ``r600`` dGPU - Does not
+ support
+ generic
+ address
+ space
+ ``rv730`` ``r600`` dGPU - Does not
+ support
+ generic
+ address
+ space
+ ``rv770`` ``r600`` dGPU - Does not
+ support
+ generic
+ address
+ space
**Radeon HD 5000 Series (Evergreen)** [AMD-RADEON-HD-5000]_
- -----------------------------------------------------------------------------------------------------------------------
- ``cedar`` ``r600`` dGPU - Does not
- support
- generic
- address
- space
- ``cypress`` ``r600`` dGPU - Does not
- support
- generic
- address
- space
- ``juniper`` ``r600`` dGPU - Does not
- support
- generic
- address
- space
- ``redwood`` ``r600`` dGPU - Does not
- support
- generic
- address
- space
- ``sumo`` ``r600`` dGPU - Does not
- support
- generic
- address
- space
+ --------------------------------------------------------------------------------------------------------------------------
+ ``cedar`` ``r600`` dGPU - Does not
+ support
+ generic
+ address
+ space
+ ``cypress`` ``r600`` dGPU - Does not
+ support
+ generic
+ address
+ space
+ ``juniper`` ``r600`` dGPU - Does not
+ support
+ generic
+ address
+ space
+ ``redwood`` ``r600`` dGPU - Does not
+ support
+ generic
+ address
+ space
+ ``sumo`` ``r600`` dGPU - Does not
+ support
+ generic
+ address
+ space
**Radeon HD 6000 Series (Northern Islands)** [AMD-RADEON-HD-6000]_
- -----------------------------------------------------------------------------------------------------------------------
- ``barts`` ``r600`` dGPU - Does not
- support
- generic
- address
- space
- ``caicos`` ``r600`` dGPU - Does not
- support
- generic
- address
- space
- ``cayman`` ``r600`` dGPU - Does not
- support
- generic
- address
- space
- ``turks`` ``r600`` dGPU - Does not
- support
- generic
- address
- space
+ --------------------------------------------------------------------------------------------------------------------------
+ ``barts`` ``r600`` dGPU - Does not
+ support
+ generic
+ address
+ space
+ ``caicos`` ``r600`` dGPU - Does not
+ support
+ generic
+ address
+ space
+ ``cayman`` ``r600`` dGPU - Does not
+ support
+ generic
+ address
+ space
+ ``turks`` ``r600`` dGPU - Does not
+ support
+ generic
+ address
+ space
**GCN GFX6 (Southern Islands (SI))** [AMD-GCN-GFX6]_
- -----------------------------------------------------------------------------------------------------------------------
- ``gfx600`` - ``tahiti`` ``amdgcn`` dGPU - Does not - *pal-amdpal*
- support
- generic
- address
- space
- ``gfx601`` - ``pitcairn`` ``amdgcn`` dGPU - Does not - *pal-amdpal*
- - ``verde`` support
- generic
- address
- space
- ``gfx602`` - ``hainan`` ``amdgcn`` dGPU - Does not - *pal-amdpal*
- - ``oland`` support
- generic
- address
- space
+ --------------------------------------------------------------------------------------------------------------------------
+ ``gfx600`` - ``tahiti`` ``amdgpu6.00`` dGPU - Does not - *pal-amdpal*
+ support
+ generic
+ address
+ space
+ ``gfx601`` - ``pitcairn`` ``amdgpu6.01`` dGPU - Does not - *pal-amdpal*
+ - ``verde`` support
+ generic
+ address
+ space
+ ``gfx602`` - ``hainan`` ``amdgpu6.02`` dGPU - Does not - *pal-amdpal*
+ - ``oland`` support
+ generic
+ address
+ space
**GCN GFX7 (Sea Islands (CI))** [AMD-GCN-GFX7]_
- -----------------------------------------------------------------------------------------------------------------------
- ``gfx700`` - ``kaveri`` ``amdgcn`` APU - Offset - *rocm-amdhsa* - A6-7000
- flat - *pal-amdhsa* - A6 Pro-7050B
- scratch - *pal-amdpal* - A8-7100
- - A8 Pro-7150B
- - A10-7300
- - A10 Pro-7350B
- - FX-7500
- - A8-7200P
- - A10-7400P
- - FX-7600P
- ``gfx701`` - ``hawaii`` ``amdgcn`` dGPU - Offset - *rocm-amdhsa* - FirePro W8100
- flat - *pal-amdhsa* - FirePro W9100
- scratch - *pal-amdpal* - FirePro S9150
- - FirePro S9170
- ``gfx702`` ``amdgcn`` dGPU - Offset - *rocm-amdhsa* - Radeon R9 290
- flat - *pal-amdhsa* - Radeon R9 290x
- scratch - *pal-amdpal* - Radeon R390
- - Radeon R390x
- ``gfx703`` - ``kabini`` ``amdgcn`` APU - Offset - *pal-amdhsa* - E1-2100
- - ``mullins`` flat - *pal-amdpal* - E1-2200
- scratch - E1-2500
- - E2-3000
- - E2-3800
- - A4-5000
- - A4-5100
- - A6-5200
- - A4 Pro-3340B
- ``gfx704`` - ``bonaire`` ``amdgcn`` dGPU - Offset - *pal-amdhsa* - Radeon HD 7790
- flat - *pal-amdpal* - Radeon HD 8770
- scratch - R7 260
- - R7 260X
- ``gfx705`` ``amdgcn`` APU - Offset - *pal-amdhsa* *TBA*
- flat - *pal-amdpal*
- scratch .. TODO::
-
- Add product
- names.
+ --------------------------------------------------------------------------------------------------------------------------
+ ``gfx700`` - ``kaveri`` ``amdgpu7.00`` APU - Offset - *rocm-amdhsa* - A6-7000
+ flat - *pal-amdhsa* - A6 Pro-7050B
+ scratch - *pal-amdpal* - A8-7100
+ - A8 Pro-7150B
+ - A10-7300
+ - A10 Pro-7350B
+ - FX-7500
+ - A8-7200P
+ - A10-7400P
+ - FX-7600P
+ ``gfx701`` - ``hawaii`` ``amdgpu7.01`` dGPU - Offset - *rocm-amdhsa* - FirePro W8100
+ flat - *pal-amdhsa* - FirePro W9100
+ scratch - *pal-amdpal* - FirePro S9150
+ - FirePro S9170
+ ``gfx702`` ``amdgpu7.02`` dGPU - Offset - *rocm-amdhsa* - Radeon R9 290
+ flat - *pal-amdhsa* - Radeon R9 290x
+ scratch - *pal-amdpal* - Radeon R390
+ - Radeon R390x
+ ``gfx703`` - ``kabini`` ``amdgpu7.03`` APU - Offset - *pal-amdhsa* - E1-2100
+ - ``mullins`` flat - *pal-amdpal* - E1-2200
+ scratch - E1-2500
+ - E2-3000
+ - E2-3800
+ - A4-5000
+ - A4-5100
+ - A6-5200
+ - A4 Pro-3340B
+ ``gfx704`` - ``bonaire`` ``amdgpu7.04`` dGPU - Offset - *pal-amdhsa* - Radeon HD 7790
+ flat - *pal-amdpal* - Radeon HD 8770
+ scratch - R7 260
+ - R7 260X
+ ``gfx705`` ``amdgpu7.05`` APU - Offset - *pal-amdhsa* *TBA*
+ flat - *pal-amdpal*
+ scratch .. TODO::
+ Add product
+ names.
**GCN GFX8 (Volcanic Islands (VI))** [AMD-GCN-GFX8]_
- -----------------------------------------------------------------------------------------------------------------------
- ``gfx801`` - ``carrizo`` ``amdgcn`` APU - xnack - Offset - *rocm-amdhsa* - A6-8500P
- flat - *pal-amdhsa* - Pro A6-8500B
- scratch - *pal-amdpal* - A8-8600P
- - Pro A8-8600B
- - FX-8800P
- - Pro A12-8800B
- - A10-8700P
- - Pro A10-8700B
- - A10-8780P
- - A10-9600P
- - A10-9630P
- - A12-9700P
- - A12-9730P
- - FX-9800P
- - FX-9830P
- - E2-9010
- - A6-9210
- - A9-9410
- ``gfx802`` - ``iceland`` ``amdgcn`` dGPU - Offset - *rocm-amdhsa* - Radeon R9 285
- - ``tonga`` flat - *pal-amdhsa* - Radeon R9 380
- scratch - *pal-amdpal* - Radeon R9 385
- ``gfx803`` - ``fiji`` ``amdgcn`` dGPU - *rocm-amdhsa* - Radeon R9 Nano
- - *pal-amdhsa* - Radeon R9 Fury
- - *pal-amdpal* - Radeon R9 FuryX
- - Radeon Pro Duo
- - FirePro S9300x2
- - Radeon Instinct MI8
- \ - ``polaris10`` ``amdgcn`` dGPU - Offset - *rocm-amdhsa* - Radeon RX 470
- flat - *pal-amdhsa* - Radeon RX 480
- scratch - *pal-amdpal* - Radeon Instinct MI6
- \ - ``polaris11`` ``amdgcn`` dGPU - Offset - *rocm-amdhsa* - Radeon RX 460
- flat - *pal-amdhsa*
- scratch - *pal-amdpal*
- ``gfx805`` - ``tongapro`` ``amdgcn`` dGPU - Offset - *rocm-amdhsa* - FirePro S7150
- flat - *pal-amdhsa* - FirePro S7100
- scratch - *pal-amdpal* - FirePro W7100
- - Mobile FirePro
- M7170
- ``gfx810`` - ``stoney`` ``amdgcn`` APU - xnack - Offset - *rocm-amdhsa* *TBA*
- flat - *pal-amdhsa*
- scratch - *pal-amdpal* .. TODO::
-
- Add product
- names.
+ --------------------------------------------------------------------------------------------------------------------------
+ ``gfx801`` - ``carrizo`` ``amdgpu8.01`` APU - xnack - Offset - *rocm-amdhsa* - A6-8500P
+ flat - *pal-amdhsa* - Pro A6-8500B
+ scratch - *pal-amdpal* - A8-8600P
+ - Pro A8-8600B
+ - FX-8800P
+ - Pro A12-8800B
+ - A10-8700P
+ - Pro A10-8700B
+ - A10-8780P
+ - A10-9600P
+ - A10-9630P
+ - A12-9700P
+ - A12-9730P
+ - FX-9800P
+ - FX-9830P
+ - E2-9010
+ - A6-9210
+ - A9-9410
+ ``gfx802`` - ``iceland`` ``amdgpu8.02`` dGPU - Offset - *rocm-amdhsa* - Radeon R9 285
+ - ``tonga`` flat - *pal-amdhsa* - Radeon R9 380
+ scratch - *pal-amdpal* - Radeon R9 385
+ ``gfx803`` - ``fiji`` ``amdgpu8.03`` dGPU - *rocm-amdhsa* - Radeon R9 Nano
+ - *pal-amdhsa* - Radeon R9 Fury
+ - *pal-amdpal* - Radeon R9 FuryX
+ - Radeon Pro Duo
+ - FirePro S9300x2
+ - Radeon Instinct MI8
+ \ - ``polaris10`` ``amdgpu8.03`` dGPU - Offset - *rocm-amdhsa* - Radeon RX 470
+ flat - *pal-amdhsa* - Radeon RX 480
+ scratch - *pal-amdpal* - Radeon Instinct MI6
+ \ - ``polaris11`` ``amdgpu8.03`` dGPU - Offset - *rocm-amdhsa* - Radeon RX 460
+ flat - *pal-amdhsa*
+ scratch - *pal-amdpal*
+ ``gfx805`` - ``tongapro`` ``amdgpu8.05`` dGPU - Offset - *rocm-amdhsa* - FirePro S7150
+ flat - *pal-amdhsa* - FirePro S7100
+ scratch - *pal-amdpal* - FirePro W7100
+ - Mobile FirePro
+ M7170
+ ``gfx810`` - ``stoney`` ``amdgpu8.10`` APU - xnack - Offset - *rocm-amdhsa* *TBA*
+ flat - *pal-amdhsa*
+ scratch - *pal-amdpal* .. TODO::
+ Add product
+ names.
**GCN GFX9 (Vega)** [AMD-GCN-GFX900-GFX904-VEGA]_ [AMD-GCN-GFX906-VEGA7NM]_ [AMD-GCN-GFX908-CDNA1]_ [AMD-GCN-GFX90A-CDNA2]_ [AMD-GCN-GFX942-CDNA3]_
- -----------------------------------------------------------------------------------------------------------------------
- ``gfx900`` ``amdgcn`` dGPU - xnack - Absolute - *rocm-amdhsa* - Radeon Vega
- flat - *pal-amdhsa* Frontier Edition
- scratch - *pal-amdpal* - Radeon RX Vega 56
- - Radeon RX Vega 64
- - Radeon RX Vega 64
- Liquid
- - Radeon Instinct MI25
- ``gfx902`` ``amdgcn`` APU - xnack - Absolute - *rocm-amdhsa* - Ryzen 3 2200G
- flat - *pal-amdhsa* - Ryzen 5 2400G
- scratch - *pal-amdpal*
- ``gfx904`` ``amdgcn`` dGPU - xnack - *rocm-amdhsa* *TBA*
- - *pal-amdhsa*
- - *pal-amdpal* .. TODO::
-
- Add product
- names.
-
- ``gfx906`` ``amdgcn`` dGPU - sramecc - Absolute - *rocm-amdhsa* - Radeon Instinct MI50
- - xnack flat - *pal-amdhsa* - Radeon Instinct MI60
- scratch - *pal-amdpal* - Radeon VII
- - Radeon Pro VII
- ``gfx908`` ``amdgcn`` dGPU - sramecc - *rocm-amdhsa* - AMD Instinct MI100 Accelerator
- - xnack - Absolute
- flat
- scratch
- ``gfx909`` ``amdgcn`` APU - xnack - Absolute - *pal-amdpal* *TBA*
- flat
- scratch .. TODO::
-
- Add product
- names.
-
- ``gfx90a`` ``amdgcn`` dGPU - sramecc - Absolute - *rocm-amdhsa* - AMD Instinct MI210 Accelerator
- - tgsplit flat - *rocm-amdhsa* - AMD Instinct MI250 Accelerator
- - xnack scratch - *rocm-amdhsa* - AMD Instinct MI250X Accelerator
- - kernarg preload - Packed
- (except MI210) work-item
- IDs
-
- ``gfx90c`` ``amdgcn`` APU - xnack - Absolute - *pal-amdpal* - Ryzen 7 4700G
- flat - Ryzen 7 4700GE
- scratch - Ryzen 5 4600G
- - Ryzen 5 4600GE
- - Ryzen 3 4300G
- - Ryzen 3 4300GE
- - Ryzen Pro 4000G
- - Ryzen 7 Pro 4700G
- - Ryzen 7 Pro 4750GE
- - Ryzen 5 Pro 4650G
- - Ryzen 5 Pro 4650GE
- - Ryzen 3 Pro 4350G
- - Ryzen 3 Pro 4350GE
-
- ``gfx942`` ``amdgcn`` dGPU - sramecc - Architected - AMD Instinct MI300X
- - tgsplit flat - AMD Instinct MI300A
- - xnack scratch
- - kernarg preload - Packed
- work-item
- IDs
-
- ``gfx950`` ``amdgcn`` dGPU - sramecc - Architected *TBA*
- - tgsplit flat
- - xnack scratch .. TODO::
- - kernarg preload - Packed
- work-item Add product
- IDs names.
+ --------------------------------------------------------------------------------------------------------------------------
+ ``gfx900`` ``amdgpu9.00`` dGPU - xnack - Absolute - *rocm-amdhsa* - Radeon Vega
+ flat - *pal-amdhsa* Frontier Edition
+ scratch - *pal-amdpal* - Radeon RX Vega 56
+ - Radeon RX Vega 64
+ - Radeon RX Vega 64
+ Liquid
+ - Radeon Instinct MI25
+ ``gfx902`` ``amdgpu9.02`` APU - xnack - Absolute - *rocm-amdhsa* - Ryzen 3 2200G
+ flat - *pal-amdhsa* - Ryzen 5 2400G
+ scratch - *pal-amdpal*
+ ``gfx904`` ``amdgpu9.05`` dGPU - xnack - *rocm-amdhsa* *TBA*
+ - *pal-amdhsa*
+ - *pal-amdpal* .. TODO::
+ Add product
+ names.
+
+ ``gfx906`` ``amdgpu9.06`` dGPU - sramecc - Absolute - *rocm-amdhsa* - Radeon Instinct MI50
+ - xnack flat - *pal-amdhsa* - Radeon Instinct MI60
+ scratch - *pal-amdpal* - Radeon VII
+ - Radeon Pro VII
+ ``gfx908`` ``amdgpu9.08`` dGPU - sramecc - *rocm-amdhsa* - AMD Instinct MI100 Accelerator
+ - xnack - Absolute
+ flat
+ scratch
+ ``gfx909`` ``amdgpu9.09`` APU - xnack - Absolute - *pal-amdpal* *TBA*
+ flat
+ scratch .. TODO::
+
+ Add product
+ names.
+
+ ``gfx90a`` ``amdgpu9.0a`` dGPU - sramecc - Absolute - *rocm-amdhsa* - AMD Instinct MI210 Accelerator
+ - tgsplit flat - *rocm-amdhsa* - AMD Instinct MI250 Accelerator
+ - xnack scratch - *rocm-amdhsa* - AMD Instinct MI250X Accelerator
+ - kernarg
+ preload - Packed
+ (except work-item
+ MI210) IDs
+
+
+ ``gfx90c`` ``amdgpu9.0c`` APU - xnack - Absolute - *pal-amdpal* - Ryzen 7 4700G
+ flat - Ryzen 7 4700GE
+ scratch - Ryzen 5 4600G
+ - Ryzen 5 4600GE
+ - Ryzen 3 4300G
+ - Ryzen 3 4300GE
+ - Ryzen Pro 4000G
+ - Ryzen 7 Pro 4700G
+ - Ryzen 7 Pro 4750GE
+ - Ryzen 5 Pro 4650G
+ - Ryzen 5 Pro 4650GE
+ - Ryzen 3 Pro 4350G
+ - Ryzen 3 Pro 4350GE
+
+ ``gfx942`` ``amdgpu9.42`` dGPU - sramecc - Architected - AMD Instinct MI300X
+ - tgsplit flat - AMD Instinct MI300A
+ - xnack scratch
+ - kernarg - Packed
+ preload work-item
+ IDs
+
+ ``gfx950`` ``amdgpu9.50`` dGPU - sramecc - Architected *TBA*
+ - tgsplit flat
+ - xnack scratch .. TODO::
+ - kernarg - Packed
+ preload work-item Add product
+ IDs names.
**GCN GFX10.1 (RDNA 1)** [AMD-GCN-GFX10-RDNA1]_
- -----------------------------------------------------------------------------------------------------------------------
- ``gfx1010`` ``amdgcn`` dGPU - cumode - Absolute - *rocm-amdhsa* - Radeon Pro 5600 XT
- - wavefrontsize64 flat - *pal-amdhsa* - Radeon RX 5600M
- - xnack scratch - *pal-amdpal* - Radeon RX 5700
- - Radeon RX 5700 XT
- ``gfx1011`` ``amdgcn`` dGPU - cumode - *rocm-amdhsa* - Radeon Pro V520
- - wavefrontsize64 - Absolute - *pal-amdhsa* - Radeon Pro 5600M
- - xnack flat - *pal-amdpal*
- scratch
- ``gfx1012`` ``amdgcn`` dGPU - cumode - Absolute - *rocm-amdhsa* - Radeon RX 5500
- - wavefrontsize64 flat - *pal-amdhsa* - Radeon RX 5500 XT
- - xnack scratch - *pal-amdpal*
- ``gfx1013`` ``amdgcn`` APU - cumode - Absolute - *rocm-amdhsa* *TBA*
- - wavefrontsize64 flat - *pal-amdhsa*
- - xnack scratch - *pal-amdpal* .. TODO::
-
- Add product
- names.
+ --------------------------------------------------------------------------------------------------------------------------
+ ``gfx1010`` ``amdgpu10.10`` dGPU - cumode - Absolute - *rocm-amdhsa* - Radeon Pro 5600 XT
+ - wavefrontsize64 flat - *pal-amdhsa* - Radeon RX 5600M
+ - xnack scratch - *pal-amdpal* - Radeon RX 5700
+ - Radeon RX 5700 XT
+ ``gfx1011`` ``amdgpu10.11`` dGPU - cumode - *rocm-amdhsa* - Radeon Pro V520
+ - wavefrontsize64 - Absolute - *pal-amdhsa* - Radeon Pro 5600M
+ - xnack flat - *pal-amdpal*
+ scratch
+ ``gfx1012`` ``amdgpu10.12`` dGPU - cumode - Absolute - *rocm-amdhsa* - Radeon RX 5500
+ - wavefrontsize64 flat - *pal-amdhsa* - Radeon RX 5500 XT
+ - xnack scratch - *pal-amdpal*
+ ``gfx1013`` ``amdgpu10.13`` APU - cumode - Absolute - *rocm-amdhsa* *TBA*
+ - wavefrontsize64 flat - *pal-amdhsa*
+ - xnack scratch - *pal-amdpal* . TODO::
+
+ Add product
+ names.
**GCN GFX10.3 (RDNA 2)** [AMD-GCN-GFX10-RDNA2]_
- -----------------------------------------------------------------------------------------------------------------------
- ``gfx1030`` ``amdgcn`` dGPU - cumode - Absolute - *rocm-amdhsa* - Radeon RX 6800
- - wavefrontsize64 flat - *pal-amdhsa* - Radeon RX 6800 XT
- scratch - *pal-amdpal* - Radeon RX 6900 XT
- - Radeon PRO W6800
- - Radeon PRO V620
- ``gfx1031`` ``amdgcn`` dGPU - cumode - Absolute - *rocm-amdhsa* - Radeon RX 6700 XT
- - wavefrontsize64 flat - *pal-amdhsa*
- scratch - *pal-amdpal*
- ``gfx1032`` ``amdgcn`` dGPU - cumode - Absolute - *rocm-amdhsa* *TBA*
- - wavefrontsize64 flat - *pal-amdhsa*
- scratch - *pal-amdpal* .. TODO::
-
- Add product
- names.
-
- ``gfx1033`` ``amdgcn`` APU - cumode - Absolute - *pal-amdpal* *TBA*
- - wavefrontsize64 flat
- scratch .. TODO::
-
- Add product
- names.
- ``gfx1034`` ``amdgcn`` dGPU - cumode - Absolute - *pal-amdpal* *TBA*
- - wavefrontsize64 flat
- scratch .. TODO::
-
- Add product
- names.
-
- ``gfx1035`` ``amdgcn`` APU - cumode - Absolute - *pal-amdpal* *TBA*
- - wavefrontsize64 flat
- scratch .. TODO::
- Add product
- names.
-
- ``gfx1036`` ``amdgcn`` APU - cumode - Absolute - *pal-amdpal* *TBA*
- - wavefrontsize64 flat
- scratch .. TODO::
-
- Add product
- names.
+ --------------------------------------------------------------------------------------------------------------------------
+ ``gfx1030`` ``amdgpu10.30`` dGPU - cumode - Absolute - *rocm-amdhsa* - Radeon RX 6800
+ - wavefrontsize64 flat - *pal-amdhsa* - Radeon RX 6800 XT
+ scratch - *pal-amdpal* - Radeon RX 6900 XT
+ - Radeon PRO W6800
+ - Radeon PRO V620
+ ``gfx1031`` ``amdgpu10.31`` dGPU - cumode - Absolute - *rocm-amdhsa* - Radeon RX 6700 XT
+ - wavefrontsize64 flat - *pal-amdhsa*
+ scratch - *pal-amdpal*
+ ``gfx1032`` ``amdgpu10.32`` dGPU - cumode - Absolute - *rocm-amdhsa* *TBA*
+ - wavefrontsize64 flat - *pal-amdhsa*
+ scratch - *pal-amdpal* .. TODO::
+
+ Add product
+ names.
+
+ ``gfx1033`` ``amdgpu10.33`` APU - cumode - Absolute - *pal-amdpal* *TBA*
+ - wavefrontsize64 flat
+ scratch . TODO::
+
+ Add product
+ names.
+ ``gfx1034`` ``amdgpu10.34`` dGPU - cumode - Absolute - *pal-amdpal* *TBA*
+ - wavefrontsize64 flat
+ scratch .. TODO::
+
+ Add product
+ names.
+
+ ``gfx1035`` ``amdgpu10.35`` APU - cumode - Absolute - *pal-amdpal* *TBA*
+ - wavefrontsize64 flat
+ scratch .. TODO::
+ Add product
+ names.
+
+ ``gfx1036`` ``amdgpu10.36`` APU - cumode - Absolute - *pal-amdpal* *TBA*
+ - wavefrontsize64 flat
+ scratch .. TODO::
+
+ Add product
+ names.
**GCN GFX11 (RDNA 3)** [AMD-GCN-GFX11-RDNA3]_
- -----------------------------------------------------------------------------------------------------------------------
- ``gfx1100`` ``amdgcn`` dGPU - cumode - Architected - *pal-amdpal* - Radeon PRO W7900 Dual Slot
- - wavefrontsize64 flat - Radeon PRO W7900
- scratch - Radeon PRO W7800
- - Packed - Radeon RX 7900 XTX
- work-item - Radeon RX 7900 XT
- IDs - Radeon RX 7900 GRE
-
- ``gfx1101`` ``amdgcn`` dGPU - cumode - Architected - Radeon RX 7800 XT
- - wavefrontsize64 flat - Radeon RX 7700 XT
- scratch - Radeon RX 7700
- - Packed
- work-item
- IDs
-
- ``gfx1102`` ``amdgcn`` dGPU - cumode - Architected - Radeon RX 7600 XT
- - wavefrontsize64 flat - Radeon RX 7600
- scratch
- - Packed
- work-item
- IDs
-
- ``gfx1103`` ``amdgcn`` APU - cumode - Architected *TBA*
- - wavefrontsize64 flat
- scratch .. TODO::
- - Packed
- work-item Add product
- IDs names.
+ --------------------------------------------------------------------------------------------------------------------------
+ ``gfx1100`` ``amdgpu11.00`` dGPU - cumode - Architected - *pal-amdpal* - Radeon PRO W7900 Dual Slot
+ - wavefrontsize64 flat - Radeon PRO W7900
+ scratch - Radeon PRO W7800
+ - Packed - Radeon RX 7900 XTX
+ work-item - Radeon RX 7900 XT
+ IDs - Radeon RX 7900 GRE
+
+ ``gfx1101`` ``amdgpu11.01`` dGPU - cumode - Architected - Radeon RX 7800 XT
+ - wavefrontsize64 flat - Radeon RX 7700 XT
+ scratch - Radeon RX 7700
+ - Packed
+ work-item
+ IDs
+
+ ``gfx1102`` ``amdgpu11.02`` dGPU - cumode - Architected - Radeon RX 7600 XT
+ - wavefrontsize64 flat - Radeon RX 7600
+ scratch
+ - Packed
+ work-item
+ IDs
+
+ ``gfx1103`` ``amdgpu11.03`` APU - cumode - Architected *TBA*
+ - wavefrontsize64 flat
+ scratch .. TODO::
+ - Packed
+ work-item Add product
+ IDs names.
**GCN GFX11.5 (RDNA 3.5)** [AMD-GCN-GFX11-RDNA3.5]_
- -----------------------------------------------------------------------------------------------------------------------
- ``gfx1150`` ``amdgcn`` APU - cumode - Architected Radeon 890M
- - wavefrontsize64 flat
- scratch .. TODO::
- - Packed
- work-item Add product
- IDs names.
-
- ``gfx1151`` ``amdgcn`` APU - cumode - Architected Radeon 8060S
- - wavefrontsize64 flat
- scratch .. TODO::
- - Packed
- work-item Add product
- IDs names.
-
- ``gfx1152`` ``amdgcn`` APU - cumode - Architected Radeon 860M
- - wavefrontsize64 flat
- scratch .. TODO::
- - Packed
- work-item Add product
- IDs names.
-
- ``gfx1153`` ``amdgcn`` APU - cumode - Architected *TBA*
- - wavefrontsize64 flat
- scratch .. TODO::
- - Packed
- work-item Add product
- IDs names.
-
- ``gfx1154`` ``amdgcn`` APU - cumode - Architected *TBA*
+ --------------------------------------------------------------------------------------------------------------------------
+ ``gfx1150`` ``amdgpu11.50`` APU - cumode - Architected Radeon 890M
+ - wavefrontsize64 flat
+ scratch .. TODO::
+ - Packed
+ work-item Add product
+ IDs names.
+
+ ``gfx1151`` ``amdgpu11.51`` APU - cumode - Architected Radeon 8060S
+ - wavefrontsize64 flat
+ scratch .. TODO::
+ - Packed
+ work-item Add product
+ IDs names.
+
+ ``gfx1152`` ``amdgpu11.52`` APU - cumode - Architected Radeon 860M
+ - wavefrontsize64 flat
+ scratch .. TODO::
+ - Packed
+ work-item Add product
+ IDs names.
+
+ ``gfx1153`` ``amdgpu11.53`` APU - cumode - Architected *TBA*
+ - wavefrontsize64 flat
+ scratch .. TODO::
+ - Packed
+ work-item Add product
+ IDs names.
+
+ ``gfx1154`` ``amdgpu11.54`` APU - cumode - Architected *TBA*
- wavefrontsize64 flat
scratch .. TODO::
- Packed
@@ -528,83 +640,85 @@ Every processor supports every OS ABI (see :ref:`amdgpu-os`) with the following
IDs names.
**GCN GFX11.7 (RDNA 4m)**
- -----------------------------------------------------------------------------------------------------------------------
- ``gfx1170`` ``amdgcn`` APU - cumode - Architected *TBA*
- - wavefrontsize64 flat
- scratch .. TODO::
- - Packed
- work-item Add product
- IDs names.
-
- ``gfx1171`` ``amdgcn`` APU - cumode - Architected *TBA*
- - wavefrontsize64 flat
- scratch .. TODO::
- - Packed
- work-item Add product
- IDs names.
-
- ``gfx1172`` ``amdgcn`` APU - cumode - Architected *TBA*
- - wavefrontsize64 flat
- scratch .. TODO::
- - Packed
- work-item Add product
- IDs names.
+ --------------------------------------------------------------------------------------------------------------------------
+ ``gfx1170`` ``amdgpu11.70`` APU - cumode - Architected *TBA*
+ - wavefrontsize64 flat
+ scratch .. TODO::
+ - Packed
+ work-item Add product
+ IDs names.
+
+ ``gfx1171`` ``amdgpu11.71`` APU - cumode - Architected *TBA*
+ - wavefrontsize64 flat
+ scratch .. TODO::
+ - Packed
+ work-item Add product
+ IDs names.
+
+ ``gfx1172`` ``amdgpu11.72`` APU - cumode - Architected *TBA*
+ - wavefrontsize64 flat
+ scratch .. TODO::
+ - Packed
+ work-item Add product
+ IDs names.
**GCN GFX12 (RDNA 4)** [AMD-GCN-GFX12-RDNA4]_
- -----------------------------------------------------------------------------------------------------------------------
- ``gfx1200`` ``amdgcn`` dGPU - cumode - Architected - Radeon RX 9060
- - wavefrontsize64 flat - Radeon RX 9060 XT
- scratch
- - Packed
- work-item
- IDs
-
- ``gfx1201`` ``amdgcn`` dGPU - cumode - Architected - Radeon RX 9070
- - wavefrontsize64 flat - Radeon RX 9070 XT
- scratch - Radeon RX 9070 GRE
- - Packed
- work-item
- IDs
-
- ``gfx1250`` ``amdgcn`` APU - Architected *TBA*
- flat
- scratch .. TODO::
- - Packed
- work-item Add product
- IDs names.
- - Globally
- Accessible
- Scratch
- - Workgroup
- Clusters
-
- ``gfx1251`` ``amdgcn`` APU - Architected *TBA*
- flat
- scratch .. TODO::
- - Packed
- work-item Add product
- IDs names.
- - Globally
- Accessible
- Scratch
- - Workgroup
- Clusters
+ --------------------------------------------------------------------------------------------------------------------------
+ ``gfx1200`` ``amdgpu12.00`` dGPU - cumode - Architected - Radeon RX 9060
+ - wavefrontsize64 flat - Radeon RX 9060 XT
+ scratch
+ - Packed
+ work-item
+ IDs
+
+ ``gfx1201`` ``amdgpu12.01`` dGPU - cumode - Architected - Radeon RX 9070
+ - wavefrontsize64 flat - Radeon RX 9070 XT
+ scratch - Radeon RX 9070 GRE
+ - Packed
+ work-item
+ IDs
+
+ ``gfx1250`` ``amdgpu12.50`` APU - Architected *TBA*
+ flat
+ scratch .. TODO::
+ - Packed
+ work-item Add product
+ IDs names.
+ - Globally
+ Accessible
+ Scratch
+ - Workgroup
+ Clusters
+
+ ``gfx1251`` ``amdgpu12.51`` APU - Architected *TBA*
+ flat
+ scratch .. TODO::
+ - Packed
+ work-item Add product
+ IDs names.
+ - Globally
+ Accessible
+ Scratch
+ - Workgroup
+ Clusters
**GCN GFX13 (RDNA 5)**
- -----------------------------------------------------------------------------------------------------------------------
- ``gfx1310`` ``amdgcn`` dGPU - cumode - Architected *TBA*
- - wavefrontsize64 flat
- scratch .. TODO::
- - Packed
- work-item Add product
- IDs names.
+ --------------------------------------------------------------------------------------------------------------------------
+ ``gfx1310`` ``amdgpu13.10`` dGPU - cumode - Architected *TBA*
+ - wavefrontsize64 flat
+ scratch .. TODO::
+ - Packed
+ work-item Add product
+ IDs names.
- =========== =============== ============ ===== ================= =============== =============== ======================
+ =========== =============== =============== ===== ================= =============== =============== ======================
Generic processors allow execution of a single code object on any of the processors that
-it supports. Such code objects may not perform as well as those for the non-generic processors.
+it supports. Such code objects may not perform as well as those for
+the non-generic processors.
-Generic processors are only available on code object V6 and above (see :ref:`amdgpu-elf-code-object`).
+Generic processors are only available on code object V6 and above (see
+:ref:`amdgpu-elf-code-object`).
Generic processor code objects are versioned. See :ref:`amdgpu-generic-processor-versioning` for more information on how versioning works.
@@ -617,7 +731,7 @@ Generic processor code objects are versioned. See :ref:`amdgpu-generic-processor
Architecture
==================== ============== ================= ================== ================= =================================
- ``gfx9-generic`` ``amdgcn`` - ``gfx900`` - xnack - Absolute flat - ``v_mad_mix`` instructions
+ ``gfx9-generic`` ``amdgpu9`` - ``gfx900`` - xnack - Absolute flat - ``v_mad_mix`` instructions
- ``gfx902`` scratch are not available on
- ``gfx904`` ``gfx900``, ``gfx902``,
- ``gfx906`` ``gfx909``, ``gfx90c``
@@ -639,13 +753,13 @@ Generic processor code objects are versioned. See :ref:`amdgpu-generic-processor
- ``v_dot2_f32_f16``
- ``gfx9-4-generic`` ``amdgcn`` - ``gfx942`` - sramecc - Architected FP8 and BF8 instructions,
+ ``gfx9-4-generic`` ``amdgpu9.4`` - ``gfx942`` - sramecc - Architected FP8 and BF8 instructions,
- ``gfx950`` - tgsplit flat scratch FP8 and BF8 conversion
- xnack - Packed instructions, as well as
- kernarg preload work-item instructions with XF32 format
IDs support are not available.
- ``gfx10-1-generic`` ``amdgcn`` - ``gfx1010`` - xnack - Absolute flat - The following instructions are
+ ``gfx10-1-generic`` ``amdgpu10.1`` - ``gfx1010`` - xnack - Absolute flat - The following instructions are
- ``gfx1011`` - wavefrontsize64 scratch not available on ``gfx1011``
- ``gfx1012`` - cumode and ``gfx1012``
- ``gfx1013``
@@ -664,7 +778,7 @@ Generic processor code objects are versioned. See :ref:`amdgpu-generic-processor
``gfx1013``
- ``gfx10-3-generic`` ``amdgcn`` - ``gfx1030`` - wavefrontsize64 - Absolute flat No restrictions.
+ ``gfx10-3-generic`` ``amdgpu10.3`` - ``gfx1030`` - wavefrontsize64 - Absolute flat No restrictions.
- ``gfx1031`` - cumode scratch
- ``gfx1032``
- ``gfx1033``
@@ -673,7 +787,7 @@ Generic processor code objects are versioned. See :ref:`amdgpu-generic-processor
- ``gfx1036``
- ``gfx11-generic`` ``amdgcn`` - ``gfx1100`` - wavefrontsize64 - Architected Various codegen pessimizations
+ ``gfx11-generic`` ``amdgpu11`` - ``gfx1100`` - wavefrontsize64 - Architected Various codegen pessimizations
- ``gfx1101`` - cumode flat scratch are applied to work around some
- ``gfx1102`` - Packed hazards specific to some targets
- ``gfx1103`` work-item within this family.
@@ -701,25 +815,25 @@ Generic processor code objects are versioned. See :ref:`amdgpu-generic-processor
- ``gfx1103``
- ``gfx11-7-generic`` ``amdgcn`` - ``gfx1170`` - wavefrontsize64 - Architected No restrictions.
+ ``gfx11-7-generic`` ``amdgpu11.7`` - ``gfx1170`` - wavefrontsize64 - Architected No restrictions.
- ``gfx1171`` - cumode flat scratch
- ``gfx1172`` - Packed
work-item
IDs
- ``gfx12-generic`` ``amdgcn`` - ``gfx1200`` - wavefrontsize64 - Architected No restrictions.
+ ``gfx12-generic`` ``amdgpu12`` - ``gfx1200`` - wavefrontsize64 - Architected No restrictions.
- ``gfx1201`` - cumode flat scratch
- Packed
work-item
IDs
- ``gfx12-5-generic`` ``amdgcn`` - ``gfx1250`` - Architected Functionally equivalent to
+ ``gfx12-5-generic`` ``amdgpu12.5`` - ``gfx1250`` - Architected Functionally equivalent to
- ``gfx1251`` flat scratch gfx1250.
- Packed
work-item
IDs
- ``gfx13-generic`` ``amdgcn`` - ``gfx1310`` - wavefrontsize64 - Architected No restrictions.
+ ``gfx13-generic`` ``amdgpu13`` - ``gfx1310`` - wavefrontsize64 - Architected No restrictions.
- cumode flat scratch
- Packed
work-item
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index d1448eb469614..e0c13b1756de0 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -191,6 +191,7 @@ Makes programs 10x faster by doing Special New Thing.
### Changes to the AMDGPU Backend
* Initial support for gfx1310
+
* The `"amdgpu-num-sgpr"` and `"amdgpu-num-vgpr"` IR function attributes
(generated by the Clang `amdgpu_num_sgpr` and `amdgpu_num_vgpr` attributes)
are now deprecated. Use `"amdgpu-waves-per-eu"` instead. The backend still
@@ -203,6 +204,8 @@ Makes programs 10x faster by doing Special New Thing.
must now set the corresponding module flag to `1` (relaxed). An absent flag is
treated as strict by the backend.
+* Changed triple naming system from "amdgcn" to "amdgpu" plus a subarch suffix.
+
### Changes to the ARM Backend
* The `r14` register can now be used as an alias for the link register `lr`
diff --git a/llvm/include/llvm/Object/ELFObjectFile.h b/llvm/include/llvm/Object/ELFObjectFile.h
index 297cb69176a2a..6d72741c3bde0 100644
--- a/llvm/include/llvm/Object/ELFObjectFile.h
+++ b/llvm/include/llvm/Object/ELFObjectFile.h
@@ -1424,7 +1424,7 @@ template <class ELFT> Triple::ArchType ELFObjectFile<ELFT>::getArch() const {
return Triple::r600;
if (MACH >= ELF::EF_AMDGPU_MACH_AMDGCN_FIRST &&
MACH <= ELF::EF_AMDGPU_MACH_AMDGCN_LAST)
- return Triple::amdgcn;
+ return Triple::amdgpu;
return Triple::UnknownArch;
}
diff --git a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.def b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
index 9e633e16b80dc..4b240a51a9a1f 100644
--- a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
+++ b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
@@ -49,7 +49,7 @@ R600_GPU ("turks", GK_TURKS, FEATURE_NONE)
#undef R600_GPU_ALIAS
#ifndef AMDGCN_GPU
-#define AMDGCN_GPU(NAME, ENUM, ISAVERSION, FEATURES)
+#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES)
#endif
#ifndef AMDGCN_GPU_ALIAS
@@ -57,76 +57,76 @@ R600_GPU ("turks", GK_TURKS, FEATURE_NONE)
#endif
// Don't bother listing the implicitly true features
-AMDGCN_GPU ("gfx600", GK_GFX600, ( 6, 0, 0), FEATURE_FAST_FMA_F32)
+AMDGCN_GPU ("gfx600", GK_GFX600, Triple::AMDGPUSubArch600, ( 6, 0, 0), FEATURE_FAST_FMA_F32)
AMDGCN_GPU_ALIAS("tahiti", GK_GFX600)
-AMDGCN_GPU ("gfx601", GK_GFX601, ( 6, 0, 1), FEATURE_NONE)
+AMDGCN_GPU ("gfx601", GK_GFX601, Triple::AMDGPUSubArch601, ( 6, 0, 1), FEATURE_NONE)
AMDGCN_GPU_ALIAS("pitcairn", GK_GFX601)
AMDGCN_GPU_ALIAS("verde", GK_GFX601)
-AMDGCN_GPU ("gfx602", GK_GFX602, ( 6, 0, 2), FEATURE_NONE)
+AMDGCN_GPU ("gfx602", GK_GFX602, Triple::AMDGPUSubArch602, ( 6, 0, 2), FEATURE_NONE)
AMDGCN_GPU_ALIAS("hainan", GK_GFX602)
AMDGCN_GPU_ALIAS("oland", GK_GFX602)
-AMDGCN_GPU ("gfx700", GK_GFX700, ( 7, 0, 0), FEATURE_NONE)
+AMDGCN_GPU ("gfx700", GK_GFX700, Triple::AMDGPUSubArch700, ( 7, 0, 0), FEATURE_NONE)
AMDGCN_GPU_ALIAS("kaveri", GK_GFX700)
-AMDGCN_GPU ("gfx701", GK_GFX701, ( 7, 0, 1), FEATURE_FAST_FMA_F32)
+AMDGCN_GPU ("gfx701", GK_GFX701, Triple::AMDGPUSubArch701, ( 7, 0, 1), FEATURE_FAST_FMA_F32)
AMDGCN_GPU_ALIAS("hawaii", GK_GFX701)
-AMDGCN_GPU ("gfx702", GK_GFX702, ( 7, 0, 2), FEATURE_FAST_FMA_F32)
-AMDGCN_GPU ("gfx703", GK_GFX703, ( 7, 0, 3), FEATURE_NONE)
+AMDGCN_GPU ("gfx702", GK_GFX702, Triple::AMDGPUSubArch702, ( 7, 0, 2), FEATURE_FAST_FMA_F32)
+AMDGCN_GPU ("gfx703", GK_GFX703, Triple::AMDGPUSubArch703, ( 7, 0, 3), FEATURE_NONE)
AMDGCN_GPU_ALIAS("kabini", GK_GFX703)
AMDGCN_GPU_ALIAS("mullins", GK_GFX703)
-AMDGCN_GPU ("gfx704", GK_GFX704, ( 7, 0, 4), FEATURE_NONE)
+AMDGCN_GPU ("gfx704", GK_GFX704, Triple::AMDGPUSubArch704, ( 7, 0, 4), FEATURE_NONE)
AMDGCN_GPU_ALIAS("bonaire", GK_GFX704)
-AMDGCN_GPU ("gfx705", GK_GFX705, ( 7, 0, 5), FEATURE_NONE)
-AMDGCN_GPU ("gfx801", GK_GFX801, ( 8, 0, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES)
+AMDGCN_GPU ("gfx705", GK_GFX705, Triple::AMDGPUSubArch705, ( 7, 0, 5), FEATURE_NONE)
+AMDGCN_GPU ("gfx801", GK_GFX801, Triple::AMDGPUSubArch801, ( 8, 0, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES)
AMDGCN_GPU_ALIAS("carrizo", GK_GFX801)
-AMDGCN_GPU ("gfx802", GK_GFX802, ( 8, 0, 2), FEATURE_FAST_DENORMAL_F32)
+AMDGCN_GPU ("gfx802", GK_GFX802, Triple::AMDGPUSubArch802, ( 8, 0, 2), FEATURE_FAST_DENORMAL_F32)
AMDGCN_GPU_ALIAS("iceland", GK_GFX802)
AMDGCN_GPU_ALIAS("tonga", GK_GFX802)
-AMDGCN_GPU ("gfx803", GK_GFX803, ( 8, 0, 3), FEATURE_FAST_DENORMAL_F32)
+AMDGCN_GPU ("gfx803", GK_GFX803, Triple::AMDGPUSubArch803, ( 8, 0, 3), FEATURE_FAST_DENORMAL_F32)
AMDGCN_GPU_ALIAS("fiji", GK_GFX803)
AMDGCN_GPU_ALIAS("polaris10", GK_GFX803)
AMDGCN_GPU_ALIAS("polaris11", GK_GFX803)
-AMDGCN_GPU ("gfx805", GK_GFX805, ( 8, 0, 5), FEATURE_FAST_DENORMAL_F32)
+AMDGCN_GPU ("gfx805", GK_GFX805, Triple::AMDGPUSubArch805, ( 8, 0, 5), FEATURE_FAST_DENORMAL_F32)
AMDGCN_GPU_ALIAS("tongapro", GK_GFX805)
-AMDGCN_GPU ("gfx810", GK_GFX810, ( 8, 1, 0), FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES)
+AMDGCN_GPU ("gfx810", GK_GFX810, Triple::AMDGPUSubArch810, ( 8, 1, 0), FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES)
AMDGCN_GPU_ALIAS("stoney", GK_GFX810)
-AMDGCN_GPU ("gfx900", GK_GFX900, ( 9, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES)
-AMDGCN_GPU ("gfx902", GK_GFX902, ( 9, 0, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES)
-AMDGCN_GPU ("gfx904", GK_GFX904, ( 9, 0, 4), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES)
-AMDGCN_GPU ("gfx906", GK_GFX906, ( 9, 0, 6), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC)
-AMDGCN_GPU ("gfx908", GK_GFX908, ( 9, 0, 8), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC)
-AMDGCN_GPU ("gfx909", GK_GFX909, ( 9, 0, 9), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES)
-AMDGCN_GPU ("gfx90a", GK_GFX90A, ( 9, 0, 10), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC)
-AMDGCN_GPU ("gfx90c", GK_GFX90C, ( 9, 0, 12), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES)
-AMDGCN_GPU ("gfx942", GK_GFX942, ( 9, 4, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC)
-AMDGCN_GPU ("gfx950", GK_GFX950, ( 9, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC)
-AMDGCN_GPU ("gfx1010", GK_GFX1010, (10, 1, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_WGP)
-AMDGCN_GPU ("gfx1011", GK_GFX1011, (10, 1, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_WGP)
-AMDGCN_GPU ("gfx1012", GK_GFX1012, (10, 1, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_WGP)
-AMDGCN_GPU ("gfx1013", GK_GFX1013, (10, 1, 3), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_WGP)
-AMDGCN_GPU ("gfx1030", GK_GFX1030, (10, 3, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1031", GK_GFX1031, (10, 3, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1032", GK_GFX1032, (10, 3, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1033", GK_GFX1033, (10, 3, 3), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1034", GK_GFX1034, (10, 3, 4), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1035", GK_GFX1035, (10, 3, 5), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1036", GK_GFX1036, (10, 3, 6), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1100", GK_GFX1100, (11, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1101", GK_GFX1101, (11, 0, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1102", GK_GFX1102, (11, 0, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1103", GK_GFX1103, (11, 0, 3), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1150", GK_GFX1150, (11, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1151", GK_GFX1151, (11, 5, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1152", GK_GFX1152, (11, 5, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1153", GK_GFX1153, (11, 5, 3), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1154", GK_GFX1154, (11, 5, 4), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1170", GK_GFX1170, (11, 7, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1171", GK_GFX1171, (11, 7, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1172", GK_GFX1172, (11, 7, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1200", GK_GFX1200, (12, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1201", GK_GFX1201, (12, 0, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1250", GK_GFX1250, (12, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_SRAMECC)
-AMDGCN_GPU ("gfx1251", GK_GFX1251, (12, 5, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_SRAMECC)
-AMDGCN_GPU ("gfx1310", GK_GFX1310, (13, 1, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx900", GK_GFX900, Triple::AMDGPUSubArch900, ( 9, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES)
+AMDGCN_GPU ("gfx902", GK_GFX902, Triple::AMDGPUSubArch902, ( 9, 0, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES)
+AMDGCN_GPU ("gfx904", GK_GFX904, Triple::AMDGPUSubArch904, ( 9, 0, 4), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES)
+AMDGCN_GPU ("gfx906", GK_GFX906, Triple::AMDGPUSubArch906, ( 9, 0, 6), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC)
+AMDGCN_GPU ("gfx908", GK_GFX908, Triple::AMDGPUSubArch908, ( 9, 0, 8), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC)
+AMDGCN_GPU ("gfx909", GK_GFX909, Triple::AMDGPUSubArch909, ( 9, 0, 9), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES)
+AMDGCN_GPU ("gfx90a", GK_GFX90A, Triple::AMDGPUSubArch90A, ( 9, 0, 10), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC)
+AMDGCN_GPU ("gfx90c", GK_GFX90C, Triple::AMDGPUSubArch90C, ( 9, 0, 12), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES)
+AMDGCN_GPU ("gfx942", GK_GFX942, Triple::AMDGPUSubArch942, ( 9, 4, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC)
+AMDGCN_GPU ("gfx950", GK_GFX950, Triple::AMDGPUSubArch950, ( 9, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC)
+AMDGCN_GPU ("gfx1010", GK_GFX1010, Triple::AMDGPUSubArch1010, (10, 1, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_WGP)
+AMDGCN_GPU ("gfx1011", GK_GFX1011, Triple::AMDGPUSubArch1011, (10, 1, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_WGP)
+AMDGCN_GPU ("gfx1012", GK_GFX1012, Triple::AMDGPUSubArch1012, (10, 1, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_WGP)
+AMDGCN_GPU ("gfx1013", GK_GFX1013, Triple::AMDGPUSubArch1013, (10, 1, 3), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_WGP)
+AMDGCN_GPU ("gfx1030", GK_GFX1030, Triple::AMDGPUSubArch1030, (10, 3, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1031", GK_GFX1031, Triple::AMDGPUSubArch1031, (10, 3, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1032", GK_GFX1032, Triple::AMDGPUSubArch1032, (10, 3, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1033", GK_GFX1033, Triple::AMDGPUSubArch1033, (10, 3, 3), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1034", GK_GFX1034, Triple::AMDGPUSubArch1034, (10, 3, 4), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1035", GK_GFX1035, Triple::AMDGPUSubArch1035, (10, 3, 5), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1036", GK_GFX1036, Triple::AMDGPUSubArch1036, (10, 3, 6), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1100", GK_GFX1100, Triple::AMDGPUSubArch1100, (11, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1101", GK_GFX1101, Triple::AMDGPUSubArch1101, (11, 0, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1102", GK_GFX1102, Triple::AMDGPUSubArch1102, (11, 0, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1103", GK_GFX1103, Triple::AMDGPUSubArch1103, (11, 0, 3), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1150", GK_GFX1150, Triple::AMDGPUSubArch1150, (11, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1151", GK_GFX1151, Triple::AMDGPUSubArch1151, (11, 5, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1152", GK_GFX1152, Triple::AMDGPUSubArch1152, (11, 5, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1153", GK_GFX1153, Triple::AMDGPUSubArch1153, (11, 5, 3), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1154", GK_GFX1154, Triple::AMDGPUSubArch1154, (11, 5, 4), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1170", GK_GFX1170, Triple::AMDGPUSubArch1170, (11, 7, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1171", GK_GFX1171, Triple::AMDGPUSubArch1171, (11, 7, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1172", GK_GFX1172, Triple::AMDGPUSubArch1172, (11, 7, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1200", GK_GFX1200, Triple::AMDGPUSubArch1200, (12, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1201", GK_GFX1201, Triple::AMDGPUSubArch1201, (12, 0, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1250", GK_GFX1250, Triple::AMDGPUSubArch1250, (12, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_SRAMECC)
+AMDGCN_GPU ("gfx1251", GK_GFX1251, Triple::AMDGPUSubArch1251, (12, 5, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_SRAMECC)
+AMDGCN_GPU ("gfx1310", GK_GFX1310, Triple::AMDGPUSubArch1310, (13, 1, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
// Generic targets return the lowest common denominator
// within their family. That is, the ISA that is the most
@@ -141,15 +141,15 @@ AMDGCN_GPU ("gfx1310", GK_GFX1310, (13, 1, 0), FEATURE_FAST_FMA_F32|FEAT
//
// TODO: Split up this API depending on its caller so
// generic target handling is more obvious and less risky.
-AMDGCN_GPU ("gfx9-generic", GK_GFX9_GENERIC, ( 9, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES)
-AMDGCN_GPU ("gfx9-4-generic", GK_GFX9_4_GENERIC, ( 9, 4, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC)
-AMDGCN_GPU ("gfx10-1-generic", GK_GFX10_1_GENERIC, (10, 1, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_WGP)
-AMDGCN_GPU ("gfx10-3-generic", GK_GFX10_3_GENERIC, (10, 3, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx11-generic", GK_GFX11_GENERIC, (11, 0, 3), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx11-7-generic", GK_GFX11_7_GENERIC, (11, 7, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx12-generic", GK_GFX12_GENERIC, (12, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx12-5-generic", GK_GFX12_5_GENERIC, (12, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK)
-AMDGCN_GPU ("gfx13-generic", GK_GFX13_GENERIC, (13, 1, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx9-generic", GK_GFX9_GENERIC, Triple::AMDGPUSubArch9, ( 9, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES)
+AMDGCN_GPU ("gfx9-4-generic", GK_GFX9_4_GENERIC, Triple::AMDGPUSubArch9_4, ( 9, 4, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC)
+AMDGCN_GPU ("gfx10-1-generic", GK_GFX10_1_GENERIC, Triple::AMDGPUSubArch10_1, (10, 1, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_WGP)
+AMDGCN_GPU ("gfx10-3-generic", GK_GFX10_3_GENERIC, Triple::AMDGPUSubArch10_3, (10, 3, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx11-generic", GK_GFX11_GENERIC, Triple::AMDGPUSubArch11, (11, 0, 3), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx11-7-generic", GK_GFX11_7_GENERIC, Triple::AMDGPUSubArch11_7, (11, 7, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx12-generic", GK_GFX12_GENERIC, Triple::AMDGPUSubArch12, (12, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx12-5-generic", GK_GFX12_5_GENERIC, Triple::AMDGPUSubArch12_5, (12, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK)
+AMDGCN_GPU ("gfx13-generic", GK_GFX13_GENERIC, Triple::AMDGPUSubArch13, (13, 1, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
#undef AMDGCN_GPU
#undef AMDGCN_GPU_ALIAS
diff --git a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
index ba447dd346d80..8496b1b483cde 100644
--- a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+++ b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
@@ -16,6 +16,7 @@
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/Support/Compiler.h"
+#include "llvm/TargetParser/Triple.h"
#include <cstdint>
#include <optional>
#include <string>
@@ -35,7 +36,7 @@ enum GPUKind : uint32_t {
GK_NONE = 0,
#define R600_GPU(NAME, ENUM, FEATURES) ENUM,
-#define AMDGCN_GPU(NAME, ENUM, ISAVERSION, FEATURES) ENUM,
+#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) ENUM,
#include "AMDGPUTargetParser.def"
GK_AMDGCN_GENERIC_FIRST = GK_GFX9_GENERIC,
@@ -47,6 +48,11 @@ struct IsaVersion {
unsigned Major;
unsigned Minor;
unsigned Stepping;
+
+ bool operator==(const IsaVersion &Other) const {
+ return Major == Other.Major && Minor == Other.Minor &&
+ Stepping == Other.Stepping;
+ }
};
// This isn't comprehensive for now, just things that are needed from the
@@ -86,19 +92,59 @@ enum FeatureError : uint32_t {
};
LLVM_ABI StringRef getArchFamilyNameAMDGCN(GPUKind AK);
+LLVM_ABI Triple::SubArchType getSubArch(GPUKind AK);
+LLVM_ABI Triple::SubArchType getMajorSubArch(Triple::SubArchType SubArch);
+LLVM_ABI bool isSubArchCompatible(const Triple &A, const Triple &B);
+
+/// Return true if subarch \p A is compatible with subarch \p B, i.e. they are
+/// equal or one is the major-family subarch of the other (e.g. AMDGPUSubArch9
+/// is compatible with AMDGPUSubArch900). NoSubArch is compatible with anything.
+LLVM_ABI bool isSubArchCompatible(Triple::SubArchType A, Triple::SubArchType B);
+
+/// Return true if the GPU \p AK is usable with the triple subarch \p SubArch.
+/// A NoSubArch triple (legacy "amdgcn") accepts any GPU. Otherwise the GPU's
+/// subarch must equal \p SubArch, or \p SubArch must be the major-family
+/// subarch of the GPU (e.g. the amdgpu9 triple accepts gfx900).
+LLVM_ABI bool isCPUValidForSubArch(Triple::SubArchType SubArch, GPUKind AK);
+
+/// Convenience overload of isCPUValidForSubArch taking a GPU name \p CPU, which
+/// is parsed via parseArchAMDGCN. An unrecognized name is never valid.
+LLVM_ABI bool isCPUValidForSubArch(Triple::SubArchType SubArch, StringRef CPU);
+
+/// Returns the effective triple appropriate to use when linking \p B into \p A
+/// by merging the subarches in case of inexact match.
+///
+/// In cases where isSubArchCompatible would return / false, returns \p B. This
+/// assumes that the non-arch triple components are the same
+LLVM_ABI std::string mergeSubArch(const Triple &A, const Triple &B);
LLVM_ABI StringRef getArchNameAMDGCN(GPUKind AK);
LLVM_ABI StringRef getArchNameR600(GPUKind AK);
+
+/// Returns the canonical GPU name for an AMDGPU subarch, e.g.
+/// AMDGPUSubArch1030 -> "gfx1030", AMDGPUSubArch9 -> "gfx9-generic",
+/// AMDGPUSubArch6 -> "gfx600". Returns "" for NoSubArch or a non-AMDGPU
+/// subarch. The major-only subarches map to their generic/lowest
+/// representative, matching the default subtarget for an unspecified -mcpu.
+LLVM_ABI StringRef getArchNameFromSubArch(Triple::SubArchType SubArch);
LLVM_ABI StringRef getCanonicalArchName(const Triple &T, StringRef Arch);
LLVM_ABI GPUKind parseArchAMDGCN(StringRef CPU);
LLVM_ABI GPUKind parseArchR600(StringRef CPU);
+LLVM_ABI GPUKind getGPUKindFromSubArch(Triple::SubArchType SubArch);
LLVM_ABI unsigned getArchAttrAMDGCN(GPUKind AK);
+LLVM_ABI unsigned getArchAttrAMDGCN(Triple::SubArchType SubArch);
LLVM_ABI unsigned getArchAttrR600(GPUKind AK);
-LLVM_ABI void fillValidArchListAMDGCN(SmallVectorImpl<StringRef> &Values);
+/// Append the valid AMDGCN GPU names to \p Values. If \p SubArch is not
+/// NoSubArch, only GPUs compatible with that subarch (see isCPUValidForSubArch)
+/// are appended.
+LLVM_ABI void
+fillValidArchListAMDGCN(SmallVectorImpl<StringRef> &Values,
+ Triple::SubArchType SubArch = Triple::NoSubArch);
LLVM_ABI void fillValidArchListR600(SmallVectorImpl<StringRef> &Values);
LLVM_ABI IsaVersion getIsaVersion(StringRef GPU);
+LLVM_ABI IsaVersion getIsaVersion(Triple::SubArchType SubArch);
/// Fills Features map with default values for given target GPU.
/// \p Features contains overriding target features and this function returns
diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h
index 852a410be03c0..4868d0223e357 100644
--- a/llvm/include/llvm/TargetParser/Triple.h
+++ b/llvm/include/llvm/TargetParser/Triple.h
@@ -74,7 +74,7 @@ class Triple {
ppc64, // PPC64: powerpc64, ppu
ppc64le, // PPC64LE: powerpc64le
r600, // R600: AMD GPUs HD2XXX - HD6XXX
- amdgcn, // AMDGCN: AMD GCN GPUs
+ amdgpu, // AMDGPU: AMD GCN+ GPUs
riscv32, // RISC-V (32-bit, little endian): riscv32
riscv64, // RISC-V (64-bit, little endian): riscv64
riscv32be, // RISC-V (32-bit, big endian): riscv32be
@@ -188,6 +188,90 @@ class Triple {
DXILSubArch_v1_8,
DXILSubArch_v1_9,
LatestDXILSubArch = DXILSubArch_v1_9,
+
+ // AMDGPU sub-arch
+ AMDGPUSubArch6,
+ AMDGPUSubArch600,
+ AMDGPUSubArch601,
+ AMDGPUSubArch602,
+
+ AMDGPUSubArch7,
+ AMDGPUSubArch700,
+ AMDGPUSubArch701,
+ AMDGPUSubArch702,
+ AMDGPUSubArch703,
+ AMDGPUSubArch704,
+ AMDGPUSubArch705,
+
+ AMDGPUSubArch8,
+ AMDGPUSubArch801,
+ AMDGPUSubArch802,
+ AMDGPUSubArch803,
+ AMDGPUSubArch805,
+
+ // 810 is its own major arch.
+ AMDGPUSubArch810,
+
+ AMDGPUSubArch9,
+ AMDGPUSubArch900,
+ AMDGPUSubArch902,
+ AMDGPUSubArch904,
+ AMDGPUSubArch906,
+ AMDGPUSubArch909,
+ AMDGPUSubArch90C,
+
+ // 908 and 90a are not covered by a generic target, and are their own major
+ // subarches.
+ AMDGPUSubArch908,
+ AMDGPUSubArch90A,
+
+ AMDGPUSubArch9_4,
+ AMDGPUSubArch942,
+ AMDGPUSubArch950,
+
+ AMDGPUSubArch10_1,
+ AMDGPUSubArch1010,
+ AMDGPUSubArch1011,
+ AMDGPUSubArch1012,
+ AMDGPUSubArch1013,
+
+ AMDGPUSubArch10_3,
+ AMDGPUSubArch1030,
+ AMDGPUSubArch1031,
+ AMDGPUSubArch1032,
+ AMDGPUSubArch1033,
+ AMDGPUSubArch1034,
+ AMDGPUSubArch1035,
+ AMDGPUSubArch1036,
+
+ AMDGPUSubArch11,
+ AMDGPUSubArch1100,
+ AMDGPUSubArch1101,
+ AMDGPUSubArch1102,
+ AMDGPUSubArch1103,
+ AMDGPUSubArch1150,
+ AMDGPUSubArch1151,
+ AMDGPUSubArch1152,
+ AMDGPUSubArch1153,
+ AMDGPUSubArch1154,
+
+ AMDGPUSubArch11_7,
+ AMDGPUSubArch1170,
+ AMDGPUSubArch1171,
+ AMDGPUSubArch1172,
+
+ AMDGPUSubArch12,
+ AMDGPUSubArch1200,
+ AMDGPUSubArch1201,
+
+ AMDGPUSubArch12_5,
+ AMDGPUSubArch1250,
+ AMDGPUSubArch1251,
+
+ AMDGPUSubArch13,
+ AMDGPUSubArch1310,
+ FirstAMDGPUSubArch = AMDGPUSubArch6,
+ LastAMDGPUSubArch = AMDGPUSubArch1310
};
enum VendorType {
UnknownVendor,
@@ -894,9 +978,9 @@ class Triple {
}
/// Tests whether the target is AMDGCN
- bool isAMDGCN() const { return getArch() == Triple::amdgcn; }
+ bool isAMDGCN() const { return getArch() == Triple::amdgpu; }
- bool isAMDGPU() const { return getArch() == Triple::r600 || isAMDGCN(); }
+ bool isAMDGPU() const { return isAMDGCN() || getArch() == Triple::r600; }
/// Tests whether the target is Thumb (little and big endian).
bool isThumb() const {
@@ -1329,6 +1413,11 @@ class Triple {
/// triple.
LLVM_ABI static ArchType parseArch(StringRef Str);
+ /// Parse the subarchitecture encoded in the first (architecture) field of the
+ /// triple (e.g. "amdgpu9.00" -> AMDGPUSubArch900). Returns NoSubArch if the
+ /// string does not encode a recognized subarchitecture.
+ LLVM_ABI static SubArchType parseSubArch(StringRef Str);
+
/// @}
/// Returns a canonicalized OS version number for the specified OS.
diff --git a/llvm/lib/Frontend/OpenMP/OMPContext.cpp b/llvm/lib/Frontend/OpenMP/OMPContext.cpp
index 7443c4c338ada..f2cdd9bbaf5e4 100644
--- a/llvm/lib/Frontend/OpenMP/OMPContext.cpp
+++ b/llvm/lib/Frontend/OpenMP/OMPContext.cpp
@@ -49,7 +49,7 @@ OMPContext::OMPContext(bool IsDeviceCompilation, Triple TargetTriple,
case Triple::x86_64:
ActiveTraits.set(unsigned(TraitProperty::target_device_kind_cpu));
break;
- case Triple::amdgcn:
+ case Triple::amdgpu:
case Triple::nvptx:
case Triple::nvptx64:
case Triple::spirv64:
@@ -92,7 +92,7 @@ OMPContext::OMPContext(bool IsDeviceCompilation, Triple TargetTriple,
ActiveTraits.set(unsigned(TraitProperty::device_kind_cpu));
ActiveTraits.set(unsigned(TraitProperty::target_device_kind_cpu));
break;
- case Triple::amdgcn:
+ case Triple::amdgpu:
case Triple::nvptx:
case Triple::nvptx64:
case Triple::spirv64:
diff --git a/llvm/lib/Object/RelocationResolver.cpp b/llvm/lib/Object/RelocationResolver.cpp
index b64df07ae7a9b..f88bb17109d99 100644
--- a/llvm/lib/Object/RelocationResolver.cpp
+++ b/llvm/lib/Object/RelocationResolver.cpp
@@ -836,7 +836,7 @@ getRelocationResolver(const ObjectFile &Obj) {
return {supportsSystemZ, resolveSystemZ};
case Triple::sparcv9:
return {supportsSparc64, resolveSparc64};
- case Triple::amdgcn:
+ case Triple::amdgpu:
return {supportsAmdgpu, resolveAmdgpu};
case Triple::riscv64:
case Triple::riscv64be:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 53d45d97ab527..1fdb2c8559c8e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -94,6 +94,8 @@ LLVMInitializeAMDGPUAsmPrinter() {
llvm::createR600AsmPrinterPass);
TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
createAMDGPUAsmPrinterPass);
+ TargetRegistry::RegisterAsmPrinter(getTheGCNLegacyTarget(),
+ createAMDGPUAsmPrinterPass);
}
namespace {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 06bfc7e1a5162..ffc4249399071 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -102,6 +102,7 @@
#include "llvm/Passes/PassBuilder.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/FormatVariadic.h"
+#include "llvm/TargetParser/AMDGPUTargetParser.h"
#include "llvm/Transforms/HipStdPar/HipStdPar.h"
#include "llvm/Transforms/IPO.h"
#include "llvm/Transforms/IPO/AlwaysInliner.h"
@@ -645,6 +646,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
// Register the target
RegisterTargetMachine<R600TargetMachine> X(getTheR600Target());
RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
+ RegisterTargetMachine<GCNTargetMachine> YLegacy(getTheGCNLegacyTarget());
PassRegistry *PR = PassRegistry::getPassRegistry();
initializeR600ClauseMergePassPass(*PR);
@@ -847,6 +849,10 @@ static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
if (!GPU.empty())
return GPU;
+ if (StringRef Name = AMDGPU::getArchNameFromSubArch(TT.getSubArch());
+ !Name.empty())
+ return Name;
+
// Need to default to a target with flat support for HSA.
if (TT.isAMDGCN())
return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
@@ -873,6 +879,24 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
TLOF(createTLOF(getTargetTriple())) {
initAsmInfo();
if (TT.isAMDGCN()) {
+ // Triple is missing a representation for non-empty, but unrecognized
+ // subarches. Only permit no subarch for any subtarget if it was really
+ // empty.
+ bool IsUnknownSubArch =
+ TT.getSubArch() == Triple::NoSubArch && TT.getArchName().size() != 6;
+ if (IsUnknownSubArch)
+ reportFatalUsageError("unknown subarch " + TT.getArchName());
+
+ if (TT.getSubArch() != Triple::NoSubArch) {
+ AMDGPU::GPUKind Kind = AMDGPU::parseArchAMDGCN(CPU);
+ Triple::SubArchType GPUSubArch = AMDGPU::getSubArch(Kind);
+ if (Kind != AMDGPU::GK_NONE && GPUSubArch != TT.getSubArch() &&
+ TT.getSubArch() != AMDGPU::getMajorSubArch(GPUSubArch)) {
+ reportFatalUsageError("invalid cpu '" + CPU + "' for subarch " +
+ TT.getArchName());
+ }
+ }
+
if (getMCSubtargetInfo().checkFeatures("+wavefrontsize64"))
MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
else if (getMCSubtargetInfo().checkFeatures("+wavefrontsize32"))
@@ -1275,6 +1299,28 @@ GCNTargetMachine::getSubtargetImpl(const Function &F) const {
auto &I = SubtargetMap[SubtargetKey];
if (!I) {
+ AMDGPU::GPUKind Kind = AMDGPU::parseArchAMDGCN(GPU);
+ Triple::SubArchType GPUSubArch = AMDGPU::getSubArch(Kind);
+
+ // Enforce the subtarget is covered by the subarch. Tolerate no subarch for
+ // legacy compatibility.
+ const Triple &TT = getTargetTriple();
+ if (GPUSubArch != TT.getSubArch()) {
+ // Check if this is a generic subarch which has subtargets. Ignore
+ // unknown subtargets with a known subarch, since for whatever reason
+ // the convention is to just print a warning and ignore unrecognized
+ // subtargets.
+ if (Kind != AMDGPU::GK_NONE &&
+ TT.getSubArch() != AMDGPU::getMajorSubArch(GPUSubArch)) {
+ bool IsLegacyEmptySubArch = TT.getSubArch() == Triple::NoSubArch;
+ if (!IsLegacyEmptySubArch &&
+ AMDGPU::getMajorSubArch(GPUSubArch) != TT.getSubArch()) {
+ F.getContext().emitError("invalid subtarget '" + Twine(GPU) +
+ "' for subarch " + TT.getArchName());
+ }
+ }
+ }
+
I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this, BufRelaxed,
TBufRelaxed);
}
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 161395fffca77..3265d7d55e3d3 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -5983,9 +5983,23 @@ bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() {
std::optional<AMDGPU::TargetID> MaybeParsed =
AMDGPU::TargetID::parseTargetIDString(TargetIDDirective);
if (!MaybeParsed)
- return getParser().Error(TargetStart, "malformed target ID");
+ return getParser().Error(TargetStart,
+ "malformed target id '" + TargetIDDirective + "'");
const AMDGPU::TargetID &ParsedTargetID = *MaybeParsed;
+ const Triple &TT = getSTI().getTargetTriple();
+
+ // The processor named in the target id must be covered by the triple's
+ // subarch.
+ if (!AMDGPU::isCPUValidForSubArch(TT.getSubArch(),
+ ParsedTargetID.getGPUKind())) {
+ return getParser().Error(
+ TargetStart, "target id '" + TargetIDDirective +
+ "' specifies a processor that is not valid for "
+ "subarch '" +
+ TT.getArchName() + "'");
+ }
+
const std::optional<AMDGPU::TargetID> &CurrentTargetID =
getTargetStreamer().getTargetID();
@@ -6695,9 +6709,22 @@ bool AMDGPUAsmParser::ParseDirectiveISAVersion() {
std::optional<AMDGPU::TargetID> MaybeParsed =
AMDGPU::TargetID::parseTargetIDString(TargetIDDirective);
if (!MaybeParsed)
- return Error(getParser().getTok().getLoc(), "malformed target id");
+ return Error(getParser().getTok().getLoc(),
+ "malformed target id '" + TargetIDDirective + "'");
const AMDGPU::TargetID &ParsedTargetID = *MaybeParsed;
+ const Triple &TT = getSTI().getTargetTriple();
+
+ // The processor named in the target id must be covered by the triple's
+ // subarch.
+ if (!AMDGPU::isCPUValidForSubArch(TT.getSubArch(),
+ ParsedTargetID.getGPUKind())) {
+ return Error(getParser().getTok().getLoc(),
+ "target id '" + TargetIDDirective +
+ "' specifies a processor that is not valid for subarch '" +
+ TT.getArchName() + "'");
+ }
+
const std::optional<AMDGPU::TargetID> &CurrentTargetID =
getTargetStreamer().getTargetID();
@@ -10727,6 +10754,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
LLVMInitializeAMDGPUAsmParser() {
RegisterMCAsmParser<AMDGPUAsmParser> A(getTheR600Target());
RegisterMCAsmParser<AMDGPUAsmParser> B(getTheGCNTarget());
+ RegisterMCAsmParser<AMDGPUAsmParser> C(getTheGCNLegacyTarget());
}
#define GET_MATCHER_IMPLEMENTATION
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index d904fc0d012bd..2589bae982d9b 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -3041,4 +3041,8 @@ LLVMInitializeAMDGPUDisassembler() {
createAMDGPUDisassembler);
TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(),
createAMDGPUSymbolizer);
+ TargetRegistry::RegisterMCDisassembler(getTheGCNLegacyTarget(),
+ createAMDGPUDisassembler);
+ TargetRegistry::RegisterMCSymbolizer(getTheGCNLegacyTarget(),
+ createAMDGPUSymbolizer);
}
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
index 23c92b9095e36..68b0e8dbbf8ae 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
@@ -26,6 +26,7 @@
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/MDBuilder.h"
+#include "llvm/TargetParser/AMDGPUTargetParser.h"
#include <algorithm>
using namespace llvm;
@@ -54,6 +55,42 @@ static cl::opt<unsigned>
GCNSubtarget::~GCNSubtarget() = default;
+static AMDGPUSubtarget::Generation computeDefaultGeneration(const Triple &TT) {
+ // Legacy triples without a subarch default to the first target that supports
+ // flat addressing for HSA, otherwise the first amdgcn target.
+ if (TT.getSubArch() == Triple::NoSubArch)
+ return TT.getOS() == Triple::AMDHSA ? AMDGPUSubtarget::SEA_ISLANDS
+ : AMDGPUSubtarget::SOUTHERN_ISLANDS;
+
+ switch (AMDGPU::getMajorSubArch(TT.getSubArch())) {
+ case Triple::AMDGPUSubArch6:
+ return AMDGPUSubtarget::SOUTHERN_ISLANDS;
+ case Triple::AMDGPUSubArch7:
+ return AMDGPUSubtarget::SEA_ISLANDS;
+ case Triple::AMDGPUSubArch8:
+ case Triple::AMDGPUSubArch810:
+ return AMDGPUSubtarget::VOLCANIC_ISLANDS;
+ case Triple::AMDGPUSubArch9:
+ case Triple::AMDGPUSubArch908:
+ case Triple::AMDGPUSubArch90A:
+ case Triple::AMDGPUSubArch9_4:
+ return AMDGPUSubtarget::GFX9;
+ case Triple::AMDGPUSubArch10_1:
+ case Triple::AMDGPUSubArch10_3:
+ return AMDGPUSubtarget::GFX10;
+ case Triple::AMDGPUSubArch11:
+ case Triple::AMDGPUSubArch11_7:
+ return AMDGPUSubtarget::GFX11;
+ case Triple::AMDGPUSubArch12:
+ case Triple::AMDGPUSubArch12_5:
+ return AMDGPUSubtarget::GFX12;
+ case Triple::AMDGPUSubArch13:
+ return AMDGPUSubtarget::GFX13;
+ default:
+ reportFatalUsageError("invalid subarch for amdgpu");
+ }
+}
+
GCNSubtarget &GCNSubtarget::initializeSubtargetDependencies(const Triple &TT,
StringRef GPU,
StringRef FS) {
@@ -94,8 +131,7 @@ GCNSubtarget &GCNSubtarget::initializeSubtargetDependencies(const Triple &TT,
// the first amdgcn target that supports flat addressing. Other OSes defaults
// to the first amdgcn target.
if (Gen == AMDGPUSubtarget::INVALID) {
- Gen = TT.getOS() == Triple::AMDHSA ? AMDGPUSubtarget::SEA_ISLANDS
- : AMDGPUSubtarget::SOUTHERN_ISLANDS;
+ Gen = computeDefaultGeneration(TT);
// Assume wave64 for the unknown target, if not explicitly set.
if (getWavefrontSizeLog2() == 0)
WavefrontSizeLog2 = 6;
@@ -177,6 +213,8 @@ void GCNSubtarget::checkSubtargetFeatures(const Function &F) const {
}
}
+// TODO: Validate subarch for subtarget
+
GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
const GCNTargetMachine &TM, bool BufferOOBRelaxed,
bool TBufferOOBRelaxed)
@@ -192,6 +230,7 @@ GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
// Frame index expansion sometimes assumes the low bit of SP is 0
FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0,
/*TransAl=*/Align(4)) {
+
// clang-format on
MaxWavesPerEU = AMDGPU::IsaInfo::getMaxWavesPerEU(*this);
EUsPerCU = AMDGPU::IsaInfo::getEUsPerCU(*this);
diff --git a/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp b/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
index 6c81cbcad3330..f22c43ee88598 100644
--- a/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
+++ b/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
@@ -366,4 +366,9 @@ LLVMInitializeAMDGPUTargetMCA() {
createAMDGPUCustomBehaviour);
TargetRegistry::RegisterInstrPostProcess(getTheGCNTarget(),
createAMDGPUInstrPostProcess);
+
+ TargetRegistry::RegisterCustomBehaviour(getTheGCNLegacyTarget(),
+ createAMDGPUCustomBehaviour);
+ TargetRegistry::RegisterInstrPostProcess(getTheGCNLegacyTarget(),
+ createAMDGPUInstrPostProcess);
}
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
index 4b0cca29b2660..641b77c150aad 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
@@ -79,8 +79,12 @@ createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
if (TT.getArch() == Triple::r600)
return createR600MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
- MCSubtargetInfo *STI =
- createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
+ StringRef ResolvedCPU = CPU;
+ if (ResolvedCPU.empty())
+ ResolvedCPU = AMDGPU::getArchNameFromSubArch(TT.getSubArch());
+
+ MCSubtargetInfo *STI = createAMDGPUMCSubtargetInfoImpl(
+ TT, ResolvedCPU, /*TuneCPU*/ ResolvedCPU, FS);
bool IsWave64 = STI->hasFeature(AMDGPU::FeatureWavefrontSize64);
bool IsWave32 = STI->hasFeature(AMDGPU::FeatureWavefrontSize32);
@@ -191,9 +195,12 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
LLVMInitializeAMDGPUTargetMC() {
TargetRegistry::RegisterMCInstrInfo(getTheGCNTarget(), createAMDGPUMCInstrInfo);
+ TargetRegistry::RegisterMCInstrInfo(getTheGCNLegacyTarget(),
+ createAMDGPUMCInstrInfo);
TargetRegistry::RegisterMCInstrInfo(getTheR600Target(),
createR600MCInstrInfo);
- for (Target *T : {&getTheR600Target(), &getTheGCNTarget()}) {
+ for (Target *T :
+ {&getTheR600Target(), &getTheGCNTarget(), &getTheGCNLegacyTarget()}) {
RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
@@ -211,13 +218,14 @@ LLVMInitializeAMDGPUTargetMC() {
getTheR600Target(), createAMDGPUObjectTargetStreamer);
// GCN specific registration
- TargetRegistry::RegisterMCCodeEmitter(getTheGCNTarget(),
- createAMDGPUMCCodeEmitter);
-
- TargetRegistry::RegisterAsmTargetStreamer(getTheGCNTarget(),
- createAMDGPUAsmTargetStreamer);
- TargetRegistry::RegisterObjectTargetStreamer(
- getTheGCNTarget(), createAMDGPUObjectTargetStreamer);
- TargetRegistry::RegisterNullTargetStreamer(getTheGCNTarget(),
- createAMDGPUNullTargetStreamer);
+ for (Target *T : {&getTheGCNTarget(), &getTheGCNLegacyTarget()}) {
+ TargetRegistry::RegisterMCCodeEmitter(*T, createAMDGPUMCCodeEmitter);
+
+ TargetRegistry::RegisterAsmTargetStreamer(*T,
+ createAMDGPUAsmTargetStreamer);
+ TargetRegistry::RegisterObjectTargetStreamer(
+ *T, createAMDGPUObjectTargetStreamer);
+ TargetRegistry::RegisterNullTargetStreamer(*T,
+ createAMDGPUNullTargetStreamer);
+ }
}
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
index 97bcec66fe318..d70ad37cca867 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
@@ -840,7 +840,7 @@ unsigned AMDGPUTargetELFStreamer::getEFlags() {
llvm_unreachable("Unsupported Arch");
case Triple::r600:
return getEFlagsR600();
- case Triple::amdgcn:
+ case Triple::amdgpu:
return getEFlagsAMDGCN();
}
}
diff --git a/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp b/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
index ad547556cf150..6174b6d79b678 100644
--- a/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
@@ -28,11 +28,27 @@ Target &llvm::getTheGCNTarget() {
return TheGCNTarget;
}
+/// The target for GCN GPUs, registered under the legacy "amdgcn" name. This
+/// should be removed when all tool users of "amdgcn" are migrated.
+Target &llvm::getTheGCNLegacyTarget() {
+ static Target TheGCNLegacyTarget;
+ return TheGCNLegacyTarget;
+}
+
/// Extern function to initialize the targets for the AMDGPU backend
extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
LLVMInitializeAMDGPUTargetInfo() {
RegisterTarget<Triple::r600, false> R600(getTheR600Target(), "r600",
"AMD GPUs HD2XXX-HD6XXX", "AMDGPU");
- RegisterTarget<Triple::amdgcn, false> GCN(getTheGCNTarget(), "amdgcn",
- "AMD GCN GPUs", "AMDGPU");
+ Target &GCNTgt = getTheGCNTarget();
+ RegisterTarget<Triple::amdgpu, false> GCN(GCNTgt, "amdgpu", "AMDGPU gfx6+",
+ "AMDGPU");
+
+ // Register the legacy "amdgcn" name for use with -march. It must not take
+ // possession of the Triple::amdgpu tag, so it uses a match function that
+ // never matches a triple. This hack is copied from AArch64's handling of
+ // "arm64".
+ TargetRegistry::RegisterTarget(getTheGCNLegacyTarget(), "amdgcn",
+ "legacy name for amdgpu", "AMDGPU",
+ [](Triple::ArchType) { return false; });
}
diff --git a/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.h b/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.h
index 45470167a3313..313619da8fbaf 100644
--- a/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.h
+++ b/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.h
@@ -23,6 +23,10 @@ Target &getTheR600Target();
/// The target for GCN GPUs.
Target &getTheGCNTarget();
+/// The target for GCN GPUs, registered under the legacy "amdgcn" architecture
+/// name for use with -march. This is an alias for the target returned by
+/// getTheGCNTarget() and does not participate in target-triple based lookup.
+Target &getTheGCNLegacyTarget();
}
#endif // LLVM_LIB_TARGET_AMDGPU_TARGETINFO_AMDGPUTARGETINFO_H
diff --git a/llvm/lib/TargetParser/AMDGPUTargetParser.cpp b/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
index 08047c8250e45..1c549810ccef5 100644
--- a/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+++ b/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
@@ -34,9 +34,157 @@ StringRef llvm::AMDGPU::getArchFamilyNameAMDGCN(GPUKind AK) {
return ArchName.empty() ? "" : ArchName.drop_back(2);
}
+Triple::SubArchType llvm::AMDGPU::getSubArch(GPUKind AK) {
+ switch (AK) {
+#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \
+ case ENUM: \
+ return SUBARCH;
+#include "llvm/TargetParser/AMDGPUTargetParser.def"
+ default:
+ return Triple::SubArchType::NoSubArch;
+ }
+}
+
+AMDGPU::GPUKind
+llvm::AMDGPU::getGPUKindFromSubArch(Triple::SubArchType SubArch) {
+ switch (SubArch) {
+#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \
+ case SUBARCH: \
+ return ENUM;
+#include "llvm/TargetParser/AMDGPUTargetParser.def"
+ default:
+ return GK_NONE;
+ }
+}
+
+static const Triple::SubArchType
+ AMDGPUMajorFamilies[Triple::LastAMDGPUSubArch - Triple::FirstAMDGPUSubArch +
+ 1] = {
+ Triple::AMDGPUSubArch6, Triple::AMDGPUSubArch6,
+ Triple::AMDGPUSubArch6, Triple::AMDGPUSubArch6,
+
+ Triple::AMDGPUSubArch7, Triple::AMDGPUSubArch7,
+ Triple::AMDGPUSubArch7, Triple::AMDGPUSubArch7,
+ Triple::AMDGPUSubArch7, Triple::AMDGPUSubArch7,
+ Triple::AMDGPUSubArch7,
+
+ Triple::AMDGPUSubArch8, Triple::AMDGPUSubArch8,
+ Triple::AMDGPUSubArch8, Triple::AMDGPUSubArch8,
+ Triple::AMDGPUSubArch8,
+
+ Triple::AMDGPUSubArch810,
+
+ Triple::AMDGPUSubArch9, Triple::AMDGPUSubArch9,
+ Triple::AMDGPUSubArch9, Triple::AMDGPUSubArch9,
+ Triple::AMDGPUSubArch9, Triple::AMDGPUSubArch9,
+ Triple::AMDGPUSubArch9,
+
+ Triple::AMDGPUSubArch908, Triple::AMDGPUSubArch90A,
+
+ Triple::AMDGPUSubArch9_4, Triple::AMDGPUSubArch9_4,
+ Triple::AMDGPUSubArch9_4,
+
+ Triple::AMDGPUSubArch10_1, Triple::AMDGPUSubArch10_1,
+ Triple::AMDGPUSubArch10_1, Triple::AMDGPUSubArch10_1,
+ Triple::AMDGPUSubArch10_1,
+
+ Triple::AMDGPUSubArch10_3, Triple::AMDGPUSubArch10_3,
+ Triple::AMDGPUSubArch10_3, Triple::AMDGPUSubArch10_3,
+ Triple::AMDGPUSubArch10_3, Triple::AMDGPUSubArch10_3,
+ Triple::AMDGPUSubArch10_3, Triple::AMDGPUSubArch10_3,
+
+ Triple::AMDGPUSubArch11, Triple::AMDGPUSubArch11,
+ Triple::AMDGPUSubArch11, Triple::AMDGPUSubArch11,
+ Triple::AMDGPUSubArch11, Triple::AMDGPUSubArch11,
+ Triple::AMDGPUSubArch11, Triple::AMDGPUSubArch11,
+ Triple::AMDGPUSubArch11, Triple::AMDGPUSubArch11,
+
+ Triple::AMDGPUSubArch11_7, Triple::AMDGPUSubArch11_7,
+ Triple::AMDGPUSubArch11_7, Triple::AMDGPUSubArch11_7,
+
+ Triple::AMDGPUSubArch12, Triple::AMDGPUSubArch12,
+ Triple::AMDGPUSubArch12,
+
+ Triple::AMDGPUSubArch12_5, Triple::AMDGPUSubArch12_5,
+ Triple::AMDGPUSubArch12_5,
+
+ Triple::AMDGPUSubArch13, Triple::AMDGPUSubArch13};
+
+Triple::SubArchType AMDGPU::getMajorSubArch(Triple::SubArchType X) {
+ if (X < Triple::FirstAMDGPUSubArch || X > Triple::LastAMDGPUSubArch)
+ return Triple::NoSubArch;
+ return AMDGPUMajorFamilies[X - Triple::FirstAMDGPUSubArch];
+}
+
+bool AMDGPU::isSubArchCompatible(Triple::SubArchType A, Triple::SubArchType B) {
+ if (A == B)
+ return true;
+
+ Triple::SubArchType MajorA = AMDGPU::getMajorSubArch(A);
+ Triple::SubArchType MajorB = AMDGPU::getMajorSubArch(B);
+
+ // One side is the major-family subarch covering the other's family.
+ if (A == MajorA)
+ return MajorA == MajorB;
+ if (B == MajorB)
+ return MajorA == MajorB;
+
+ return false;
+}
+
+bool AMDGPU::isCPUValidForSubArch(Triple::SubArchType SubArch, GPUKind AK) {
+ // An unrecognized GPU is never valid.
+ if (AK == GK_NONE)
+ return false;
+ // A legacy triple without a subarch accepts any known GPU.
+ if (SubArch == Triple::NoSubArch)
+ return true;
+ return isSubArchCompatible(getSubArch(AK), SubArch);
+}
+
+bool AMDGPU::isCPUValidForSubArch(Triple::SubArchType SubArch, StringRef CPU) {
+ return isCPUValidForSubArch(SubArch, parseArchAMDGCN(CPU));
+}
+
+bool AMDGPU::isSubArchCompatible(const Triple &A, const Triple &B) {
+ // Tolerate subarch mismatch if one entry is none. This is a hack for bitcode
+ // libraries.
+ // There's a missing enum entry for an unknown subarch. Make sure the
+ // subarch is really empty.
+ if ((A.getSubArch() == Triple::NoSubArch && A.getArchName().size() == 6) ||
+ (B.getSubArch() == Triple::NoSubArch && B.getArchName().size() == 6))
+ return true;
+
+ return isSubArchCompatible(A.getSubArch(), B.getSubArch());
+}
+
+std::string AMDGPU::mergeSubArch(const Triple &A, const Triple &B) {
+ if (A.getSubArch() == Triple::NoSubArch)
+ return B.str();
+ if (B.getSubArch() == Triple::NoSubArch)
+ return A.str();
+
+ Triple::SubArchType MajorA = AMDGPU::getMajorSubArch(A.getSubArch());
+ Triple::SubArchType MajorB = AMDGPU::getMajorSubArch(B.getSubArch());
+
+ // With a compatible major arch, return the specific subarch.
+ if (A.getSubArch() == MajorA) {
+ if (MajorA == MajorB)
+ return B.str();
+ }
+
+ if (B.getSubArch() == MajorB) {
+ if (MajorA == MajorB)
+ return A.str();
+ }
+
+ // Invalid case.
+ return B.str();
+}
+
StringRef llvm::AMDGPU::getArchNameAMDGCN(GPUKind AK) {
switch (AK) {
-#define AMDGCN_GPU(NAME, ENUM, ISAVERSION, FEATURES) \
+#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \
case ENUM: \
return NAME;
#include "llvm/TargetParser/AMDGPUTargetParser.def"
@@ -45,6 +193,53 @@ StringRef llvm::AMDGPU::getArchNameAMDGCN(GPUKind AK) {
}
}
+// Canonical GPU name for each AMDGPU subarch, indexed by SubArch -
+// Triple::FirstAMDGPUSubArch.
+static const StringLiteral AMDGPUSubArchNames[Triple::LastAMDGPUSubArch -
+ Triple::FirstAMDGPUSubArch + 1] =
+ {"gfx600", // AMDGPUSubArch6 (no generic target)
+ "gfx600", "gfx601", "gfx602",
+
+ "gfx700", // AMDGPUSubArch7 (no generic target)
+ "gfx700", "gfx701", "gfx702", "gfx703", "gfx704",
+ "gfx705",
+
+ "gfx801", // AMDGPUSubArch8 (no generic target)
+ "gfx801", "gfx802", "gfx803", "gfx805",
+
+ "gfx810",
+
+ "gfx9-generic", "gfx900", "gfx902", "gfx904", "gfx906",
+ "gfx909", "gfx90c",
+
+ "gfx908", "gfx90a",
+
+ "gfx9-4-generic", "gfx942", "gfx950",
+
+ "gfx10-1-generic", "gfx1010", "gfx1011", "gfx1012", "gfx1013",
+
+ "gfx10-3-generic", "gfx1030", "gfx1031", "gfx1032", "gfx1033",
+ "gfx1034", "gfx1035", "gfx1036",
+
+ "gfx11-generic", "gfx1100", "gfx1101", "gfx1102", "gfx1103",
+ "gfx1150", "gfx1151", "gfx1152", "gfx1153", "gfx1154",
+
+ "gfx1170", // AMDGPUSubArch11_7 (no generic target)
+ "gfx1170", "gfx1171", "gfx1172",
+
+ "gfx12-generic", "gfx1200", "gfx1201", "gfx12-5-generic", "gfx1250",
+ "gfx1251",
+
+ "gfx1310", // AMDGPUSubArch13 (no generic target)
+ "gfx1310"};
+
+StringRef llvm::AMDGPU::getArchNameFromSubArch(Triple::SubArchType SubArch) {
+ if (SubArch < Triple::FirstAMDGPUSubArch ||
+ SubArch > Triple::LastAMDGPUSubArch)
+ return "";
+ return AMDGPUSubArchNames[SubArch - Triple::FirstAMDGPUSubArch];
+}
+
StringRef llvm::AMDGPU::getArchNameR600(GPUKind AK) {
switch (AK) {
#define R600_GPU(NAME, ENUM, FEATURES) \
@@ -58,7 +253,7 @@ StringRef llvm::AMDGPU::getArchNameR600(GPUKind AK) {
AMDGPU::GPUKind llvm::AMDGPU::parseArchAMDGCN(StringRef CPU) {
return StringSwitch<AMDGPU::GPUKind>(CPU)
-#define AMDGCN_GPU(NAME, ENUM, ISAVERSION, FEATURES) .Case(NAME, ENUM)
+#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) .Case(NAME, ENUM)
#define AMDGCN_GPU_ALIAS(NAME, ENUM) .Case(NAME, ENUM)
#include "llvm/TargetParser/AMDGPUTargetParser.def"
.Case("generic", AMDGPU::GPUKind::GK_GFX600)
@@ -76,7 +271,7 @@ AMDGPU::GPUKind llvm::AMDGPU::parseArchR600(StringRef CPU) {
unsigned AMDGPU::getArchAttrAMDGCN(GPUKind AK) {
switch (AK) {
-#define AMDGCN_GPU(NAME, ENUM, ISAVERSION, FEATURES) \
+#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \
case ENUM: \
return FEATURES;
#include "llvm/TargetParser/AMDGPUTargetParser.def"
@@ -85,6 +280,17 @@ unsigned AMDGPU::getArchAttrAMDGCN(GPUKind AK) {
}
}
+unsigned AMDGPU::getArchAttrAMDGCN(Triple::SubArchType SubArch) {
+ switch (SubArch) {
+#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \
+ case SUBARCH: \
+ return FEATURES;
+#include "llvm/TargetParser/AMDGPUTargetParser.def"
+ default:
+ return FEATURE_NONE;
+ }
+}
+
unsigned AMDGPU::getArchAttrR600(GPUKind AK) {
switch (AK) {
#define R600_GPU(NAME, ENUM, FEATURES) \
@@ -96,13 +302,17 @@ unsigned AMDGPU::getArchAttrR600(GPUKind AK) {
}
}
-void AMDGPU::fillValidArchListAMDGCN(SmallVectorImpl<StringRef> &Values) {
+void AMDGPU::fillValidArchListAMDGCN(SmallVectorImpl<StringRef> &Values,
+ Triple::SubArchType SubArch) {
// XXX: Should this only report unique canonical names?
- Values.append({
-#define AMDGCN_GPU(NAME, ENUM, ISAVERSION, FEATURES) NAME,
-#define AMDGCN_GPU_ALIAS(NAME, ENUM) NAME,
+ // An alias shares its GPU's GPUKind, so it is filtered alongside it.
+#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \
+ if (isCPUValidForSubArch(SubArch, ENUM)) \
+ Values.push_back(NAME);
+#define AMDGCN_GPU_ALIAS(NAME, ENUM) \
+ if (isCPUValidForSubArch(SubArch, ENUM)) \
+ Values.push_back(NAME);
#include "llvm/TargetParser/AMDGPUTargetParser.def"
- });
}
void AMDGPU::fillValidArchListR600(SmallVectorImpl<StringRef> &Values) {
@@ -125,7 +335,7 @@ AMDGPU::IsaVersion AMDGPU::getIsaVersion(StringRef GPU) {
switch (AK) {
#define MAKE_ISAVERSION(A, B, C) {A, B, C}
-#define AMDGCN_GPU(NAME, ENUM, ISAVERSION, FEATURES) \
+#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \
case ENUM: \
return MAKE_ISAVERSION ISAVERSION;
#include "llvm/TargetParser/AMDGPUTargetParser.def"
@@ -135,6 +345,19 @@ AMDGPU::IsaVersion AMDGPU::getIsaVersion(StringRef GPU) {
}
}
+AMDGPU::IsaVersion AMDGPU::getIsaVersion(Triple::SubArchType SubArch) {
+ switch (SubArch) {
+#define MAKE_ISAVERSION(A, B, C) {A, B, C}
+#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \
+ case SUBARCH: \
+ return MAKE_ISAVERSION ISAVERSION;
+#include "llvm/TargetParser/AMDGPUTargetParser.def"
+#undef MAKE_ISAVERSION
+ default:
+ return {0, 0, 0};
+ }
+}
+
StringRef AMDGPU::getCanonicalArchName(const Triple &T, StringRef Arch) {
assert(T.isAMDGPU());
auto ProcKind = T.isAMDGCN() ? parseArchAMDGCN(Arch) : parseArchR600(Arch);
@@ -726,10 +949,17 @@ TargetID::parseTargetIDString(StringRef TargetIDDirective) {
StringRef CPUName = FeatureSplit[0];
- // Determine xnack/sramecc support based on the architecture attributes
- GPUKind Arch = parseArchAMDGCN(CPUName);
+ // Prefer the explicitly named processor so the parsed target id reflects it
+ // (e.g. for validation against the triple subarch). The processor field may
+ // be empty when the ISA is already encoded in the triple's subarch
+ // (e.g. "amdgpu12.50-amd-amdhsa-unknown-"), in which case derive the arch
+ // from the subarch.
+ GPUKind Arch = CPUName.empty() ? getGPUKindFromSubArch(TT.getSubArch())
+ : parseArchAMDGCN(CPUName);
+
unsigned ArchAttr = getArchAttrAMDGCN(Arch);
+ // Determine xnack/sramecc support based on the architecture attributes.
TargetIDSetting XnackSetting = (ArchAttr & FEATURE_XNACK)
? TargetIDSetting::Any
: TargetIDSetting::Unsupported;
diff --git a/llvm/lib/TargetParser/TargetDataLayout.cpp b/llvm/lib/TargetParser/TargetDataLayout.cpp
index a2125eeb82932..410120320f7fd 100644
--- a/llvm/lib/TargetParser/TargetDataLayout.cpp
+++ b/llvm/lib/TargetParser/TargetDataLayout.cpp
@@ -597,8 +597,8 @@ std::string Triple::computeDataLayout(StringRef ABIName) const {
case Triple::ppc64:
case Triple::ppc64le:
return computePowerDataLayout(*this, ABIName);
+ case Triple::amdgpu:
case Triple::r600:
- case Triple::amdgcn:
return computeAMDDataLayout(*this);
case Triple::riscv32:
case Triple::riscv64:
diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp
index 501cf81c1b031..552c5b90edeb6 100644
--- a/llvm/lib/TargetParser/Triple.cpp
+++ b/llvm/lib/TargetParser/Triple.cpp
@@ -14,9 +14,11 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/SwapByteOrder.h"
#include "llvm/Support/VersionTuple.h"
+#include "llvm/TargetParser/AMDGPUTargetParser.h"
#include "llvm/TargetParser/ARMTargetParser.h"
#include "llvm/TargetParser/ARMTargetParserCommon.h"
#include "llvm/TargetParser/Host.h"
+#include "llvm/TargetParser/TargetParser.h"
#include <cassert>
#include <cstring>
using namespace llvm;
@@ -44,8 +46,8 @@ StringRef Triple::getArchTypeName(ArchType Kind) {
return "aarch64_32";
case aarch64_be:
return "aarch64_be";
- case amdgcn:
- return "amdgcn";
+ case amdgpu:
+ return "amdgpu";
case amdil64:
return "amdil64";
case amdil:
@@ -240,6 +242,51 @@ StringRef Triple::getArchName(ArchType Kind, SubArchType SubArch) {
break;
}
break;
+ case Triple::amdgpu: {
+ if (SubArch < Triple::FirstAMDGPUSubArch ||
+ SubArch > Triple::LastAMDGPUSubArch)
+ break;
+
+ static const StringLiteral AMDGPUSubArchNames[Triple::LastAMDGPUSubArch -
+ Triple::FirstAMDGPUSubArch +
+ 1] = {
+ "amdgpu6", "amdgpu6.00", "amdgpu6.01", "amdgpu6.02",
+
+ "amdgpu7", "amdgpu7.00", "amdgpu7.01", "amdgpu7.02",
+ "amdgpu7.03", "amdgpu7.04", "amdgpu7.05",
+
+ "amdgpu8", "amdgpu8.01", "amdgpu8.02", "amdgpu8.03",
+ "amdgpu8.05",
+
+ "amdgpu8.10",
+
+ "amdgpu9", "amdgpu9.00", "amdgpu9.02", "amdgpu9.04",
+ "amdgpu9.06", "amdgpu9.09", "amdgpu9.0c",
+
+ "amdgpu9.08", "amdgpu9.0a",
+
+ "amdgpu9.4", "amdgpu9.42", "amdgpu9.50",
+
+ "amdgpu10.1", "amdgpu10.10", "amdgpu10.11", "amdgpu10.12",
+ "amdgpu10.13",
+
+ "amdgpu10.3", "amdgpu10.30", "amdgpu10.31", "amdgpu10.32",
+ "amdgpu10.33", "amdgpu10.34", "amdgpu10.35", "amdgpu10.36",
+
+ "amdgpu11", "amdgpu11.00", "amdgpu11.01", "amdgpu11.02",
+ "amdgpu11.03", "amdgpu11.50", "amdgpu11.51", "amdgpu11.52",
+ "amdgpu11.53", "amdgpu11.54",
+
+ "amdgpu11.7", "amdgpu11.70", "amdgpu11.71", "amdgpu11.72",
+
+ "amdgpu12", "amdgpu12.00", "amdgpu12.01",
+
+ "amdgpu12.5", "amdgpu12.50", "amdgpu12.51",
+
+ "amdgpu13", "amdgpu13.10"};
+
+ return AMDGPUSubArchNames[SubArch - Triple::FirstAMDGPUSubArch];
+ }
default:
break;
}
@@ -286,7 +333,8 @@ StringRef Triple::getArchTypePrefix(ArchType Kind) {
case hexagon:
return "hexagon";
- case amdgcn:
+ // Intrinsics use amdgcn prefix.
+ case amdgpu:
return "amdgcn";
case r600:
return "r600";
@@ -693,8 +741,9 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
.Case("ppc32le", ppcle)
.Case("ppcle", ppcle)
.Case("ppc64le", ppc64le)
+ .Case("amdgpu", amdgpu)
+ .Case("amdgcn", amdgpu) // Legacy name
.Case("r600", r600)
- .Case("amdgcn", amdgcn)
.Case("riscv32", riscv32)
.Case("riscv64", riscv64)
.Case("riscv32be", riscv32be)
@@ -845,8 +894,9 @@ Triple::ArchType Triple::parseArch(StringRef ArchName) {
.Cases({"mips64el", "mipsn32el", "mipsisa64r6el", "mips64r6el",
"mipsn32r6el"},
Triple::mips64el)
+ .StartsWith("amdgpu", Triple::amdgpu)
+ .Case("amdgcn", Triple::amdgpu)
.Case("r600", Triple::r600)
- .Case("amdgcn", Triple::amdgcn)
.Case("riscv32", Triple::riscv32)
.Case("riscv64", Triple::riscv64)
.Case("riscv32be", Triple::riscv32be)
@@ -1055,7 +1105,7 @@ static Triple::ObjectFormatType parseFormat(StringRef EnvironmentName) {
.Default(Triple::UnknownObjectFormat);
}
-static Triple::SubArchType parseSubArch(StringRef SubArchName) {
+Triple::SubArchType Triple::parseSubArch(StringRef SubArchName) {
if (SubArchName.starts_with("mips") &&
(SubArchName.ends_with("r6el") || SubArchName.ends_with("r6")))
return Triple::MipsSubArch_r6;
@@ -1097,6 +1147,77 @@ static Triple::SubArchType parseSubArch(StringRef SubArchName) {
.EndsWith("v1.9", Triple::DXILSubArch_v1_9)
.Default(Triple::NoSubArch);
+ if (SubArchName.consume_front("amdgpu")) {
+ return StringSwitch<Triple::SubArchType>(SubArchName)
+ .Case("6", Triple::AMDGPUSubArch6)
+ .Case("6.00", Triple::AMDGPUSubArch600)
+ .Case("6.01", Triple::AMDGPUSubArch601)
+ .Case("6.02", Triple::AMDGPUSubArch602)
+ .Case("7", Triple::AMDGPUSubArch7)
+ .Case("7.00", Triple::AMDGPUSubArch700)
+ .Case("7.01", Triple::AMDGPUSubArch701)
+ .Case("7.02", Triple::AMDGPUSubArch702)
+ .Case("7.03", Triple::AMDGPUSubArch703)
+ .Case("7.04", Triple::AMDGPUSubArch704)
+ .Case("7.05", Triple::AMDGPUSubArch705)
+ .Case("8", Triple::AMDGPUSubArch8)
+ .Case("8.01", Triple::AMDGPUSubArch801)
+ .Case("8.02", Triple::AMDGPUSubArch802)
+ .Case("8.03", Triple::AMDGPUSubArch803)
+ .Case("8.05", Triple::AMDGPUSubArch805)
+ .Case("8.10", Triple::AMDGPUSubArch810)
+ .Case("9", Triple::AMDGPUSubArch9)
+ .Case("9.00", Triple::AMDGPUSubArch900)
+ .Case("9.02", Triple::AMDGPUSubArch902)
+ .Case("9.04", Triple::AMDGPUSubArch904)
+ .Case("9.06", Triple::AMDGPUSubArch906)
+ .Case("9.08", Triple::AMDGPUSubArch908)
+ .Case("9.09", Triple::AMDGPUSubArch909)
+ .Case("9.0a", Triple::AMDGPUSubArch90A)
+ .Case("9.0c", Triple::AMDGPUSubArch90C)
+ .Case("9.4", Triple::AMDGPUSubArch9_4)
+ .Case("9.5", Triple::AMDGPUSubArch9_4)
+ .Case("9.42", Triple::AMDGPUSubArch942)
+ .Case("9.50", Triple::AMDGPUSubArch950)
+ .Case("10", Triple::AMDGPUSubArch10_1)
+ .Case("10.1", Triple::AMDGPUSubArch10_1)
+ .Case("10.10", Triple::AMDGPUSubArch1010)
+ .Case("10.11", Triple::AMDGPUSubArch1011)
+ .Case("10.12", Triple::AMDGPUSubArch1012)
+ .Case("10.13", Triple::AMDGPUSubArch1013)
+ .Case("10.3", Triple::AMDGPUSubArch10_3)
+ .Case("10.30", Triple::AMDGPUSubArch1030)
+ .Case("10.31", Triple::AMDGPUSubArch1031)
+ .Case("10.32", Triple::AMDGPUSubArch1032)
+ .Case("10.33", Triple::AMDGPUSubArch1033)
+ .Case("10.34", Triple::AMDGPUSubArch1034)
+ .Case("10.35", Triple::AMDGPUSubArch1035)
+ .Case("10.36", Triple::AMDGPUSubArch1036)
+ .Case("11", Triple::AMDGPUSubArch11)
+ .Case("11.00", Triple::AMDGPUSubArch1100)
+ .Case("11.01", Triple::AMDGPUSubArch1101)
+ .Case("11.02", Triple::AMDGPUSubArch1102)
+ .Case("11.03", Triple::AMDGPUSubArch1103)
+ .Case("11.50", Triple::AMDGPUSubArch1150)
+ .Case("11.51", Triple::AMDGPUSubArch1151)
+ .Case("11.52", Triple::AMDGPUSubArch1152)
+ .Case("11.53", Triple::AMDGPUSubArch1153)
+ .Case("11.54", Triple::AMDGPUSubArch1154)
+ .Case("11.7", Triple::AMDGPUSubArch11_7)
+ .Case("11.70", Triple::AMDGPUSubArch1170)
+ .Case("11.71", Triple::AMDGPUSubArch1171)
+ .Case("11.72", Triple::AMDGPUSubArch1172)
+ .Case("12", Triple::AMDGPUSubArch12)
+ .Case("12.00", Triple::AMDGPUSubArch1200)
+ .Case("12.01", Triple::AMDGPUSubArch1201)
+ .Case("12.5", Triple::AMDGPUSubArch12_5)
+ .Case("12.50", Triple::AMDGPUSubArch1250)
+ .Case("12.51", Triple::AMDGPUSubArch1251)
+ .Case("13", Triple::AMDGPUSubArch13)
+ .Case("13.10", Triple::AMDGPUSubArch1310)
+ .Default(Triple::NoSubArch);
+ }
+
StringRef ARMSubArch = ARM::getCanonicalArchName(SubArchName);
// For now, this is the small part. Early return.
@@ -1209,7 +1330,7 @@ static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
return T.isOSDarwin() ? Triple::MachO : Triple::ELF;
}
case Triple::aarch64_be:
- case Triple::amdgcn:
+ case Triple::amdgpu:
case Triple::amdil64:
case Triple::amdil:
case Triple::arc:
@@ -2024,7 +2145,7 @@ unsigned Triple::getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
case llvm::Triple::aarch64:
case llvm::Triple::aarch64_be:
- case llvm::Triple::amdgcn:
+ case llvm::Triple::amdgpu:
case llvm::Triple::amdil64:
case llvm::Triple::bpfeb:
case llvm::Triple::bpfel:
@@ -2086,7 +2207,7 @@ Triple Triple::get32BitArchVariant() const {
Triple T(*this);
switch (getArch()) {
case Triple::UnknownArch:
- case Triple::amdgcn:
+ case Triple::amdgpu:
case Triple::avr:
case Triple::bpfeb:
case Triple::bpfel:
@@ -2220,7 +2341,7 @@ Triple Triple::get64BitArchVariant() const {
case Triple::aarch64:
case Triple::aarch64_be:
- case Triple::amdgcn:
+ case Triple::amdgpu:
case Triple::amdil64:
case Triple::bpfeb:
case Triple::bpfel:
@@ -2323,7 +2444,7 @@ Triple Triple::getBigEndianArchVariant() const {
return T;
switch (getArch()) {
case Triple::UnknownArch:
- case Triple::amdgcn:
+ case Triple::amdgpu:
case Triple::amdil64:
case Triple::amdil:
case Triple::avr:
@@ -2458,7 +2579,7 @@ bool Triple::isLittleEndian() const {
switch (getArch()) {
case Triple::aarch64:
case Triple::aarch64_32:
- case Triple::amdgcn:
+ case Triple::amdgpu:
case Triple::amdil64:
case Triple::amdil:
case Triple::arm:
@@ -2538,6 +2659,14 @@ bool Triple::isCompatibleWith(const Triple &Other) const {
getObjectFormat() == Other.getObjectFormat();
}
+ if (getArch() == Triple::amdgpu && Other.getArch() == Triple::amdgpu) {
+ if (getOS() != Other.getOS() || getVendor() != Other.getVendor() ||
+ getEnvironment() != Other.getEnvironment() ||
+ getObjectFormat() != Other.getObjectFormat())
+ return false;
+ return AMDGPU::isSubArchCompatible(*this, Other);
+ }
+
// If vendor is apple, ignore the version number (the environment field)
// and the object format.
if (getVendor() == Triple::Apple)
@@ -2554,9 +2683,15 @@ bool Triple::isCompatibleWith(const Triple &Other) const {
std::string Triple::merge(const Triple &Other) const {
// If vendor is apple, pick the triple with the larger version number.
- if (getVendor() == Triple::Apple)
- if (Other.isOSVersionLT(*this))
+ if (getVendor() == Triple::Apple) {
+ if (Other.isOSVersionLT(*this)) {
return str();
+ }
+ }
+
+ if (isAMDGCN() && getOS() == Other.getOS() &&
+ getVendor() == Other.getVendor())
+ return AMDGPU::mergeSubArch(*this, Other);
return Other.str();
}
diff --git a/llvm/lib/Transforms/IPO/ExpandVariadics.cpp b/llvm/lib/Transforms/IPO/ExpandVariadics.cpp
index 2996657bc693a..4a45e8d5137a4 100644
--- a/llvm/lib/Transforms/IPO/ExpandVariadics.cpp
+++ b/llvm/lib/Transforms/IPO/ExpandVariadics.cpp
@@ -1121,8 +1121,8 @@ struct Wasm final : public VariadicABIInfo {
std::unique_ptr<VariadicABIInfo> VariadicABIInfo::create(const Triple &T) {
switch (T.getArch()) {
- case Triple::r600:
- case Triple::amdgcn: {
+ case Triple::amdgpu:
+ case Triple::r600: {
return std::make_unique<Amdgpu>();
}
diff --git a/llvm/lib/Transforms/IPO/OpenMPOpt.cpp b/llvm/lib/Transforms/IPO/OpenMPOpt.cpp
index 012ea3aad490d..e36b05564ff1c 100644
--- a/llvm/lib/Transforms/IPO/OpenMPOpt.cpp
+++ b/llvm/lib/Transforms/IPO/OpenMPOpt.cpp
@@ -292,7 +292,7 @@ struct OMPInformationCache : public InformationCache {
switch (T.getArch()) {
case llvm::Triple::nvptx:
case llvm::Triple::nvptx64:
- case llvm::Triple::amdgcn:
+ case llvm::Triple::amdgpu:
assert(OMPBuilder.Config.IsTargetDevice &&
"OpenMP AMDGPU/NVPTX is only prepared to deal with device code.");
OMPBuilder.Config.IsGPU = true;
diff --git a/llvm/lib/Transforms/Utils/CodeExtractor.cpp b/llvm/lib/Transforms/Utils/CodeExtractor.cpp
index 975294ab00f73..4c33848dacf51 100644
--- a/llvm/lib/Transforms/Utils/CodeExtractor.cpp
+++ b/llvm/lib/Transforms/Utils/CodeExtractor.cpp
@@ -246,7 +246,7 @@ buildExtractionBlockSet(ArrayRef<BasicBlock *> BBs, DominatorTree *DT,
/// for specified target preserves original alignment
static bool isAlignmentPreservedForAddrCast(const Triple &TargetTriple) {
switch (TargetTriple.getArch()) {
- case Triple::ArchType::amdgcn:
+ case Triple::ArchType::amdgpu:
case Triple::ArchType::r600:
return true;
// TODO: Add other architectures for which we are certain that alignment
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-triple.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-triple.ll
new file mode 100644
index 0000000000000..0a5121d908ae5
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-triple.ll
@@ -0,0 +1,72 @@
+; RUN: llc -mtriple=amdgpu6-amd-amdhsa < %s | FileCheck -check-prefixes=GFX6 %s
+; RUN: llc -mtriple=amdgpu6-amd-amdhsa -mcpu=gfx601 < %s | FileCheck -check-prefixes=GFX601 %s
+
+; RUN: llc -mtriple=amdgpu7-amd-amdhsa < %s | FileCheck -check-prefixes=GFX7 %s
+; RUN: llc -mtriple=amdgpu7-amd-amdhsa -mcpu=gfx701 < %s | FileCheck -check-prefixes=GFX701 %s
+
+; RUN: llc -mtriple=amdgpu8-amd-amdhsa < %s | FileCheck -check-prefixes=GFX8 %s
+; RUN: llc -mtriple=amdgpu8-amd-amdhsa -mcpu=gfx803 < %s | FileCheck -check-prefixes=GFX803 %s
+
+; RUN: llc -mtriple=amdgpu9-amd-amdhsa < %s | FileCheck -check-prefixes=GFX9 %s
+; RUN: llc -mtriple=amdgpu9.08-amd-amdhsa -mcpu=gfx908 < %s | FileCheck -check-prefixes=GFX908 %s
+
+; RUN: llc -mtriple=amdgpu9.4-amd-amdhsa < %s | FileCheck -check-prefixes=GFX94 %s
+; RUN: llc -mtriple=amdgpu9.4-amd-amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942 %s
+
+; RUN: llc -mtriple=amdgpu10-amd-amdhsa < %s | FileCheck -check-prefixes=GFX10 %s
+; RUN: llc -mtriple=amdgpu10.1-amd-amdhsa < %s | FileCheck -check-prefixes=GFX10_1 %s
+
+; RUN: llc -mtriple=amdgpu10.1-amd-amdhsa -mcpu=gfx1012 < %s | FileCheck -check-prefixes=GFX1012 %s
+
+; RUN: llc -mtriple=amdgpu10.3-amd-amdhsa < %s | FileCheck -check-prefixes=GFX10_3 %s
+; RUN: llc -mtriple=amdgpu10.3-amd-amdhsa -mcpu=gfx1031 < %s | FileCheck -check-prefixes=GFX1031 %s
+
+; RUN: llc -mtriple=amdgpu11-amd-amdhsa < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgpu11-amd-amdhsa -mcpu=gfx1101 < %s | FileCheck -check-prefixes=GFX1101 %s
+
+; RUN: llc -mtriple=amdgpu12-amd-amdhsa < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -mtriple=amdgpu12-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX1200 %s
+
+; RUN: llc -mtriple=amdgpu12.5-amd-amdhsa < %s | FileCheck -check-prefixes=GFX125 %s
+; RUN: llc -mtriple=amdgpu12.5-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250 %s
+
+; RUN: llc -mtriple=amdgpu13-amd-amdhsa < %s | FileCheck -check-prefixes=GFX13 %s
+; RUN: llc -mtriple=amdgpu13-amd-amdhsa -mcpu=gfx1310 < %s | FileCheck -check-prefixes=GFX1310 %s
+
+; GFX6: .amdgcn_target "amdgpu6-amd-amdhsa-unknown-gfx600"
+; GFX601: .amdgcn_target "amdgpu6-amd-amdhsa-unknown-gfx601"
+
+; GFX7: .amdgcn_target "amdgpu7-amd-amdhsa-unknown-gfx700"
+; GFX701: .amdgcn_target "amdgpu7-amd-amdhsa-unknown-gfx701"
+
+; GFX8: .amdgcn_target "amdgpu8-amd-amdhsa-unknown-gfx801"
+; GFX803: .amdgcn_target "amdgpu8-amd-amdhsa-unknown-gfx803"
+
+; GFX9: .amdgcn_target "amdgpu9-amd-amdhsa-unknown-gfx9-generic"
+; GFX908: .amdgcn_target "amdgpu9.08-amd-amdhsa-unknown-gfx908"
+
+; GFX94: .amdgcn_target "amdgpu9.4-amd-amdhsa-unknown-gfx9-4-generic"
+; GFX942: .amdgcn_target "amdgpu9.4-amd-amdhsa-unknown-gfx942"
+
+; FIXME: Normalize this
+; GFX10: .amdgcn_target "amdgpu10-amd-amdhsa-unknown-gfx10-1-generic"
+; GFX10_1: .amdgcn_target "amdgpu10.1-amd-amdhsa-unknown-gfx10-1-generic"
+; GFX1012: .amdgcn_target "amdgpu10.1-amd-amdhsa-unknown-gfx1012"
+
+; GFX10_3: .amdgcn_target "amdgpu10.3-amd-amdhsa-unknown-gfx10-3-generic"
+; GFX1031: .amdgcn_target "amdgpu10.3-amd-amdhsa-unknown-gfx1031"
+
+; GFX11: .amdgcn_target "amdgpu11-amd-amdhsa-unknown-gfx11-generic"
+; GFX1101: .amdgcn_target "amdgpu11-amd-amdhsa-unknown-gfx1101"
+
+; GFX12: .amdgcn_target "amdgpu12-amd-amdhsa-unknown-gfx12-generic"
+; GFX1200: .amdgcn_target "amdgpu12-amd-amdhsa-unknown-gfx1200"
+
+; GFX125: .amdgcn_target "amdgpu12.5-amd-amdhsa-unknown-gfx12-5-generic"
+; GFX1250: .amdgcn_target "amdgpu12.5-amd-amdhsa-unknown-gfx1250"
+
+; GFX13: .amdgcn_target "amdgpu13-amd-amdhsa-unknown-gfx1310"
+; GFX1310: .amdgcn_target "amdgpu13-amd-amdhsa-unknown-gfx1310"
+define amdgpu_kernel void @kernel() {
+ ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll b/llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
index bcc8e96cedd6e..a5ba17d3c644c 100644
--- a/llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
+++ b/llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
@@ -103,7 +103,7 @@
; ARCH-R600: AddressSize: 32bit
; ARCH-GCN: Format: elf64-amdgpu
-; ARCH-GCN: Arch: amdgcn
+; ARCH-GCN: Arch: amdgpu
; ARCH-GCN: AddressSize: 64bit
; ALL: Flags [
diff --git a/llvm/test/CodeGen/AMDGPU/loop-prefetch.ll b/llvm/test/CodeGen/AMDGPU/loop-prefetch.ll
index 595a78ca0c08c..88a5fec54cbdb 100644
--- a/llvm/test/CodeGen/AMDGPU/loop-prefetch.ll
+++ b/llvm/test/CodeGen/AMDGPU/loop-prefetch.ll
@@ -1,5 +1,5 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -asm-verbose=0 < %s | FileCheck --check-prefixes=GCN,GFX10,GFX10-ASM %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 < %s -filetype=obj | llvm-objdump -d --arch-name=amdgcn --mcpu=gfx1030 --symbolize-operands - | FileCheck --check-prefixes=GCN,GFX10,GFX10-DIS %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 < %s -filetype=obj | llvm-objdump -d --arch-name=amdgpu --mcpu=gfx1030 --symbolize-operands - | FileCheck --check-prefixes=GCN,GFX10,GFX10-DIS %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck --check-prefix=GFX8 %s
; GFX8-NOT: s_inst_prefetch
diff --git a/llvm/test/CodeGen/AMDGPU/march-amdgcn-legacy-arch-name.ll b/llvm/test/CodeGen/AMDGPU/march-amdgcn-legacy-arch-name.ll
new file mode 100644
index 0000000000000..a2110c861128b
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/march-amdgcn-legacy-arch-name.ll
@@ -0,0 +1,10 @@
+; The architecture name was renamed from "amdgcn" to "amdgpu". Check that the
+; legacy "amdgcn" name still works when passed via -march.
+
+; RUN: llc -march=amdgcn -mcpu=gfx900 < %s | FileCheck %s
+
+; CHECK: f:
+; CHECK: s_setpc_b64
+define void @f() {
+ ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/target-id-from-triple.ll b/llvm/test/CodeGen/AMDGPU/target-id-from-triple.ll
new file mode 100644
index 0000000000000..5114960b1faf9
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/target-id-from-triple.ll
@@ -0,0 +1,177 @@
+; RUN: llc -mtriple=amdgpu6-amd-amdhsa < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -mtriple=amdgpu6.00-amd-amdhsa < %s | FileCheck -check-prefix=GFX600 %s
+; RUN: llc -mtriple=amdgpu6.01-amd-amdhsa < %s | FileCheck -check-prefix=GFX601 %s
+; RUN: llc -mtriple=amdgpu6.02-amd-amdhsa < %s | FileCheck -check-prefix=GFX602 %s
+
+; RUN: llc -mtriple=amdgpu7-amd-amdhsa < %s | FileCheck -check-prefix=GFX7 %s
+; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefix=GFX700 %s
+; RUN: llc -mtriple=amdgpu7.01-amd-amdhsa < %s | FileCheck -check-prefix=GFX701 %s
+; RUN: llc -mtriple=amdgpu7.02-amd-amdhsa < %s | FileCheck -check-prefix=GFX702 %s
+; RUN: llc -mtriple=amdgpu7.03-amd-amdhsa < %s | FileCheck -check-prefix=GFX703 %s
+; RUN: llc -mtriple=amdgpu7.04-amd-amdhsa < %s | FileCheck -check-prefix=GFX704 %s
+; RUN: llc -mtriple=amdgpu7.05-amd-amdhsa < %s | FileCheck -check-prefix=GFX705 %s
+
+; RUN: llc -mtriple=amdgpu8.01-amd-amdhsa < %s | FileCheck -check-prefix=GFX801 %s
+; RUN: llc -mtriple=amdgpu8.02-amd-amdhsa < %s | FileCheck -check-prefix=GFX802 %s
+; RUN: llc -mtriple=amdgpu8.03-amd-amdhsa < %s | FileCheck -check-prefix=GFX803 %s
+; RUN: llc -mtriple=amdgpu8.05-amd-amdhsa < %s | FileCheck -check-prefix=GFX805 %s
+; RUN: llc -mtriple=amdgpu8.10-amd-amdhsa < %s | FileCheck -check-prefix=GFX810 %s
+
+; RUN: llc -mtriple=amdgpu9-amd-amdhsa < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -check-prefix=GFX900 %s
+; RUN: llc -mtriple=amdgpu9.02-amd-amdhsa < %s | FileCheck -check-prefix=GFX902 %s
+; RUN: llc -mtriple=amdgpu9.04-amd-amdhsa < %s | FileCheck -check-prefix=GFX904 %s
+; RUN: llc -mtriple=amdgpu9.06-amd-amdhsa < %s | FileCheck -check-prefix=GFX906 %s
+; RUN: llc -mtriple=amdgpu9.08-amd-amdhsa < %s | FileCheck -check-prefix=GFX908 %s
+; RUN: llc -mtriple=amdgpu9.09-amd-amdhsa < %s | FileCheck -check-prefix=GFX909 %s
+; RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa < %s | FileCheck -check-prefix=GFX90A %s
+; RUN: llc -mtriple=amdgpu9.0c-amd-amdhsa < %s | FileCheck -check-prefix=GFX90C %s
+; RUN: llc -mtriple=amdgpu9.4-amd-amdhsa < %s | FileCheck -check-prefix=GFX94 %s
+; RUN: llc -mtriple=amdgpu9.42-amd-amdhsa < %s | FileCheck -check-prefix=GFX942 %s
+; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa < %s | FileCheck -check-prefix=GFX950 %s
+
+; RUN: llc -mtriple=amdgpu10.1-amd-amdhsa < %s | FileCheck -check-prefix=GFX101 %s
+; RUN: llc -mtriple=amdgpu10.10-amd-amdhsa < %s | FileCheck -check-prefix=GFX1010 %s
+; RUN: llc -mtriple=amdgpu10.11-amd-amdhsa < %s | FileCheck -check-prefix=GFX1011 %s
+; RUN: llc -mtriple=amdgpu10.12-amd-amdhsa < %s | FileCheck -check-prefix=GFX1012 %s
+; RUN: llc -mtriple=amdgpu10.13-amd-amdhsa < %s | FileCheck -check-prefix=GFX1013 %s
+
+; RUN: llc -mtriple=amdgpu10.3-amd-amdhsa < %s | FileCheck -check-prefix=GFX103 %s
+; RUN: llc -mtriple=amdgpu10.30-amd-amdhsa < %s | FileCheck -check-prefix=GFX1030 %s
+; RUN: llc -mtriple=amdgpu10.31-amd-amdhsa < %s | FileCheck -check-prefix=GFX1031 %s
+; RUN: llc -mtriple=amdgpu10.32-amd-amdhsa < %s | FileCheck -check-prefix=GFX1032 %s
+; RUN: llc -mtriple=amdgpu10.33-amd-amdhsa < %s | FileCheck -check-prefix=GFX1033 %s
+; RUN: llc -mtriple=amdgpu10.34-amd-amdhsa < %s | FileCheck -check-prefix=GFX1034 %s
+; RUN: llc -mtriple=amdgpu10.35-amd-amdhsa < %s | FileCheck -check-prefix=GFX1035 %s
+; RUN: llc -mtriple=amdgpu10.36-amd-amdhsa < %s | FileCheck -check-prefix=GFX1036 %s
+
+; RUN: llc -mtriple=amdgpu11-amd-amdhsa < %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa < %s | FileCheck -check-prefix=GFX1100 %s
+; RUN: llc -mtriple=amdgpu11.01-amd-amdhsa < %s | FileCheck -check-prefix=GFX1101 %s
+; RUN: llc -mtriple=amdgpu11.02-amd-amdhsa < %s | FileCheck -check-prefix=GFX1102 %s
+; RUN: llc -mtriple=amdgpu11.03-amd-amdhsa < %s | FileCheck -check-prefix=GFX1103 %s
+; RUN: llc -mtriple=amdgpu11.50-amd-amdhsa < %s | FileCheck -check-prefix=GFX1150 %s
+; RUN: llc -mtriple=amdgpu11.51-amd-amdhsa < %s | FileCheck -check-prefix=GFX1151 %s
+; RUN: llc -mtriple=amdgpu11.52-amd-amdhsa < %s | FileCheck -check-prefix=GFX1152 %s
+; RUN: llc -mtriple=amdgpu11.53-amd-amdhsa < %s | FileCheck -check-prefix=GFX1153 %s
+; RUN: llc -mtriple=amdgpu11.54-amd-amdhsa < %s | FileCheck -check-prefix=GFX1154 %s
+; RUN: llc -mtriple=amdgpu11.7-amd-amdhsa < %s | FileCheck -check-prefix=GFX11_7 %s
+; RUN: llc -mtriple=amdgpu11.70-amd-amdhsa < %s | FileCheck -check-prefix=GFX1170 %s
+; RUN: llc -mtriple=amdgpu11.71-amd-amdhsa < %s | FileCheck -check-prefix=GFX1171 %s
+; RUN: llc -mtriple=amdgpu11.72-amd-amdhsa < %s | FileCheck -check-prefix=GFX1172 %s
+
+; RUN: llc -mtriple=amdgpu12-amd-amdhsa < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -mtriple=amdgpu12.00-amd-amdhsa < %s | FileCheck -check-prefix=GFX1200 %s
+; RUN: llc -mtriple=amdgpu12.01-amd-amdhsa < %s | FileCheck -check-prefix=GFX1201 %s
+
+; RUN: llc -mtriple=amdgpu12.5-amd-amdhsa < %s | FileCheck -check-prefix=GFX12_5 %s
+; RUN: llc -mtriple=amdgpu12.50-amd-amdhsa < %s | FileCheck -check-prefix=GFX1250 %s
+; RUN: llc -mtriple=amdgpu12.51-amd-amdhsa < %s | FileCheck -check-prefix=GFX1251 %s
+
+; RUN: llc -mtriple=amdgpu13-amd-amdhsa < %s | FileCheck -check-prefix=GFX13 %s
+; RUN: llc -mtriple=amdgpu13.10-amd-amdhsa < %s | FileCheck -check-prefix=GFX1310 %s
+
+; A major-family subarch combined with a more specific (valid) -mcpu keeps
+; the specific processor rather than the subarch's generic/default one.
+; RUN: llc -mtriple=amdgpu6-amd-amdhsa -mcpu=gfx602 < %s | FileCheck -check-prefix=MAJOR-GFX602 %s
+; RUN: llc -mtriple=amdgpu8-amd-amdhsa -mcpu=gfx803 < %s | FileCheck -check-prefix=MAJOR-GFX803 %s
+; RUN: llc -mtriple=amdgpu9-amd-amdhsa -mcpu=gfx906 < %s | FileCheck -check-prefix=MAJOR-GFX906 %s
+; RUN: llc -mtriple=amdgpu12-amd-amdhsa -mcpu=gfx1201 < %s | FileCheck -check-prefix=MAJOR-GFX1201 %s
+
+; MAJOR-GFX602: .amdgcn_target "amdgpu6-amd-amdhsa-unknown-gfx602"
+; MAJOR-GFX803: .amdgcn_target "amdgpu8-amd-amdhsa-unknown-gfx803"
+; MAJOR-GFX906: .amdgcn_target "amdgpu9-amd-amdhsa-unknown-gfx906"
+; MAJOR-GFX1201: .amdgcn_target "amdgpu12-amd-amdhsa-unknown-gfx1201"
+
+; An unrecognized -mcpu is ignored. The resulting target ID has an
+; empty processor field.
+; RUN: llc -mtriple=amdgpu6.00-amd-amdhsa -mcpu=invalid < %s | FileCheck -check-prefix=INVALID-CPU-GFX6 %s
+; RUN: llc -mtriple=amdgpu9-amd-amdhsa -mcpu=invalid < %s | FileCheck -check-prefix=INVALID-CPU-GFX9 %s
+; RUN: llc -mtriple=amdgpu12.50-amd-amdhsa -mcpu=invalid < %s | FileCheck -check-prefix=INVALID-CPU-GFX1250 %s
+
+; INVALID-CPU-GFX6: .amdgcn_target "amdgpu6.00-amd-amdhsa-unknown-"
+; INVALID-CPU-GFX9: .amdgcn_target "amdgpu9-amd-amdhsa-unknown-"
+; INVALID-CPU-GFX1250: .amdgcn_target "amdgpu12.50-amd-amdhsa-unknown-"
+
+; GFX6: .amdgcn_target "amdgpu6-amd-amdhsa-unknown-gfx600"
+; GFX600: .amdgcn_target "amdgpu6.00-amd-amdhsa-unknown-gfx600"
+; GFX601: .amdgcn_target "amdgpu6.01-amd-amdhsa-unknown-gfx601"
+; GFX602: .amdgcn_target "amdgpu6.02-amd-amdhsa-unknown-gfx602"
+
+; GFX7: .amdgcn_target "amdgpu7-amd-amdhsa-unknown-gfx700"
+; GFX700: .amdgcn_target "amdgpu7.00-amd-amdhsa-unknown-gfx700"
+; GFX701: .amdgcn_target "amdgpu7.01-amd-amdhsa-unknown-gfx701"
+; GFX702: .amdgcn_target "amdgpu7.02-amd-amdhsa-unknown-gfx702"
+; GFX703: .amdgcn_target "amdgpu7.03-amd-amdhsa-unknown-gfx703"
+; GFX704: .amdgcn_target "amdgpu7.04-amd-amdhsa-unknown-gfx704"
+; GFX705: .amdgcn_target "amdgpu7.05-amd-amdhsa-unknown-gfx705"
+
+; GFX8: .amdgcn_target "amdgpu8-amd-amdhsa-unknown-gfx800"
+; GFX801: .amdgcn_target "amdgpu8.01-amd-amdhsa-unknown-gfx801"
+; GFX802: .amdgcn_target "amdgpu8.02-amd-amdhsa-unknown-gfx802"
+; GFX803: .amdgcn_target "amdgpu8.03-amd-amdhsa-unknown-gfx803"
+; GFX805: .amdgcn_target "amdgpu8.05-amd-amdhsa-unknown-gfx805"
+
+; GFX810: .amdgcn_target "amdgpu8.10-amd-amdhsa-unknown-gfx810"
+
+; GFX9: .amdgcn_target "amdgpu9-amd-amdhsa-unknown-gfx9-generic"
+; GFX900: .amdgcn_target "amdgpu9.00-amd-amdhsa-unknown-gfx900"
+; GFX902: .amdgcn_target "amdgpu9.02-amd-amdhsa-unknown-gfx902"
+; GFX904: .amdgcn_target "amdgpu9.04-amd-amdhsa-unknown-gfx904"
+; GFX906: .amdgcn_target "amdgpu9.06-amd-amdhsa-unknown-gfx906"
+; GFX908: .amdgcn_target "amdgpu9.08-amd-amdhsa-unknown-gfx908"
+; GFX909: .amdgcn_target "amdgpu9.09-amd-amdhsa-unknown-gfx909"
+; GFX90A: .amdgcn_target "amdgpu9.0a-amd-amdhsa-unknown-gfx90a"
+; GFX90C: .amdgcn_target "amdgpu9.0c-amd-amdhsa-unknown-gfx90c"
+
+; GFX94: .amdgcn_target "amdgpu9.4-amd-amdhsa-unknown-gfx9-4-generic"
+; GFX942: .amdgcn_target "amdgpu9.42-amd-amdhsa-unknown-gfx942"
+; GFX950: .amdgcn_target "amdgpu9.50-amd-amdhsa-unknown-gfx950"
+
+; GFX101: .amdgcn_target "amdgpu10.1-amd-amdhsa-unknown-gfx10-1-generic"
+; GFX1010: .amdgcn_target "amdgpu10.10-amd-amdhsa-unknown-gfx1010"
+; GFX1011: .amdgcn_target "amdgpu10.11-amd-amdhsa-unknown-gfx1011"
+; GFX1012: .amdgcn_target "amdgpu10.12-amd-amdhsa-unknown-gfx1012"
+; GFX1013: .amdgcn_target "amdgpu10.13-amd-amdhsa-unknown-gfx1013"
+
+
+; GFX103: .amdgcn_target "amdgpu10.3-amd-amdhsa-unknown-gfx10-3-generic"
+; GFX1030: .amdgcn_target "amdgpu10.30-amd-amdhsa-unknown-gfx1030"
+; GFX1031: .amdgcn_target "amdgpu10.31-amd-amdhsa-unknown-gfx1031"
+; GFX1032: .amdgcn_target "amdgpu10.32-amd-amdhsa-unknown-gfx1032"
+; GFX1033: .amdgcn_target "amdgpu10.33-amd-amdhsa-unknown-gfx1033"
+; GFX1034: .amdgcn_target "amdgpu10.34-amd-amdhsa-unknown-gfx1034"
+; GFX1035: .amdgcn_target "amdgpu10.35-amd-amdhsa-unknown-gfx1035"
+; GFX1036: .amdgcn_target "amdgpu10.36-amd-amdhsa-unknown-gfx1036"
+
+; GFX11: .amdgcn_target "amdgpu11-amd-amdhsa-unknown-gfx11-generic"
+; GFX1100: .amdgcn_target "amdgpu11.00-amd-amdhsa-unknown-gfx1100"
+; GFX1101: .amdgcn_target "amdgpu11.01-amd-amdhsa-unknown-gfx1101"
+; GFX1102: .amdgcn_target "amdgpu11.02-amd-amdhsa-unknown-gfx1102"
+; GFX1103: .amdgcn_target "amdgpu11.03-amd-amdhsa-unknown-gfx1103"
+
+; GFX1150: .amdgcn_target "amdgpu11.50-amd-amdhsa-unknown-gfx1150"
+; GFX1151: .amdgcn_target "amdgpu11.51-amd-amdhsa-unknown-gfx1151"
+; GFX1152: .amdgcn_target "amdgpu11.52-amd-amdhsa-unknown-gfx1152"
+; GFX1153: .amdgcn_target "amdgpu11.53-amd-amdhsa-unknown-gfx1153"
+; GFX1154: .amdgcn_target "amdgpu11.54-amd-amdhsa-unknown-gfx1154"
+
+; GFX11_7: .amdgcn_target "amdgpu11.7-amd-amdhsa-unknown-gfx1170"
+; GFX1170: .amdgcn_target "amdgpu11.70-amd-amdhsa-unknown-gfx1170"
+; GFX1171: .amdgcn_target "amdgpu11.71-amd-amdhsa-unknown-gfx1171"
+; GFX1172: .amdgcn_target "amdgpu11.72-amd-amdhsa-unknown-gfx1172"
+
+; GFX12: .amdgcn_target "amdgpu12-amd-amdhsa-unknown-gfx12-generic"
+; GFX1200: .amdgcn_target "amdgpu12.00-amd-amdhsa-unknown-gfx1200"
+; GFX1201: .amdgcn_target "amdgpu12.01-amd-amdhsa-unknown-gfx1201"
+
+; GFX12_5: .amdgcn_target "amdgpu12.5-amd-amdhsa-unknown-gfx12-5-generic"
+; GFX1250: .amdgcn_target "amdgpu12.50-amd-amdhsa-unknown-gfx1250"
+; GFX1251: .amdgcn_target "amdgpu12.51-amd-amdhsa-unknown-gfx1251"
+
+; GFX13: .amdgcn_target "amdgpu13-amd-amdhsa-unknown-gfx1310"
+; GFX1310: .amdgcn_target "amdgpu13.10-amd-amdhsa-unknown-gfx1310"
+
+define amdgpu_kernel void @foo() {
+ ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/validate-subtarget-subarch-empty-module.ll b/llvm/test/CodeGen/AMDGPU/validate-subtarget-subarch-empty-module.ll
new file mode 100644
index 0000000000000..97f4695a681f2
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/validate-subtarget-subarch-empty-module.ll
@@ -0,0 +1,10 @@
+; Make sure we still diagose invalid cpu for the subarch even if there
+; are no functions in the module. This differs from
+; validate-subtarget-subarch.ll in that a subtarget is never
+; constructed.
+
+; RUN: not llc -mtriple=amdgpu9 -mcpu=gfx1030 -filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s
+; RUN: not llc -mtriple=amdgpu12345 -mcpu=gfx600 -filetype=null %s 2>&1 | FileCheck -check-prefix=UNKNOWN-SUBARCH %s
+
+; ERR: LLVM ERROR: invalid cpu 'gfx1030' for subarch amdgpu9
+; UNKNOWN-SUBARCH: LLVM ERROR: unknown subarch amdgpu12345
diff --git a/llvm/test/CodeGen/AMDGPU/validate-subtarget-subarch.ll b/llvm/test/CodeGen/AMDGPU/validate-subtarget-subarch.ll
new file mode 100644
index 0000000000000..445e1858f70d5
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/validate-subtarget-subarch.ll
@@ -0,0 +1,47 @@
+; RUN: llc -mtriple=amdgpu6 -mcpu=gfx600 -filetype=null %s
+; RUN: llc -mtriple=amdgpu6.00 -mcpu=gfx600 -filetype=null %s
+; RUN: llc -mtriple=amdgpu9 -mcpu=gfx900 -filetype=null %s
+; RUN: llc -mtriple=amdgpu9.0a -mcpu=gfx90a -filetype=null %s
+; RUN: llc -mtriple=amdgpu9.08 -mcpu=gfx908 -filetype=null %s
+; RUN: llc -mtriple=amdgpu9.4 -mcpu=gfx950 -filetype=null %s
+; RUN: llc -mtriple=amdgpu11 -mcpu=gfx1100 -filetype=null %s
+; RUN: llc -mtriple=amdgpu11.7 -mcpu=gfx1170 -filetype=null %s
+
+; Test legacy missing subarch
+; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -filetype=null %s
+; RUN: llc -mtriple=amdgpu -mcpu=gfx950 -filetype=null %s
+; RUN: llc -mtriple=amdgpu -mcpu=gfx600 -filetype=null %s
+
+; RUN: llc -mtriple=amdgpu9 -mcpu=invalid -filetype=null %s 2>&1 | FileCheck -check-prefix=INVALID-MCPU-VALID-SUBARCH %s
+
+; RUN: sed 's/TARGET_CPU/invalid/g' < %s | llc -mtriple=amdgpu12.50-amd-amdhsa -filetype=null 2>&1 | FileCheck -check-prefix=INVALID-MCPU-VALID-SUBARCH %s
+; RUN: sed 's/TARGET_CPU/invalid/g' < %s | llc -mtriple=amdgpu12.51-amd-amdhsa -filetype=null 2>&1 | FileCheck -check-prefix=INVALID-MCPU-VALID-SUBARCH %s
+; RUN: sed 's/TARGET_CPU/gfx900/g'< %s | not llc -mtriple=amdgpu12345 -filetype=null 2>&1 | FileCheck -check-prefix=INVALID-SUBARCH-VALID-MCPU %s
+
+; RUN: sed 's/TARGET_CPU/gfx601/g' < %s | not llc -mtriple=amdgpu6.00 -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
+; RUN: sed 's/TARGET_CPU/gfx600/g' < %s | not llc -mtriple=amdgpu6.01 -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
+; RUN: sed 's/TARGET_CPU/gfx600/g' < %s | not llc -mtriple=amdgpu7 -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
+; RUN: sed 's/TARGET_CPU/gfx810/g' < %s | not llc -mtriple=amdgpu8.03 -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
+; RUN: sed 's/TARGET_CPU/gfx810/g' < %s | not llc -mtriple=amdgpu8 -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
+; RUN: sed 's/TARGET_CPU/gfx942/g' < %s | not llc -mtriple=amdgpu9 -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
+; RUN: sed 's/TARGET_CPU/gfx900/g' < %s | not llc -mtriple=amdgpu9.4 -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
+; RUN: sed 's/TARGET_CPU/gfx1030/g' < %s | not llc -mtriple=amdgpu9.4 -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
+; RUN: sed 's/TARGET_CPU/gfx900/g' < %s | not llc -mtriple=amdgpu9.08 -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
+; RUN: sed 's/TARGET_CPU/gfx90a/g' < %s | not llc -mtriple=amdgpu9 -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
+; RUN: sed 's/TARGET_CPU/gfx908/g' < %s | not llc -mtriple=amdgpu9 -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
+; RUN: sed 's/TARGET_CPU/gfx1170/g' < %s | not llc -mtriple=amdgpu11 -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
+; RUN: sed 's/TARGET_CPU/gfx1100/g' < %s | not llc -mtriple=amdgpu11.7 -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
+
+; Check that subtargets not covered by the subarch are rejected. This
+; tests the error on subtarget construction, which is different from
+; the error on TargetMachine construction.
+
+
+; INVALID-MCPU: error: invalid subtarget 'invalid' for subarch amdgpu{{[0-9.]+}}
+; INVALID-SUBARCH-VALID-MCPU: LLVM ERROR: unknown subarch amdgpu12345
+; INVALID-MCPU-VALID-SUBARCH: 'invalid' is not a recognized processor for this target (ignoring processor)
+
+; ERR: error: invalid subtarget 'gfx{{.+}}' for subarch amdgpu{{[0-9.]+}}
+define amdgpu_kernel void @foo() "target-cpu"="TARGET_CPU" {
+ ret void
+}
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/init-whole.wave.ll b/llvm/test/CodeGen/MIR/AMDGPU/init-whole.wave.ll
index f3b8deff61918..92ba0e548caa9 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/init-whole.wave.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/init-whole.wave.ll
@@ -1,5 +1,5 @@
-; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1100 -stop-after=finalize-isel < %s | FileCheck --check-prefix=GCN %s
-; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1100 -stop-after=finalize-isel < %s | FileCheck --check-prefix=GCN %s
+; RUN: llc -global-isel=0 -march=amdgpu -mcpu=gfx1100 -stop-after=finalize-isel < %s | FileCheck --check-prefix=GCN %s
+; RUN: llc -global-isel=1 -march=amdgpu -mcpu=gfx1100 -stop-after=finalize-isel < %s | FileCheck --check-prefix=GCN %s
; GCN-LABEL: name: init_wwm
; GCN: hasInitWholeWave: true
diff --git a/llvm/test/Linker/Inputs/amdgpu-amdpal-no-subarch.ll b/llvm/test/Linker/Inputs/amdgpu-amdpal-no-subarch.ll
new file mode 100644
index 0000000000000..e254233d258e7
--- /dev/null
+++ b/llvm/test/Linker/Inputs/amdgpu-amdpal-no-subarch.ll
@@ -0,0 +1,5 @@
+target triple = "amdgpu-amd-amdpal"
+
+define i32 @foo() {
+ ret i32 3
+}
diff --git a/llvm/test/Linker/Inputs/amdgpu-no-subarch.ll b/llvm/test/Linker/Inputs/amdgpu-no-subarch.ll
new file mode 100644
index 0000000000000..03e1e03338486
--- /dev/null
+++ b/llvm/test/Linker/Inputs/amdgpu-no-subarch.ll
@@ -0,0 +1,5 @@
+target triple = "amdgpu-amd-amdhsa"
+
+define i32 @foo() {
+ ret i32 3
+}
diff --git a/llvm/test/Linker/Inputs/amdgpu10-subarch.ll b/llvm/test/Linker/Inputs/amdgpu10-subarch.ll
new file mode 100644
index 0000000000000..e8234f059c4a4
--- /dev/null
+++ b/llvm/test/Linker/Inputs/amdgpu10-subarch.ll
@@ -0,0 +1,5 @@
+target triple = "amdgpu10-amd-amdhsa"
+
+define i32 @foo() {
+ ret i32 10
+}
diff --git a/llvm/test/Linker/Inputs/amdgpu9.00-subarch.ll b/llvm/test/Linker/Inputs/amdgpu9.00-subarch.ll
new file mode 100644
index 0000000000000..c4bc4518a3038
--- /dev/null
+++ b/llvm/test/Linker/Inputs/amdgpu9.00-subarch.ll
@@ -0,0 +1,5 @@
+target triple = "amdgpu9.00-amd-amdhsa"
+
+define i32 @foo() {
+ ret i32 10
+}
diff --git a/llvm/test/Linker/amdgpu-triple-os-mismatch.ll b/llvm/test/Linker/amdgpu-triple-os-mismatch.ll
new file mode 100644
index 0000000000000..64c46cc4f3cab
--- /dev/null
+++ b/llvm/test/Linker/amdgpu-triple-os-mismatch.ll
@@ -0,0 +1,19 @@
+; RUN: llvm-link -S %s %S/Inputs/amdgpu-amdpal-no-subarch.ll -o %t0.ll 2>&1 | FileCheck -check-prefix=WARN_A %s
+; RUN: llvm-link -S %S/Inputs/amdgpu-amdpal-no-subarch.ll %s -o %t1.ll 2>&1 | FileCheck -check-prefix=WARN_B %s
+; RUN: FileCheck -check-prefix=LINKED0 %s < %t0.ll
+; RUN: FileCheck -check-prefix=LINKED1 %s < %t1.ll
+
+; WARN_A: warning: Linking two modules of different target triples: '{{.*}}' is 'amdgpu-amd-amdpal' whereas 'llvm-link' is 'amdgpu9-amd-amdhsa'
+; WARN_B: warning: Linking two modules of different target triples: '{{.*}}' is 'amdgpu9-amd-amdhsa' whereas 'llvm-link' is 'amdgpu-amd-amdpal'
+
+; LINKED0: target triple = "amdgpu9-amd-amdhsa"
+; LINKED1: target triple = "amdgpu-amd-amdpal"
+
+target triple = "amdgpu9-amd-amdhsa"
+
+declare i32 @foo()
+
+define i32 @bar() {
+ %x = call i32 @foo()
+ ret i32 %x
+}
diff --git a/llvm/test/Linker/amdgpu-triple-subarch.ll b/llvm/test/Linker/amdgpu-triple-subarch.ll
new file mode 100644
index 0000000000000..1a66fe6fbde22
--- /dev/null
+++ b/llvm/test/Linker/amdgpu-triple-subarch.ll
@@ -0,0 +1,42 @@
+
+; Merge amdgpu + amdgpu9 => amdgpu9 without a warning.
+; RUN: llvm-link -S %s %S/Inputs/amdgpu-no-subarch.ll -o %t0.ll 2>&1 | FileCheck --allow-empty -check-prefix=NO-WARN %s
+; RUN: llvm-link -S %S/Inputs/amdgpu-no-subarch.ll %s -o %t1.ll 2>&1 | FileCheck --allow-empty -check-prefix=NO-WARN %s
+; RUN: FileCheck -check-prefix=LINKED0 %s < %t0.ll
+; RUN: FileCheck -check-prefix=LINKED0 %s < %t1.ll
+
+; Invalid merge of amdgpu9 + amdgpu10, but the second triple wins and a warning is produced
+; RUN: llvm-link -S %s %S/Inputs/amdgpu10-subarch.ll -o %t2.ll 2>&1 | FileCheck -check-prefix=WARN_A %s
+; RUN: llvm-link -S %S/Inputs/amdgpu10-subarch.ll %s -o %t3.ll 2>&1 | FileCheck -check-prefix=WARN_B %s
+; RUN: FileCheck -check-prefix=LINKED1 %s < %t2.ll
+; RUN: FileCheck -check-prefix=LINKED2 %s < %t3.ll
+
+; Merge amdgpu9 + amdgpu9.00 = amdgpu9.00, and do not warn.
+; RUN: llvm-link -S %s %S/Inputs/amdgpu9.00-subarch.ll -o %t4.ll 2>&1 | FileCheck --allow-empty -check-prefix=NO-WARN %s
+; RUN: llvm-link -S %S/Inputs/amdgpu9.00-subarch.ll %s -o %t5.ll 2>&1 | FileCheck --allow-empty -check-prefix=NO-WARN %s
+; RUN: FileCheck -check-prefix=LINKED3 %s < %t4.ll
+; RUN: FileCheck -check-prefix=LINKED3 %s < %t5.ll
+
+; NO-WARN: {{^$}}
+
+; LINKED0: target triple = "amdgpu9-amd-amdhsa"
+; LINKED1: target triple = "amdgpu9-amd-amdhsa"
+; LINKED2: target triple = "amdgpu10-amd-amdhsa"
+; LINKED3: target triple = "amdgpu9.00-amd-amdhsa"
+
+; Check that there is no warning when linking an amdgpu triple without
+; a subarch with one with a subarch.
+
+
+; WARN_A: warning: Linking two modules of different target triples: '{{.*}}' is 'amdgpu10-amd-amdhsa' whereas 'llvm-link' is 'amdgpu9-amd-amdhsa'
+; WARN_B: warning: Linking two modules of different target triples: '{{.*}}' is 'amdgpu9-amd-amdhsa' whereas 'llvm-link' is 'amdgpu10-amd-amdhsa'
+
+
+target triple = "amdgpu9-amd-amdhsa"
+
+declare i32 @foo()
+
+define i32 @bar() {
+ %x = call i32 @foo()
+ ret i32 %x
+}
diff --git a/llvm/test/MC/AMDGPU/amd-amdgpu-isa-malformed-target-id.s b/llvm/test/MC/AMDGPU/amd-amdgpu-isa-malformed-target-id.s
index efce3612f0300..c88e9e464cf8c 100644
--- a/llvm/test/MC/AMDGPU/amd-amdgpu-isa-malformed-target-id.s
+++ b/llvm/test/MC/AMDGPU/amd-amdgpu-isa-malformed-target-id.s
@@ -1,5 +1,5 @@
// RUN: not llvm-mc -triple amdgcn-amd-unknown -mcpu=gfx900 %s 2>&1 | FileCheck %s
// Test malformed target ID error handling in .amd_amdgpu_isa directive
-// CHECK: [[#@LINE+1]]:17: error: malformed target id
+// CHECK: [[#@LINE+1]]:17: error: malformed target id 'not-a-valid-target-id'
.amd_amdgpu_isa "not-a-valid-target-id"
diff --git a/llvm/test/MC/AMDGPU/amdgcn-target-directive-subarch-cpu-field.s b/llvm/test/MC/AMDGPU/amdgcn-target-directive-subarch-cpu-field.s
new file mode 100644
index 0000000000000..98613f2bafb4d
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/amdgcn-target-directive-subarch-cpu-field.s
@@ -0,0 +1,58 @@
+// RUN: split-file %s %t
+// RUN: llvm-mc -triple amdgpu12.50-amd-amdhsa %t/amdhsa.s | FileCheck --check-prefix=AMDHSA %s
+// RUN: not llvm-mc -triple amdgpu12.5-amd-amdhsa --amdhsa-code-object-version=6 %t/amdhsa-generic-subarch-cpu.s -filetype=null 2>&1 | FileCheck --check-prefix=AMDHSA-GENERIC-SUBARCH %s
+// RUN: llvm-mc -triple amdgpu12.50-amd-amdpal %t/amdpal.s | FileCheck --check-prefix=AMDPAL %s
+// RUN: not llvm-mc -triple amdgpu12.5-amd-amdpal --amdhsa-code-object-version=6 %t/amdpal-generic-subarch-cpu.s -filetype=null 2>&1 | FileCheck --check-prefix=AMDPAL-GENERIC-SUBARCH %s
+// RUN: llvm-mc -triple amdgpu12.50-amd-amdhsa %t/cpu.s | FileCheck --check-prefix=AMDHSA %s
+// RUN: not llvm-mc -triple amdgpu12.50-amd-amdhsa %t/subarch-mismatch.s -filetype=null 2>&1 | FileCheck --check-prefix=ERR %s
+// RUN: not llvm-mc -triple amdgpu12.50-amd-amdhsa %t/cpu-not-covered.s -filetype=null 2>&1 | FileCheck --check-prefix=NOTCOVERED %s
+// RUN: not llvm-mc -triple amdgpu12.50-amd-amdhsa %t/cpu-not-covered-same-major.s -filetype=null 2>&1 | FileCheck --check-prefix=NOTCOVERED-SAME-MAJOR %s
+// RUN: not llvm-mc -triple amdgpu12.50-amd-amdpal %t/isa-cpu-not-covered.s -filetype=null 2>&1 | FileCheck --check-prefix=ISA-NOTCOVERED %s
+
+// Check how the CPU field is validated against the triple
+// subarch. The processor name field may be empty, but if it's not it
+// must be compatible with triple's subarch.
+
+//--- amdhsa.s
+// AMDHSA: .amdgcn_target "amdgpu12.50-amd-amdhsa-unknown-gfx1250"
+.amdgcn_target "amdgpu12.50-amd-amdhsa-unknown-"
+
+//--- amdhsa-generic-subarch-cpu.s
+// FIXME: This should be accepted and passed through as-is
+// AMDHSA-GENERIC-SUBARCH: error: .amdgcn_target directive's target id amdgpu12.5-amd-amdhsa-unknown-gfx1251 does not match the specified target id amdgpu12.5-amd-amdhsa-unknown-gfx12-5-generic
+.amdgcn_target "amdgpu12.5-amd-amdhsa-unknown-gfx1251"
+
+//--- amdpal.s
+// AMDPAL: .amd_amdgpu_isa "amdgpu12.50-amd-amdpal-unknown-gfx1250"
+.amd_amdgpu_isa "amdgpu12.50-amd-amdpal-unknown-"
+
+//--- amdpal-generic-subarch-cpu.s
+// FIXME: This should be accepted and passed through as-is
+// AMDPAL-GENERIC-SUBARCH: error: .amd_amdgpu_isa directive's target id amdgpu12.5-amd-amdpal-unknown-gfx1251 does not match the specified target id amdgpu12.5-amd-amdpal-unknown-gfx12-5-generic
+.amd_amdgpu_isa "amdgpu12.5-amd-amdpal-unknown-gfx1251"
+
+//--- cpu.s
+// A processor covered by the subarch is accepted.
+.amdgcn_target "amdgpu12.50-amd-amdhsa-unknown-gfx1250"
+
+//--- subarch-mismatch.s
+// A target id whose subarch conflicts with the triple is rejected: the subarch
+// resolves to a processor that is not valid for the triple's subarch.
+// ERR: {{.*}}: error: target id 'amdgpu9.00-amd-amdhsa-unknown-' specifies a processor that is not valid for subarch 'amdgpu12.50'
+.amdgcn_target "amdgpu9.00-amd-amdhsa-unknown-"
+
+//--- cpu-not-covered.s
+// A processor not covered by the triple's subarch is rejected.
+// NOTCOVERED: {{.*}}: error: target id 'amdgpu12.50-amd-amdhsa-unknown-gfx900' specifies a processor that is not valid for subarch 'amdgpu12.50'
+.amdgcn_target "amdgpu12.50-amd-amdhsa-unknown-gfx900"
+
+//--- cpu-not-covered-same-major.s
+// A sibling processor sharing the major subarch (gfx1251 and gfx1250 are both
+// gfx12.5) is still not covered by a specific subarch (amdgpu12.50).
+// NOTCOVERED-SAME-MAJOR: {{.*}}: error: target id 'amdgpu12.50-amd-amdhsa-unknown-gfx1251' specifies a processor that is not valid for subarch 'amdgpu12.50'
+.amdgcn_target "amdgpu12.50-amd-amdhsa-unknown-gfx1251"
+
+//--- isa-cpu-not-covered.s
+// The same check applies to .amd_amdgpu_isa.
+// ISA-NOTCOVERED: {{.*}}: error: target id 'amdgpu12.50-amd-amdpal-unknown-gfx900' specifies a processor that is not valid for subarch 'amdgpu12.50'
+.amd_amdgpu_isa "amdgpu12.50-amd-amdpal-unknown-gfx900"
diff --git a/llvm/test/MC/AMDGPU/amdgcn-target-malformed-target-id.s b/llvm/test/MC/AMDGPU/amdgcn-target-malformed-target-id.s
index d4f89b5ac0142..000ece52ab701 100644
--- a/llvm/test/MC/AMDGPU/amdgcn-target-malformed-target-id.s
+++ b/llvm/test/MC/AMDGPU/amdgcn-target-malformed-target-id.s
@@ -1,5 +1,5 @@
// RUN: not llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx900 %s -filetype=null 2>&1 | FileCheck %s
// Test malformed target ID error handling in .amdgcn_target directive
-// CHECK: [[#@LINE+1]]:16: error: malformed target ID
+// CHECK: [[#@LINE+1]]:16: error: malformed target id 'not-a-valid-target-id'
.amdgcn_target "not-a-valid-target-id"
diff --git a/llvm/test/MC/AMDGPU/amdgcn_target_directive_from_eflags.s b/llvm/test/MC/AMDGPU/amdgcn_target_directive_from_eflags.s
index 8a91985909ed8..451dc4aa0a5a8 100644
--- a/llvm/test/MC/AMDGPU/amdgcn_target_directive_from_eflags.s
+++ b/llvm/test/MC/AMDGPU/amdgcn_target_directive_from_eflags.s
@@ -43,30 +43,30 @@
// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-sramecc -filetype=obj %s -o %t-sramecc-off-only.o
// RUN: llvm-objdump --disassemble-all %t-sramecc-off-only.o | FileCheck --check-prefix=CHECK-SRAMECC-OFF-ONLY %s
-// CHECK-GFX900: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx900"
+// CHECK-GFX900: .amdgcn_target "amdgpu-amd-amdhsa-unknown-gfx900"
-// CHECK-GFX908: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx908"
+// CHECK-GFX908: .amdgcn_target "amdgpu-amd-amdhsa-unknown-gfx908"
-// CHECK-GFX1010: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx1010"
+// CHECK-GFX1010: .amdgcn_target "amdgpu-amd-amdhsa-unknown-gfx1010"
-// CHECK-GFX1100: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx1100"
+// CHECK-GFX1100: .amdgcn_target "amdgpu-amd-amdhsa-unknown-gfx1100"
-// CHECK-GFX1200: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx1200"
+// CHECK-GFX1200: .amdgcn_target "amdgpu-amd-amdhsa-unknown-gfx1200"
-// CHECK-DEFAULT: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx908"
+// CHECK-DEFAULT: .amdgcn_target "amdgpu-amd-amdhsa-unknown-gfx908"
-// CHECK-BOTH-ON: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx908:sramecc+:xnack+"
+// CHECK-BOTH-ON: .amdgcn_target "amdgpu-amd-amdhsa-unknown-gfx908:sramecc+:xnack+"
-// CHECK-BOTH-OFF: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx908:sramecc-:xnack-"
+// CHECK-BOTH-OFF: .amdgcn_target "amdgpu-amd-amdhsa-unknown-gfx908:sramecc-:xnack-"
-// CHECK-XNACK-ON: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx908:sramecc-:xnack+"
+// CHECK-XNACK-ON: .amdgcn_target "amdgpu-amd-amdhsa-unknown-gfx908:sramecc-:xnack+"
-// CHECK-SRAMECC-ON: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx908:sramecc+:xnack-"
+// CHECK-SRAMECC-ON: .amdgcn_target "amdgpu-amd-amdhsa-unknown-gfx908:sramecc+:xnack-"
-// CHECK-XNACK-ONLY: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx908:xnack+"
+// CHECK-XNACK-ONLY: .amdgcn_target "amdgpu-amd-amdhsa-unknown-gfx908:xnack+"
-// CHECK-XNACK-OFF-ONLY: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx908:xnack-"
+// CHECK-XNACK-OFF-ONLY: .amdgcn_target "amdgpu-amd-amdhsa-unknown-gfx908:xnack-"
-// CHECK-SRAMECC-ONLY: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx908:sramecc+"
+// CHECK-SRAMECC-ONLY: .amdgcn_target "amdgpu-amd-amdhsa-unknown-gfx908:sramecc+"
-// CHECK-SRAMECC-OFF-ONLY: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx908:sramecc-"
+// CHECK-SRAMECC-OFF-ONLY: .amdgcn_target "amdgpu-amd-amdhsa-unknown-gfx908:sramecc-"
diff --git a/llvm/test/MC/AMDGPU/arch-amdgcn-legacy-arch-name.s b/llvm/test/MC/AMDGPU/arch-amdgcn-legacy-arch-name.s
new file mode 100644
index 0000000000000..445c319871dca
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/arch-amdgcn-legacy-arch-name.s
@@ -0,0 +1,7 @@
+# The architecture name was renamed from "amdgcn" to "amdgpu". Check that the
+# legacy "amdgcn" name still works when passed via -arch.
+
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+
+# CHECK: s_nop 0 ; encoding: [0x00,0x00,0x80,0xbf]
+s_nop 0
diff --git a/llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml b/llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
index 9975a52a6c68e..2a24c2d438e7f 100644
--- a/llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
+++ b/llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
@@ -366,7 +366,7 @@
# ELF-AMDGCN-ALL: Format: elf64-amdgpu
-# ELF-AMDGCN-ALL: Arch: amdgcn
+# ELF-AMDGCN-ALL: Arch: amdgpu
# ELF-AMDGCN-ALL: AddressSize: 64bit
# ELF-AMDGCN-ALL: Flags [
diff --git a/llvm/test/Object/AMDGPU/objdump.s b/llvm/test/Object/AMDGPU/objdump.s
index 07823b8323692..6f671a69a8df9 100644
--- a/llvm/test/Object/AMDGPU/objdump.s
+++ b/llvm/test/Object/AMDGPU/objdump.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple=amdgcn -mcpu=tonga %s -filetype=obj | llvm-objdump -d --arch-name=amdgcn --mcpu=tonga - | FileCheck %s
+// RUN: llvm-mc -triple=amdgpu -mcpu=tonga %s -filetype=obj | llvm-objdump -d --arch-name=amdgpu --mcpu=tonga - | FileCheck %s
.text
diff --git a/llvm/test/tools/llvm-objdump/AMDGPU/arch-amdgcn-legacy-arch-name.s b/llvm/test/tools/llvm-objdump/AMDGPU/arch-amdgcn-legacy-arch-name.s
new file mode 100644
index 0000000000000..041d725698e59
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/AMDGPU/arch-amdgcn-legacy-arch-name.s
@@ -0,0 +1,8 @@
+# The architecture name was renamed from "amdgcn" to "amdgpu". Check that the
+# legacy "amdgcn" name still works when passed via --arch-name.
+
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -filetype=obj %s -o %t.o
+# RUN: llvm-objdump -d --arch-name=amdgcn --mcpu=gfx900 %t.o | FileCheck %s
+
+# CHECK: s_nop 0
+s_nop 0
diff --git a/llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx10.s b/llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx10.s
index a492291fabef9..bc16708dcd647 100644
--- a/llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx10.s
+++ b/llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx10.s
@@ -17,7 +17,7 @@
; OBJDUMP-NEXT: 0010 00000000 00000000 00000000 00000000
; OBJDUMP-NEXT: 0020 00000000 00000000 00000000 00000000
; OBJDUMP-NEXT: 0030 01000000 00000000 00000000 00000000
-; OBJDUMP-NEXT: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx1010:xnack-"
+; OBJDUMP-NEXT: .amdgcn_target "amdgpu-amd-amdhsa-unknown-gfx1010:xnack-"
; OBJDUMP-EMPTY:
; OBJDUMP-LABEL: Disassembly of section .text:
diff --git a/llvm/test/tools/llvm-objdump/ELF/AMDGPU/subarch-triple.s b/llvm/test/tools/llvm-objdump/ELF/AMDGPU/subarch-triple.s
new file mode 100644
index 0000000000000..56ae9fe1a2ad7
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/ELF/AMDGPU/subarch-triple.s
@@ -0,0 +1,37 @@
+## Test that llvm-objdump accepts the subtarget spelled either as a legacy
+## amdgcn triple plus an explicit --mcpu, or as an amdgpu subarch triple with
+## no --mcpu. Both forms must select the same subtarget and disassemble
+## identically.
+
+# RUN: llvm-mc -triple=amdgpu12.50-amd-amdhsa -filetype=obj -o %t.o %s
+
+## Legacy amdgcn triple + explicit cpu.
+# RUN: llvm-objdump -d --triple=amdgcn-amd-amdhsa --mcpu=gfx1250 %t.o \
+# RUN: | FileCheck --check-prefixes=DIS,DIS-AMDGCN %s
+
+## Subarch triple, no cpu: selects the same subtarget and decodes identically.
+# RUN: llvm-objdump -d --triple=amdgpu12.50-amd-amdhsa %t.o \
+# RUN: | FileCheck --check-prefixes=DIS,DIS-SUBARCH %s
+
+## No triple, just cpu: the triple is taken from the object.
+# RUN: llvm-objdump -d --mcpu=gfx1250 %t.o \
+# RUN: | FileCheck --check-prefixes=DIS,DIS-DETECT %s
+
+## No target arguments at all: both the triple and cpu are taken from the
+## object's ELF header.
+# RUN: llvm-objdump -d %t.o \
+# RUN: | FileCheck --check-prefixes=DIS,DIS-DETECT %s
+
+# DIS-AMDGCN: .amdgcn_target "amdgcn-amd-amdhsa{{ ?}}-unknown-gfx1250"
+# DIS-SUBARCH: .amdgcn_target "amdgpu12.50-amd-amdhsa-unknown-gfx1250"
+# DIS-DETECT: .amdgcn_target "amdgpu-amd-amdhsa-unknown-gfx1250"
+
+# DIS-LABEL: <kernel>:
+# DIS: s_set_vgpr_msb 0x41
+# DIS-NEXT: s_endpgm
+
+.text
+.globl kernel
+kernel:
+ s_set_vgpr_msb 0x41
+ s_endpgm
diff --git a/llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll b/llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
index df34fd13f7026..218a7e8dec159 100644
--- a/llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
+++ b/llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
@@ -7,7 +7,7 @@ define amdgpu_kernel void @test_kernel() {
; ----------------------------------GFX13--------------------------------------
;
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1310 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1310 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1310 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
;
@@ -19,32 +19,32 @@ define amdgpu_kernel void @test_kernel() {
; ----------------------------------GFX12--------------------------------------
;
; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=6 -mcpu=gfx12-generic -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn -mllvm --amdhsa-code-object-version=6 --mcpu=gfx12-generic %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu -mllvm --amdhsa-code-object-version=6 --mcpu=gfx12-generic %t.o > %t-specify.txt
; RUN: llvm-objdump -D -mllvm --amdhsa-code-object-version=6 %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
;
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1201 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1201 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1201 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
;
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1200 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1200 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=6 -mcpu=gfx12-5-generic -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn -mllvm --amdhsa-code-object-version=6 --mcpu=gfx12-5-generic %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu -mllvm --amdhsa-code-object-version=6 --mcpu=gfx12-5-generic %t.o > %t-specify.txt
; RUN: llvm-objdump -D -mllvm --amdhsa-code-object-version=6 %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1250 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1250 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1251 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1251 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1251 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
@@ -56,22 +56,22 @@ define amdgpu_kernel void @test_kernel() {
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=6 -mcpu=gfx11-generic -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn -mllvm --amdhsa-code-object-version=6 --mcpu=gfx11-generic %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu -mllvm --amdhsa-code-object-version=6 --mcpu=gfx11-generic %t.o > %t-specify.txt
; RUN: llvm-objdump -D -mllvm --amdhsa-code-object-version=6 %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1172 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1172 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1172 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1171 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1171 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1171 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1170 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1170 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1170 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
@@ -81,108 +81,108 @@ define amdgpu_kernel void @test_kernel() {
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1153 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1153 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1153 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1152 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1152 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1152 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1151 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1151 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1151 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1150 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1150 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1150 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1103 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1103 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1103 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1102 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1102 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1102 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1101 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1101 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1101 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1100 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1100 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; ----------------------------------GFX10--------------------------------------
; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=6 -mcpu=gfx10-3-generic -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn -mllvm --amdhsa-code-object-version=6 --mcpu=gfx10-3-generic %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu -mllvm --amdhsa-code-object-version=6 --mcpu=gfx10-3-generic %t.o > %t-specify.txt
; RUN: llvm-objdump -D -mllvm --amdhsa-code-object-version=6 %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1036 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1036 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1036 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1035 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1035 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1035 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1034 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1034 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1034 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1033 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1033 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1033 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1032 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1032 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1032 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1031 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1031 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1030 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1030 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=6 -mcpu=gfx10-1-generic -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn -mllvm --amdhsa-code-object-version=6 --mcpu=gfx10-1-generic %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu -mllvm --amdhsa-code-object-version=6 --mcpu=gfx10-1-generic %t.o > %t-specify.txt
; RUN: llvm-objdump -D -mllvm --amdhsa-code-object-version=6 %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1013 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1013 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1013 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1012 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1012 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1012 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1011 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1011 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1011 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1010 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx1010 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
@@ -190,62 +190,62 @@ define amdgpu_kernel void @test_kernel() {
; ----------------------------------GFX9---------------------------------------
;
; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=6 -mcpu=gfx9-4-generic -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn -mllvm --amdhsa-code-object-version=6 --mcpu=gfx9-4-generic %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu -mllvm --amdhsa-code-object-version=6 --mcpu=gfx9-4-generic %t.o > %t-specify.txt
; RUN: llvm-objdump -D -mllvm --amdhsa-code-object-version=6 %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=6 -mcpu=gfx9-generic -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn -mllvm --amdhsa-code-object-version=6 --mcpu=gfx9-generic %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu -mllvm --amdhsa-code-object-version=6 --mcpu=gfx9-generic %t.o > %t-specify.txt
; RUN: llvm-objdump -D -mllvm --amdhsa-code-object-version=6 %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx950 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx950 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx942 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx942 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90c -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx90c %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx90c %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx90a %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx90a %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx909 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx909 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx909 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx908 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx908 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx906 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx906 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx904 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx904 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx904 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx902 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx902 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx902 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx900 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx900 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
@@ -253,21 +253,21 @@ define amdgpu_kernel void @test_kernel() {
; ----------------------------------GFX8---------------------------------------
;
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx810 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx810 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx810 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx803 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx803 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx802 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx802 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx801 -filetype=obj -O0 -o %t.o %s
-; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx801 %t.o > %t-specify.txt
+; RUN: llvm-objdump -D --arch-name=amdgpu --mcpu=gfx801 %t.o > %t-specify.txt
; RUN: llvm-objdump -D %t.o > %t-detect.txt
; RUN: diff %t-specify.txt %t-detect.txt
diff --git a/llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test b/llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
index 848d9784025df..c802aed428631 100644
--- a/llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
+++ b/llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
@@ -538,7 +538,7 @@ FileHeader:
# ALL: File: [[FILE]]
# ALL-NEXT: Format: elf64-amdgpu
-# ALL-NEXT: Arch: amdgcn
+# ALL-NEXT: Arch: amdgpu
# ALL-NEXT: AddressSize: 64bit
# ALL-NEXT: LoadName: <Not found>
# ALL-NEXT: ElfHeader {
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index daebae588cfff..7074c8af696e2 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -1122,7 +1122,7 @@ PrettyPrinter &selectPrettyPrinter(Triple const &Triple) {
return PrettyPrinterInst;
case Triple::hexagon:
return HexagonPrettyPrinterInst;
- case Triple::amdgcn:
+ case Triple::amdgpu:
return AMDGCNPrettyPrinterInst;
case Triple::bpfel:
case Triple::bpfeb:
@@ -2137,7 +2137,7 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
unwrapOrError(Section.getContents(), Obj.getFileName()));
std::vector<std::unique_ptr<std::string>> SynthesizedLabelNames;
- if (Obj.isELF() && Obj.getArch() == Triple::amdgcn) {
+ if (Obj.isELF() && Obj.getArch() == Triple::amdgpu) {
// AMDGPU disassembler uses symbolizer for printing labels
addSymbolizer(*DT->Context, DT->TheTarget, DT->TheTriple,
DT->DisAsm.get(), SectionAddr, Bytes, Symbols,
diff --git a/llvm/unittests/Object/ELFObjectFileTest.cpp b/llvm/unittests/Object/ELFObjectFileTest.cpp
index 6113bae63828f..f30aaa1e96afa 100644
--- a/llvm/unittests/Object/ELFObjectFileTest.cpp
+++ b/llvm/unittests/Object/ELFObjectFileTest.cpp
@@ -287,7 +287,7 @@ TEST(ELFObjectFileTest, MachineTestForXtensa) {
TEST(ELFObjectFileTest, CheckOSAndTriple) {
std::tuple<uint16_t, uint8_t, StringRef> Formats[] = {
- {ELF::EM_AMDGPU, ELF::ELFOSABI_AMDGPU_HSA, "amdgcn-amd-amdhsa"},
+ {ELF::EM_AMDGPU, ELF::ELFOSABI_AMDGPU_HSA, "amdgpu-amd-amdhsa"},
{ELF::EM_X86_64, ELF::ELFOSABI_LINUX, "x86_64--linux"},
{ELF::EM_X86_64, ELF::ELFOSABI_NETBSD, "x86_64--netbsd"},
{ELF::EM_X86_64, ELF::ELFOSABI_HURD, "x86_64--hurd"},
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 61da68940d9a1..3a949b4048154 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -8,6 +8,7 @@
#include "llvm/TargetParser/TargetParser.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringRef.h"
@@ -15,6 +16,7 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/FormatVariadic.h"
#include "llvm/TargetParser/AArch64TargetParser.h"
+#include "llvm/TargetParser/AMDGPUTargetParser.h"
#include "llvm/TargetParser/ARMTargetParser.h"
#include "llvm/TargetParser/ARMTargetParserCommon.h"
#include "llvm/TargetParser/Triple.h"
@@ -2363,4 +2365,419 @@ TEST(TargetParserTest, checkFindSinglePrecisionFPU) {
}
}
+TEST(TargetParserTest, testAMDGPUArch) {
+ EXPECT_EQ(Triple("amdgpu--").getArch(), Triple::amdgpu);
+ EXPECT_EQ(Triple("amdgpu--").getSubArch(), Triple::NoSubArch);
+ EXPECT_EQ(Triple("amdgpu0--").getSubArch(), Triple::NoSubArch);
+ EXPECT_EQ(Triple("amdgpufoo--").getSubArch(), Triple::NoSubArch);
+
+ {
+ EXPECT_EQ(Triple("amdgpu6--").getSubArch(), Triple::AMDGPUSubArch6);
+ EXPECT_EQ(Triple("amdgpu6.0").getSubArch(), Triple::NoSubArch); // Unknown
+ EXPECT_EQ(Triple("amdgpu6.00").getSubArch(), Triple::AMDGPUSubArch600);
+ EXPECT_EQ(Triple("amdgpu6.01").getSubArch(), Triple::AMDGPUSubArch601);
+ EXPECT_EQ(Triple("amdgpu6.02").getSubArch(), Triple::AMDGPUSubArch602);
+ EXPECT_EQ(Triple("amdgpu6.03").getSubArch(), Triple::NoSubArch); // Unknown
+ EXPECT_EQ(Triple("amdgpu60").getSubArch(), Triple::NoSubArch); // Unknown
+ }
+
+ {
+ EXPECT_EQ(Triple("amdgpu7--").getSubArch(), Triple::AMDGPUSubArch7);
+ EXPECT_EQ(Triple("amdgpu7.0--").getSubArch(), Triple::NoSubArch); // Unknown
+ EXPECT_EQ(Triple("amdgpu7.00").getSubArch(), Triple::AMDGPUSubArch700);
+ EXPECT_EQ(Triple("amdgpu7.01").getSubArch(), Triple::AMDGPUSubArch701);
+ EXPECT_EQ(Triple("amdgpu7.02").getSubArch(), Triple::AMDGPUSubArch702);
+ EXPECT_EQ(Triple("amdgpu7.03").getSubArch(), Triple::AMDGPUSubArch703);
+ EXPECT_EQ(Triple("amdgpu7.04").getSubArch(), Triple::AMDGPUSubArch704);
+ EXPECT_EQ(Triple("amdgpu7.05").getSubArch(), Triple::AMDGPUSubArch705);
+ EXPECT_EQ(Triple("amdgpu7.06").getSubArch(), Triple::NoSubArch); // Unknown
+ EXPECT_EQ(Triple("amdgpu71").getSubArch(), Triple::NoSubArch); // Unknown
+ }
+
+ {
+ EXPECT_EQ(Triple("amdgpu8--").getSubArch(), Triple::AMDGPUSubArch8);
+ EXPECT_EQ(Triple("amdgpu8.0--").getSubArch(), Triple::NoSubArch); // Unknown
+ EXPECT_EQ(Triple("amdgpu8.01--").getSubArch(), Triple::AMDGPUSubArch801);
+ EXPECT_EQ(Triple("amdgpu8.02--").getSubArch(), Triple::AMDGPUSubArch802);
+ EXPECT_EQ(Triple("amdgpu8.03--").getSubArch(), Triple::AMDGPUSubArch803);
+ EXPECT_EQ(Triple("amdgpu8.05--").getSubArch(), Triple::AMDGPUSubArch805);
+ EXPECT_EQ(Triple("amdgpu8.1--").getSubArch(), Triple::NoSubArch); // Unknown
+ EXPECT_EQ(Triple("amdgpu8.10--").getSubArch(), Triple::AMDGPUSubArch810);
+ EXPECT_EQ(Triple("amdgpu81--").getSubArch(), Triple::NoSubArch); // Unknown
+ }
+
+ {
+ EXPECT_EQ(Triple("amdgpu9--").getArch(), Triple::amdgpu);
+ EXPECT_EQ(Triple("amdgpu9--").getSubArch(), Triple::AMDGPUSubArch9);
+ EXPECT_EQ(Triple("amdgpu9.0--").getSubArch(), Triple::NoSubArch); // Unknown
+ EXPECT_EQ(Triple("amdgpu9.00--").getSubArch(), Triple::AMDGPUSubArch900);
+ EXPECT_EQ(Triple("amdgpu9.02--").getSubArch(), Triple::AMDGPUSubArch902);
+ EXPECT_EQ(Triple("amdgpu9.04--").getSubArch(), Triple::AMDGPUSubArch904);
+ EXPECT_EQ(Triple("amdgpu9.06--").getSubArch(), Triple::AMDGPUSubArch906);
+ EXPECT_EQ(Triple("amdgpu9.08--").getSubArch(), Triple::AMDGPUSubArch908);
+ EXPECT_EQ(Triple("amdgpu9.0a--").getSubArch(), Triple::AMDGPUSubArch90A);
+ EXPECT_EQ(Triple("amdgpu9.0c--").getSubArch(), Triple::AMDGPUSubArch90C);
+
+ EXPECT_EQ(Triple("amdgpu9.4--").getSubArch(), Triple::AMDGPUSubArch9_4);
+ EXPECT_EQ(Triple("amdgpu9.42--").getSubArch(), Triple::AMDGPUSubArch942);
+ EXPECT_EQ(Triple("amdgpu9.50--").getSubArch(), Triple::AMDGPUSubArch950);
+ EXPECT_EQ(Triple("amdgpu99").getSubArch(), Triple::NoSubArch); // Unknown
+ }
+
+ {
+ EXPECT_EQ(Triple("amdgpu10--").getArch(), Triple::amdgpu);
+ EXPECT_EQ(Triple("amdgpu10--").getSubArch(), Triple::AMDGPUSubArch10_1);
+ EXPECT_EQ(Triple("amdgpu10.1--").getSubArch(), Triple::AMDGPUSubArch10_1);
+ EXPECT_EQ(Triple("amdgpu10.10--").getSubArch(), Triple::AMDGPUSubArch1010);
+ EXPECT_EQ(Triple("amdgpu10.11--").getSubArch(), Triple::AMDGPUSubArch1011);
+ EXPECT_EQ(Triple("amdgpu10.12--").getSubArch(), Triple::AMDGPUSubArch1012);
+ EXPECT_EQ(Triple("amdgpu10.13--").getSubArch(), Triple::AMDGPUSubArch1013);
+ EXPECT_EQ(Triple("amdgpu101").getSubArch(), Triple::NoSubArch); // Unknown
+ }
+
+ {
+ EXPECT_EQ(Triple("amdgpu10.3--").getSubArch(), Triple::AMDGPUSubArch10_3);
+ EXPECT_EQ(Triple("amdgpu10.30--").getSubArch(), Triple::AMDGPUSubArch1030);
+ EXPECT_EQ(Triple("amdgpu10.31--").getSubArch(), Triple::AMDGPUSubArch1031);
+ EXPECT_EQ(Triple("amdgpu10.32--").getSubArch(), Triple::AMDGPUSubArch1032);
+ EXPECT_EQ(Triple("amdgpu10.33--").getSubArch(), Triple::AMDGPUSubArch1033);
+ EXPECT_EQ(Triple("amdgpu10.34--").getSubArch(), Triple::AMDGPUSubArch1034);
+ EXPECT_EQ(Triple("amdgpu10.35--").getSubArch(), Triple::AMDGPUSubArch1035);
+ EXPECT_EQ(Triple("amdgpu10.36--").getSubArch(), Triple::AMDGPUSubArch1036);
+ EXPECT_EQ(Triple("amdgpu10.39").getSubArch(), Triple::NoSubArch); // Unknown
+ }
+
+ {
+ EXPECT_EQ(Triple("amdgpu11--").getSubArch(), Triple::AMDGPUSubArch11);
+ EXPECT_EQ(Triple("amdgpu11.0--").getSubArch(),
+ Triple::NoSubArch); // Unknown
+ EXPECT_EQ(Triple("amdgpu11.00--").getSubArch(), Triple::AMDGPUSubArch1100);
+ EXPECT_EQ(Triple("amdgpu11.01--").getSubArch(), Triple::AMDGPUSubArch1101);
+ EXPECT_EQ(Triple("amdgpu11.02--").getSubArch(), Triple::AMDGPUSubArch1102);
+ EXPECT_EQ(Triple("amdgpu11.03--").getSubArch(), Triple::AMDGPUSubArch1103);
+ EXPECT_EQ(Triple("amdgpu11.5--").getSubArch(),
+ Triple::NoSubArch); // Unknown
+ EXPECT_EQ(Triple("amdgpu11.50--").getSubArch(), Triple::AMDGPUSubArch1150);
+ EXPECT_EQ(Triple("amdgpu11.51--").getSubArch(), Triple::AMDGPUSubArch1151);
+ EXPECT_EQ(Triple("amdgpu11.52--").getSubArch(), Triple::AMDGPUSubArch1152);
+ EXPECT_EQ(Triple("amdgpu11.53--").getSubArch(), Triple::AMDGPUSubArch1153);
+ EXPECT_EQ(Triple("amdgpu11.54--").getSubArch(), Triple::AMDGPUSubArch1154);
+ EXPECT_EQ(Triple("amdgpu11.7--").getSubArch(), Triple::AMDGPUSubArch11_7);
+ EXPECT_EQ(Triple("amdgpu11.70--").getSubArch(), Triple::AMDGPUSubArch1170);
+ EXPECT_EQ(Triple("amdgpu11.71--").getSubArch(), Triple::AMDGPUSubArch1171);
+ EXPECT_EQ(Triple("amdgpu11.72--").getSubArch(), Triple::AMDGPUSubArch1172);
+ EXPECT_EQ(Triple("amdgpu111--").getSubArch(), Triple::NoSubArch); // Unknown
+ }
+
+ {
+ EXPECT_EQ(Triple("amdgpu12--").getSubArch(), Triple::AMDGPUSubArch12);
+ EXPECT_EQ(Triple("amdgpu12.0--").getSubArch(),
+ Triple::NoSubArch); // Unknown
+ EXPECT_EQ(Triple("amdgpu12.00--").getSubArch(), Triple::AMDGPUSubArch1200);
+ EXPECT_EQ(Triple("amdgpu12.01--").getSubArch(), Triple::AMDGPUSubArch1201);
+ EXPECT_EQ(Triple("amdgpu12.5--").getSubArch(), Triple::AMDGPUSubArch12_5);
+ EXPECT_EQ(Triple("amdgpu12.50--").getSubArch(), Triple::AMDGPUSubArch1250);
+ EXPECT_EQ(Triple("amdgpu12.51--").getSubArch(), Triple::AMDGPUSubArch1251);
+ EXPECT_EQ(Triple("amdgpu122--").getSubArch(), Triple::NoSubArch); // Unknown
+ EXPECT_EQ(Triple("amdgpu12.59--").getSubArch(),
+ Triple::NoSubArch); // Unknown
+ }
+
+ {
+ EXPECT_EQ(Triple("amdgpu13--").getSubArch(), Triple::AMDGPUSubArch13);
+ EXPECT_EQ(Triple("amdgpu13.10--").getSubArch(), Triple::AMDGPUSubArch1310);
+ EXPECT_EQ(Triple("amdgpu13.1").getSubArch(), Triple::NoSubArch); // Unknown
+ EXPECT_EQ(Triple("amdgpu131").getSubArch(), Triple::NoSubArch); // Unknown
+ }
+}
+
+TEST(TargetParserTest, testAMDGPUgetMajorSubArch) {
+ // Make sure every subarch is handled by the function
+ for (unsigned SubArch = Triple::FirstAMDGPUSubArch;
+ SubArch <= Triple::LastAMDGPUSubArch; ++SubArch) {
+
+ EXPECT_NE(
+ AMDGPU::getMajorSubArch(static_cast<Triple::SubArchType>(SubArch)),
+ Triple::NoSubArch);
+ }
+}
+
+TEST(TargetParserTest, testAMDGPUisSubArchCompatible) {
+ // A major-family subarch is compatible with itself and with any specific
+ // subarch in its family.
+ EXPECT_TRUE(AMDGPU::isSubArchCompatible(Triple::AMDGPUSubArch9,
+ Triple::AMDGPUSubArch9));
+ EXPECT_TRUE(AMDGPU::isSubArchCompatible(Triple::AMDGPUSubArch9,
+ Triple::AMDGPUSubArch900));
+ EXPECT_TRUE(AMDGPU::isSubArchCompatible(Triple::AMDGPUSubArch900,
+ Triple::AMDGPUSubArch9));
+ EXPECT_TRUE(AMDGPU::isSubArchCompatible(Triple::AMDGPUSubArch9,
+ Triple::AMDGPUSubArch90C));
+
+ // gfx9 and gfx9.4 are distinct major families.
+ EXPECT_FALSE(AMDGPU::isSubArchCompatible(Triple::AMDGPUSubArch9,
+ Triple::AMDGPUSubArch9_4));
+ EXPECT_FALSE(AMDGPU::isSubArchCompatible(Triple::AMDGPUSubArch9,
+ Triple::AMDGPUSubArch942));
+
+ // gfx908 and gfx90a are their own major families, not part of gfx9-generic,
+ // because they have ABI-incompatible feature differences (e.g. gfx90a
+ // requires aligned VGPRs).
+ EXPECT_FALSE(AMDGPU::isSubArchCompatible(Triple::AMDGPUSubArch9,
+ Triple::AMDGPUSubArch908));
+ EXPECT_FALSE(AMDGPU::isSubArchCompatible(Triple::AMDGPUSubArch9,
+ Triple::AMDGPUSubArch90A));
+ EXPECT_TRUE(AMDGPU::isSubArchCompatible(Triple::AMDGPUSubArch90A,
+ Triple::AMDGPUSubArch90A));
+
+ // gfx11 and gfx11.7 are distinct major families.
+ EXPECT_TRUE(AMDGPU::isSubArchCompatible(Triple::AMDGPUSubArch11_7,
+ Triple::AMDGPUSubArch11_7));
+ EXPECT_TRUE(AMDGPU::isSubArchCompatible(Triple::AMDGPUSubArch11_7,
+ Triple::AMDGPUSubArch1170));
+ EXPECT_TRUE(AMDGPU::isSubArchCompatible(Triple::AMDGPUSubArch1172,
+ Triple::AMDGPUSubArch11_7));
+ EXPECT_FALSE(AMDGPU::isSubArchCompatible(Triple::AMDGPUSubArch11,
+ Triple::AMDGPUSubArch11_7));
+ EXPECT_FALSE(AMDGPU::isSubArchCompatible(Triple::AMDGPUSubArch11,
+ Triple::AMDGPUSubArch1170));
+
+ // Two specific subarches in the same family are not compatible with each
+ // other; only the major-family subarch is.
+ EXPECT_FALSE(AMDGPU::isSubArchCompatible(Triple::AMDGPUSubArch900,
+ Triple::AMDGPUSubArch90A));
+
+ // Different major families are incompatible.
+ EXPECT_FALSE(AMDGPU::isSubArchCompatible(Triple::AMDGPUSubArch9,
+ Triple::AMDGPUSubArch10_3));
+ EXPECT_FALSE(AMDGPU::isSubArchCompatible(Triple::AMDGPUSubArch10_3,
+ Triple::AMDGPUSubArch9));
+ EXPECT_FALSE(AMDGPU::isSubArchCompatible(Triple::AMDGPUSubArch900,
+ Triple::AMDGPUSubArch1030));
+ EXPECT_FALSE(AMDGPU::isSubArchCompatible(Triple::AMDGPUSubArch1030,
+ Triple::AMDGPUSubArch900));
+
+ // An unrecognized subarch (NoSubArch) is only compatible with NoSubArch.
+ EXPECT_TRUE(
+ AMDGPU::isSubArchCompatible(Triple::NoSubArch, Triple::NoSubArch));
+ EXPECT_FALSE(
+ AMDGPU::isSubArchCompatible(Triple::NoSubArch, Triple::AMDGPUSubArch9));
+ EXPECT_FALSE(
+ AMDGPU::isSubArchCompatible(Triple::AMDGPUSubArch9, Triple::NoSubArch));
+ EXPECT_FALSE(
+ AMDGPU::isSubArchCompatible(Triple::NoSubArch, Triple::AMDGPUSubArch900));
+
+ // The Triple-based overload checks the same compatibility.
+ EXPECT_TRUE(AMDGPU::isSubArchCompatible(Triple("amdgpu9-amd-amdhsa"),
+ Triple("amdgpu9.00-amd-amdhsa")));
+ EXPECT_TRUE(AMDGPU::isSubArchCompatible(Triple("amdgpu-amd-amdhsa"),
+ Triple("amdgpu9.00-amd-amdhsa")));
+
+ EXPECT_FALSE(AMDGPU::isSubArchCompatible(Triple("amdgpu9.00-amd-amdhsa"),
+ Triple("amdgpu9.0a-amd-amdhsa")));
+
+ EXPECT_FALSE(AMDGPU::isSubArchCompatible(Triple("amdgpu9.0a-amd-amdhsa"),
+ Triple("amdgpu9.00-amd-amdhsa")));
+
+ EXPECT_FALSE(AMDGPU::isSubArchCompatible(Triple("amdgpu9-amd-amdhsa"),
+ Triple("amdgpu10.3-amd-amdhsa")));
+ EXPECT_FALSE(AMDGPU::isSubArchCompatible(Triple("amdgpu10.3-amd-amdhsa"),
+ Triple("amdgpu9-amd-amdhsa")));
+
+ // An unrecognized subarch is incompatible with any recognized subarch.
+ EXPECT_FALSE(AMDGPU::isSubArchCompatible(Triple("amdgpu9.99-amd-amdhsa"),
+ Triple("amdgpu9.00-amd-amdhsa")));
+}
+
+TEST(TargetParserTest, testAMDGPUisCPUValidForSubArch) {
+ EXPECT_TRUE(
+ AMDGPU::isCPUValidForSubArch(Triple::AMDGPUSubArch9, AMDGPU::GK_GFX900));
+ EXPECT_TRUE(AMDGPU::isCPUValidForSubArch(Triple::AMDGPUSubArch9, "gfx900"));
+
+ EXPECT_TRUE(AMDGPU::isCPUValidForSubArch(Triple::AMDGPUSubArch900,
+ AMDGPU::GK_GFX900));
+ EXPECT_TRUE(AMDGPU::isCPUValidForSubArch(Triple::AMDGPUSubArch900, "gfx900"));
+
+ EXPECT_FALSE(AMDGPU::isCPUValidForSubArch(Triple::AMDGPUSubArch900,
+ AMDGPU::GK_GFX902));
+ EXPECT_FALSE(
+ AMDGPU::isCPUValidForSubArch(Triple::AMDGPUSubArch900, "gfx902"));
+
+ EXPECT_TRUE(
+ AMDGPU::isCPUValidForSubArch(Triple::NoSubArch, AMDGPU::GK_GFX900));
+ EXPECT_TRUE(AMDGPU::isCPUValidForSubArch(Triple::NoSubArch, "gfx900"));
+
+ EXPECT_FALSE(
+ AMDGPU::isCPUValidForSubArch(Triple::NoSubArch, AMDGPU::GK_NONE));
+ EXPECT_FALSE(AMDGPU::isCPUValidForSubArch(Triple::NoSubArch, ""));
+}
+
+TEST(TargetParserTest, testAMDGPUfillValidArchListAMDGCN) {
+ SmallVector<StringRef, 0> All;
+ AMDGPU::fillValidArchListAMDGCN(All, Triple::NoSubArch);
+ EXPECT_FALSE(All.empty());
+
+ SmallVector<StringRef, 16> Filtered;
+
+ // For every subarch, the filtered list must agree exactly with
+ // isCPUValidForSubArch over the full set of names.
+ for (unsigned SA = Triple::FirstAMDGPUSubArch;
+ SA <= Triple::LastAMDGPUSubArch; ++SA) {
+ auto SubArch = static_cast<Triple::SubArchType>(SA);
+ Triple::SubArchType Major = AMDGPU::getMajorSubArch(SubArch);
+
+ AMDGPU::fillValidArchListAMDGCN(Filtered, SubArch);
+
+ for (StringRef Name : All) {
+ AMDGPU::GPUKind Kind = AMDGPU::parseArchAMDGCN(Name);
+ bool Valid = AMDGPU::isCPUValidForSubArch(SubArch, Kind);
+ EXPECT_EQ(Valid, llvm::is_contained(Filtered, Name))
+ << "subarch " << Triple::getArchName(Triple::amdgpu, SubArch)
+ << " name " << Name;
+ }
+
+ for (StringRef Name : Filtered)
+ EXPECT_TRUE(llvm::is_contained(All, Name)) << Name;
+
+ // A specific subarch matches its own concrete GPU, plus the family-generic
+ // GPU. Names may repeat through aliases, so compare distinct GPUKinds.
+ if (Major != SubArch) {
+ SmallSet<AMDGPU::GPUKind, 2> Kinds;
+ for (StringRef Name : Filtered)
+ Kinds.insert(AMDGPU::parseArchAMDGCN(Name));
+
+ bool FamilyHasGeneric =
+ AMDGPU::getGPUKindFromSubArch(Major) != AMDGPU::GK_NONE;
+ EXPECT_EQ(Kinds.size(), FamilyHasGeneric ? 2u : 1u)
+ << "subarch " << Triple::getArchName(Triple::amdgpu, SubArch);
+ }
+
+ Filtered.clear();
+ }
+}
+
+TEST(TargetParserTest, testAMDGPUgetGPUKindFromSubArch) {
+ EXPECT_EQ(AMDGPU::getGPUKindFromSubArch(Triple::NoSubArch), AMDGPU::GK_NONE);
+
+ struct SubArchMapping {
+ Triple::SubArchType SubArch;
+ AMDGPU::GPUKind Kind;
+ };
+
+ static const SubArchMapping Mappings[] = {
+ // GFX6 family
+ {Triple::AMDGPUSubArch6, AMDGPU::GK_NONE},
+ {Triple::AMDGPUSubArch600, AMDGPU::GK_GFX600},
+ {Triple::AMDGPUSubArch601, AMDGPU::GK_GFX601},
+ {Triple::AMDGPUSubArch602, AMDGPU::GK_GFX602},
+
+ // GFX7 family
+ {Triple::AMDGPUSubArch7, AMDGPU::GK_NONE},
+ {Triple::AMDGPUSubArch700, AMDGPU::GK_GFX700},
+ {Triple::AMDGPUSubArch701, AMDGPU::GK_GFX701},
+ {Triple::AMDGPUSubArch702, AMDGPU::GK_GFX702},
+ {Triple::AMDGPUSubArch703, AMDGPU::GK_GFX703},
+ {Triple::AMDGPUSubArch704, AMDGPU::GK_GFX704},
+ {Triple::AMDGPUSubArch705, AMDGPU::GK_GFX705},
+
+ // GFX8 family
+ {Triple::AMDGPUSubArch8, AMDGPU::GK_NONE},
+ {Triple::AMDGPUSubArch801, AMDGPU::GK_GFX801},
+ {Triple::AMDGPUSubArch802, AMDGPU::GK_GFX802},
+ {Triple::AMDGPUSubArch803, AMDGPU::GK_GFX803},
+ {Triple::AMDGPUSubArch805, AMDGPU::GK_GFX805},
+ {Triple::AMDGPUSubArch810, AMDGPU::GK_GFX810},
+
+ // GFX9 family
+ {Triple::AMDGPUSubArch9, AMDGPU::GK_GFX9_GENERIC},
+ {Triple::AMDGPUSubArch900, AMDGPU::GK_GFX900},
+ {Triple::AMDGPUSubArch902, AMDGPU::GK_GFX902},
+ {Triple::AMDGPUSubArch904, AMDGPU::GK_GFX904},
+ {Triple::AMDGPUSubArch906, AMDGPU::GK_GFX906},
+ {Triple::AMDGPUSubArch908, AMDGPU::GK_GFX908},
+ {Triple::AMDGPUSubArch909, AMDGPU::GK_GFX909},
+ {Triple::AMDGPUSubArch90A, AMDGPU::GK_GFX90A},
+ {Triple::AMDGPUSubArch90C, AMDGPU::GK_GFX90C},
+ {Triple::AMDGPUSubArch9_4, AMDGPU::GK_GFX9_4_GENERIC},
+ {Triple::AMDGPUSubArch942, AMDGPU::GK_GFX942},
+ {Triple::AMDGPUSubArch950, AMDGPU::GK_GFX950},
+
+ // GFX10 family
+ {Triple::AMDGPUSubArch10_1, AMDGPU::GK_GFX10_1_GENERIC},
+ {Triple::AMDGPUSubArch1010, AMDGPU::GK_GFX1010},
+ {Triple::AMDGPUSubArch1011, AMDGPU::GK_GFX1011},
+ {Triple::AMDGPUSubArch1012, AMDGPU::GK_GFX1012},
+ {Triple::AMDGPUSubArch1013, AMDGPU::GK_GFX1013},
+ {Triple::AMDGPUSubArch10_3, AMDGPU::GK_GFX10_3_GENERIC},
+ {Triple::AMDGPUSubArch1030, AMDGPU::GK_GFX1030},
+ {Triple::AMDGPUSubArch1031, AMDGPU::GK_GFX1031},
+ {Triple::AMDGPUSubArch1032, AMDGPU::GK_GFX1032},
+ {Triple::AMDGPUSubArch1033, AMDGPU::GK_GFX1033},
+ {Triple::AMDGPUSubArch1034, AMDGPU::GK_GFX1034},
+ {Triple::AMDGPUSubArch1035, AMDGPU::GK_GFX1035},
+ {Triple::AMDGPUSubArch1036, AMDGPU::GK_GFX1036},
+
+ // GFX11 family
+ {Triple::AMDGPUSubArch11, AMDGPU::GK_GFX11_GENERIC},
+ {Triple::AMDGPUSubArch1100, AMDGPU::GK_GFX1100},
+ {Triple::AMDGPUSubArch1101, AMDGPU::GK_GFX1101},
+ {Triple::AMDGPUSubArch1102, AMDGPU::GK_GFX1102},
+ {Triple::AMDGPUSubArch1103, AMDGPU::GK_GFX1103},
+ {Triple::AMDGPUSubArch1150, AMDGPU::GK_GFX1150},
+ {Triple::AMDGPUSubArch1151, AMDGPU::GK_GFX1151},
+ {Triple::AMDGPUSubArch1152, AMDGPU::GK_GFX1152},
+ {Triple::AMDGPUSubArch1153, AMDGPU::GK_GFX1153},
+ {Triple::AMDGPUSubArch1154, AMDGPU::GK_GFX1154},
+ {Triple::AMDGPUSubArch11_7, AMDGPU::GK_NONE},
+ {Triple::AMDGPUSubArch1170, AMDGPU::GK_GFX1170},
+ {Triple::AMDGPUSubArch1171, AMDGPU::GK_GFX1171},
+ {Triple::AMDGPUSubArch1172, AMDGPU::GK_GFX1172},
+
+ // GFX12 family
+ {Triple::AMDGPUSubArch12, AMDGPU::GK_GFX12_GENERIC},
+ {Triple::AMDGPUSubArch1200, AMDGPU::GK_GFX1200},
+ {Triple::AMDGPUSubArch1201, AMDGPU::GK_GFX1201},
+ {Triple::AMDGPUSubArch12_5, AMDGPU::GK_GFX12_5_GENERIC},
+ {Triple::AMDGPUSubArch1250, AMDGPU::GK_GFX1250},
+ {Triple::AMDGPUSubArch1251, AMDGPU::GK_GFX1251},
+
+ // GFX13 family
+ {Triple::AMDGPUSubArch13, AMDGPU::GK_NONE},
+ {Triple::AMDGPUSubArch1310, AMDGPU::GK_GFX1310},
+ };
+
+ for (const auto &Mapping : Mappings)
+ EXPECT_EQ(AMDGPU::getGPUKindFromSubArch(Mapping.SubArch), Mapping.Kind);
+}
+
+TEST(TargetParserTest, testAMDGPUgetIsaVersionFromSubArch) {
+ // Concrete subarches map to their exact ISA version.
+ EXPECT_EQ(AMDGPU::getIsaVersion(Triple::AMDGPUSubArch600),
+ (AMDGPU::IsaVersion{6, 0, 0}));
+ EXPECT_EQ(AMDGPU::getIsaVersion(Triple::AMDGPUSubArch900),
+ (AMDGPU::IsaVersion{9, 0, 0}));
+ EXPECT_EQ(AMDGPU::getIsaVersion(Triple::AMDGPUSubArch1250),
+ (AMDGPU::IsaVersion{12, 5, 0}));
+ EXPECT_EQ(AMDGPU::getIsaVersion(Triple::AMDGPUSubArch1251),
+ (AMDGPU::IsaVersion{12, 5, 1}));
+ EXPECT_EQ(AMDGPU::getIsaVersion(Triple::AMDGPUSubArch1310),
+ (AMDGPU::IsaVersion{13, 1, 0}));
+
+ // Generic subarches map to the generic target's version.
+ EXPECT_EQ(AMDGPU::getIsaVersion(Triple::AMDGPUSubArch9),
+ (AMDGPU::IsaVersion{9, 0, 0}));
+ EXPECT_EQ(AMDGPU::getIsaVersion(Triple::AMDGPUSubArch12),
+ (AMDGPU::IsaVersion{12, 0, 0}));
+ EXPECT_EQ(AMDGPU::getIsaVersion(Triple::AMDGPUSubArch12_5),
+ (AMDGPU::IsaVersion{12, 5, 0}));
+
+ // Major-family subarches with no associated GPU have no version.
+ EXPECT_EQ(AMDGPU::getIsaVersion(Triple::AMDGPUSubArch6),
+ (AMDGPU::IsaVersion{0, 0, 0}));
+ EXPECT_EQ(AMDGPU::getIsaVersion(Triple::AMDGPUSubArch13),
+ (AMDGPU::IsaVersion{0, 0, 0}));
+ EXPECT_EQ(AMDGPU::getIsaVersion(Triple::NoSubArch),
+ (AMDGPU::IsaVersion{0, 0, 0}));
+}
+
} // namespace
diff --git a/llvm/unittests/TargetParser/TripleTest.cpp b/llvm/unittests/TargetParser/TripleTest.cpp
index ff090429d74ca..67ab26eee8119 100644
--- a/llvm/unittests/TargetParser/TripleTest.cpp
+++ b/llvm/unittests/TargetParser/TripleTest.cpp
@@ -687,19 +687,25 @@ TEST(TripleTest, ParsedIDs) {
EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
T = Triple("amdgcn-mesa-mesa3d");
- EXPECT_EQ(Triple::amdgcn, T.getArch());
+ EXPECT_EQ(Triple::amdgpu, T.getArch());
+ EXPECT_EQ(Triple::Mesa, T.getVendor());
+ EXPECT_EQ(Triple::Mesa3D, T.getOS());
+ EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
+
+ T = Triple("amdgpu-mesa-mesa3d");
+ EXPECT_EQ(Triple::amdgpu, T.getArch());
EXPECT_EQ(Triple::Mesa, T.getVendor());
EXPECT_EQ(Triple::Mesa3D, T.getOS());
EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
T = Triple("amdgcn-amd-amdhsa");
- EXPECT_EQ(Triple::amdgcn, T.getArch());
+ EXPECT_EQ(Triple::amdgpu, T.getArch());
EXPECT_EQ(Triple::AMD, T.getVendor());
EXPECT_EQ(Triple::AMDHSA, T.getOS());
EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
T = Triple("amdgcn-amd-amdpal");
- EXPECT_EQ(Triple::amdgcn, T.getArch());
+ EXPECT_EQ(Triple::amdgpu, T.getArch());
EXPECT_EQ(Triple::AMD, T.getVendor());
EXPECT_EQ(Triple::AMDPAL, T.getOS());
EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
@@ -1479,35 +1485,35 @@ TEST(TripleTest, ParsedIDs) {
TEST(TripleTest, EnumConstructor) {
{
- Triple T(Triple::amdgcn, Triple::NoSubArch, Triple::AMD, Triple::AMDHSA);
- EXPECT_EQ(T.getArch(), Triple::amdgcn);
+ Triple T(Triple::amdgpu, Triple::NoSubArch, Triple::AMD, Triple::AMDHSA);
+ EXPECT_EQ(T.getArch(), Triple::amdgpu);
EXPECT_EQ(T.getVendor(), Triple::AMD);
EXPECT_EQ(T.getOS(), Triple::AMDHSA);
EXPECT_EQ(T.getEnvironment(), Triple::UnknownEnvironment);
EXPECT_EQ(T.getObjectFormat(), Triple::ELF);
- EXPECT_EQ(T.str(), "amdgcn-amd-amdhsa");
+ EXPECT_EQ(T.str(), "amdgpu-amd-amdhsa");
}
{
- Triple T(Triple::amdgcn, Triple::NoSubArch, Triple::AMD, Triple::AMDHSA,
+ Triple T(Triple::amdgpu, Triple::NoSubArch, Triple::AMD, Triple::AMDHSA,
Triple::LLVM, Triple::ELF);
- EXPECT_EQ(T.getArch(), Triple::amdgcn);
+ EXPECT_EQ(T.getArch(), Triple::amdgpu);
EXPECT_EQ(T.getVendor(), Triple::AMD);
EXPECT_EQ(T.getOS(), Triple::AMDHSA);
EXPECT_EQ(T.getEnvironment(), Triple::LLVM);
EXPECT_EQ(T.getObjectFormat(), Triple::ELF);
- EXPECT_EQ(T.str(), "amdgcn-amd-amdhsa-llvm-elf");
+ EXPECT_EQ(T.str(), "amdgpu-amd-amdhsa-llvm-elf");
}
{
- Triple T(Triple::amdgcn, Triple::NoSubArch, Triple::AMD, Triple::AMDHSA,
+ Triple T(Triple::amdgpu, Triple::NoSubArch, Triple::AMD, Triple::AMDHSA,
Triple::LLVM);
- EXPECT_EQ(T.getArch(), Triple::amdgcn);
+ EXPECT_EQ(T.getArch(), Triple::amdgpu);
EXPECT_EQ(T.getVendor(), Triple::AMD);
EXPECT_EQ(T.getOS(), Triple::AMDHSA);
EXPECT_EQ(T.getEnvironment(), Triple::LLVM);
EXPECT_EQ(T.getObjectFormat(), Triple::ELF);
- EXPECT_EQ(T.str(), "amdgcn-amd-amdhsa-llvm");
+ EXPECT_EQ(T.str(), "amdgpu-amd-amdhsa-llvm");
}
{
@@ -1998,6 +2004,18 @@ TEST(TripleTest, BitWidthChecks) {
EXPECT_TRUE(T.isArch64Bit());
EXPECT_EQ(T.getArchPointerBitWidth(), 64U);
+ T.setArch(Triple::amdgpu);
+ EXPECT_FALSE(T.isArch16Bit());
+ EXPECT_FALSE(T.isArch32Bit());
+ EXPECT_TRUE(T.isArch64Bit());
+ EXPECT_EQ(T.getArchPointerBitWidth(), 64U);
+
+ T.setArch(Triple::amdgpu);
+ EXPECT_FALSE(T.isArch16Bit());
+ EXPECT_FALSE(T.isArch32Bit());
+ EXPECT_TRUE(T.isArch64Bit());
+ EXPECT_EQ(T.getArchPointerBitWidth(), 64U);
+
T.setArch(Triple::hsail);
EXPECT_FALSE(T.isArch16Bit());
EXPECT_TRUE(T.isArch32Bit());
@@ -2972,6 +2990,10 @@ TEST(TripleTest, FileFormat) {
EXPECT_EQ(Triple::SPIRV, Triple("spirv32-unknown-unknown").getObjectFormat());
EXPECT_EQ(Triple::SPIRV, Triple("spirv64-unknown-unknown").getObjectFormat());
+ EXPECT_EQ(Triple::ELF, Triple("amdgcn-unknown-unknown").getObjectFormat());
+ EXPECT_EQ(Triple::ELF, Triple("amdgpu-unknown-unknown").getObjectFormat());
+ EXPECT_EQ(Triple::ELF, Triple("amdgpu-amd-amdhsa").getObjectFormat());
+
EXPECT_EQ(Triple::ELF,
Triple("loongarch32-unknown-unknown").getObjectFormat());
EXPECT_EQ(Triple::ELF, Triple("loongarch64-unknown-linux").getObjectFormat());
@@ -3013,6 +3035,7 @@ TEST(TripleTest, FileFormat) {
EXPECT_EQ("spirv", Triple::getObjectFormatTypeName(T.getObjectFormat()));
EXPECT_EQ(Triple::ELF, Triple("amdgcn-apple-macosx").getObjectFormat());
+ EXPECT_EQ(Triple::ELF, Triple("amdgpu-apple-macosx").getObjectFormat());
EXPECT_EQ(Triple::ELF, Triple("r600-apple-macosx").getObjectFormat());
EXPECT_EQ(Triple::SPIRV, Triple("spirv-apple-macosx").getObjectFormat());
EXPECT_EQ(Triple::SPIRV, Triple("spirv32-apple-macosx").getObjectFormat());
@@ -3054,6 +3077,8 @@ TEST(TripleTest, DefaultExceptionHandling) {
EXPECT_EQ(ExceptionHandling::None,
Triple("amdgcn--").getDefaultExceptionHandling());
+ EXPECT_EQ(ExceptionHandling::None,
+ Triple("amdgpu--").getDefaultExceptionHandling());
EXPECT_EQ(ExceptionHandling::None,
Triple("nvptx64--").getDefaultExceptionHandling());
EXPECT_EQ(ExceptionHandling::None,
@@ -3505,6 +3530,107 @@ TEST(TripleTest, isCompatibleWith) {
{"i686-w64-windows-gnu", "i386-w64-windows-gnu", true},
{"x86_64-w64-windows-gnu", "x86_64-pc-windows-gnu", true},
{"armv7-w64-windows-gnu", "thumbv7-pc-windows-gnu", true},
+ {"amdgpu9-amd-amdhsa", "amdgpu-amd-amdhsa", true},
+ {"amdgpu9-amd-amdhsa-llvm", "amdgpu-amd-amdhsa", false},
+ {"amdgpu6-amd-amdhsa-llvm", "amdgpu9-amd-amdhsa", false},
+ {"amdgpu9-amd-amdhsa-coff", "amdgpu9-amd-amdhsa", false},
+ {"amdgpu-unknown-amdhsa-coff", "amdgpu-amd-amdhsa", false},
+ {"amdgpu9-amd-amdhsa-llvm", "amdgpu9-amd-amdhsa", false},
+
+ {"amdgpu6-amd-amdhsa", "amdgpu6.00-amd-amdhsa", true},
+ {"amdgpu6-amd-amdhsa", "amdgpu6.01-amd-amdhsa", true},
+ {"amdgpu6-amd-amdhsa", "amdgpu6.02-amd-amdhsa", true},
+ {"amdgpu6-amd-amdhsa", "amdgpu7-amd-amdhsa", false},
+ {"amdgpu6-amd-amdhsa", "amdgpu8-amd-amdhsa", false},
+ {"amdgpu6-amd-amdhsa", "amdgpu9-amd-amdhsa", false},
+ {"amdgpu6-amd-amdhsa", "amdgpu9.4-amd-amdhsa", false},
+ {"amdgpu6-amd-amdhsa", "amdgpu10.1-amd-amdhsa", false},
+ {"amdgpu6-amd-amdhsa", "amdgpu7.00-amd-amdhsa", false},
+ {"amdgpu6-amd-amdhsa", "amdgpu700-amd-amdhsa", false},
+
+ {"amdgpu7-amd-amdhsa", "amdgpu7.00-amd-amdhsa", true},
+ {"amdgpu7-amd-amdhsa", "amdgpu7.01-amd-amdhsa", true},
+ {"amdgpu7-amd-amdhsa", "amdgpu7.02-amd-amdhsa", true},
+ {"amdgpu7-amd-amdhsa", "amdgpu7.03-amd-amdhsa", true},
+ {"amdgpu7-amd-amdhsa", "amdgpu7.04-amd-amdhsa", true},
+ {"amdgpu7-amd-amdhsa", "amdgpu7.05-amd-amdhsa", true},
+ {"amdgpu7-amd-amdhsa", "amdgpu8-amd-amdhsa", false},
+
+ {"amdgpu8-amd-amdhsa", "amdgpu8.01-amd-amdhsa", true},
+ {"amdgpu8-amd-amdhsa", "amdgpu8.02-amd-amdhsa", true},
+ {"amdgpu8-amd-amdhsa", "amdgpu8.03-amd-amdhsa", true},
+ {"amdgpu8-amd-amdhsa", "amdgpu8.10-amd-amdhsa", false},
+
+ {"amdgpu9-amd-amdhsa", "amdgpu9.00-amd-amdhsa", true},
+ {"amdgpu9-amd-amdhsa", "amdgpu9.02-amd-amdhsa", true},
+ {"amdgpu9-amd-amdhsa", "amdgpu9.04-amd-amdhsa", true},
+ {"amdgpu9-amd-amdhsa", "amdgpu9.06-amd-amdhsa", true},
+ {"amdgpu9-amd-amdhsa", "amdgpu9.08-amd-amdhsa", false},
+ {"amdgpu9-amd-amdhsa", "amdgpu9.09-amd-amdhsa", true},
+ {"amdgpu9-amd-amdhsa", "amdgpu9.0a-amd-amdhsa", false},
+ {"amdgpu9-amd-amdhsa", "amdgpu9.0c-amd-amdhsa", true},
+ {"amdgpu9.08-amd-amdhsa", "amdgpu9.08-amd-amdhsa", true},
+ {"amdgpu9.0a-amd-amdhsa", "amdgpu9.0a-amd-amdhsa", true},
+ {"amdgpu9-amd-amdhsa", "amdgpu9.4-amd-amdhsa", false},
+ {"amdgpu9-amd-amdhsa", "amdgpu9.42-amd-amdhsa", false},
+ {"amdgpu9-amd-amdhsa", "amdgpu9.50-amd-amdhsa", false},
+ {"amdgpu9.00-amd-amdhsa", "amdgpu9.50-amd-amdhsa", false},
+ {"amdgpu9.50-amd-amdhsa", "amdgpu9.00-amd-amdhsa", false},
+ {"amdgpu9.00-amd-amdhsa", "amdgpu9.08-amd-amdhsa", false},
+ {"amdgpu9.08-amd-amdhsa", "amdgpu9.00-amd-amdhsa", false},
+ {"amdgpu9.00-amd-amdhsa", "amdgpu9.06-amd-amdhsa", false},
+ {"amdgpu9.06-amd-amdhsa", "amdgpu9.00-amd-amdhsa", false},
+ {"amdgpu10.1-amd-amdhsa", "amdgpu10.10-amd-amdhsa", true},
+ {"amdgpu10.1-amd-amdhsa", "amdgpu10.11-amd-amdhsa", true},
+ {"amdgpu10.1-amd-amdhsa", "amdgpu10.12-amd-amdhsa", true},
+ {"amdgpu10.1-amd-amdhsa", "amdgpu10.13-amd-amdhsa", true},
+
+ {"amdgpu10.3-amd-amdhsa", "amdgpu10.1-amd-amdhsa", false},
+ {"amdgpu10.3-amd-amdhsa", "amdgpu10.10-amd-amdhsa", false},
+ {"amdgpu10.3-amd-amdhsa", "amdgpu10.30-amd-amdhsa", true},
+ {"amdgpu10.3-amd-amdhsa", "amdgpu10.31-amd-amdhsa", true},
+ {"amdgpu10.3-amd-amdhsa", "amdgpu10.32-amd-amdhsa", true},
+ {"amdgpu10.3-amd-amdhsa", "amdgpu10.33-amd-amdhsa", true},
+ {"amdgpu10.3-amd-amdhsa", "amdgpu10.34-amd-amdhsa", true},
+ {"amdgpu10.3-amd-amdhsa", "amdgpu10.35-amd-amdhsa", true},
+ {"amdgpu10.3-amd-amdhsa", "amdgpu10.36-amd-amdhsa", true},
+
+ {"amdgpu11-amd-amdhsa", "amdgpu10.1-amd-amdhsa", false},
+ {"amdgpu11-amd-amdhsa", "amdgpu11.00-amd-amdhsa", true},
+ {"amdgpu11-amd-amdhsa", "amdgpu11.01-amd-amdhsa", true},
+ {"amdgpu11-amd-amdhsa", "amdgpu11.02-amd-amdhsa", true},
+ {"amdgpu11-amd-amdhsa", "amdgpu11.03-amd-amdhsa", true},
+ {"amdgpu11-amd-amdhsa", "amdgpu11.50-amd-amdhsa", true},
+ {"amdgpu11-amd-amdhsa", "amdgpu11.51-amd-amdhsa", true},
+ {"amdgpu11-amd-amdhsa", "amdgpu11.52-amd-amdhsa", true},
+ {"amdgpu11-amd-amdhsa", "amdgpu11.53-amd-amdhsa", true},
+ {"amdgpu11-amd-amdhsa", "amdgpu11.54-amd-amdhsa", true},
+ {"amdgpu11-amd-amdhsa", "amdgpu11.7-amd-amdhsa", false},
+ {"amdgpu11-amd-amdhsa", "amdgpu11.70-amd-amdhsa", false},
+ {"amdgpu11-amd-amdhsa", "amdgpu11.71-amd-amdhsa", false},
+ {"amdgpu11-amd-amdhsa", "amdgpu11.72-amd-amdhsa", false},
+
+ {"amdgpu11.7-amd-amdhsa", "amdgpu11-amd-amdhsa", false},
+ {"amdgpu11.7-amd-amdhsa", "amdgpu11.70-amd-amdhsa", true},
+ {"amdgpu11.7-amd-amdhsa", "amdgpu11.71-amd-amdhsa", true},
+ {"amdgpu11.7-amd-amdhsa", "amdgpu11.72-amd-amdhsa", true},
+
+ {"amdgpu12-amd-amdhsa", "amdgpu12.00-amd-amdhsa", true},
+ {"amdgpu12-amd-amdhsa", "amdgpu12.01-amd-amdhsa", true},
+ {"amdgpu12-amd-amdhsa", "amdgpu12.5-amd-amdhsa", false},
+ {"amdgpu12-amd-amdhsa", "amdgpu12.50-amd-amdhsa", false},
+ {"amdgpu12-amd-amdhsa", "amdgpu12.51-amd-amdhsa", false},
+
+ {"amdgpu12.5-amd-amdhsa", "amdgpu12.50-amd-amdhsa", true},
+ {"amdgpu12.5-amd-amdhsa", "amdgpu12.51-amd-amdhsa", true},
+
+ {"amdgpu13-amd-amdhsa", "amdgpu13.10-amd-amdhsa", true},
+
+ // A vendor mismatch is incompatible even when the subarch is otherwise
+ // compatible.
+ {"amdgpu9-amd-amdhsa", "amdgpu9.00-unknown-amdhsa", false},
+ {"amdgpu9.00-amd-amdhsa", "amdgpu9.00-unknown-amdhsa", false},
+ {"amdgpu12.5-amd-amdhsa", "amdgpu12.50-unknown-amdhsa", false},
};
auto DoTest = [](const char *A, const char *B,
diff --git a/llvm/utils/UpdateTestChecks/asm.py b/llvm/utils/UpdateTestChecks/asm.py
index 5f441227092f4..f4214559b011b 100644
--- a/llvm/utils/UpdateTestChecks/asm.py
+++ b/llvm/utils/UpdateTestChecks/asm.py
@@ -575,6 +575,7 @@ def get_run_handler(triple):
"hexagon": (scrub_asm_hexagon, ASM_FUNCTION_HEXAGON_RE),
"r600": (scrub_asm_amdgpu, ASM_FUNCTION_AMDGPU_RE),
"amdgcn": (scrub_asm_amdgpu, ASM_FUNCTION_AMDGPU_RE),
+ "amdgpu": (scrub_asm_amdgpu, ASM_FUNCTION_AMDGPU_RE),
"arm": (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_RE),
"arm64": (scrub_asm_arm_eabi, ASM_FUNCTION_AARCH64_RE),
"arm64e": (scrub_asm_arm_eabi, ASM_FUNCTION_AARCH64_DARWIN_RE),
diff --git a/offload/plugins-nextgen/amdgpu/src/rtl.cpp b/offload/plugins-nextgen/amdgpu/src/rtl.cpp
index dda905607c2ed..e6ceeea5331d1 100644
--- a/offload/plugins-nextgen/amdgpu/src/rtl.cpp
+++ b/offload/plugins-nextgen/amdgpu/src/rtl.cpp
@@ -4031,7 +4031,7 @@ struct AMDGPUPluginTy final : public GenericPluginTy {
return new AMDGPUGlobalHandlerTy();
}
- Triple::ArchType getTripleArch() const override { return Triple::amdgcn; }
+ Triple::ArchType getTripleArch() const override { return Triple::amdgpu; }
const char *getName() const override { return GETNAME(TARGET_NAME); }
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