[flang-commits] [clang-tools-extra] [flang] [compiler-rt] [llvm] [clang] [PowerPC][CodeGen] Exploit STMW and LMW in 32-bit big-endian mode. (PR #74415)

[Chen Zheng via flang-commits]

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@@ -2399,6 +2405,29 @@ bool PPCFrameLowering::assignCalleeSavedSpillSlots(
   return AllSpilledToReg;
 }
 
+static void findContinuousLoadStore(ArrayRef<CalleeSavedInfo> CSI,
+                                    Register &MergeFrom) {
+  unsigned I = 1, E = CSI.size(), BeginI = 0;
+  for (; I < E; ++I) {
+    // Find continuous store/load.
+    int RegDiff = CSI[I].getReg() - CSI[I - 1].getReg();
+    int FrameIdxDiff = CSI[I - 1].getFrameIdx() - CSI[I].getFrameIdx();
+    Register BeginReg = CSI[BeginI].getReg();
+    if (BeginReg < PPC::R0 || BeginReg > PPC::R31 ||
+        CSI[BeginI].isSpilledToReg() || RegDiff != 1 || FrameIdxDiff != 1)
+      BeginI = I;
+    if (CSI[I].getReg() == PPC::R31)
+      break;
+  }
+
+  if (I == E || CSI[BeginI].getReg() >= PPC::R31)
+    return;
+
+  // Record the first reg that STMW/LMW are going to merge since STMW/LMW save
+  // from rN to r31.
+  MergeFrom = CSI[BeginI].getReg();
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chenzheng1030 wrote:

This is unnecessary complicating. LMW/STMW only applies for AIX 32-bit. For AIX, we just need to find the first GPR(assume the CSI is sorted on ascending ordering), that would be the MergeFrom. On AIX, CSRs always contain the lowest GPR till R31.

https://github.com/llvm/llvm-project/pull/74415