[clang] [llvm] [RISCV][P-ext] Test cleanup and improvements. NFC (PR #235322)

[Craig Topper via cfe-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/235322

-Use script to generate pnclip tests in rvp-intrinsics.c
-Add missing pnclip tests to riscv_packed_simd.c
-Add missing tests to rvp-intrinsics.c

>From ee38aa393062b261a4025af724426c3455d7aa61 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 23 Oct 2026 17:59:14 -0700
Subject: [PATCH 1/5] Add blank lines between tests

---
 clang/test/CodeGen/RISCV/rvp-intrinsics.c | 79 +++++++++++++++++++++++
 1 file changed, 79 insertions(+)

diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
index ea42d98eec04c1..662847606ed11c 100644
--- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c
+++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
@@ -2139,6 +2139,7 @@ uint16x4_t test_pmaxu_u16x4(uint16x4_t a, uint16x4_t b) {
 uint32x2_t test_pmaxu_u32x2(uint32x2_t a, uint32x2_t b) {
   return __riscv_pmaxu_u32x2(a, b);
 }
+
 /* Packed Comparison (32-bit) */
 
 // CHECK-LABEL: define dso_local i32 @test_pmseq_i8x4_u8x4(
@@ -6735,6 +6736,7 @@ int32x2_t test_pmulqr_i32x2(int32x2_t rs1, int32x2_t rs2) {
 uint32_t test_preinterpret_u8x4_u32(uint8x4_t x) {
   return __riscv_preinterpret_u8x4_u32(x);
 }
+
 // RV32-LABEL: define dso_local i32 @test_preinterpret_u16x2_u32(
 // RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // RV32-NEXT:  [[ENTRY:.*:]]
@@ -6748,6 +6750,7 @@ uint32_t test_preinterpret_u8x4_u32(uint8x4_t x) {
 uint32_t test_preinterpret_u16x2_u32(uint16x2_t x) {
   return __riscv_preinterpret_u16x2_u32(x);
 }
+
 // RV32-LABEL: define dso_local i32 @test_preinterpret_i8x4_u32(
 // RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // RV32-NEXT:  [[ENTRY:.*:]]
@@ -6761,6 +6764,7 @@ uint32_t test_preinterpret_u16x2_u32(uint16x2_t x) {
 uint32_t test_preinterpret_i8x4_u32(int8x4_t x) {
   return __riscv_preinterpret_i8x4_u32(x);
 }
+
 // RV32-LABEL: define dso_local i32 @test_preinterpret_i16x2_u32(
 // RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // RV32-NEXT:  [[ENTRY:.*:]]
@@ -6774,6 +6778,7 @@ uint32_t test_preinterpret_i8x4_u32(int8x4_t x) {
 uint32_t test_preinterpret_i16x2_u32(int16x2_t x) {
   return __riscv_preinterpret_i16x2_u32(x);
 }
+
 // RV32-LABEL: define dso_local i32 @test_preinterpret_u8x4_i32(
 // RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // RV32-NEXT:  [[ENTRY:.*:]]
@@ -6787,6 +6792,7 @@ uint32_t test_preinterpret_i16x2_u32(int16x2_t x) {
 int32_t test_preinterpret_u8x4_i32(uint8x4_t x) {
   return __riscv_preinterpret_u8x4_i32(x);
 }
+
 // RV32-LABEL: define dso_local i32 @test_preinterpret_u16x2_i32(
 // RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // RV32-NEXT:  [[ENTRY:.*:]]
@@ -6800,6 +6806,7 @@ int32_t test_preinterpret_u8x4_i32(uint8x4_t x) {
 int32_t test_preinterpret_u16x2_i32(uint16x2_t x) {
   return __riscv_preinterpret_u16x2_i32(x);
 }
+
 // RV32-LABEL: define dso_local i32 @test_preinterpret_i8x4_i32(
 // RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // RV32-NEXT:  [[ENTRY:.*:]]
@@ -6813,6 +6820,7 @@ int32_t test_preinterpret_u16x2_i32(uint16x2_t x) {
 int32_t test_preinterpret_i8x4_i32(int8x4_t x) {
   return __riscv_preinterpret_i8x4_i32(x);
 }
+
 // RV32-LABEL: define dso_local i32 @test_preinterpret_i16x2_i32(
 // RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // RV32-NEXT:  [[ENTRY:.*:]]
@@ -6826,6 +6834,7 @@ int32_t test_preinterpret_i8x4_i32(int8x4_t x) {
 int32_t test_preinterpret_i16x2_i32(int16x2_t x) {
   return __riscv_preinterpret_i16x2_i32(x);
 }
+
 // RV32-LABEL: define dso_local i32 @test_preinterpret_u32_u8x4(
 // RV32-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
 // RV32-NEXT:  [[ENTRY:.*:]]
@@ -6839,6 +6848,7 @@ int32_t test_preinterpret_i16x2_i32(int16x2_t x) {
 uint8x4_t test_preinterpret_u32_u8x4(uint32_t x) {
   return __riscv_preinterpret_u32_u8x4(x);
 }
+
 // RV32-LABEL: define dso_local i32 @test_preinterpret_u32_u16x2(
 // RV32-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
 // RV32-NEXT:  [[ENTRY:.*:]]
@@ -6852,6 +6862,7 @@ uint8x4_t test_preinterpret_u32_u8x4(uint32_t x) {
 uint16x2_t test_preinterpret_u32_u16x2(uint32_t x) {
   return __riscv_preinterpret_u32_u16x2(x);
 }
+
 // RV32-LABEL: define dso_local i32 @test_preinterpret_u32_i8x4(
 // RV32-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
 // RV32-NEXT:  [[ENTRY:.*:]]
@@ -6865,6 +6876,7 @@ uint16x2_t test_preinterpret_u32_u16x2(uint32_t x) {
 int8x4_t test_preinterpret_u32_i8x4(uint32_t x) {
   return __riscv_preinterpret_u32_i8x4(x);
 }
+
 // RV32-LABEL: define dso_local i32 @test_preinterpret_u32_i16x2(
 // RV32-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
 // RV32-NEXT:  [[ENTRY:.*:]]
@@ -6878,6 +6890,7 @@ int8x4_t test_preinterpret_u32_i8x4(uint32_t x) {
 int16x2_t test_preinterpret_u32_i16x2(uint32_t x) {
   return __riscv_preinterpret_u32_i16x2(x);
 }
+
 // RV32-LABEL: define dso_local i32 @test_preinterpret_i32_u8x4(
 // RV32-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
 // RV32-NEXT:  [[ENTRY:.*:]]
@@ -6891,6 +6904,7 @@ int16x2_t test_preinterpret_u32_i16x2(uint32_t x) {
 uint8x4_t test_preinterpret_i32_u8x4(int32_t x) {
   return __riscv_preinterpret_i32_u8x4(x);
 }
+
 // RV32-LABEL: define dso_local i32 @test_preinterpret_i32_u16x2(
 // RV32-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
 // RV32-NEXT:  [[ENTRY:.*:]]
@@ -6904,6 +6918,7 @@ uint8x4_t test_preinterpret_i32_u8x4(int32_t x) {
 uint16x2_t test_preinterpret_i32_u16x2(int32_t x) {
   return __riscv_preinterpret_i32_u16x2(x);
 }
+
 // RV32-LABEL: define dso_local i32 @test_preinterpret_i32_i8x4(
 // RV32-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
 // RV32-NEXT:  [[ENTRY:.*:]]
@@ -6917,6 +6932,7 @@ uint16x2_t test_preinterpret_i32_u16x2(int32_t x) {
 int8x4_t test_preinterpret_i32_i8x4(int32_t x) {
   return __riscv_preinterpret_i32_i8x4(x);
 }
+
 // RV32-LABEL: define dso_local i32 @test_preinterpret_i32_i16x2(
 // RV32-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
 // RV32-NEXT:  [[ENTRY:.*:]]
@@ -6940,6 +6956,7 @@ int16x2_t test_preinterpret_i32_i16x2(int32_t x) {
 uint64_t test_preinterpret_u8x8_u64(uint8x8_t x) {
   return __riscv_preinterpret_u8x8_u64(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u16x4_u64(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -6948,6 +6965,7 @@ uint64_t test_preinterpret_u8x8_u64(uint8x8_t x) {
 uint64_t test_preinterpret_u16x4_u64(uint16x4_t x) {
   return __riscv_preinterpret_u16x4_u64(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u32x2_u64(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -6956,6 +6974,7 @@ uint64_t test_preinterpret_u16x4_u64(uint16x4_t x) {
 uint64_t test_preinterpret_u32x2_u64(uint32x2_t x) {
   return __riscv_preinterpret_u32x2_u64(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i8x8_u64(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -6964,6 +6983,7 @@ uint64_t test_preinterpret_u32x2_u64(uint32x2_t x) {
 uint64_t test_preinterpret_i8x8_u64(int8x8_t x) {
   return __riscv_preinterpret_i8x8_u64(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i16x4_u64(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -6972,6 +6992,7 @@ uint64_t test_preinterpret_i8x8_u64(int8x8_t x) {
 uint64_t test_preinterpret_i16x4_u64(int16x4_t x) {
   return __riscv_preinterpret_i16x4_u64(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i32x2_u64(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -6980,6 +7001,7 @@ uint64_t test_preinterpret_i16x4_u64(int16x4_t x) {
 uint64_t test_preinterpret_i32x2_u64(int32x2_t x) {
   return __riscv_preinterpret_i32x2_u64(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u8x8_i64(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -6988,6 +7010,7 @@ uint64_t test_preinterpret_i32x2_u64(int32x2_t x) {
 int64_t test_preinterpret_u8x8_i64(uint8x8_t x) {
   return __riscv_preinterpret_u8x8_i64(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u16x4_i64(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -6996,6 +7019,7 @@ int64_t test_preinterpret_u8x8_i64(uint8x8_t x) {
 int64_t test_preinterpret_u16x4_i64(uint16x4_t x) {
   return __riscv_preinterpret_u16x4_i64(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u32x2_i64(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7004,6 +7028,7 @@ int64_t test_preinterpret_u16x4_i64(uint16x4_t x) {
 int64_t test_preinterpret_u32x2_i64(uint32x2_t x) {
   return __riscv_preinterpret_u32x2_i64(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i8x8_i64(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7012,6 +7037,7 @@ int64_t test_preinterpret_u32x2_i64(uint32x2_t x) {
 int64_t test_preinterpret_i8x8_i64(int8x8_t x) {
   return __riscv_preinterpret_i8x8_i64(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i16x4_i64(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7020,6 +7046,7 @@ int64_t test_preinterpret_i8x8_i64(int8x8_t x) {
 int64_t test_preinterpret_i16x4_i64(int16x4_t x) {
   return __riscv_preinterpret_i16x4_i64(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i32x2_i64(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7028,6 +7055,7 @@ int64_t test_preinterpret_i16x4_i64(int16x4_t x) {
 int64_t test_preinterpret_i32x2_i64(int32x2_t x) {
   return __riscv_preinterpret_i32x2_i64(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u64_u8x8(
 // CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7036,6 +7064,7 @@ int64_t test_preinterpret_i32x2_i64(int32x2_t x) {
 uint8x8_t test_preinterpret_u64_u8x8(uint64_t x) {
   return __riscv_preinterpret_u64_u8x8(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u64_u16x4(
 // CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7044,6 +7073,7 @@ uint8x8_t test_preinterpret_u64_u8x8(uint64_t x) {
 uint16x4_t test_preinterpret_u64_u16x4(uint64_t x) {
   return __riscv_preinterpret_u64_u16x4(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u64_u32x2(
 // CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7052,6 +7082,7 @@ uint16x4_t test_preinterpret_u64_u16x4(uint64_t x) {
 uint32x2_t test_preinterpret_u64_u32x2(uint64_t x) {
   return __riscv_preinterpret_u64_u32x2(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u64_i8x8(
 // CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7060,6 +7091,7 @@ uint32x2_t test_preinterpret_u64_u32x2(uint64_t x) {
 int8x8_t test_preinterpret_u64_i8x8(uint64_t x) {
   return __riscv_preinterpret_u64_i8x8(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u64_i16x4(
 // CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7068,6 +7100,7 @@ int8x8_t test_preinterpret_u64_i8x8(uint64_t x) {
 int16x4_t test_preinterpret_u64_i16x4(uint64_t x) {
   return __riscv_preinterpret_u64_i16x4(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u64_i32x2(
 // CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7076,6 +7109,7 @@ int16x4_t test_preinterpret_u64_i16x4(uint64_t x) {
 int32x2_t test_preinterpret_u64_i32x2(uint64_t x) {
   return __riscv_preinterpret_u64_i32x2(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i64_u8x8(
 // CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7084,6 +7118,7 @@ int32x2_t test_preinterpret_u64_i32x2(uint64_t x) {
 uint8x8_t test_preinterpret_i64_u8x8(int64_t x) {
   return __riscv_preinterpret_i64_u8x8(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i64_u16x4(
 // CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7092,6 +7127,7 @@ uint8x8_t test_preinterpret_i64_u8x8(int64_t x) {
 uint16x4_t test_preinterpret_i64_u16x4(int64_t x) {
   return __riscv_preinterpret_i64_u16x4(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i64_u32x2(
 // CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7100,6 +7136,7 @@ uint16x4_t test_preinterpret_i64_u16x4(int64_t x) {
 uint32x2_t test_preinterpret_i64_u32x2(int64_t x) {
   return __riscv_preinterpret_i64_u32x2(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i64_i8x8(
 // CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7108,6 +7145,7 @@ uint32x2_t test_preinterpret_i64_u32x2(int64_t x) {
 int8x8_t test_preinterpret_i64_i8x8(int64_t x) {
   return __riscv_preinterpret_i64_i8x8(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i64_i16x4(
 // CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7116,6 +7154,7 @@ int8x8_t test_preinterpret_i64_i8x8(int64_t x) {
 int16x4_t test_preinterpret_i64_i16x4(int64_t x) {
   return __riscv_preinterpret_i64_i16x4(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i64_i32x2(
 // CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7134,6 +7173,7 @@ int32x2_t test_preinterpret_i64_i32x2(int64_t x) {
 uint8x4_t test_preinterpret_i8x4_u8x4(int8x4_t x) {
   return __riscv_preinterpret_i8x4_u8x4(x);
 }
+
 // CHECK-LABEL: define dso_local i32 @test_preinterpret_u16x2_u8x4(
 // CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7142,6 +7182,7 @@ uint8x4_t test_preinterpret_i8x4_u8x4(int8x4_t x) {
 uint8x4_t test_preinterpret_u16x2_u8x4(uint16x2_t x) {
   return __riscv_preinterpret_u16x2_u8x4(x);
 }
+
 // CHECK-LABEL: define dso_local i32 @test_preinterpret_i16x2_u8x4(
 // CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7150,6 +7191,7 @@ uint8x4_t test_preinterpret_u16x2_u8x4(uint16x2_t x) {
 uint8x4_t test_preinterpret_i16x2_u8x4(int16x2_t x) {
   return __riscv_preinterpret_i16x2_u8x4(x);
 }
+
 // CHECK-LABEL: define dso_local i32 @test_preinterpret_u8x4_i8x4(
 // CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7158,6 +7200,7 @@ uint8x4_t test_preinterpret_i16x2_u8x4(int16x2_t x) {
 int8x4_t test_preinterpret_u8x4_i8x4(uint8x4_t x) {
   return __riscv_preinterpret_u8x4_i8x4(x);
 }
+
 // CHECK-LABEL: define dso_local i32 @test_preinterpret_u16x2_i8x4(
 // CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7166,6 +7209,7 @@ int8x4_t test_preinterpret_u8x4_i8x4(uint8x4_t x) {
 int8x4_t test_preinterpret_u16x2_i8x4(uint16x2_t x) {
   return __riscv_preinterpret_u16x2_i8x4(x);
 }
+
 // CHECK-LABEL: define dso_local i32 @test_preinterpret_i16x2_i8x4(
 // CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7174,6 +7218,7 @@ int8x4_t test_preinterpret_u16x2_i8x4(uint16x2_t x) {
 int8x4_t test_preinterpret_i16x2_i8x4(int16x2_t x) {
   return __riscv_preinterpret_i16x2_i8x4(x);
 }
+
 // CHECK-LABEL: define dso_local i32 @test_preinterpret_u8x4_u16x2(
 // CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7182,6 +7227,7 @@ int8x4_t test_preinterpret_i16x2_i8x4(int16x2_t x) {
 uint16x2_t test_preinterpret_u8x4_u16x2(uint8x4_t x) {
   return __riscv_preinterpret_u8x4_u16x2(x);
 }
+
 // CHECK-LABEL: define dso_local i32 @test_preinterpret_i8x4_u16x2(
 // CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7190,6 +7236,7 @@ uint16x2_t test_preinterpret_u8x4_u16x2(uint8x4_t x) {
 uint16x2_t test_preinterpret_i8x4_u16x2(int8x4_t x) {
   return __riscv_preinterpret_i8x4_u16x2(x);
 }
+
 // CHECK-LABEL: define dso_local i32 @test_preinterpret_i16x2_u16x2(
 // CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7198,6 +7245,7 @@ uint16x2_t test_preinterpret_i8x4_u16x2(int8x4_t x) {
 uint16x2_t test_preinterpret_i16x2_u16x2(int16x2_t x) {
   return __riscv_preinterpret_i16x2_u16x2(x);
 }
+
 // CHECK-LABEL: define dso_local i32 @test_preinterpret_u8x4_i16x2(
 // CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7206,6 +7254,7 @@ uint16x2_t test_preinterpret_i16x2_u16x2(int16x2_t x) {
 int16x2_t test_preinterpret_u8x4_i16x2(uint8x4_t x) {
   return __riscv_preinterpret_u8x4_i16x2(x);
 }
+
 // CHECK-LABEL: define dso_local i32 @test_preinterpret_i8x4_i16x2(
 // CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7214,6 +7263,7 @@ int16x2_t test_preinterpret_u8x4_i16x2(uint8x4_t x) {
 int16x2_t test_preinterpret_i8x4_i16x2(int8x4_t x) {
   return __riscv_preinterpret_i8x4_i16x2(x);
 }
+
 // CHECK-LABEL: define dso_local i32 @test_preinterpret_u16x2_i16x2(
 // CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7232,6 +7282,7 @@ int16x2_t test_preinterpret_u16x2_i16x2(uint16x2_t x) {
 uint8x8_t test_preinterpret_i8x8_u8x8(int8x8_t x) {
   return __riscv_preinterpret_i8x8_u8x8(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u16x4_u8x8(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7240,6 +7291,7 @@ uint8x8_t test_preinterpret_i8x8_u8x8(int8x8_t x) {
 uint8x8_t test_preinterpret_u16x4_u8x8(uint16x4_t x) {
   return __riscv_preinterpret_u16x4_u8x8(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i16x4_u8x8(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7248,6 +7300,7 @@ uint8x8_t test_preinterpret_u16x4_u8x8(uint16x4_t x) {
 uint8x8_t test_preinterpret_i16x4_u8x8(int16x4_t x) {
   return __riscv_preinterpret_i16x4_u8x8(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u32x2_u8x8(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7256,6 +7309,7 @@ uint8x8_t test_preinterpret_i16x4_u8x8(int16x4_t x) {
 uint8x8_t test_preinterpret_u32x2_u8x8(uint32x2_t x) {
   return __riscv_preinterpret_u32x2_u8x8(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i32x2_u8x8(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7264,6 +7318,7 @@ uint8x8_t test_preinterpret_u32x2_u8x8(uint32x2_t x) {
 uint8x8_t test_preinterpret_i32x2_u8x8(int32x2_t x) {
   return __riscv_preinterpret_i32x2_u8x8(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u8x8_i8x8(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7272,6 +7327,7 @@ uint8x8_t test_preinterpret_i32x2_u8x8(int32x2_t x) {
 int8x8_t test_preinterpret_u8x8_i8x8(uint8x8_t x) {
   return __riscv_preinterpret_u8x8_i8x8(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u16x4_i8x8(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7280,6 +7336,7 @@ int8x8_t test_preinterpret_u8x8_i8x8(uint8x8_t x) {
 int8x8_t test_preinterpret_u16x4_i8x8(uint16x4_t x) {
   return __riscv_preinterpret_u16x4_i8x8(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i16x4_i8x8(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7288,6 +7345,7 @@ int8x8_t test_preinterpret_u16x4_i8x8(uint16x4_t x) {
 int8x8_t test_preinterpret_i16x4_i8x8(int16x4_t x) {
   return __riscv_preinterpret_i16x4_i8x8(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u32x2_i8x8(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7296,6 +7354,7 @@ int8x8_t test_preinterpret_i16x4_i8x8(int16x4_t x) {
 int8x8_t test_preinterpret_u32x2_i8x8(uint32x2_t x) {
   return __riscv_preinterpret_u32x2_i8x8(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i32x2_i8x8(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7304,6 +7363,7 @@ int8x8_t test_preinterpret_u32x2_i8x8(uint32x2_t x) {
 int8x8_t test_preinterpret_i32x2_i8x8(int32x2_t x) {
   return __riscv_preinterpret_i32x2_i8x8(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u8x8_u16x4(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7312,6 +7372,7 @@ int8x8_t test_preinterpret_i32x2_i8x8(int32x2_t x) {
 uint16x4_t test_preinterpret_u8x8_u16x4(uint8x8_t x) {
   return __riscv_preinterpret_u8x8_u16x4(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i8x8_u16x4(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7320,6 +7381,7 @@ uint16x4_t test_preinterpret_u8x8_u16x4(uint8x8_t x) {
 uint16x4_t test_preinterpret_i8x8_u16x4(int8x8_t x) {
   return __riscv_preinterpret_i8x8_u16x4(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i16x4_u16x4(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7328,6 +7390,7 @@ uint16x4_t test_preinterpret_i8x8_u16x4(int8x8_t x) {
 uint16x4_t test_preinterpret_i16x4_u16x4(int16x4_t x) {
   return __riscv_preinterpret_i16x4_u16x4(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u32x2_u16x4(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7336,6 +7399,7 @@ uint16x4_t test_preinterpret_i16x4_u16x4(int16x4_t x) {
 uint16x4_t test_preinterpret_u32x2_u16x4(uint32x2_t x) {
   return __riscv_preinterpret_u32x2_u16x4(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i32x2_u16x4(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7344,6 +7408,7 @@ uint16x4_t test_preinterpret_u32x2_u16x4(uint32x2_t x) {
 uint16x4_t test_preinterpret_i32x2_u16x4(int32x2_t x) {
   return __riscv_preinterpret_i32x2_u16x4(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u8x8_i16x4(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7352,6 +7417,7 @@ uint16x4_t test_preinterpret_i32x2_u16x4(int32x2_t x) {
 int16x4_t test_preinterpret_u8x8_i16x4(uint8x8_t x) {
   return __riscv_preinterpret_u8x8_i16x4(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i8x8_i16x4(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7360,6 +7426,7 @@ int16x4_t test_preinterpret_u8x8_i16x4(uint8x8_t x) {
 int16x4_t test_preinterpret_i8x8_i16x4(int8x8_t x) {
   return __riscv_preinterpret_i8x8_i16x4(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u16x4_i16x4(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7368,6 +7435,7 @@ int16x4_t test_preinterpret_i8x8_i16x4(int8x8_t x) {
 int16x4_t test_preinterpret_u16x4_i16x4(uint16x4_t x) {
   return __riscv_preinterpret_u16x4_i16x4(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u32x2_i16x4(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7376,6 +7444,7 @@ int16x4_t test_preinterpret_u16x4_i16x4(uint16x4_t x) {
 int16x4_t test_preinterpret_u32x2_i16x4(uint32x2_t x) {
   return __riscv_preinterpret_u32x2_i16x4(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i32x2_i16x4(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7384,6 +7453,7 @@ int16x4_t test_preinterpret_u32x2_i16x4(uint32x2_t x) {
 int16x4_t test_preinterpret_i32x2_i16x4(int32x2_t x) {
   return __riscv_preinterpret_i32x2_i16x4(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u8x8_u32x2(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7392,6 +7462,7 @@ int16x4_t test_preinterpret_i32x2_i16x4(int32x2_t x) {
 uint32x2_t test_preinterpret_u8x8_u32x2(uint8x8_t x) {
   return __riscv_preinterpret_u8x8_u32x2(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i8x8_u32x2(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7400,6 +7471,7 @@ uint32x2_t test_preinterpret_u8x8_u32x2(uint8x8_t x) {
 uint32x2_t test_preinterpret_i8x8_u32x2(int8x8_t x) {
   return __riscv_preinterpret_i8x8_u32x2(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u16x4_u32x2(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7408,6 +7480,7 @@ uint32x2_t test_preinterpret_i8x8_u32x2(int8x8_t x) {
 uint32x2_t test_preinterpret_u16x4_u32x2(uint16x4_t x) {
   return __riscv_preinterpret_u16x4_u32x2(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i16x4_u32x2(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7416,6 +7489,7 @@ uint32x2_t test_preinterpret_u16x4_u32x2(uint16x4_t x) {
 uint32x2_t test_preinterpret_i16x4_u32x2(int16x4_t x) {
   return __riscv_preinterpret_i16x4_u32x2(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i32x2_u32x2(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7424,6 +7498,7 @@ uint32x2_t test_preinterpret_i16x4_u32x2(int16x4_t x) {
 uint32x2_t test_preinterpret_i32x2_u32x2(int32x2_t x) {
   return __riscv_preinterpret_i32x2_u32x2(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u8x8_i32x2(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7432,6 +7507,7 @@ uint32x2_t test_preinterpret_i32x2_u32x2(int32x2_t x) {
 int32x2_t test_preinterpret_u8x8_i32x2(uint8x8_t x) {
   return __riscv_preinterpret_u8x8_i32x2(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i8x8_i32x2(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7440,6 +7516,7 @@ int32x2_t test_preinterpret_u8x8_i32x2(uint8x8_t x) {
 int32x2_t test_preinterpret_i8x8_i32x2(int8x8_t x) {
   return __riscv_preinterpret_i8x8_i32x2(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u16x4_i32x2(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7448,6 +7525,7 @@ int32x2_t test_preinterpret_i8x8_i32x2(int8x8_t x) {
 int32x2_t test_preinterpret_u16x4_i32x2(uint16x4_t x) {
   return __riscv_preinterpret_u16x4_i32x2(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_i16x4_i32x2(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
@@ -7456,6 +7534,7 @@ int32x2_t test_preinterpret_u16x4_i32x2(uint16x4_t x) {
 int32x2_t test_preinterpret_i16x4_i32x2(int16x4_t x) {
   return __riscv_preinterpret_i16x4_i32x2(x);
 }
+
 // CHECK-LABEL: define dso_local i64 @test_preinterpret_u32x2_i32x2(
 // CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]

>From 1c0924f8c71d57c92e95b1e54519d5bef527fe5a Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 23 Oct 2026 17:59:39 -0700
Subject: [PATCH 2/5] Use script to generate pnclip tests

---
 clang/test/CodeGen/RISCV/rvp-intrinsics.c | 152 +++++++++++++++-------
 1 file changed, 104 insertions(+), 48 deletions(-)

diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
index 662847606ed11c..4c01744b2c9c77 100644
--- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c
+++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
@@ -7704,105 +7704,161 @@ uint16x4_t test_pnziph_u16x4(uint32x2_t rs1, uint32x2_t rs2) {
 
 /* Packed Narrowing Clip */
 
-// CHECK-LABEL: define dso_local i32 @test_pnclipu_s_u8x4(
+// RV32-LABEL: define dso_local i32 @test_pnclipu_s_u8x4(
 // RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnclipu.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]])
+// RV32-NEXT:    [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i32 @test_pnclipu_s_u8x4(
 // RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT:  [[ENTRY:.*:]]
-// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnclipu.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]])
-// CHECK-NEXT:    [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
-// CHECK-NEXT:    ret i32 [[TMP2]]
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnclipu.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]])
+// RV64-NEXT:    [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
+// RV64-NEXT:    ret i32 [[TMP2]]
 //
 uint8x4_t test_pnclipu_s_u8x4(uint16x4_t rs1, unsigned shamt) {
   return __riscv_pnclipu_s_u8x4(rs1, shamt);
 }
 
-// CHECK-LABEL: define dso_local i32 @test_pnclipu_s_u16x2(
+// RV32-LABEL: define dso_local i32 @test_pnclipu_s_u16x2(
 // RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV32-NEXT:    [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnclipu.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]])
+// RV32-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i32 @test_pnclipu_s_u16x2(
 // RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT:  [[ENTRY:.*:]]
-// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnclipu.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]])
-// CHECK-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-// CHECK-NEXT:    ret i32 [[TMP2]]
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV64-NEXT:    [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnclipu.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]])
+// RV64-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
+// RV64-NEXT:    ret i32 [[TMP2]]
 //
 uint16x2_t test_pnclipu_s_u16x2(uint32x2_t rs1, unsigned shamt) {
   return __riscv_pnclipu_s_u16x2(rs1, shamt);
 }
 
-// CHECK-LABEL: define dso_local i32 @test_pnclipru_s_u8x4(
+// RV32-LABEL: define dso_local i32 @test_pnclipru_s_u8x4(
 // RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnclipru.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]])
+// RV32-NEXT:    [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i32 @test_pnclipru_s_u8x4(
 // RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT:  [[ENTRY:.*:]]
-// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnclipru.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]])
-// CHECK-NEXT:    [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
-// CHECK-NEXT:    ret i32 [[TMP2]]
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnclipru.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]])
+// RV64-NEXT:    [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
+// RV64-NEXT:    ret i32 [[TMP2]]
 //
 uint8x4_t test_pnclipru_s_u8x4(uint16x4_t rs1, unsigned shamt) {
   return __riscv_pnclipru_s_u8x4(rs1, shamt);
 }
 
-// CHECK-LABEL: define dso_local i32 @test_pnclipru_s_u16x2(
+// RV32-LABEL: define dso_local i32 @test_pnclipru_s_u16x2(
 // RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV32-NEXT:    [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnclipru.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]])
+// RV32-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i32 @test_pnclipru_s_u16x2(
 // RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT:  [[ENTRY:.*:]]
-// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnclipru.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]])
-// CHECK-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-// CHECK-NEXT:    ret i32 [[TMP2]]
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV64-NEXT:    [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnclipru.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]])
+// RV64-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
+// RV64-NEXT:    ret i32 [[TMP2]]
 //
 uint16x2_t test_pnclipru_s_u16x2(uint32x2_t rs1, unsigned shamt) {
   return __riscv_pnclipru_s_u16x2(rs1, shamt);
 }
 
-// CHECK-LABEL: define dso_local i32 @test_pnclip_s_i8x4(
+// RV32-LABEL: define dso_local i32 @test_pnclip_s_i8x4(
 // RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnclip.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]])
+// RV32-NEXT:    [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i32 @test_pnclip_s_i8x4(
 // RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT:  [[ENTRY:.*:]]
-// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnclip.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]])
-// CHECK-NEXT:    [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
-// CHECK-NEXT:    ret i32 [[TMP2]]
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnclip.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]])
+// RV64-NEXT:    [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
+// RV64-NEXT:    ret i32 [[TMP2]]
 //
 int8x4_t test_pnclip_s_i8x4(int16x4_t rs1, unsigned shamt) {
   return __riscv_pnclip_s_i8x4(rs1, shamt);
 }
 
-// CHECK-LABEL: define dso_local i32 @test_pnclip_s_i16x2(
+// RV32-LABEL: define dso_local i32 @test_pnclip_s_i16x2(
 // RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV32-NEXT:    [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnclip.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]])
+// RV32-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i32 @test_pnclip_s_i16x2(
 // RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT:  [[ENTRY:.*:]]
-// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnclip.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]])
-// CHECK-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-// CHECK-NEXT:    ret i32 [[TMP2]]
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV64-NEXT:    [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnclip.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]])
+// RV64-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
+// RV64-NEXT:    ret i32 [[TMP2]]
 //
 int16x2_t test_pnclip_s_i16x2(int32x2_t rs1, unsigned shamt) {
   return __riscv_pnclip_s_i16x2(rs1, shamt);
 }
 
-// CHECK-LABEL: define dso_local i32 @test_pnclipr_s_i8x4(
+// RV32-LABEL: define dso_local i32 @test_pnclipr_s_i8x4(
 // RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnclipr.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]])
+// RV32-NEXT:    [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i32 @test_pnclipr_s_i8x4(
 // RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT:  [[ENTRY:.*:]]
-// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnclipr.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]])
-// CHECK-NEXT:    [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
-// CHECK-NEXT:    ret i32 [[TMP2]]
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnclipr.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]])
+// RV64-NEXT:    [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
+// RV64-NEXT:    ret i32 [[TMP2]]
 //
 int8x4_t test_pnclipr_s_i8x4(int16x4_t rs1, unsigned shamt) {
   return __riscv_pnclipr_s_i8x4(rs1, shamt);
 }
 
-// CHECK-LABEL: define dso_local i32 @test_pnclipr_s_i16x2(
+// RV32-LABEL: define dso_local i32 @test_pnclipr_s_i16x2(
 // RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV32-NEXT:    [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnclipr.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]])
+// RV32-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i32 @test_pnclipr_s_i16x2(
 // RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT:  [[ENTRY:.*:]]
-// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnclipr.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]])
-// CHECK-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-// CHECK-NEXT:    ret i32 [[TMP2]]
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV64-NEXT:    [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnclipr.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]])
+// RV64-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
+// RV64-NEXT:    ret i32 [[TMP2]]
 //
 int16x2_t test_pnclipr_s_i16x2(int32x2_t rs1, unsigned shamt) {
   return __riscv_pnclipr_s_i16x2(rs1, shamt);

>From 144c66dbc80ca8f1150d8d2ac48218f77245b706 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 23 Oct 2026 17:59:49 -0700
Subject: [PATCH 3/5] Add blank lines between tests

---
 clang/test/CodeGen/RISCV/rvp-intrinsics.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
index 4c01744b2c9c77..9a0b82f9f5d5f2 100644
--- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c
+++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
@@ -8025,6 +8025,7 @@ uint32x2_t test_pnclipup_u32x2(uint64_t rs1, uint64_t rs2) {
 int32_t test_mqacc_h00_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) {
   return __riscv_mqacc_h00_i32(rd, rs1, rs2);
 }
+
 // RV32-LABEL: define dso_local i32 @test_mqacc_h01_i32(
 // RV32-SAME: i32 noundef [[RD:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
 // RV32-NEXT:  [[ENTRY:.*:]]

>From c50b0c4f33a2fb83aac7accb9abda44d636bb700 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 23 Oct 2026 18:00:11 -0700
Subject: [PATCH 4/5] Add missing tests to rvp-intrinsics.c

---
 clang/test/CodeGen/RISCV/rvp-intrinsics.c | 2151 +++++++++++++++++++++
 1 file changed, 2151 insertions(+)

diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
index 9a0b82f9f5d5f2..0fa253c1cba893 100644
--- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c
+++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
@@ -10875,3 +10875,2154 @@ uint32x2_t test_pm4addau_u8x8(uint32x2_t rd, uint8x8_t a, uint8x8_t b) {
 int32x2_t test_pm4addasu_i8x8(int32x2_t rd, int8x8_t a, uint8x8_t b) {
   return __riscv_pm4addasu_i8x8(rd, a, b);
 }
+
+// CHECK-LABEL: define dso_local i32 @test_pmul_b00_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmul.00.v2i16(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT:    ret i32 [[TMP3]]
+//
+int16x2_t test_pmul_b00_i16x2(int8x4_t a, int8x4_t b) {
+  return __riscv_pmul_b00_i16x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmul_b01_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmul.01.v2i16(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT:    ret i32 [[TMP3]]
+//
+int16x2_t test_pmul_b01_i16x2(int8x4_t a, int8x4_t b) {
+  return __riscv_pmul_b01_i16x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmul_b11_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmul.11.v2i16(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT:    ret i32 [[TMP3]]
+//
+int16x2_t test_pmul_b11_i16x2(int8x4_t a, int8x4_t b) {
+  return __riscv_pmul_b11_i16x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmulu_b00_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulu.00.v2i16(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT:    ret i32 [[TMP3]]
+//
+uint16x2_t test_pmulu_b00_u16x2(uint8x4_t a, uint8x4_t b) {
+  return __riscv_pmulu_b00_u16x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmulu_b01_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulu.01.v2i16(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT:    ret i32 [[TMP3]]
+//
+uint16x2_t test_pmulu_b01_u16x2(uint8x4_t a, uint8x4_t b) {
+  return __riscv_pmulu_b01_u16x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmulu_b11_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulu.11.v2i16(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT:    ret i32 [[TMP3]]
+//
+uint16x2_t test_pmulu_b11_u16x2(uint8x4_t a, uint8x4_t b) {
+  return __riscv_pmulu_b11_u16x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmulsu_b00_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulsu.00.v2i16(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT:    ret i32 [[TMP3]]
+//
+int16x2_t test_pmulsu_b00_i16x2(int8x4_t a, uint8x4_t b) {
+  return __riscv_pmulsu_b00_i16x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmulsu_b11_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulsu.11.v2i16(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT:    ret i32 [[TMP3]]
+//
+int16x2_t test_pmulsu_b11_i16x2(int8x4_t a, uint8x4_t b) {
+  return __riscv_pmulsu_b11_i16x2(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_mul_h00_i32(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.mul.00.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_mul_h00_i32(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.mul.00.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_mul_h00_i32(int16x2_t a, int16x2_t b) {
+  return __riscv_mul_h00_i32(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_mul_h01_i32(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.mul.01.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_mul_h01_i32(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.mul.01.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_mul_h01_i32(int16x2_t a, int16x2_t b) {
+  return __riscv_mul_h01_i32(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_mul_h11_i32(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.mul.11.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_mul_h11_i32(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.mul.11.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_mul_h11_i32(int16x2_t a, int16x2_t b) {
+  return __riscv_mul_h11_i32(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_mulu_h00_u32(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.mulu.00.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_mulu_h00_u32(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.mulu.00.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+uint32_t test_mulu_h00_u32(uint16x2_t a, uint16x2_t b) {
+  return __riscv_mulu_h00_u32(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_mulu_h01_u32(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.mulu.01.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_mulu_h01_u32(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.mulu.01.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+uint32_t test_mulu_h01_u32(uint16x2_t a, uint16x2_t b) {
+  return __riscv_mulu_h01_u32(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_mulu_h11_u32(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.mulu.11.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_mulu_h11_u32(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.mulu.11.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+uint32_t test_mulu_h11_u32(uint16x2_t a, uint16x2_t b) {
+  return __riscv_mulu_h11_u32(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_mulsu_h00_i32(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.mulsu.00.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_mulsu_h00_i32(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.mulsu.00.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_mulsu_h00_i32(int16x2_t a, uint16x2_t b) {
+  return __riscv_mulsu_h00_i32(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_mulsu_h11_i32(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.mulsu.11.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_mulsu_h11_i32(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.mulsu.11.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_mulsu_h11_i32(int16x2_t a, uint16x2_t b) {
+  return __riscv_mulsu_h11_i32(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmul_b00_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmul.00.v4i16(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int16x4_t test_pmul_b00_i16x4(int8x8_t a, int8x8_t b) {
+  return __riscv_pmul_b00_i16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmul_b01_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmul.01.v4i16(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int16x4_t test_pmul_b01_i16x4(int8x8_t a, int8x8_t b) {
+  return __riscv_pmul_b01_i16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmul_b11_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmul.11.v4i16(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int16x4_t test_pmul_b11_i16x4(int8x8_t a, int8x8_t b) {
+  return __riscv_pmul_b11_i16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulu_b00_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulu.00.v4i16(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+uint16x4_t test_pmulu_b00_u16x4(uint8x8_t a, uint8x8_t b) {
+  return __riscv_pmulu_b00_u16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulu_b01_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulu.01.v4i16(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+uint16x4_t test_pmulu_b01_u16x4(uint8x8_t a, uint8x8_t b) {
+  return __riscv_pmulu_b01_u16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulu_b11_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulu.11.v4i16(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+uint16x4_t test_pmulu_b11_u16x4(uint8x8_t a, uint8x8_t b) {
+  return __riscv_pmulu_b11_u16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulsu_b00_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulsu.00.v4i16(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int16x4_t test_pmulsu_b00_i16x4(int8x8_t a, uint8x8_t b) {
+  return __riscv_pmulsu_b00_i16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulsu_b11_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulsu.11.v4i16(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int16x4_t test_pmulsu_b11_i16x4(int8x8_t a, uint8x8_t b) {
+  return __riscv_pmulsu_b11_i16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmul_h00_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmul.00.v2i32(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int32x2_t test_pmul_h00_i32x2(int16x4_t a, int16x4_t b) {
+  return __riscv_pmul_h00_i32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmul_h01_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmul.01.v2i32(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int32x2_t test_pmul_h01_i32x2(int16x4_t a, int16x4_t b) {
+  return __riscv_pmul_h01_i32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmul_h11_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmul.11.v2i32(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int32x2_t test_pmul_h11_i32x2(int16x4_t a, int16x4_t b) {
+  return __riscv_pmul_h11_i32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulu_h00_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulu.00.v2i32(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+uint32x2_t test_pmulu_h00_u32x2(uint16x4_t a, uint16x4_t b) {
+  return __riscv_pmulu_h00_u32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulu_h01_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulu.01.v2i32(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+uint32x2_t test_pmulu_h01_u32x2(uint16x4_t a, uint16x4_t b) {
+  return __riscv_pmulu_h01_u32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulu_h11_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulu.11.v2i32(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+uint32x2_t test_pmulu_h11_u32x2(uint16x4_t a, uint16x4_t b) {
+  return __riscv_pmulu_h11_u32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulsu_h00_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulsu.00.v2i32(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int32x2_t test_pmulsu_h00_i32x2(int16x4_t a, uint16x4_t b) {
+  return __riscv_pmulsu_h00_i32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulsu_h11_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulsu.11.v2i32(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int32x2_t test_pmulsu_h11_i32x2(int16x4_t a, uint16x4_t b) {
+  return __riscv_pmulsu_h11_i32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_mul_w00_i64(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.mul.00.i64.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+int64_t test_mul_w00_i64(int32x2_t a, int32x2_t b) {
+  return __riscv_mul_w00_i64(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_mul_w01_i64(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.mul.01.i64.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+int64_t test_mul_w01_i64(int32x2_t a, int32x2_t b) {
+  return __riscv_mul_w01_i64(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_mul_w11_i64(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.mul.11.i64.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+int64_t test_mul_w11_i64(int32x2_t a, int32x2_t b) {
+  return __riscv_mul_w11_i64(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_mulu_w00_u64(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.mulu.00.i64.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+uint64_t test_mulu_w00_u64(uint32x2_t a, uint32x2_t b) {
+  return __riscv_mulu_w00_u64(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_mulu_w01_u64(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.mulu.01.i64.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+uint64_t test_mulu_w01_u64(uint32x2_t a, uint32x2_t b) {
+  return __riscv_mulu_w01_u64(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_mulu_w11_u64(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.mulu.11.i64.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+uint64_t test_mulu_w11_u64(uint32x2_t a, uint32x2_t b) {
+  return __riscv_mulu_w11_u64(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_mulsu_w00_i64(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.mulsu.00.i64.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+int64_t test_mulsu_w00_i64(int32x2_t a, uint32x2_t b) {
+  return __riscv_mulsu_w00_i64(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_mulsu_w11_i64(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.mulsu.11.i64.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+int64_t test_mulsu_w11_i64(int32x2_t a, uint32x2_t b) {
+  return __riscv_mulsu_w11_i64(a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmulh_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i16> @llvm.smulh.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT:    ret i32 [[TMP3]]
+//
+int16x2_t test_pmulh_i16x2(int16x2_t a, int16x2_t b) {
+  return __riscv_pmulh_i16x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmulhr_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhr.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT:    ret i32 [[TMP3]]
+//
+int16x2_t test_pmulhr_i16x2(int16x2_t a, int16x2_t b) {
+  return __riscv_pmulhr_i16x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmulhu_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i16> @llvm.umulh.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT:    ret i32 [[TMP3]]
+//
+uint16x2_t test_pmulhu_u16x2(uint16x2_t a, uint16x2_t b) {
+  return __riscv_pmulhu_u16x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmulhru_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhru.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT:    ret i32 [[TMP3]]
+//
+uint16x2_t test_pmulhru_u16x2(uint16x2_t a, uint16x2_t b) {
+  return __riscv_pmulhru_u16x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmulhsu_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT:    ret i32 [[TMP3]]
+//
+int16x2_t test_pmulhsu_i16x2(int16x2_t a, uint16x2_t b) {
+  return __riscv_pmulhsu_i16x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmulhrsu_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhrsu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT:    ret i32 [[TMP3]]
+//
+int16x2_t test_pmulhrsu_i16x2(int16x2_t a, uint16x2_t b) {
+  return __riscv_pmulhrsu_i16x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmhacc_i16x2(
+// CHECK-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmhacc.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32
+// CHECK-NEXT:    ret i32 [[TMP4]]
+//
+int16x2_t test_pmhacc_i16x2(int16x2_t rd, int16x2_t a, int16x2_t b) {
+  return __riscv_pmhacc_i16x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmhracc_i16x2(
+// CHECK-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmhracc.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32
+// CHECK-NEXT:    ret i32 [[TMP4]]
+//
+int16x2_t test_pmhracc_i16x2(int16x2_t rd, int16x2_t a, int16x2_t b) {
+  return __riscv_pmhracc_i16x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmhaccu_u16x2(
+// CHECK-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmhaccu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32
+// CHECK-NEXT:    ret i32 [[TMP4]]
+//
+uint16x2_t test_pmhaccu_u16x2(uint16x2_t rd, uint16x2_t a, uint16x2_t b) {
+  return __riscv_pmhaccu_u16x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmhraccu_u16x2(
+// CHECK-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmhraccu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32
+// CHECK-NEXT:    ret i32 [[TMP4]]
+//
+uint16x2_t test_pmhraccu_u16x2(uint16x2_t rd, uint16x2_t a, uint16x2_t b) {
+  return __riscv_pmhraccu_u16x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmhaccsu_i16x2(
+// CHECK-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmhaccsu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32
+// CHECK-NEXT:    ret i32 [[TMP4]]
+//
+int16x2_t test_pmhaccsu_i16x2(int16x2_t rd, int16x2_t a, uint16x2_t b) {
+  return __riscv_pmhaccsu_i16x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmhraccsu_i16x2(
+// CHECK-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmhraccsu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32
+// CHECK-NEXT:    ret i32 [[TMP4]]
+//
+int16x2_t test_pmhraccsu_i16x2(int16x2_t rd, int16x2_t a, uint16x2_t b) {
+  return __riscv_pmhraccsu_i16x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulh_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i16> @llvm.smulh.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int16x4_t test_pmulh_i16x4(int16x4_t a, int16x4_t b) {
+  return __riscv_pmulh_i16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulh_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.smulh.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int32x2_t test_pmulh_i32x2(int32x2_t a, int32x2_t b) {
+  return __riscv_pmulh_i32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulhr_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhr.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int16x4_t test_pmulhr_i16x4(int16x4_t a, int16x4_t b) {
+  return __riscv_pmulhr_i16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulhr_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhr.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int32x2_t test_pmulhr_i32x2(int32x2_t a, int32x2_t b) {
+  return __riscv_pmulhr_i32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulhu_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i16> @llvm.umulh.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+uint16x4_t test_pmulhu_u16x4(uint16x4_t a, uint16x4_t b) {
+  return __riscv_pmulhu_u16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulhu_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.umulh.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+uint32x2_t test_pmulhu_u32x2(uint32x2_t a, uint32x2_t b) {
+  return __riscv_pmulhu_u32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulhru_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhru.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+uint16x4_t test_pmulhru_u16x4(uint16x4_t a, uint16x4_t b) {
+  return __riscv_pmulhru_u16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulhru_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhru.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+uint32x2_t test_pmulhru_u32x2(uint32x2_t a, uint32x2_t b) {
+  return __riscv_pmulhru_u32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulhsu_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhsu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int16x4_t test_pmulhsu_i16x4(int16x4_t a, uint16x4_t b) {
+  return __riscv_pmulhsu_i16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulhsu_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhsu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int32x2_t test_pmulhsu_i32x2(int32x2_t a, uint32x2_t b) {
+  return __riscv_pmulhsu_i32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulhrsu_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhrsu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int16x4_t test_pmulhrsu_i16x4(int16x4_t a, uint16x4_t b) {
+  return __riscv_pmulhrsu_i16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulhrsu_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhrsu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int32x2_t test_pmulhrsu_i32x2(int32x2_t a, uint32x2_t b) {
+  return __riscv_pmulhrsu_i32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmhacc_i16x4(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmhacc.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int16x4_t test_pmhacc_i16x4(int16x4_t rd, int16x4_t a, int16x4_t b) {
+  return __riscv_pmhacc_i16x4(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmhacc_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmhacc.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int32x2_t test_pmhacc_i32x2(int32x2_t rd, int32x2_t a, int32x2_t b) {
+  return __riscv_pmhacc_i32x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmhracc_i16x4(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmhracc.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int16x4_t test_pmhracc_i16x4(int16x4_t rd, int16x4_t a, int16x4_t b) {
+  return __riscv_pmhracc_i16x4(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmhracc_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmhracc.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int32x2_t test_pmhracc_i32x2(int32x2_t rd, int32x2_t a, int32x2_t b) {
+  return __riscv_pmhracc_i32x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmhaccu_u16x4(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmhaccu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+uint16x4_t test_pmhaccu_u16x4(uint16x4_t rd, uint16x4_t a, uint16x4_t b) {
+  return __riscv_pmhaccu_u16x4(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmhaccu_u32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmhaccu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+uint32x2_t test_pmhaccu_u32x2(uint32x2_t rd, uint32x2_t a, uint32x2_t b) {
+  return __riscv_pmhaccu_u32x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmhraccu_u16x4(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmhraccu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+uint16x4_t test_pmhraccu_u16x4(uint16x4_t rd, uint16x4_t a, uint16x4_t b) {
+  return __riscv_pmhraccu_u16x4(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmhraccu_u32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmhraccu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+uint32x2_t test_pmhraccu_u32x2(uint32x2_t rd, uint32x2_t a, uint32x2_t b) {
+  return __riscv_pmhraccu_u32x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmhaccsu_i16x4(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmhaccsu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int16x4_t test_pmhaccsu_i16x4(int16x4_t rd, int16x4_t a, uint16x4_t b) {
+  return __riscv_pmhaccsu_i16x4(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmhaccsu_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmhaccsu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int32x2_t test_pmhaccsu_i32x2(int32x2_t rd, int32x2_t a, uint32x2_t b) {
+  return __riscv_pmhaccsu_i32x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmhraccsu_i16x4(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmhraccsu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int16x4_t test_pmhraccsu_i16x4(int16x4_t rd, int16x4_t a, uint16x4_t b) {
+  return __riscv_pmhraccsu_i16x4(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmhraccsu_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmhraccsu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int32x2_t test_pmhraccsu_i32x2(int32x2_t rd, int32x2_t a, uint32x2_t b) {
+  return __riscv_pmhraccsu_i32x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmhacc_b0_i16x2(
+// CHECK-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmhacc.b0.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i8> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32
+// CHECK-NEXT:    ret i32 [[TMP4]]
+//
+int16x2_t test_pmhacc_b0_i16x2(int16x2_t rd, int16x2_t a, int8x4_t b) {
+  return __riscv_pmhacc_b0_i16x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmhacc_b1_i16x2(
+// CHECK-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmhacc.b1.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i8> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32
+// CHECK-NEXT:    ret i32 [[TMP4]]
+//
+int16x2_t test_pmhacc_b1_i16x2(int16x2_t rd, int16x2_t a, int8x4_t b) {
+  return __riscv_pmhacc_b1_i16x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmhaccsu_b0_i16x2(
+// CHECK-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmhaccsu.b0.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i8> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32
+// CHECK-NEXT:    ret i32 [[TMP4]]
+//
+int16x2_t test_pmhaccsu_b0_i16x2(int16x2_t rd, int16x2_t a, uint8x4_t b) {
+  return __riscv_pmhaccsu_b0_i16x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pmhaccsu_b1_i16x2(
+// CHECK-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmhaccsu.b1.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i8> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32
+// CHECK-NEXT:    ret i32 [[TMP4]]
+//
+int16x2_t test_pmhaccsu_b1_i16x2(int16x2_t rd, int16x2_t a, uint8x4_t b) {
+  return __riscv_pmhaccsu_b1_i16x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmhacc_b0_i16x4(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmhacc.b0.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <8 x i8> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int16x4_t test_pmhacc_b0_i16x4(int16x4_t rd, int16x4_t a, int8x8_t b) {
+  return __riscv_pmhacc_b0_i16x4(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmhacc_b1_i16x4(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmhacc.b1.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <8 x i8> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int16x4_t test_pmhacc_b1_i16x4(int16x4_t rd, int16x4_t a, int8x8_t b) {
+  return __riscv_pmhacc_b1_i16x4(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmhaccsu_b0_i16x4(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmhaccsu.b0.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <8 x i8> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int16x4_t test_pmhaccsu_b0_i16x4(int16x4_t rd, int16x4_t a, uint8x8_t b) {
+  return __riscv_pmhaccsu_b0_i16x4(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmhaccsu_b1_i16x4(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmhaccsu.b1.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <8 x i8> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int16x4_t test_pmhaccsu_b1_i16x4(int16x4_t rd, int16x4_t a, uint8x8_t b) {
+  return __riscv_pmhaccsu_b1_i16x4(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmhacc_h0_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmhacc.h0.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int32x2_t test_pmhacc_h0_i32x2(int32x2_t rd, int32x2_t a, int16x4_t b) {
+  return __riscv_pmhacc_h0_i32x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmhacc_h1_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmhacc.h1.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int32x2_t test_pmhacc_h1_i32x2(int32x2_t rd, int32x2_t a, int16x4_t b) {
+  return __riscv_pmhacc_h1_i32x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmhaccsu_h0_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmhaccsu.h0.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int32x2_t test_pmhaccsu_h0_i32x2(int32x2_t rd, int32x2_t a, uint16x4_t b) {
+  return __riscv_pmhaccsu_h0_i32x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmhaccsu_h1_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmhaccsu.h1.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int32x2_t test_pmhaccsu_h1_i32x2(int32x2_t rd, int32x2_t a, uint16x4_t b) {
+  return __riscv_pmhaccsu_h1_i32x2(rd, a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pm4add_i8x4(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm4add.i32.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_pm4add_i8x4(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm4add.i32.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_pm4add_i8x4(int8x4_t a, int8x4_t b) {
+  return __riscv_pm4add_i8x4(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pm2add_i16x2(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm2add.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_pm2add_i16x2(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm2add.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_pm2add_i16x2(int16x2_t a, int16x2_t b) {
+  return __riscv_pm2add_i16x2(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pm2add_x_i16x2(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm2add.x.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_pm2add_x_i16x2(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm2add.x.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_pm2add_x_i16x2(int16x2_t a, int16x2_t b) {
+  return __riscv_pm2add_x_i16x2(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pm4addu_u8x4(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm4addu.i32.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_pm4addu_u8x4(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm4addu.i32.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+uint32_t test_pm4addu_u8x4(uint8x4_t a, uint8x4_t b) {
+  return __riscv_pm4addu_u8x4(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pm2addu_u16x2(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm2addu.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_pm2addu_u16x2(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm2addu.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+uint32_t test_pm2addu_u16x2(uint16x2_t a, uint16x2_t b) {
+  return __riscv_pm2addu_u16x2(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pmq2add_i16x2(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pmq2add.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_pmq2add_i16x2(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pmq2add.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_pmq2add_i16x2(int16x2_t a, int16x2_t b) {
+  return __riscv_pmq2add_i16x2(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pmqr2add_i16x2(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pmqr2add.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_pmqr2add_i16x2(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pmqr2add.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_pmqr2add_i16x2(int16x2_t a, int16x2_t b) {
+  return __riscv_pmqr2add_i16x2(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pm2sadd_i16x2(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm2sadd.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_pm2sadd_i16x2(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm2sadd.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_pm2sadd_i16x2(int16x2_t a, int16x2_t b) {
+  return __riscv_pm2sadd_i16x2(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pm2sadd_x_i16x2(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm2sadd.x.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_pm2sadd_x_i16x2(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm2sadd.x.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_pm2sadd_x_i16x2(int16x2_t a, int16x2_t b) {
+  return __riscv_pm2sadd_x_i16x2(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pm2sub_i16x2(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm2sub.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_pm2sub_i16x2(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm2sub.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_pm2sub_i16x2(int16x2_t a, int16x2_t b) {
+  return __riscv_pm2sub_i16x2(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pm2sub_x_i16x2(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm2sub.x.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_pm2sub_x_i16x2(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm2sub.x.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_pm2sub_x_i16x2(int16x2_t a, int16x2_t b) {
+  return __riscv_pm2sub_x_i16x2(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pm4addsu_i8x4(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm4addsu.i32.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_pm4addsu_i8x4(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm4addsu.i32.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_pm4addsu_i8x4(int8x4_t a, uint8x4_t b) {
+  return __riscv_pm4addsu_i8x4(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pm2addsu_i16x2(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm2addsu.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_pm2addsu_i16x2(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.pm2addsu.i32.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_pm2addsu_i16x2(int16x2_t a, uint16x2_t b) {
+  return __riscv_pm2addsu_i16x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pm4add_i8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pm4add.v2i32.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int32x2_t test_pm4add_i8x8(int8x8_t a, int8x8_t b) {
+  return __riscv_pm4add_i8x8(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pm2add_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pm2add.v2i32.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int32x2_t test_pm2add_i16x4(int16x4_t a, int16x4_t b) {
+  return __riscv_pm2add_i16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pm2add_x_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pm2add.x.v2i32.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int32x2_t test_pm2add_x_i16x4(int16x4_t a, int16x4_t b) {
+  return __riscv_pm2add_x_i16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pm4addu_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pm4addu.v2i32.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+uint32x2_t test_pm4addu_u8x8(uint8x8_t a, uint8x8_t b) {
+  return __riscv_pm4addu_u8x8(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pm2addu_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pm2addu.v2i32.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+uint32x2_t test_pm2addu_u16x4(uint16x4_t a, uint16x4_t b) {
+  return __riscv_pm2addu_u16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmq2add_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmq2add.v2i32.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int32x2_t test_pmq2add_i16x4(int16x4_t a, int16x4_t b) {
+  return __riscv_pmq2add_i16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmqr2add_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmqr2add.v2i32.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int32x2_t test_pmqr2add_i16x4(int16x4_t a, int16x4_t b) {
+  return __riscv_pmqr2add_i16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pm2sadd_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pm2sadd.v2i32.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int32x2_t test_pm2sadd_i16x4(int16x4_t a, int16x4_t b) {
+  return __riscv_pm2sadd_i16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pm2sadd_x_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pm2sadd.x.v2i32.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int32x2_t test_pm2sadd_x_i16x4(int16x4_t a, int16x4_t b) {
+  return __riscv_pm2sadd_x_i16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pm2sub_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pm2sub.v2i32.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int32x2_t test_pm2sub_i16x4(int16x4_t a, int16x4_t b) {
+  return __riscv_pm2sub_i16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pm2sub_x_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pm2sub.x.v2i32.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int32x2_t test_pm2sub_x_i16x4(int16x4_t a, int16x4_t b) {
+  return __riscv_pm2sub_x_i16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pm4addsu_i8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pm4addsu.v2i32.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int32x2_t test_pm4addsu_i8x8(int8x8_t a, uint8x8_t b) {
+  return __riscv_pm4addsu_i8x8(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pm2addsu_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pm2addsu.v2i32.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT:    ret i64 [[TMP3]]
+//
+int32x2_t test_pm2addsu_i16x4(int16x4_t a, uint16x4_t b) {
+  return __riscv_pm2addsu_i16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pm2add_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.pm2add.i64.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+int64_t test_pm2add_i32x2(int32x2_t a, int32x2_t b) {
+  return __riscv_pm2add_i32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pm2add_x_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.pm2add.x.i64.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+int64_t test_pm2add_x_i32x2(int32x2_t a, int32x2_t b) {
+  return __riscv_pm2add_x_i32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pm2addu_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.pm2addu.i64.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+uint64_t test_pm2addu_u32x2(uint32x2_t a, uint32x2_t b) {
+  return __riscv_pm2addu_u32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmq2add_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.pmq2add.i64.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+int64_t test_pmq2add_i32x2(int32x2_t a, int32x2_t b) {
+  return __riscv_pmq2add_i32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pm2sub_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.pm2sub.i64.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+int64_t test_pm2sub_i32x2(int32x2_t a, int32x2_t b) {
+  return __riscv_pm2sub_i32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pm2sub_x_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.pm2sub.x.i64.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+int64_t test_pm2sub_x_i32x2(int32x2_t a, int32x2_t b) {
+  return __riscv_pm2sub_x_i32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pm2addsu_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.pm2addsu.i64.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+int64_t test_pm2addsu_i32x2(int32x2_t a, uint32x2_t b) {
+  return __riscv_pm2addsu_i32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmqr2add_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.pmqr2add.i64.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+int64_t test_pmqr2add_i32x2(int32x2_t a, int32x2_t b) {
+  return __riscv_pmqr2add_i32x2(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pm4add_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.pm4add.i64.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+int64_t test_pm4add_i16x4(int16x4_t a, int16x4_t b) {
+  return __riscv_pm4add_i16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pm4addu_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.pm4addu.i64.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+uint64_t test_pm4addu_u16x4(uint16x4_t a, uint16x4_t b) {
+  return __riscv_pm4addu_u16x4(a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pm4addsu_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.pm4addsu.i64.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+int64_t test_pm4addsu_i16x4(int16x4_t a, uint16x4_t b) {
+  return __riscv_pm4addsu_i16x4(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_macc_h00_i32(
+// RV32-SAME: i32 noundef [[RD:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.macc.00.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_macc_h00_i32(
+// RV64-SAME: i32 noundef signext [[RD:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.macc.00.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_macc_h00_i32(int32_t rd, int16x2_t a, int16x2_t b) {
+  return __riscv_macc_h00_i32(rd, a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_macc_h01_i32(
+// RV32-SAME: i32 noundef [[RD:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.macc.01.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_macc_h01_i32(
+// RV64-SAME: i32 noundef signext [[RD:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.macc.01.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_macc_h01_i32(int32_t rd, int16x2_t a, int16x2_t b) {
+  return __riscv_macc_h01_i32(rd, a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_macc_h11_i32(
+// RV32-SAME: i32 noundef [[RD:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.macc.11.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_macc_h11_i32(
+// RV64-SAME: i32 noundef signext [[RD:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.macc.11.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_macc_h11_i32(int32_t rd, int16x2_t a, int16x2_t b) {
+  return __riscv_macc_h11_i32(rd, a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_maccu_h00_u32(
+// RV32-SAME: i32 noundef [[RD:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.maccu.00.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_maccu_h00_u32(
+// RV64-SAME: i32 noundef signext [[RD:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.maccu.00.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+uint32_t test_maccu_h00_u32(uint32_t rd, uint16x2_t a, uint16x2_t b) {
+  return __riscv_maccu_h00_u32(rd, a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_maccu_h01_u32(
+// RV32-SAME: i32 noundef [[RD:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.maccu.01.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_maccu_h01_u32(
+// RV64-SAME: i32 noundef signext [[RD:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.maccu.01.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+uint32_t test_maccu_h01_u32(uint32_t rd, uint16x2_t a, uint16x2_t b) {
+  return __riscv_maccu_h01_u32(rd, a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_maccu_h11_u32(
+// RV32-SAME: i32 noundef [[RD:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.maccu.11.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_maccu_h11_u32(
+// RV64-SAME: i32 noundef signext [[RD:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.maccu.11.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+uint32_t test_maccu_h11_u32(uint32_t rd, uint16x2_t a, uint16x2_t b) {
+  return __riscv_maccu_h11_u32(rd, a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_maccsu_h00_i32(
+// RV32-SAME: i32 noundef [[RD:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.maccsu.00.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_maccsu_h00_i32(
+// RV64-SAME: i32 noundef signext [[RD:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.maccsu.00.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_maccsu_h00_i32(int32_t rd, int16x2_t a, uint16x2_t b) {
+  return __riscv_maccsu_h00_i32(rd, a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_maccsu_h11_i32(
+// RV32-SAME: i32 noundef [[RD:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT:  [[ENTRY:.*:]]
+// RV32-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.maccsu.11.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT:    ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_maccsu_h11_i32(
+// RV64-SAME: i32 noundef signext [[RD:%.*]], i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT:  [[ENTRY:.*:]]
+// RV64-NEXT:    [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.maccsu.11.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT:    ret i32 [[TMP2]]
+//
+int32_t test_maccsu_h11_i32(int32_t rd, int16x2_t a, uint16x2_t b) {
+  return __riscv_maccsu_h11_i32(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmacc_h00_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.macc.00.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int32x2_t test_pmacc_h00_i32x2(int32x2_t rd, int16x4_t a, int16x4_t b) {
+  return __riscv_pmacc_h00_i32x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmacc_h01_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.macc.01.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int32x2_t test_pmacc_h01_i32x2(int32x2_t rd, int16x4_t a, int16x4_t b) {
+  return __riscv_pmacc_h01_i32x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmacc_h11_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.macc.11.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int32x2_t test_pmacc_h11_i32x2(int32x2_t rd, int16x4_t a, int16x4_t b) {
+  return __riscv_pmacc_h11_i32x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmaccu_h00_u32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.maccu.00.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+uint32x2_t test_pmaccu_h00_u32x2(uint32x2_t rd, uint16x4_t a, uint16x4_t b) {
+  return __riscv_pmaccu_h00_u32x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmaccu_h01_u32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.maccu.01.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+uint32x2_t test_pmaccu_h01_u32x2(uint32x2_t rd, uint16x4_t a, uint16x4_t b) {
+  return __riscv_pmaccu_h01_u32x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmaccu_h11_u32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.maccu.11.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+uint32x2_t test_pmaccu_h11_u32x2(uint32x2_t rd, uint16x4_t a, uint16x4_t b) {
+  return __riscv_pmaccu_h11_u32x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmaccsu_h00_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.maccsu.00.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int32x2_t test_pmaccsu_h00_i32x2(int32x2_t rd, int16x4_t a, uint16x4_t b) {
+  return __riscv_pmaccsu_h00_i32x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmaccsu_h11_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT:    [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.maccsu.11.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT:    ret i64 [[TMP4]]
+//
+int32x2_t test_pmaccsu_h11_i32x2(int32x2_t rd, int16x4_t a, uint16x4_t b) {
+  return __riscv_pmaccsu_h11_i32x2(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_macc_w00_i64(
+// CHECK-SAME: i64 noundef [[RD:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.macc.00.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+int64_t test_macc_w00_i64(int64_t rd, int32x2_t a, int32x2_t b) {
+  return __riscv_macc_w00_i64(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_macc_w01_i64(
+// CHECK-SAME: i64 noundef [[RD:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.macc.01.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+int64_t test_macc_w01_i64(int64_t rd, int32x2_t a, int32x2_t b) {
+  return __riscv_macc_w01_i64(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_macc_w11_i64(
+// CHECK-SAME: i64 noundef [[RD:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.macc.11.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+int64_t test_macc_w11_i64(int64_t rd, int32x2_t a, int32x2_t b) {
+  return __riscv_macc_w11_i64(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_maccu_w00_u64(
+// CHECK-SAME: i64 noundef [[RD:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.maccu.00.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+uint64_t test_maccu_w00_u64(uint64_t rd, uint32x2_t a, uint32x2_t b) {
+  return __riscv_maccu_w00_u64(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_maccu_w01_u64(
+// CHECK-SAME: i64 noundef [[RD:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.maccu.01.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+uint64_t test_maccu_w01_u64(uint64_t rd, uint32x2_t a, uint32x2_t b) {
+  return __riscv_maccu_w01_u64(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_maccu_w11_u64(
+// CHECK-SAME: i64 noundef [[RD:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.maccu.11.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+uint64_t test_maccu_w11_u64(uint64_t rd, uint32x2_t a, uint32x2_t b) {
+  return __riscv_maccu_w11_u64(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_maccsu_w00_i64(
+// CHECK-SAME: i64 noundef [[RD:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.maccsu.00.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+int64_t test_maccsu_w00_i64(int64_t rd, int32x2_t a, uint32x2_t b) {
+  return __riscv_maccsu_w00_i64(rd, a, b);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_maccsu_w11_i64(
+// CHECK-SAME: i64 noundef [[RD:%.*]], i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.maccsu.11.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT:    ret i64 [[TMP2]]
+//
+int64_t test_maccsu_w11_i64(int64_t rd, int32x2_t a, uint32x2_t b) {
+  return __riscv_maccsu_w11_i64(rd, a, b);
+}

>From 15352d5dccd5d2c2c86833942df665ad69150850 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 23 Oct 2026 18:13:26 -0700
Subject: [PATCH 5/5] Add missing pnclip tests to riscv_packed_simd.c

---
 .../riscv_packed_simd.c                       | 72 +++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
index 365af7c993a5f6..8ce714923c25d8 100644
--- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
@@ -4086,6 +4086,78 @@ uint16x2_t test_pnclipup_u16x2(uint32_t a, uint32_t b) {
   return __riscv_pnclipup_u16x2(a, b);
 }
 
+// CHECK-LABEL: test_pnclipu_s_u8x4:
+// RV32:        pnclipu.bs
+// RV64:        psrl.hs
+// RV64:        pnclipup.b
+uint8x4_t test_pnclipu_s_u8x4(uint16x4_t a, unsigned shamt) {
+  return __riscv_pnclipu_s_u8x4(a, shamt);
+}
+
+// CHECK-LABEL: test_pnclipu_s_u16x2:
+// RV32:        pnclipu.hs
+// RV64:        psrl.ws
+// RV64:        pnclipup.h
+uint16x2_t test_pnclipu_s_u16x2(uint32x2_t a, unsigned shamt) {
+  return __riscv_pnclipu_s_u16x2(a, shamt);
+}
+
+// CHECK-LABEL: test_pnclipru_s_u8x4:
+// RV32:        pnclipru.bs
+// RV64:        andi [[REG:a[0-9]+]], a1, 31
+// RV64-NEXT:   neg [[REG2:a[0-9]+]], [[REG]]
+// RV64-NEXT:   psshlr.hs a0, a0, [[REG2]]
+// RV64-NEXT:   pnclipup.b a0, a0, zero
+uint8x4_t test_pnclipru_s_u8x4(uint16x4_t a, unsigned shamt) {
+  return __riscv_pnclipru_s_u8x4(a, shamt);
+}
+
+// CHECK-LABEL: test_pnclipru_s_u16x2:
+// RV32:        pnclipru.hs
+// RV64:        andi [[REG:a[0-9]+]], a1, 31
+// RV64-NEXT:   neg [[REG2:a[0-9]+]], [[REG]]
+// RV64-NEXT:   psshlr.ws a0, a0, [[REG2]]
+// RV64-NEXT:   pnclipup.h a0, a0, zero
+uint16x2_t test_pnclipru_s_u16x2(uint32x2_t a, unsigned shamt) {
+  return __riscv_pnclipru_s_u16x2(a, shamt);
+}
+
+// CHECK-LABEL: test_pnclip_s_i8x4:
+// RV32:        pnclip.bs
+// RV64:        psra.hs
+// RV64:        pnclipp.b
+int8x4_t test_pnclip_s_i8x4(int16x4_t a, unsigned shamt) {
+  return __riscv_pnclip_s_i8x4(a, shamt);
+}
+
+// CHECK-LABEL: test_pnclip_s_i16x2:
+// RV32:        pnclip.hs
+// RV64:        psra.ws
+// RV64:        pnclipp.h
+int16x2_t test_pnclip_s_i16x2(int32x2_t a, unsigned shamt) {
+  return __riscv_pnclip_s_i16x2(a, shamt);
+}
+
+// CHECK-LABEL: test_pnclipr_s_i8x4:
+// RV32:        pnclipr.bs
+// RV64:        andi [[REG:a[0-9]+]], a1, 31
+// RV64-NEXT:   neg [[REG2:a[0-9]+]], [[REG]]
+// RV64-NEXT:   psshar.hs a0, a0, [[REG2]]
+// RV64-NEXT:   pnclipp.b a0, a0, zero
+int8x4_t test_pnclipr_s_i8x4(int16x4_t a, unsigned shamt) {
+  return __riscv_pnclipr_s_i8x4(a, shamt);
+}
+
+// CHECK-LABEL: test_pnclipr_s_i16x2:
+// RV32:        pnclipr.hs
+// RV64:        andi [[REG:a[0-9]+]], a1, 31
+// RV64-NEXT:   neg [[REG2:a[0-9]+]], [[REG]]
+// RV64-NEXT:   psshar.ws a0, a0, [[REG]]
+// RV64-NEXT:   pnclipp.h a0, a0, zero
+int16x2_t test_pnclipr_s_i16x2(int32x2_t a, unsigned shamt) {
+  return __riscv_pnclipr_s_i16x2(a, shamt);
+}
+
 // CHECK-LABEL: test_pnclipp_i8x8:
 // RV32:        pnclipi.b
 // RV32:        pnclipi.b