[clang] b0e8245 - [RISCV][P-ext] Support Packed Slide (#234629)
via cfe-commits
cfe-commits at lists.llvm.org
Fri Oct 23 22:18:05 PDT 2026
Author: Hongyu Chen
Date: 2026-10-24T05:17:59Z
New Revision: b0e824572198bd0474480998708f25ebcdebcc73
URL: https://github.com/llvm/llvm-project/commit/b0e824572198bd0474480998708f25ebcdebcc73
DIFF: https://github.com/llvm/llvm-project/commit/b0e824572198bd0474480998708f25ebcdebcc73.diff
LOG: [RISCV][P-ext] Support Packed Slide (#234629)
This patch supports packed slide intrinsics using funnel shifts.
On RV32, the 64-bit funnel shift expands into select instructions, so it
involves branches.
Added:
Modified:
clang/lib/Headers/riscv_packed_simd.h
clang/test/CodeGen/RISCV/rvp-intrinsics.c
cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
llvm/test/CodeGen/RISCV/rvp-simd-32.ll
llvm/test/CodeGen/RISCV/rvp-simd-64.ll
Removed:
################################################################################
diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h
index 88c330cf7761d..89f678a63e94e 100644
--- a/clang/lib/Headers/riscv_packed_simd.h
+++ b/clang/lib/Headers/riscv_packed_simd.h
@@ -179,6 +179,24 @@ typedef uint32_t uint32x2_t __attribute__((__vector_size__(8)));
return __builtin_elementwise_fshr(__rs1, __rd, (ty)__shamt); \
}
+#define __packed_slideupx(name, ty, bits_ty, log2_elt_bits) \
+ static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rd, ty __rs1, \
+ unsigned __rs2) { \
+ bits_ty __bits = __builtin_elementwise_fshl( \
+ __builtin_bit_cast(bits_ty, __rd), __builtin_bit_cast(bits_ty, __rs1), \
+ (bits_ty)__rs2 << (log2_elt_bits)); \
+ return __builtin_bit_cast(ty, __bits); \
+ }
+
+#define __packed_slidedownx(name, ty, bits_ty, log2_elt_bits) \
+ static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rd, ty __rs1, \
+ unsigned __rs2) { \
+ bits_ty __bits = __builtin_elementwise_fshr( \
+ __builtin_bit_cast(bits_ty, __rs1), __builtin_bit_cast(bits_ty, __rd), \
+ (bits_ty)__rs2 << (log2_elt_bits)); \
+ return __builtin_bit_cast(ty, __bits); \
+ }
+
#define __packed_widen_convert(name, rty, ty) \
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return __builtin_convertvector(__rs1, rty); \
@@ -1473,6 +1491,30 @@ __packed_slide1(pslide1down_u16x4, uint16x4_t, uint16_t, 1, 2, 3, 4)
__packed_slide1(pslide1down_i32x2, int32x2_t, int32_t, 1, 2)
__packed_slide1(pslide1down_u32x2, uint32x2_t, uint32_t, 1, 2)
+/* Packed Slide (32-bit) */
+__packed_slideupx(pslideupx_i8x4, int8x4_t, uint32_t, 3)
+__packed_slideupx(pslideupx_u8x4, uint8x4_t, uint32_t, 3)
+__packed_slideupx(pslideupx_i16x2, int16x2_t, uint32_t, 4)
+__packed_slideupx(pslideupx_u16x2, uint16x2_t, uint32_t, 4)
+__packed_slidedownx(pslidedownx_i8x4, int8x4_t, uint32_t, 3)
+__packed_slidedownx(pslidedownx_u8x4, uint8x4_t, uint32_t, 3)
+__packed_slidedownx(pslidedownx_i16x2, int16x2_t, uint32_t, 4)
+__packed_slidedownx(pslidedownx_u16x2, uint16x2_t, uint32_t, 4)
+
+/* Packed Slide (64-bit) */
+__packed_slideupx(pslideupx_i8x8, int8x8_t, uint64_t, 3)
+__packed_slideupx(pslideupx_u8x8, uint8x8_t, uint64_t, 3)
+__packed_slideupx(pslideupx_i16x4, int16x4_t, uint64_t, 4)
+__packed_slideupx(pslideupx_u16x4, uint16x4_t, uint64_t, 4)
+__packed_slideupx(pslideupx_i32x2, int32x2_t, uint64_t, 5)
+__packed_slideupx(pslideupx_u32x2, uint32x2_t, uint64_t, 5)
+__packed_slidedownx(pslidedownx_i8x8, int8x8_t, uint64_t, 3)
+__packed_slidedownx(pslidedownx_u8x8, uint8x8_t, uint64_t, 3)
+__packed_slidedownx(pslidedownx_i16x4, int16x4_t, uint64_t, 4)
+__packed_slidedownx(pslidedownx_u16x4, uint16x4_t, uint64_t, 4)
+__packed_slidedownx(pslidedownx_i32x2, int32x2_t, uint64_t, 5)
+__packed_slidedownx(pslidedownx_u32x2, uint32x2_t, uint64_t, 5)
+
/* Packed Subvector Extract */
__packed_subvector_extract8(pget_i8x8_i8x4, int8x4_t, int8x8_t)
__packed_subvector_extract8(pget_u8x8_u8x4, uint8x4_t, uint8x8_t)
@@ -1674,6 +1716,8 @@ __packed_reinterpret(u32x2_i32x2, int32x2_t, uint32x2_t)
#undef __packed_cls
#undef __packed_slx
#undef __packed_srx
+#undef __packed_slideupx
+#undef __packed_slidedownx
#undef __packed_widen_convert
#undef __packed_widen_binary_op
#undef __packed_widen_binary_acc_op
diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
index 928520c11c0a4..ea42d98eec04c 100644
--- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c
+++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
@@ -10302,6 +10302,397 @@ int64_t test_pm2waddasu_i64(int64_t rd, int16x2_t rs1, uint16x2_t rs2) {
return __riscv_pm2waddasu_i64(rd, rs1, rs2);
}
+/* Packed Slide (32-bit) */
+
+// RV32-LABEL: define dso_local i32 @test_pslideupx_i8x4(
+// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3
+// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]])
+// RV32-NEXT: ret i32 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i32 @test_pslideupx_i8x4(
+// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3
+// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]])
+// RV64-NEXT: ret i32 [[TMP0]]
+//
+int8x4_t test_pslideupx_i8x4(int8x4_t rd, int8x4_t rs1, unsigned rs2) {
+ return __riscv_pslideupx_i8x4(rd, rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pslideupx_u8x4(
+// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3
+// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]])
+// RV32-NEXT: ret i32 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i32 @test_pslideupx_u8x4(
+// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3
+// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]])
+// RV64-NEXT: ret i32 [[TMP0]]
+//
+uint8x4_t test_pslideupx_u8x4(uint8x4_t rd, uint8x4_t rs1, unsigned rs2) {
+ return __riscv_pslideupx_u8x4(rd, rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pslideupx_i16x2(
+// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4
+// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]])
+// RV32-NEXT: ret i32 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i32 @test_pslideupx_i16x2(
+// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4
+// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]])
+// RV64-NEXT: ret i32 [[TMP0]]
+//
+int16x2_t test_pslideupx_i16x2(int16x2_t rd, int16x2_t rs1, unsigned rs2) {
+ return __riscv_pslideupx_i16x2(rd, rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pslideupx_u16x2(
+// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4
+// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]])
+// RV32-NEXT: ret i32 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i32 @test_pslideupx_u16x2(
+// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4
+// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]])
+// RV64-NEXT: ret i32 [[TMP0]]
+//
+uint16x2_t test_pslideupx_u16x2(uint16x2_t rd, uint16x2_t rs1, unsigned rs2) {
+ return __riscv_pslideupx_u16x2(rd, rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pslidedownx_i8x4(
+// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3
+// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]])
+// RV32-NEXT: ret i32 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i32 @test_pslidedownx_i8x4(
+// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3
+// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]])
+// RV64-NEXT: ret i32 [[TMP0]]
+//
+int8x4_t test_pslidedownx_i8x4(int8x4_t rd, int8x4_t rs1, unsigned rs2) {
+ return __riscv_pslidedownx_i8x4(rd, rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pslidedownx_u8x4(
+// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3
+// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]])
+// RV32-NEXT: ret i32 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i32 @test_pslidedownx_u8x4(
+// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3
+// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]])
+// RV64-NEXT: ret i32 [[TMP0]]
+//
+uint8x4_t test_pslidedownx_u8x4(uint8x4_t rd, uint8x4_t rs1, unsigned rs2) {
+ return __riscv_pslidedownx_u8x4(rd, rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pslidedownx_i16x2(
+// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4
+// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]])
+// RV32-NEXT: ret i32 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i32 @test_pslidedownx_i16x2(
+// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4
+// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]])
+// RV64-NEXT: ret i32 [[TMP0]]
+//
+int16x2_t test_pslidedownx_i16x2(int16x2_t rd, int16x2_t rs1, unsigned rs2) {
+ return __riscv_pslidedownx_i16x2(rd, rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pslidedownx_u16x2(
+// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4
+// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]])
+// RV32-NEXT: ret i32 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i32 @test_pslidedownx_u16x2(
+// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4
+// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]])
+// RV64-NEXT: ret i32 [[TMP0]]
+//
+uint16x2_t test_pslidedownx_u16x2(uint16x2_t rd, uint16x2_t rs1,
+ unsigned rs2) {
+ return __riscv_pslidedownx_u16x2(rd, rs1, rs2);
+}
+
+/* Packed Slide (64-bit) */
+
+// RV32-LABEL: define dso_local i64 @test_pslideupx_i8x8(
+// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3
+// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]])
+// RV32-NEXT: ret i64 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i64 @test_pslideupx_i8x8(
+// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3
+// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]])
+// RV64-NEXT: ret i64 [[TMP0]]
+//
+int8x8_t test_pslideupx_i8x8(int8x8_t rd, int8x8_t rs1, unsigned rs2) {
+ return __riscv_pslideupx_i8x8(rd, rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pslideupx_u8x8(
+// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3
+// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]])
+// RV32-NEXT: ret i64 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i64 @test_pslideupx_u8x8(
+// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3
+// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]])
+// RV64-NEXT: ret i64 [[TMP0]]
+//
+uint8x8_t test_pslideupx_u8x8(uint8x8_t rd, uint8x8_t rs1, unsigned rs2) {
+ return __riscv_pslideupx_u8x8(rd, rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pslideupx_i16x4(
+// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 4
+// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]])
+// RV32-NEXT: ret i64 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i64 @test_pslideupx_i16x4(
+// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 4
+// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]])
+// RV64-NEXT: ret i64 [[TMP0]]
+//
+int16x4_t test_pslideupx_i16x4(int16x4_t rd, int16x4_t rs1, unsigned rs2) {
+ return __riscv_pslideupx_i16x4(rd, rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pslideupx_u16x4(
+// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 4
+// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]])
+// RV32-NEXT: ret i64 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i64 @test_pslideupx_u16x4(
+// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 4
+// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]])
+// RV64-NEXT: ret i64 [[TMP0]]
+//
+uint16x4_t test_pslideupx_u16x4(uint16x4_t rd, uint16x4_t rs1, unsigned rs2) {
+ return __riscv_pslideupx_u16x4(rd, rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pslideupx_i32x2(
+// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 5
+// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]])
+// RV32-NEXT: ret i64 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i64 @test_pslideupx_i32x2(
+// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 5
+// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]])
+// RV64-NEXT: ret i64 [[TMP0]]
+//
+int32x2_t test_pslideupx_i32x2(int32x2_t rd, int32x2_t rs1, unsigned rs2) {
+ return __riscv_pslideupx_i32x2(rd, rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pslideupx_u32x2(
+// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 5
+// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]])
+// RV32-NEXT: ret i64 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i64 @test_pslideupx_u32x2(
+// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 5
+// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]])
+// RV64-NEXT: ret i64 [[TMP0]]
+//
+uint32x2_t test_pslideupx_u32x2(uint32x2_t rd, uint32x2_t rs1, unsigned rs2) {
+ return __riscv_pslideupx_u32x2(rd, rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pslidedownx_i8x8(
+// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3
+// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]])
+// RV32-NEXT: ret i64 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i64 @test_pslidedownx_i8x8(
+// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3
+// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]])
+// RV64-NEXT: ret i64 [[TMP0]]
+//
+int8x8_t test_pslidedownx_i8x8(int8x8_t rd, int8x8_t rs1, unsigned rs2) {
+ return __riscv_pslidedownx_i8x8(rd, rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pslidedownx_u8x8(
+// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3
+// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]])
+// RV32-NEXT: ret i64 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i64 @test_pslidedownx_u8x8(
+// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3
+// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]])
+// RV64-NEXT: ret i64 [[TMP0]]
+//
+uint8x8_t test_pslidedownx_u8x8(uint8x8_t rd, uint8x8_t rs1, unsigned rs2) {
+ return __riscv_pslidedownx_u8x8(rd, rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pslidedownx_i16x4(
+// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 4
+// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]])
+// RV32-NEXT: ret i64 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i64 @test_pslidedownx_i16x4(
+// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 4
+// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]])
+// RV64-NEXT: ret i64 [[TMP0]]
+//
+int16x4_t test_pslidedownx_i16x4(int16x4_t rd, int16x4_t rs1, unsigned rs2) {
+ return __riscv_pslidedownx_i16x4(rd, rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pslidedownx_u16x4(
+// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 4
+// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]])
+// RV32-NEXT: ret i64 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i64 @test_pslidedownx_u16x4(
+// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 4
+// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]])
+// RV64-NEXT: ret i64 [[TMP0]]
+//
+uint16x4_t test_pslidedownx_u16x4(uint16x4_t rd, uint16x4_t rs1,
+ unsigned rs2) {
+ return __riscv_pslidedownx_u16x4(rd, rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pslidedownx_i32x2(
+// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 5
+// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]])
+// RV32-NEXT: ret i64 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i64 @test_pslidedownx_i32x2(
+// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 5
+// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]])
+// RV64-NEXT: ret i64 [[TMP0]]
+//
+int32x2_t test_pslidedownx_i32x2(int32x2_t rd, int32x2_t rs1, unsigned rs2) {
+ return __riscv_pslidedownx_i32x2(rd, rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pslidedownx_u32x2(
+// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 5
+// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]])
+// RV32-NEXT: ret i64 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i64 @test_pslidedownx_u32x2(
+// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64
+// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 5
+// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]])
+// RV64-NEXT: ret i64 [[TMP0]]
+//
+uint32x2_t test_pslidedownx_u32x2(uint32x2_t rd, uint32x2_t rs1,
+ unsigned rs2) {
+ return __riscv_pslidedownx_u32x2(rd, rs1, rs2);
+}
+
/* Packed Byte Multiplication with Horizontal Addition and Accumulate */
// CHECK-LABEL: define dso_local i64 @test_pm4adda_i8x8(
diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
index 134f2f5159807..365af7c993a5f 100644
--- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
@@ -6128,3 +6128,127 @@ int32x2_t test_pslide1down_i32x2(int32x2_t rd, int32_t rs1) {
uint32x2_t test_pslide1down_u32x2(uint32x2_t rd, uint32_t rs1) {
return __riscv_pslide1down_u32x2(rd, rs1);
}
+
+/* Packed Slide (32-bit) */
+
+// CHECK-LABEL: test_pslideupx_i8x4:
+// CHECK: slx
+int8x4_t test_pslideupx_i8x4(int8x4_t rd, int8x4_t rs1, unsigned rs2) {
+ return __riscv_pslideupx_i8x4(rd, rs1, rs2);
+}
+
+// CHECK-LABEL: test_pslideupx_u8x4:
+// CHECK: slx
+uint8x4_t test_pslideupx_u8x4(uint8x4_t rd, uint8x4_t rs1, unsigned rs2) {
+ return __riscv_pslideupx_u8x4(rd, rs1, rs2);
+}
+
+// CHECK-LABEL: test_pslideupx_i16x2:
+// CHECK: slx
+int16x2_t test_pslideupx_i16x2(int16x2_t rd, int16x2_t rs1, unsigned rs2) {
+ return __riscv_pslideupx_i16x2(rd, rs1, rs2);
+}
+
+// CHECK-LABEL: test_pslideupx_u16x2:
+// CHECK: slx
+uint16x2_t test_pslideupx_u16x2(uint16x2_t rd, uint16x2_t rs1, unsigned rs2) {
+ return __riscv_pslideupx_u16x2(rd, rs1, rs2);
+}
+
+// CHECK-LABEL: test_pslidedownx_i8x4:
+// CHECK: srx
+int8x4_t test_pslidedownx_i8x4(int8x4_t rd, int8x4_t rs1, unsigned rs2) {
+ return __riscv_pslidedownx_i8x4(rd, rs1, rs2);
+}
+
+// CHECK-LABEL: test_pslidedownx_u8x4:
+// CHECK: srx
+uint8x4_t test_pslidedownx_u8x4(uint8x4_t rd, uint8x4_t rs1, unsigned rs2) {
+ return __riscv_pslidedownx_u8x4(rd, rs1, rs2);
+}
+
+// CHECK-LABEL: test_pslidedownx_i16x2:
+// CHECK: srx
+int16x2_t test_pslidedownx_i16x2(int16x2_t rd, int16x2_t rs1, unsigned rs2) {
+ return __riscv_pslidedownx_i16x2(rd, rs1, rs2);
+}
+
+// CHECK-LABEL: test_pslidedownx_u16x2:
+// CHECK: srx
+uint16x2_t test_pslidedownx_u16x2(uint16x2_t rd, uint16x2_t rs1, unsigned rs2) {
+ return __riscv_pslidedownx_u16x2(rd, rs1, rs2);
+}
+
+/* Packed Slide (64-bit) */
+
+// CHECK-LABEL: test_pslideupx_i8x8:
+// CHECK: slx
+int8x8_t test_pslideupx_i8x8(int8x8_t rd, int8x8_t rs1, unsigned rs2) {
+ return __riscv_pslideupx_i8x8(rd, rs1, rs2);
+}
+
+// CHECK-LABEL: test_pslideupx_u8x8:
+// CHECK: slx
+uint8x8_t test_pslideupx_u8x8(uint8x8_t rd, uint8x8_t rs1, unsigned rs2) {
+ return __riscv_pslideupx_u8x8(rd, rs1, rs2);
+}
+
+// CHECK-LABEL: test_pslideupx_i16x4:
+// CHECK: slx
+int16x4_t test_pslideupx_i16x4(int16x4_t rd, int16x4_t rs1, unsigned rs2) {
+ return __riscv_pslideupx_i16x4(rd, rs1, rs2);
+}
+
+// CHECK-LABEL: test_pslideupx_u16x4:
+// CHECK: slx
+uint16x4_t test_pslideupx_u16x4(uint16x4_t rd, uint16x4_t rs1, unsigned rs2) {
+ return __riscv_pslideupx_u16x4(rd, rs1, rs2);
+}
+
+// CHECK-LABEL: test_pslideupx_i32x2:
+// RV64: slx
+int32x2_t test_pslideupx_i32x2(int32x2_t rd, int32x2_t rs1, unsigned rs2) {
+ return __riscv_pslideupx_i32x2(rd, rs1, rs2);
+}
+
+// CHECK-LABEL: test_pslideupx_u32x2:
+// RV64: slx
+uint32x2_t test_pslideupx_u32x2(uint32x2_t rd, uint32x2_t rs1, unsigned rs2) {
+ return __riscv_pslideupx_u32x2(rd, rs1, rs2);
+}
+
+// CHECK-LABEL: test_pslidedownx_i8x8:
+// CHECK: srx
+int8x8_t test_pslidedownx_i8x8(int8x8_t rd, int8x8_t rs1, unsigned rs2) {
+ return __riscv_pslidedownx_i8x8(rd, rs1, rs2);
+}
+
+// CHECK-LABEL: test_pslidedownx_u8x8:
+// CHECK: srx
+uint8x8_t test_pslidedownx_u8x8(uint8x8_t rd, uint8x8_t rs1, unsigned rs2) {
+ return __riscv_pslidedownx_u8x8(rd, rs1, rs2);
+}
+
+// CHECK-LABEL: test_pslidedownx_i16x4:
+// CHECK: srx
+int16x4_t test_pslidedownx_i16x4(int16x4_t rd, int16x4_t rs1, unsigned rs2) {
+ return __riscv_pslidedownx_i16x4(rd, rs1, rs2);
+}
+
+// CHECK-LABEL: test_pslidedownx_u16x4:
+// CHECK: srx
+uint16x4_t test_pslidedownx_u16x4(uint16x4_t rd, uint16x4_t rs1, unsigned rs2) {
+ return __riscv_pslidedownx_u16x4(rd, rs1, rs2);
+}
+
+// CHECK-LABEL: test_pslidedownx_i32x2:
+// RV64: srx
+int32x2_t test_pslidedownx_i32x2(int32x2_t rd, int32x2_t rs1, unsigned rs2) {
+ return __riscv_pslidedownx_i32x2(rd, rs1, rs2);
+}
+
+// CHECK-LABEL: test_pslidedownx_u32x2:
+// RV64: srx
+uint32x2_t test_pslidedownx_u32x2(uint32x2_t rd, uint32x2_t rs1, unsigned rs2) {
+ return __riscv_pslidedownx_u32x2(rd, rs1, rs2);
+}
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
index ac29235202b41..fc49df7ea6279 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
@@ -4150,3 +4150,93 @@ define <2 x i16> @test_pslide1down_v2i16(<2 x i16> %rd, i16 %rs1) {
%res = shufflevector <2 x i16> %rd, <2 x i16> %scalar, <2 x i32> <i32 1, i32 2>
ret <2 x i16> %res
}
+
+define <4 x i8> @test_pslideupx_v4i8(<4 x i8> %rd, <4 x i8> %rs1, i32 %rs2) {
+; RV32-LABEL: test_pslideupx_v4i8:
+; RV32: # %bb.0:
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: slx a0, a1, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pslideupx_v4i8:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: slli a1, a1, 32
+; RV64-NEXT: andi a2, a2, 24
+; RV64-NEXT: slx a0, a1, a2
+; RV64-NEXT: ret
+ %rd.bits = bitcast <4 x i8> %rd to i32
+ %rs1.bits = bitcast <4 x i8> %rs1 to i32
+ %shamt = shl i32 %rs2, 3
+ %res.bits = call i32 @llvm.fshl.i32(i32 %rd.bits, i32 %rs1.bits, i32 %shamt)
+ %res = bitcast i32 %res.bits to <4 x i8>
+ ret <4 x i8> %res
+}
+
+define <4 x i8> @test_pslidedownx_v4i8(<4 x i8> %rd, <4 x i8> %rs1, i32 %rs2) {
+; RV32-LABEL: test_pslidedownx_v4i8:
+; RV32: # %bb.0:
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: srx a0, a1, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pslidedownx_v4i8:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: ori a2, a2, 32
+; RV64-NEXT: srx a0, a1, a2
+; RV64-NEXT: ret
+ %rd.bits = bitcast <4 x i8> %rd to i32
+ %rs1.bits = bitcast <4 x i8> %rs1 to i32
+ %shamt = shl i32 %rs2, 3
+ %res.bits = call i32 @llvm.fshr.i32(i32 %rs1.bits, i32 %rd.bits, i32 %shamt)
+ %res = bitcast i32 %res.bits to <4 x i8>
+ ret <4 x i8> %res
+}
+
+define <2 x i16> @test_pslideupx_v2i16(<2 x i16> %rd, <2 x i16> %rs1,
+ i32 %rs2) {
+; RV32-LABEL: test_pslideupx_v2i16:
+; RV32: # %bb.0:
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: slx a0, a1, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pslideupx_v2i16:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a2, a2, 4
+; RV64-NEXT: slli a1, a1, 32
+; RV64-NEXT: andi a2, a2, 16
+; RV64-NEXT: slx a0, a1, a2
+; RV64-NEXT: ret
+ %rd.bits = bitcast <2 x i16> %rd to i32
+ %rs1.bits = bitcast <2 x i16> %rs1 to i32
+ %shamt = shl i32 %rs2, 4
+ %res.bits = call i32 @llvm.fshl.i32(i32 %rd.bits, i32 %rs1.bits, i32 %shamt)
+ %res = bitcast i32 %res.bits to <2 x i16>
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_pslidedownx_v2i16(<2 x i16> %rd, <2 x i16> %rs1,
+ i32 %rs2) {
+; RV32-LABEL: test_pslidedownx_v2i16:
+; RV32: # %bb.0:
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: srx a0, a1, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pslidedownx_v2i16:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a2, a2, 4
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: ori a2, a2, 32
+; RV64-NEXT: srx a0, a1, a2
+; RV64-NEXT: ret
+ %rd.bits = bitcast <2 x i16> %rd to i32
+ %rs1.bits = bitcast <2 x i16> %rs1 to i32
+ %shamt = shl i32 %rs2, 4
+ %res.bits = call i32 @llvm.fshr.i32(i32 %rs1.bits, i32 %rd.bits, i32 %shamt)
+ %res = bitcast i32 %res.bits to <2 x i16>
+ ret <2 x i16> %res
+}
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
index 8e190a181400f..45d3e90405f4c 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
@@ -9084,3 +9084,207 @@ define <2 x i32> @test_pslide1down_v2i32(<2 x i32> %rd, i32 %rs1) {
%res = shufflevector <2 x i32> %rd, <2 x i32> %scalar, <2 x i32> <i32 1, i32 2>
ret <2 x i32> %res
}
+
+define <8 x i8> @test_pslideupx_v8i8(<8 x i8> %rd, <8 x i8> %rs1, i32 %rs2) {
+; RV32-LABEL: test_pslideupx_v8i8:
+; RV32: # %bb.0:
+; RV32-NEXT: mv a5, a0
+; RV32-NEXT: slli a0, a4, 29
+; RV32-NEXT: srli a6, a0, 31
+; RV32-NEXT: slli a4, a4, 3
+; RV32-NEXT: bnez a6, .LBB536_2
+; RV32-NEXT: # %bb.1:
+; RV32-NEXT: mv a0, a5
+; RV32-NEXT: mv a5, a1
+; RV32-NEXT: slx a5, a0, a4
+; RV32-NEXT: beqz a6, .LBB536_3
+; RV32-NEXT: j .LBB536_4
+; RV32-NEXT: .LBB536_2:
+; RV32-NEXT: mv a0, a3
+; RV32-NEXT: slx a5, a3, a4
+; RV32-NEXT: bnez a6, .LBB536_4
+; RV32-NEXT: .LBB536_3:
+; RV32-NEXT: mv a2, a3
+; RV32-NEXT: .LBB536_4:
+; RV32-NEXT: slx a0, a2, a4
+; RV32-NEXT: mv a1, a5
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pslideupx_v8i8:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: slx a0, a1, a2
+; RV64-NEXT: ret
+ %rd.bits = bitcast <8 x i8> %rd to i64
+ %rs1.bits = bitcast <8 x i8> %rs1 to i64
+ %rs2.ext = zext i32 %rs2 to i64
+ %shamt = shl i64 %rs2.ext, 3
+ %res.bits = call i64 @llvm.fshl.i64(i64 %rd.bits, i64 %rs1.bits, i64 %shamt)
+ %res = bitcast i64 %res.bits to <8 x i8>
+ ret <8 x i8> %res
+}
+
+define <8 x i8> @test_pslidedownx_v8i8(<8 x i8> %rd, <8 x i8> %rs1,
+ i32 %rs2) {
+; RV32-LABEL: test_pslidedownx_v8i8:
+; RV32: # %bb.0:
+; RV32-NEXT: slli a5, a4, 3
+; RV32-NEXT: andi a6, a5, 32
+; RV32-NEXT: bnez a6, .LBB537_2
+; RV32-NEXT: # %bb.1:
+; RV32-NEXT: mv a3, a2
+; RV32-NEXT: mv a2, a1
+; RV32-NEXT: .LBB537_2:
+; RV32-NEXT: mv a4, a2
+; RV32-NEXT: srx a4, a3, a5
+; RV32-NEXT: beqz a6, .LBB537_4
+; RV32-NEXT: # %bb.3:
+; RV32-NEXT: mv a0, a1
+; RV32-NEXT: .LBB537_4:
+; RV32-NEXT: srx a0, a2, a5
+; RV32-NEXT: mv a1, a4
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pslidedownx_v8i8:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: srx a0, a1, a2
+; RV64-NEXT: ret
+ %rd.bits = bitcast <8 x i8> %rd to i64
+ %rs1.bits = bitcast <8 x i8> %rs1 to i64
+ %rs2.ext = zext i32 %rs2 to i64
+ %shamt = shl i64 %rs2.ext, 3
+ %res.bits = call i64 @llvm.fshr.i64(i64 %rs1.bits, i64 %rd.bits, i64 %shamt)
+ %res = bitcast i64 %res.bits to <8 x i8>
+ ret <8 x i8> %res
+}
+
+define <4 x i16> @test_pslideupx_v4i16(<4 x i16> %rd, <4 x i16> %rs1,
+ i32 %rs2) {
+; RV32-LABEL: test_pslideupx_v4i16:
+; RV32: # %bb.0:
+; RV32-NEXT: mv a5, a0
+; RV32-NEXT: slli a0, a4, 30
+; RV32-NEXT: srli a6, a0, 31
+; RV32-NEXT: slli a4, a4, 4
+; RV32-NEXT: bnez a6, .LBB538_2
+; RV32-NEXT: # %bb.1:
+; RV32-NEXT: mv a0, a5
+; RV32-NEXT: mv a5, a1
+; RV32-NEXT: slx a5, a0, a4
+; RV32-NEXT: beqz a6, .LBB538_3
+; RV32-NEXT: j .LBB538_4
+; RV32-NEXT: .LBB538_2:
+; RV32-NEXT: mv a0, a3
+; RV32-NEXT: slx a5, a3, a4
+; RV32-NEXT: bnez a6, .LBB538_4
+; RV32-NEXT: .LBB538_3:
+; RV32-NEXT: mv a2, a3
+; RV32-NEXT: .LBB538_4:
+; RV32-NEXT: slx a0, a2, a4
+; RV32-NEXT: mv a1, a5
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pslideupx_v4i16:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a2, a2, 4
+; RV64-NEXT: slx a0, a1, a2
+; RV64-NEXT: ret
+ %rd.bits = bitcast <4 x i16> %rd to i64
+ %rs1.bits = bitcast <4 x i16> %rs1 to i64
+ %rs2.ext = zext i32 %rs2 to i64
+ %shamt = shl i64 %rs2.ext, 4
+ %res.bits = call i64 @llvm.fshl.i64(i64 %rd.bits, i64 %rs1.bits, i64 %shamt)
+ %res = bitcast i64 %res.bits to <4 x i16>
+ ret <4 x i16> %res
+}
+
+define <4 x i16> @test_pslidedownx_v4i16(<4 x i16> %rd, <4 x i16> %rs1,
+ i32 %rs2) {
+; RV32-LABEL: test_pslidedownx_v4i16:
+; RV32: # %bb.0:
+; RV32-NEXT: slli a5, a4, 4
+; RV32-NEXT: andi a6, a5, 32
+; RV32-NEXT: bnez a6, .LBB539_2
+; RV32-NEXT: # %bb.1:
+; RV32-NEXT: mv a3, a2
+; RV32-NEXT: mv a2, a1
+; RV32-NEXT: .LBB539_2:
+; RV32-NEXT: mv a4, a2
+; RV32-NEXT: srx a4, a3, a5
+; RV32-NEXT: beqz a6, .LBB539_4
+; RV32-NEXT: # %bb.3:
+; RV32-NEXT: mv a0, a1
+; RV32-NEXT: .LBB539_4:
+; RV32-NEXT: srx a0, a2, a5
+; RV32-NEXT: mv a1, a4
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pslidedownx_v4i16:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a2, a2, 4
+; RV64-NEXT: srx a0, a1, a2
+; RV64-NEXT: ret
+ %rd.bits = bitcast <4 x i16> %rd to i64
+ %rs1.bits = bitcast <4 x i16> %rs1 to i64
+ %rs2.ext = zext i32 %rs2 to i64
+ %shamt = shl i64 %rs2.ext, 4
+ %res.bits = call i64 @llvm.fshr.i64(i64 %rs1.bits, i64 %rd.bits, i64 %shamt)
+ %res = bitcast i64 %res.bits to <4 x i16>
+ ret <4 x i16> %res
+}
+
+define <2 x i32> @test_pslideupx_v2i32(<2 x i32> %rd, <2 x i32> %rs1,
+ i32 %rs2) {
+; RV32-LABEL: test_pslideupx_v2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: andi a4, a4, 1
+; RV32-NEXT: beqz a4, .LBB540_2
+; RV32-NEXT: # %bb.1:
+; RV32-NEXT: mv a1, a0
+; RV32-NEXT: mv a0, a3
+; RV32-NEXT: .LBB540_2:
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pslideupx_v2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a2, a2, 5
+; RV64-NEXT: slx a0, a1, a2
+; RV64-NEXT: ret
+ %rd.bits = bitcast <2 x i32> %rd to i64
+ %rs1.bits = bitcast <2 x i32> %rs1 to i64
+ %rs2.ext = zext i32 %rs2 to i64
+ %shamt = shl i64 %rs2.ext, 5
+ %res.bits = call i64 @llvm.fshl.i64(i64 %rd.bits, i64 %rs1.bits, i64 %shamt)
+ %res = bitcast i64 %res.bits to <2 x i32>
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_pslidedownx_v2i32(<2 x i32> %rd, <2 x i32> %rs1,
+ i32 %rs2) {
+; RV32-LABEL: test_pslidedownx_v2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: slli a4, a4, 31
+; RV32-NEXT: srli a4, a4, 26
+; RV32-NEXT: bnez a4, .LBB541_2
+; RV32-NEXT: # %bb.1:
+; RV32-NEXT: mv a2, a1
+; RV32-NEXT: mv a1, a0
+; RV32-NEXT: .LBB541_2:
+; RV32-NEXT: mv a0, a1
+; RV32-NEXT: mv a1, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pslidedownx_v2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a2, a2, 5
+; RV64-NEXT: srx a0, a1, a2
+; RV64-NEXT: ret
+ %rd.bits = bitcast <2 x i32> %rd to i64
+ %rs1.bits = bitcast <2 x i32> %rs1 to i64
+ %rs2.ext = zext i32 %rs2 to i64
+ %shamt = shl i64 %rs2.ext, 5
+ %res.bits = call i64 @llvm.fshr.i64(i64 %rs1.bits, i64 %rd.bits, i64 %shamt)
+ %res = bitcast i64 %res.bits to <2 x i32>
+ ret <2 x i32> %res
+}
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