[clang] 1535406 - [RISCV] Mark RVA23.1 and RVB23.1 profiles as non-experimental (#234064)
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cfe-commits at lists.llvm.org
Tue Oct 20 23:00:15 PDT 2026
Author: Liao Chunyu
Date: 2026-10-21T14:00:10+08:00
New Revision: 15354062581dab747d2f931f13a7b188bfec0112
URL: https://github.com/llvm/llvm-project/commit/15354062581dab747d2f931f13a7b188bfec0112
DIFF: https://github.com/llvm/llvm-project/commit/15354062581dab747d2f931f13a7b188bfec0112.diff
LOG: [RISCV] Mark RVA23.1 and RVB23.1 profiles as non-experimental (#234064)
The RVA23.1 and RVB23.1 profiles have been ratified as version 1.0.
Remove their experimental status and update the documentation and tests.
Added:
Modified:
clang/test/Driver/print-supported-extensions-riscv.c
clang/test/Driver/riscv-profiles.c
llvm/docs/RISCVUsage.md
llvm/docs/ReleaseNotes.md
llvm/lib/Target/RISCV/RISCVProfiles.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/CodeGen/RISCV/features-info.ll
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Removed:
################################################################################
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index f916bef0a6519..e7a4ace4eb735 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -296,16 +296,16 @@
// CHECK-NEXT: rva20u64
// CHECK-NEXT: rva22s64
// CHECK-NEXT: rva22u64
+// CHECK-NEXT: rva23p1s64
// CHECK-NEXT: rva23s64
// CHECK-NEXT: rva23u64
+// CHECK-NEXT: rvb23p1s64
// CHECK-NEXT: rvb23s64
// CHECK-NEXT: rvb23u64
// CHECK-NEXT: rvi20u32
// CHECK-NEXT: rvi20u64
// CHECK-EMPTY:
// CHECK-NEXT: Experimental Profiles
-// CHECK-NEXT: rva23p1s64
-// CHECK-NEXT: rvb23p1s64
// CHECK-NEXT: rvm23u32
// CHECK-EMPTY:
// CHECK-NEXT: Use -march to specify the target's extension.
diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c
index 036b428e040f1..825c1cee7d1bb 100644
--- a/clang/test/Driver/riscv-profiles.c
+++ b/clang/test/Driver/riscv-profiles.c
@@ -154,7 +154,7 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23s64 \
// RUN: | FileCheck -check-prefix=RVA23S64 %s
-// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23p1s64 -menable-experimental-extensions \
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23p1s64 \
// RUN: | FileCheck -check-prefix=RVA23S64 %s
// RVA23S64: "-target-feature" "+m"
// RVA23S64: "-target-feature" "+a"
@@ -251,7 +251,7 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23s64 \
// RUN: | FileCheck -check-prefix=RVB23S64 %s
-// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23p1s64 -menable-experimental-extensions \
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23p1s64 \
// RUN: | FileCheck -check-prefix=RVB23S64 %s
// RVB23S64: "-target-feature" "+m"
// RVB23S64: "-target-feature" "+a"
@@ -298,12 +298,12 @@
// RVB23S64: "-target-feature" "+svpbmt"
// RUN: %clang --target=riscv64 -### -c %s \
-// RUN: -march=rva23p1s64_ssccfg_ssctr_ssdbltrp_ssqosid_svrsw60t59b -menable-experimental-extensions \
+// RUN: -march=rva23p1s64_ssccfg_ssctr_ssdbltrp_ssqosid_svrsw60t59b \
// RUN: > %t-rva23p1s64-options 2>&1
// RUN: FileCheck -check-prefix=RVA23S64 %s < %t-rva23p1s64-options
// RUN: FileCheck -check-prefix=PROFILE-P1-OPTIONS %s < %t-rva23p1s64-options
// RUN: %clang --target=riscv64 -### -c %s \
-// RUN: -march=rvb23p1s64_ssccfg_ssctr_ssdbltrp_ssqosid_svrsw60t59b -menable-experimental-extensions \
+// RUN: -march=rvb23p1s64_ssccfg_ssctr_ssdbltrp_ssqosid_svrsw60t59b \
// RUN: > %t-rvb23p1s64-options 2>&1
// RUN: FileCheck -check-prefix=RVB23S64 %s < %t-rvb23p1s64-options
// RUN: FileCheck -check-prefix=PROFILE-P1-OPTIONS %s < %t-rvb23p1s64-options
@@ -355,14 +355,6 @@
// RUN: not %clang --target=riscv64 -### -c %s 2>&1 -march=rva22u64zfa | FileCheck -check-prefix=INVALID-ADDITIONAL %s
// INVALID-ADDITIONAL: error: invalid arch name 'rva22u64zfa', additional extensions must be after separator '_'
-// RUN: not %clang --target=riscv64 -### -c %s 2>&1 -march=rva23p1s64 | FileCheck -check-prefix=RVA23P1-EXPERIMENTAL-NOFLAG %s
-// RVA23P1-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rva23p1s64'
-// RVA23P1-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions' for profile 'rva23p1s64'
-
-// RUN: not %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23p1s64 | FileCheck -check-prefix=RVB23P1-EXPERIMENTAL-NOFLAG %s
-// RVB23P1-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rvb23p1s64'
-// RVB23P1-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions' for profile 'rvb23p1s64'
-
// RUN: not %clang --target=riscv32 -### -c %s 2>&1 -march=rvm23u32 | FileCheck -check-prefix=EXPERIMENTAL-NOFLAG %s
// EXPERIMENTAL-NOFLAG: error: invalid arch name 'rvm23u32'
// EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions' for profile 'rvm23u32'
diff --git a/llvm/docs/RISCVUsage.md b/llvm/docs/RISCVUsage.md
index 424dff9c4f7a8..91ee1385fb785 100644
--- a/llvm/docs/RISCVUsage.md
+++ b/llvm/docs/RISCVUsage.md
@@ -72,8 +72,10 @@ ISA naming string. Currently supported profiles:
- `rva22s64`
- `rva23u64`
- `rva23s64`
+- `rva23p1s64`
- `rvb23u64`
- `rvb23s64`
+- `rvb23p1s64`
Note that you can also append additional extension names to be enabled, e.g.
`rva20u64_zicond` will enable the `zicond` extension in addition to those
@@ -83,14 +85,12 @@ Profiles that are not yet ratified cannot be used unless
`-menable-experimental-extensions` (or equivalent for other tools) is
specified. This applies to the following profiles:
-- `rva23p1s64`
-- `rvb23p1s64`
- `rvm23u32`
The `rva23p1s64` and `rvb23p1s64` profiles enable the same mandatory extensions
as `rva23s64` and `rvb23s64`, respectively. Their additional optional extensions
must be requested explicitly, for example
-`-march=rva23p1s64_ssctr -menable-experimental-extensions`.
+`-march=rva23p1s64_ssctr`.
(riscv-extensions)=
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 77d639d218ef2..cb3ac832fb48e 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -324,7 +324,7 @@ Makes programs 10x faster by doing Special New Thing.
* Added support for `tail symbol, rt` form that takes an address (materialisation)
register, that is used when software guarded branch is needed.
* Updated the experimental `Zvzip` extension to the v0.3 draft specification.
-* Added the experimental `RVA23P1S64` and `RVB23P1S64` profiles.
+* Added the `RVA23P1S64` and `RVB23P1S64` profiles (version 1.0).
* Updated the canonical order of one-letter RISC-V extensions to match the
latest specification, placing ``p`` after ``v`` and removing unused ``n``.
* Adds experimental assembler support for the `Xqccmi` (Qualcomm 16-bit Instruction Lookup Table) vendor extension.
diff --git a/llvm/lib/Target/RISCV/RISCVProfiles.td b/llvm/lib/Target/RISCV/RISCVProfiles.td
index 374ead904fe9b..5ce94a8861c01 100644
--- a/llvm/lib/Target/RISCV/RISCVProfiles.td
+++ b/llvm/lib/Target/RISCV/RISCVProfiles.td
@@ -160,6 +160,6 @@ def RVA23U64 : RISCVProfile<"rva23u64", RVA23U64Features>;
def RVA23S64 : RISCVProfile<"rva23s64", RVA23S64Features>;
def RVB23U64 : RISCVProfile<"rvb23u64", RVB23U64Features>;
def RVB23S64 : RISCVProfile<"rvb23s64", RVB23S64Features>;
-def RVA23P1S64 : RISCVExperimentalProfile<"rva23p1s64", RVA23S64Features>;
-def RVB23P1S64 : RISCVExperimentalProfile<"rvb23p1s64", RVB23S64Features>;
+def RVA23P1S64 : RISCVProfile<"rva23p1s64", RVA23S64Features>;
+def RVB23P1S64 : RISCVProfile<"rvb23p1s64", RVB23S64Features>;
def RVM23U32 : RISCVExperimentalProfile<"rvm23u32", RVM23U32Features>;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 765245ef4db72..ec5b810faa332 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -363,10 +363,10 @@
; RUN: llc -mtriple=riscv64 -mattr=+rva23s64 %s -o - | FileCheck --check-prefix=RVA23S64 %s
; RUN: llc -mtriple=riscv64 -mattr=+rvb23u64 %s -o - | FileCheck --check-prefix=RVB23U64 %s
; RUN: llc -mtriple=riscv64 -mattr=+rvb23s64 %s -o - | FileCheck --check-prefix=RVB23S64 %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-rva23p1s64 %s -o - | FileCheck --check-prefix=RVA23S64 %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-rvb23p1s64 %s -o - | FileCheck --check-prefix=RVB23S64 %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-rva23p1s64,+ssccfg,+ssctr,+ssdbltrp,+ssqosid,+svrsw60t59b %s -o - | FileCheck --check-prefix=RVA23P1S64-OPTIONS %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-rvb23p1s64,+ssccfg,+ssctr,+ssdbltrp,+ssqosid,+svrsw60t59b %s -o - | FileCheck --check-prefix=RVB23P1S64-OPTIONS %s
+; RUN: llc -mtriple=riscv64 -mattr=+rva23p1s64 %s -o - | FileCheck --check-prefix=RVA23S64 %s
+; RUN: llc -mtriple=riscv64 -mattr=+rvb23p1s64 %s -o - | FileCheck --check-prefix=RVB23S64 %s
+; RUN: llc -mtriple=riscv64 -mattr=+rva23p1s64,+ssccfg,+ssctr,+ssdbltrp,+ssqosid,+svrsw60t59b %s -o - | FileCheck --check-prefix=RVA23P1S64-OPTIONS %s
+; RUN: llc -mtriple=riscv64 -mattr=+rvb23p1s64,+ssccfg,+ssctr,+ssdbltrp,+ssqosid,+svrsw60t59b %s -o - | FileCheck --check-prefix=RVB23P1S64-OPTIONS %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-rvm23u32 %s -o - | FileCheck --check-prefix=RVM23U32 %s
; CHECK: .attribute 4, 16
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index d35ddb20a6a44..b999fb062862b 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -24,8 +24,6 @@
; CHECK-NEXT: exact-asm - Enable Exact Assembly (Disables Compression and Relaxation).
; CHECK-NEXT: experimental - Experimental intrinsics.
; CHECK-NEXT: experimental-p - 'P' ('Base P' (Packed SIMD)).
-; CHECK-NEXT: experimental-rva23p1s64 - RISC-V experimental-rva23p1s64 profile.
-; CHECK-NEXT: experimental-rvb23p1s64 - RISC-V experimental-rvb23p1s64 profile.
; CHECK-NEXT: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile.
; CHECK-NEXT: experimental-smcsps - 'Smcsps' (Conditional Stack Pointer Swap at Machine Level).
; CHECK-NEXT: experimental-smehv - 'Smehv' (Synchronous Exception Hardware Vectoring at Machine Level).
@@ -154,8 +152,10 @@
; CHECK-NEXT: rva20u64 - RISC-V rva20u64 profile.
; CHECK-NEXT: rva22s64 - RISC-V rva22s64 profile.
; CHECK-NEXT: rva22u64 - RISC-V rva22u64 profile.
+; CHECK-NEXT: rva23p1s64 - RISC-V rva23p1s64 profile.
; CHECK-NEXT: rva23s64 - RISC-V rva23s64 profile.
; CHECK-NEXT: rva23u64 - RISC-V rva23u64 profile.
+; CHECK-NEXT: rvb23p1s64 - RISC-V rvb23p1s64 profile.
; CHECK-NEXT: rvb23s64 - RISC-V rvb23s64 profile.
; CHECK-NEXT: rvb23u64 - RISC-V rvb23u64 profile.
; CHECK-NEXT: rvi20u32 - RISC-V rvi20u32 profile.
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index fc258241d0ef9..4df2993cf21b6 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -974,12 +974,6 @@ TEST(ParseArchString,
TEST(ParseArchString,
RejectsExperimentalProfilesIfEnableExperimentalExtensionsNotSet) {
- EXPECT_EQ(
- toString(RISCVISAInfo::parseArchString("rva23p1s64", false).takeError()),
- "requires '-menable-experimental-extensions' for profile 'rva23p1s64'");
- EXPECT_EQ(
- toString(RISCVISAInfo::parseArchString("rvb23p1s64", false).takeError()),
- "requires '-menable-experimental-extensions' for profile 'rvb23p1s64'");
EXPECT_EQ(
toString(RISCVISAInfo::parseArchString("rvm23u32", false).takeError()),
"requires '-menable-experimental-extensions' for profile 'rvm23u32'");
@@ -1754,16 +1748,16 @@ Supported Profiles
rva20u64
rva22s64
rva22u64
+ rva23p1s64
rva23s64
rva23u64
+ rvb23p1s64
rvb23s64
rvb23u64
rvi20u32
rvi20u64
Experimental Profiles
- rva23p1s64
- rvb23p1s64
rvm23u32
Use -march to specify the target's extension.
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