[libunwind] [llvm] [AArch64] Add .cfi_non_hint_pauth_frame when PAuth_LR instructions used for signing (PR #233885)
Kerry McLaughlin via cfe-commits
cfe-commits at lists.llvm.org
Tue Oct 20 08:56:56 PDT 2026
https://github.com/kmclaughlin-arm created https://github.com/llvm/llvm-project/pull/233885
The .cfi_set_ra_state directive indicates whether the value of PC was used
as a diversifier for return address signing. However, it is not sufficient
to distinguish whether hint-space instructions were used.
For example, when PSTATE.PACM is 1, then the PACIASP instruction is extended
to take the PC as an additional diversifier. This means that the hint-space
sequence PACM; PACIASP may produce the same result as the FEAT_PAUTH_LR
instruction PACIASPPC.
However, if PACM has a trivial implementation and does not affect PSTATE.PACM,
the sequences will give different results [1].
If FEAT_PAuth_LR instructions were used to sign the return address, the
CFI directive .cfi_non_hint_pauth_frame is emitted for the frame and the
'N' character will be added to the CIE augmentation string [2]. Libunwind
uses this information to recover the correct sequence of instructions for
authentication which matches signing (e.g. PACM; AUTIA1716 or AUTIA171615).
[1] Issue: https://github.com/ARM-software/abi-aa/issues/396
[2] ABI: https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst#43common-information-entries
>From 20b9ae261201ef2042713b2d9c9b1bd94a143e64 Mon Sep 17 00:00:00 2001
From: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: Mon, 21 Sep 2026 13:40:37 +0000
Subject: [PATCH] [AArch64] Add .cfi_non_hint_pauth_frame when PAuth_LR
instructions used for signing
The .cfi_set_ra_state directive indicates whether the value of PC was used
as a diversifier for return address signing. However, it is not sufficient
to distinguish whether hint-space instructions were used.
For example, when PSTATE.PACM is 1, then the PACIASP instruction is extended
to take the PC as an additional diversifier. This means that the hint-space
sequence PACM; PACIASP may produce the same result as the FEAT_PAUTH_LR
instruction PACIASPPC.
However, if PACM has a trivial implementation and does not affect PSTATE.PACM,
the sequences will give different results [1].
If FEAT_PAuth_LR instructions were used to sign the return address, the
CFI directive .cfi_non_hint_pauth_frame is emitted for the frame and the
'N' character will be added to the CIE augmentation string [2]. Libunwind
uses this information to recover the correct sequence of instructions for
authentication which matches signing (e.g. PACM; AUTIA1716 or AUTIA171615).
[1] Issue: https://github.com/ARM-software/abi-aa/issues/396
[2] ABI: https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst#43common-information-entries
---
libunwind/src/DwarfInstructions.hpp | 43 +-
libunwind/src/DwarfParser.hpp | 5 +
libunwind/test/ra_sign_state_lr.pass.cpp | 159 +++++
llvm/include/llvm/MC/MCDwarf.h | 1 +
llvm/include/llvm/MC/MCStreamer.h | 1 +
llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp | 4 +
llvm/lib/MC/MCAsmStreamer.cpp | 7 +
llvm/lib/MC/MCDwarf.cpp | 13 +-
llvm/lib/MC/MCStreamer.cpp | 7 +
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 9 +-
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 4 +
.../lib/Target/AArch64/AArch64PointerAuth.cpp | 2 +
.../AArch64/AsmParser/AArch64AsmParser.cpp | 12 +
.../AArch64/pauth-lr-tail-call-fpdiff.ll | 8 +
.../sign-return-address-pauth-lr-mir.ll | 13 +
.../AArch64/sign-return-address-pauth-lr.ll | 32 +-
.../sign-return-address-pauthlr-slh.ll | 2 +
.../test/CodeGen/AArch64/swifttail-ptrauth.ll | 4 +
.../MC/AArch64/directives-case_insensitive.s | 2 +
llvm/test/MC/ELF/AArch64/cfi.s | 569 +++++++++---------
20 files changed, 601 insertions(+), 296 deletions(-)
create mode 100644 libunwind/test/ra_sign_state_lr.pass.cpp
diff --git a/libunwind/src/DwarfInstructions.hpp b/libunwind/src/DwarfInstructions.hpp
index b06877d45f689..07c594ff668a8 100644
--- a/libunwind/src/DwarfInstructions.hpp
+++ b/libunwind/src/DwarfInstructions.hpp
@@ -84,6 +84,9 @@ class DwarfInstructions {
static RASignStatus getReturnAddressSignStatus(A &addressSpace, R registers,
pint_t cfa,
PrologInfo &prolog);
+
+ __attribute__((target("pauth-lr"))) static pint_t
+ emitPAuthLRInsts(pint_t ptrAuthDiv, pint_t cfa, pint_t returnAddr, bool BKey);
#endif
};
@@ -204,6 +207,21 @@ DwarfInstructions<A, R>::getReturnAddressSignStatus(A &addressSpace,
assert((raSignState & 0x3) != 3 && "unexpected RA sign state");
return static_cast<RASignStatus>(raSignState & 0x3);
}
+
+template <typename A, typename R>
+__attribute__((target("pauth-lr"))) typename A::pint_t
+DwarfInstructions<A, R>::emitPAuthLRInsts(pint_t ptrAuthDiv, pint_t cfa,
+ pint_t returnAddr, bool BKey) {
+ register unsigned long long x15 __asm("x15") = ptrAuthDiv;
+ register unsigned long long x16 __asm("x16") = cfa;
+ register unsigned long long x17 __asm("x17") = returnAddr;
+ if (BKey)
+ asm("autib171615" : "+r"(x17) : "r"(x16), "r"(x15));
+ else
+ asm("autia171615" : "+r"(x17) : "r"(x16), "r"(x15));
+
+ return x17;
+}
#endif
template <typename A, typename R>
@@ -343,18 +361,23 @@ int DwarfInstructions<A, R>::stepWithDwarf(
if (RAState == RASignedWithPC) {
register unsigned long long x15 __asm("x15") =
prolog.ptrAuthDiversifier;
- if (cieInfo.addressesSignedWithBKey) {
- asm("hint 0x27\n\t" // pacm
- "hint 0xe"
- : "+r"(x17)
- : "r"(x16), "r"(x15)); // autib1716
- } else {
- asm("hint 0x27\n\t" // pacm
- "hint 0xc"
- : "+r"(x17)
- : "r"(x16), "r"(x15)); // autia1716
+ if (cieInfo.nonHintPAuthFrame)
+ x17 =
+ emitPAuthLRInsts(prolog.ptrAuthDiversifier, cfa, returnAddress,
+ cieInfo.addressesSignedWithBKey);
+ else {
+ asm("hint 0x27\n\t"); // pacm
+
+ if (cieInfo.addressesSignedWithBKey) {
+ asm("hint 0xe" : "+r"(x17) : "r"(x16), "r"(x15)); // autib1716
+ } else {
+ asm("hint 0xc" : "+r"(x17) : "r"(x16), "r"(x15)); // autia1716
+ }
}
} else {
+ assert(!cieInfo.nonHintPAuthFrame &&
+ "Non-hint space FEAT_PAuth_LR instructions expect"
+ "RASignedWithPC");
if (cieInfo.addressesSignedWithBKey)
asm("hint 0xe" : "+r"(x17) : "r"(x16)); // autib1716
else
diff --git a/libunwind/src/DwarfParser.hpp b/libunwind/src/DwarfParser.hpp
index d60e3e11325d3..cb276ab3cfdf4 100644
--- a/libunwind/src/DwarfParser.hpp
+++ b/libunwind/src/DwarfParser.hpp
@@ -57,6 +57,7 @@ class CFI_Parser {
#if defined(_LIBUNWIND_TARGET_AARCH64)
bool addressesSignedWithBKey;
bool mteTaggedFrame;
+ bool nonHintPAuthFrame;
#endif
};
@@ -342,6 +343,7 @@ const char *CFI_Parser<A>::parseCIE(A &addressSpace, pint_t cie,
#if defined(_LIBUNWIND_TARGET_AARCH64)
cieInfo->addressesSignedWithBKey = false;
cieInfo->mteTaggedFrame = false;
+ cieInfo->nonHintPAuthFrame = false;
#endif
cieInfo->cieStart = cie;
pint_t p = cie;
@@ -443,6 +445,9 @@ const char *CFI_Parser<A>::parseCIE(A &addressSpace, pint_t cie,
case 'G':
cieInfo->mteTaggedFrame = true;
break;
+ case 'N':
+ cieInfo->nonHintPAuthFrame = true;
+ break;
#endif
default:
// ignore unknown letters
diff --git a/libunwind/test/ra_sign_state_lr.pass.cpp b/libunwind/test/ra_sign_state_lr.pass.cpp
new file mode 100644
index 0000000000000..86ac6da1bee95
--- /dev/null
+++ b/libunwind/test/ra_sign_state_lr.pass.cpp
@@ -0,0 +1,159 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// clang-format off
+
+// REQUIRES: target={{aarch64.*}}
+// UNSUPPORTED: target={{.*-windows.*}}
+
+// clang-format on
+
+#undef NDEBUG
+#include "../src/config.h"
+#include "support/func_bounds.h"
+
+#include <assert.h>
+#include <inttypes.h>
+#include <libunwind.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/types.h>
+#include <unistd.h>
+#include <unwind.h>
+
+#if defined(_LIBUNWIND_HAVE_GETAUXVAL) || defined(_LIBUNWIND_HAVE_ELF_AUX_INFO)
+#include <asm/hwcap.h>
+#include <sys/auxv.h>
+#endif
+
+// Note: This test requires FEAT_PAuth_LR (and is setup to pass on other
+// targets).
+
+static bool hasPAuthLR() {
+ uint64_t isa_r1, isa_r2;
+ asm("mrs %0, ID_AA64ISAR1_EL1" : "=r"(isa_r1));
+ asm("mrs %0, ID_AA64ISAR2_EL1" : "=r"(isa_r2));
+
+ uint64_t api = (isa_r1 >> 8) & 0xf;
+ uint64_t apa = (isa_r1 >> 4) & 0xf;
+ uint64_t apa3 = (isa_r2 >> 12) & 0xf;
+
+ return api == 6 || apa == 6 || apa3 == 6;
+}
+
+#if defined(_LIBUNWIND_HAVE_GETAUXVAL)
+static bool checkHasPAuthLR() {
+ unsigned long hwcap = getauxval(AT_HWCAP);
+ if ((hwcap & HWCAP_CPUID) == 0)
+ return false;
+
+ return hasPAuthLR();
+}
+#elif defined(_LIBUNWIND_HAVE_ELF_AUX_INFO)
+static bool checkHasPAuthLR() {
+ unsigned long hwcap;
+ if (elf_aux_info(AT_HWCAP, &hwcap, sizeof(hwcap)) != 0)
+ return false;
+
+ if ((hwcap & HWCAP_CPUID) == 0)
+ return false;
+
+ return hasPAuthLR();
+}
+#elif defined(_LIBUNWIND_IS_BAREMETAL)
+static bool checkHasPAuthLR() {
+ return hasPAuthLR();
+}
+#else
+static bool checkHasPAuthLR() {
+ // TODO: Support other platforms.
+ return false;
+}
+#endif
+
+FUNC_BOUNDS_DECL(main_func);
+
+static _Unwind_Reason_Code frame_handler(struct _Unwind_Context *ctx,
+ void *arg) {
+ fprintf(stderr, "frame_handler\n");
+ uintptr_t ip = _Unwind_GetIP(ctx);
+
+ if (ip >= (uintptr_t)FUNC_START(main_func) &&
+ ip < (uintptr_t)FUNC_END(main_func)) {
+ *(bool *)arg = true;
+
+ // Unwind until main is reached, above frames depend on the platform and
+ // architecture.
+ return _URC_END_OF_STACK;
+ }
+
+ return _URC_NO_REASON;
+}
+
+__attribute__((noinline)) extern "C" uintptr_t reaches_main_via_backtrace() {
+ bool reached_main = false;
+ _Unwind_Backtrace(frame_handler, &reached_main);
+ fprintf(stderr, "reached_main = %d\n", reached_main);
+ return reached_main;
+}
+
+__attribute__((noinline)) static uint64_t check_vanilla() {
+ return reaches_main_via_backtrace();
+}
+
+#if defined(HAVE_CFI_SET_RA_STATE)
+__attribute__((naked, target("pauth-lr"))) uint64_t check_set() {
+ // clang-format off
+ asm(
+ ".cfi_b_key_frame\n"
+ ".cfi_non_hint_pauth_frame\n"
+ ".Lsign:\n"
+ "pacibsppc\n"
+ ".cfi_set_ra_state 2, .Lsign\n"
+
+ "stp x29, x30, [sp, #-16]!\n"
+ ".cfi_def_cfa_offset 16\n"
+ ".cfi_offset x29, -16\n"
+ ".cfi_offset x30, -8\n"
+
+ "bl " SYMBOL_NAME(reaches_main_via_backtrace) "\n"
+
+ "ldp x29, x30, [sp], #16\n"
+ ".cfi_def_cfa_offset 0\n"
+ ".cfi_restore x29\n"
+ ".cfi_restore x30\n"
+
+ ".cfi_set_ra_state 0, -20\n"
+ "retabsppc .Lsign");
+ // clang-format on
+}
+#endif
+
+FUNC_ATTR(main_func) int main(int, char **) {
+ uint64_t ret;
+
+ ret = check_vanilla();
+ fprintf(stderr, "check_vanilla: ret = 0x%" PRIx64 "\n", ret);
+ assert(ret == 1);
+
+ if (!checkHasPAuthLR()) {
+ fprintf(stderr, "target does not have FEAT_PAuth_LR\n");
+ return 0;
+ }
+
+#if defined(HAVE_CFI_SET_RA_STATE)
+ ret = check_set();
+ fprintf(stderr, "check_set: ret = 0x%" PRIx64 "\n", ret);
+ assert(ret == 1);
+#endif
+
+ fprintf(stderr, "success\n");
+ return 0;
+}
diff --git a/llvm/include/llvm/MC/MCDwarf.h b/llvm/include/llvm/MC/MCDwarf.h
index 3534a4f349331..ce9237efd4280 100644
--- a/llvm/include/llvm/MC/MCDwarf.h
+++ b/llvm/include/llvm/MC/MCDwarf.h
@@ -913,6 +913,7 @@ struct MCDwarfFrameInfo {
unsigned RAReg = static_cast<unsigned>(INT_MAX);
bool IsBKeyFrame = false;
bool IsMTETaggedFrame = false;
+ bool IsNonHintPAuthFrame = false;
};
// Emit DWARF call frame information and, when available, compact unwind
diff --git a/llvm/include/llvm/MC/MCStreamer.h b/llvm/include/llvm/MC/MCStreamer.h
index 614b8d79c5da4..33e8c78d8eae8 100644
--- a/llvm/include/llvm/MC/MCStreamer.h
+++ b/llvm/include/llvm/MC/MCStreamer.h
@@ -915,6 +915,7 @@ class LLVM_ABI MCStreamer {
virtual void emitCFIBKeyFrame();
virtual void emitCFIMTETaggedFrame();
+ virtual void emitCFINonHintPAuthFrame();
/// This implements the DWARF2 '.loc fileno lineno ...' assembler
/// directive.
diff --git a/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp b/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp
index b88967ae20cfa..ebcc67100a2d1 100644
--- a/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp
+++ b/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp
@@ -312,6 +312,10 @@ Error DWARFDebugFrame::parse(DWARFDataExtractor Data, bool ParseCFIProgram) {
// untagged on unwind.
case 'G':
break;
+ case 'N':
+ // Non hint-space FEAT_PAuth_LR instructions used for signing
+ // functions associated with this augmentation string.
+ break;
}
}
diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp
index 2dd964edb738a..16f5607b21a7c 100644
--- a/llvm/lib/MC/MCAsmStreamer.cpp
+++ b/llvm/lib/MC/MCAsmStreamer.cpp
@@ -473,6 +473,7 @@ class MCAsmStreamer final : public MCAsmBaseStreamer {
void emitIdent(StringRef IdentString) override;
void emitCFIBKeyFrame() override;
void emitCFIMTETaggedFrame() override;
+ void emitCFINonHintPAuthFrame() override;
void emitCFISections(bool EH, bool Debug, bool SFrame) override;
void emitCFIDefCfa(int64_t Register, int64_t Offset, SMLoc Loc) override;
void emitCFIDefCfaOffset(int64_t Offset, SMLoc Loc) override;
@@ -2436,6 +2437,12 @@ void MCAsmStreamer::emitCFIMTETaggedFrame() {
EmitEOL();
}
+void MCAsmStreamer::emitCFINonHintPAuthFrame() {
+ MCStreamer::emitCFINonHintPAuthFrame();
+ OS << "\t.cfi_non_hint_pauth_frame";
+ EmitEOL();
+}
+
void MCAsmStreamer::emitCFIValOffset(int64_t Register, int64_t Offset,
SMLoc Loc) {
MCStreamer::emitCFIValOffset(Register, Offset, Loc);
diff --git a/llvm/lib/MC/MCDwarf.cpp b/llvm/lib/MC/MCDwarf.cpp
index da8e057f0f9ee..4aeb1e7d4ad42 100644
--- a/llvm/lib/MC/MCDwarf.cpp
+++ b/llvm/lib/MC/MCDwarf.cpp
@@ -1943,6 +1943,8 @@ const MCSymbol &FrameEmitterImpl::EmitCIE(const MCDwarfFrameInfo &Frame) {
Augmentation += "B";
if (Frame.IsMTETaggedFrame)
Augmentation += "G";
+ if (Frame.IsNonHintPAuthFrame)
+ Augmentation += "N";
Streamer.emitBytes(Augmentation);
}
Streamer.emitInt8(0);
@@ -2112,7 +2114,8 @@ struct CIEKey {
LsdaEncoding(Frame.LsdaEncoding), IsSignalFrame(Frame.IsSignalFrame),
IsSimple(Frame.IsSimple), RAReg(Frame.RAReg),
IsBKeyFrame(Frame.IsBKeyFrame),
- IsMTETaggedFrame(Frame.IsMTETaggedFrame), IsEH(IsEH) {}
+ IsMTETaggedFrame(Frame.IsMTETaggedFrame),
+ IsNonHintPAuthFrame(Frame.IsNonHintPAuthFrame), IsEH(IsEH) {}
StringRef PersonalityName() const {
if (!Personality)
@@ -2128,11 +2131,11 @@ struct CIEKey {
return std::make_tuple(PersonalityName(), PersonalityEncoding, LsdaEncoding,
IsSignalFrame, IsSimple, RAReg, IsBKeyFrame,
- IsMTETaggedFrame) <
+ IsMTETaggedFrame, IsNonHintPAuthFrame) <
std::make_tuple(Other.PersonalityName(), Other.PersonalityEncoding,
Other.LsdaEncoding, Other.IsSignalFrame,
Other.IsSimple, Other.RAReg, Other.IsBKeyFrame,
- Other.IsMTETaggedFrame);
+ Other.IsMTETaggedFrame, Other.IsNonHintPAuthFrame);
}
bool operator==(const CIEKey &Other) const {
@@ -2145,7 +2148,8 @@ struct CIEKey {
LsdaEncoding == Other.LsdaEncoding &&
IsSignalFrame == Other.IsSignalFrame && IsSimple == Other.IsSimple &&
RAReg == Other.RAReg && IsBKeyFrame == Other.IsBKeyFrame &&
- IsMTETaggedFrame == Other.IsMTETaggedFrame;
+ IsMTETaggedFrame == Other.IsMTETaggedFrame &&
+ IsNonHintPAuthFrame == Other.IsNonHintPAuthFrame;
}
bool operator!=(const CIEKey &Other) const { return !(*this == Other); }
@@ -2157,6 +2161,7 @@ struct CIEKey {
unsigned RAReg = UINT_MAX;
bool IsBKeyFrame = false;
bool IsMTETaggedFrame = false;
+ bool IsNonHintPAuthFrame = false;
bool IsEH = false;
};
diff --git a/llvm/lib/MC/MCStreamer.cpp b/llvm/lib/MC/MCStreamer.cpp
index 1d51fbc46a43c..85ac375027539 100644
--- a/llvm/lib/MC/MCStreamer.cpp
+++ b/llvm/lib/MC/MCStreamer.cpp
@@ -232,6 +232,13 @@ void MCStreamer::emitCFIMTETaggedFrame() {
CurFrame->IsMTETaggedFrame = true;
}
+void MCStreamer::emitCFINonHintPAuthFrame() {
+ MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo();
+ if (!CurFrame)
+ return;
+ CurFrame->IsNonHintPAuthFrame = true;
+}
+
void MCStreamer::emitDwarfLocDirective(unsigned FileNo, unsigned Line,
unsigned Column, unsigned Flags,
unsigned Isa, unsigned Discriminator,
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 683b8ffb94e43..acf89a3d90ca2 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -3588,7 +3588,8 @@ void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) {
}
return;
- case AArch64::EMITBKEY: {
+ case AArch64::EMITBKEY:
+ case AArch64::EMITPAUTH: {
ExceptionHandling ExceptionHandlingType = MAI.getExceptionHandlingType();
if (ExceptionHandlingType != ExceptionHandling::DwarfCFI &&
ExceptionHandlingType != ExceptionHandling::ARM)
@@ -3597,7 +3598,11 @@ void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) {
if (getFunctionCFISectionType(*MF) == CFISection::None)
return;
- OutStreamer->emitCFIBKeyFrame();
+ if (MI->getOpcode() == AArch64::EMITBKEY)
+ OutStreamer->emitCFIBKeyFrame();
+ else
+ OutStreamer->emitCFINonHintPAuthFrame();
+
return;
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 2afc537225dca..61e01882ef53b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3791,6 +3791,10 @@ def EMITBKEY : Pseudo<(outs), (ins), []>, Sched<[]> {}
// augmentation string.
def EMITMTETAGGED : Pseudo<(outs), (ins), []>, Sched<[]> {}
+// Pseudo instruction to tell the streamer to emit an 'N' character into the
+// augmentation string.
+def EMITPAUTH : Pseudo<(outs), (ins), []>, Sched<[]> {}
+
// FIXME: maybe the scratch register used shouldn't be fixed to X1?
// FIXME: can "hasSideEffects be dropped?
// This gets lowered to an instruction sequence which takes 16 bytes
diff --git a/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp b/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
index 606a160e3572e..dd28f8ac66c5c 100644
--- a/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
+++ b/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
@@ -251,6 +251,8 @@ void AArch64PointerAuthImpl::signLR(MachineFunction &MF,
// No SEH opcode for this one; it doesn't materialize into an
// instruction on Windows.
if (MFnI.branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) {
+ BuildMI(MBB, MBBI, DL, TII->get(AArch64::EMITPAUTH))
+ .setMIFlag(MachineInstr::FrameSetup);
decoratePACWithCFI(MBB, MBBI, EmitCFI, [&]() {
BuildMI(MBB, MBBI, DL,
TII->get(UseBKey ? AArch64::PACIBSPPC : AArch64::PACIASPPC))
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 69a807bf866fd..499df76938ec2 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -203,6 +203,7 @@ class AArch64AsmParser : public MCTargetAsmParser {
bool parseDirectiveCFILLVMSetRAState();
bool parseDirectiveCFIBKeyFrame();
bool parseDirectiveCFIMTETaggedFrame();
+ bool parseDirectiveCFINonHintPAuthFrame();
bool parseDirectiveVariantPCS(SMLoc L);
@@ -7125,6 +7126,8 @@ bool AArch64AsmParser::ParseDirective(AsmToken DirectiveID) {
parseDirectiveCFIBKeyFrame();
else if (IDVal == ".cfi_mte_tagged_frame")
parseDirectiveCFIMTETaggedFrame();
+ else if (IDVal == ".cfi_non_hint_pauth_frame")
+ parseDirectiveCFINonHintPAuthFrame();
else if (IDVal == ".arch_extension")
parseDirectiveArchExtension(Loc);
else if (IDVal == ".variant_pcs")
@@ -7647,6 +7650,15 @@ bool AArch64AsmParser::parseDirectiveCFIMTETaggedFrame() {
return false;
}
+/// parseDirectiveCFINonHintPAuthFrame
+/// ::= .cfi_non_hint_pauth_frame
+bool AArch64AsmParser::parseDirectiveCFINonHintPAuthFrame() {
+ if (parseEOL())
+ return true;
+ getStreamer().emitCFINonHintPAuthFrame();
+ return false;
+}
+
/// parseDirectiveVariantPCS
/// ::= .variant_pcs symbolname
bool AArch64AsmParser::parseDirectiveVariantPCS(SMLoc L) {
diff --git a/llvm/test/CodeGen/AArch64/pauth-lr-tail-call-fpdiff.ll b/llvm/test/CodeGen/AArch64/pauth-lr-tail-call-fpdiff.ll
index 34a8dc5143eee..e416d57e66b37 100644
--- a/llvm/test/CodeGen/AArch64/pauth-lr-tail-call-fpdiff.ll
+++ b/llvm/test/CodeGen/AArch64/pauth-lr-tail-call-fpdiff.ll
@@ -27,6 +27,7 @@ define swifttailcc void @tail_call_fpdiff_a_key(ptr swiftasync %ctx) "branch-pro
; V83A-NEXT: paciasp
; V83A-NEXT: .cfi_set_ra_state 2, .Ltmp0
+; V9A-NEXT: .cfi_non_hint_pauth_frame
; V9A-NEXT: .Ltmp0:
; V9A-NEXT: paciasppc
; V9A-NEXT: .cfi_set_ra_state 2, .Ltmp0
@@ -109,6 +110,7 @@ define swifttailcc void @tail_call_fpdiff_b_key(ptr swiftasync %ctx) "branch-pro
; V83A-NEXT: pacibsp
; V83A-NEXT: .cfi_set_ra_state 2, .Ltmp1
+; V9A-NEXT: .cfi_non_hint_pauth_frame
; V9A-NEXT: .Ltmp1:
; V9A-NEXT: pacibsppc
; V9A-NEXT: .cfi_set_ra_state 2, .Ltmp1
@@ -190,6 +192,7 @@ define swifttailcc void @tail_call_no_fpdiff_a_key(ptr swiftasync %ctx) "branch-
; V83A-NEXT: paciasp
; V83A-NEXT: .cfi_set_ra_state 2, .Ltmp2
+; V9A-NEXT: .cfi_non_hint_pauth_frame
; V9A-NEXT: .Ltmp2:
; V9A-NEXT: paciasppc
; V9A-NEXT: .cfi_set_ra_state 2, .Ltmp2
@@ -253,6 +256,7 @@ define swifttailcc void @tail_call_no_fpdiff_b_key(ptr swiftasync %ctx) "branch-
; V83A-NEXT: pacibsp
; V83A-NEXT: .cfi_set_ra_state 2, .Ltmp3
+; V9A-NEXT: .cfi_non_hint_pauth_frame
; V9A-NEXT: .Ltmp3:
; V9A-NEXT: pacibsppc
; V9A-NEXT: .cfi_set_ra_state 2, .Ltmp3
@@ -315,6 +319,7 @@ define swifttailcc void @indirect_tail_call_fpdiff_a_key(ptr swiftasync %ctx, pt
; V83A-NEXT: paciasp
; V83A-NEXT: .cfi_set_ra_state 2, .Ltmp4
+; V9A-NEXT: .cfi_non_hint_pauth_frame
; V9A-NEXT: .Ltmp4:
; V9A-NEXT: paciasppc
; V9A-NEXT: .cfi_set_ra_state 2, .Ltmp4
@@ -398,6 +403,7 @@ define swifttailcc void @indirect_tail_call_fpdiff_b_key(ptr swiftasync %ctx, pt
; V83A-NEXT: pacibsp
; V83A-NEXT: .cfi_set_ra_state 2, .Ltmp5
+; V9A-NEXT: .cfi_non_hint_pauth_frame
; V9A-NEXT: .Ltmp5:
; V9A-NEXT: pacibsppc
; V9A-NEXT: .cfi_set_ra_state 2, .Ltmp5
@@ -480,6 +486,7 @@ define swifttailcc void @indirect_tail_call_no_fpdiff_a_key(ptr swiftasync %ctx,
; V83A-NEXT: paciasp
; V83A-NEXT: .cfi_set_ra_state 2, .Ltmp6
+; V9A-NEXT: .cfi_non_hint_pauth_frame
; V9A-NEXT: .Ltmp6:
; V9A-NEXT: paciasppc
; V9A-NEXT: .cfi_set_ra_state 2, .Ltmp6
@@ -543,6 +550,7 @@ define swifttailcc void @indirect_tail_call_no_fpdiff_b_key(ptr swiftasync %ctx,
; V83A-NEXT: pacibsp
; V83A-NEXT: .cfi_set_ra_state 2, .Ltmp7
+; V9A-NEXT: .cfi_non_hint_pauth_frame
; V9A-NEXT: .Ltmp7:
; V9A-NEXT: pacibsppc
; V9A-NEXT: .cfi_set_ra_state 2, .Ltmp7
diff --git a/llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr-mir.ll b/llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr-mir.ll
index d975350b1e9e6..1e9835bce4261 100644
--- a/llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr-mir.ll
+++ b/llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr-mir.ll
@@ -81,6 +81,7 @@ define i32 @leaf_sign_all(i32 %x) "branch-protection-pauth-lr" "sign-return-addr
; PAUTHLR-MIR: bb.0 (%ir-block.0):
; PAUTHLR-MIR-NEXT: liveins: $w0
; PAUTHLR-MIR-NEXT: {{ $}}
+ ; PAUTHLR-MIR-NEXT: frame-setup EMITPAUTH
; PAUTHLR-MIR-NEXT: frame-setup PACIASPPC implicit-def $lr, implicit $lr, implicit $sp, pre-instr-symbol <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-setup CFI_INSTRUCTION llvm_set_ra_state 2, <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-destroy RETAASPPCi <mcsymbol >, implicit $lr, implicit $sp, implicit-def $lr, implicit killed $lr, implicit $sp
@@ -127,6 +128,7 @@ define i64 @leaf_clobbers_lr(i64 %x) "branch-protection-pauth-lr" "sign-return-a
; PAUTHLR-MIR: bb.0 (%ir-block.0):
; PAUTHLR-MIR-NEXT: liveins: $x0, $lr
; PAUTHLR-MIR-NEXT: {{ $}}
+ ; PAUTHLR-MIR-NEXT: frame-setup EMITPAUTH
; PAUTHLR-MIR-NEXT: frame-setup PACIASPPC implicit-def $lr, implicit $lr, implicit $sp, pre-instr-symbol <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-setup CFI_INSTRUCTION llvm_set_ra_state 2, <mcsymbol >
; PAUTHLR-MIR-NEXT: early-clobber $sp = frame-setup STRXpre killed $lr, $sp, -16 :: (store (s64) into %stack.0)
@@ -181,6 +183,7 @@ define i32 @non_leaf_sign_all(i32 %x) "branch-protection-pauth-lr" "sign-return-
; PAUTHLR-MIR: bb.0 (%ir-block.0):
; PAUTHLR-MIR-NEXT: liveins: $w0, $lr
; PAUTHLR-MIR-NEXT: {{ $}}
+ ; PAUTHLR-MIR-NEXT: frame-setup EMITPAUTH
; PAUTHLR-MIR-NEXT: frame-setup PACIASPPC implicit-def $lr, implicit $lr, implicit $sp, pre-instr-symbol <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-setup CFI_INSTRUCTION llvm_set_ra_state 2, <mcsymbol >
; PAUTHLR-MIR-NEXT: early-clobber $sp = frame-setup STRXpre killed $lr, $sp, -16 :: (store (s64) into %stack.0)
@@ -233,6 +236,7 @@ define i32 @non_leaf_sign_non_leaf(i32 %x) "branch-protection-pauth-lr" "sign-re
; PAUTHLR-MIR: bb.0 (%ir-block.0):
; PAUTHLR-MIR-NEXT: liveins: $w0, $lr
; PAUTHLR-MIR-NEXT: {{ $}}
+ ; PAUTHLR-MIR-NEXT: frame-setup EMITPAUTH
; PAUTHLR-MIR-NEXT: frame-setup PACIASPPC implicit-def $lr, implicit $lr, implicit $sp, pre-instr-symbol <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-setup CFI_INSTRUCTION llvm_set_ra_state 2, <mcsymbol >
; PAUTHLR-MIR-NEXT: early-clobber $sp = frame-setup STRXpre killed $lr, $sp, -16 :: (store (s64) into %stack.0)
@@ -271,6 +275,7 @@ define i32 @non_leaf_scs(i32 %x) "branch-protection-pauth-lr" "sign-return-addre
; PAUTHLR-MIR: bb.0 (%ir-block.0):
; PAUTHLR-MIR-NEXT: liveins: $w0, $lr, $x18
; PAUTHLR-MIR-NEXT: {{ $}}
+ ; PAUTHLR-MIR-NEXT: frame-setup EMITPAUTH
; PAUTHLR-MIR-NEXT: frame-setup PACIASPPC implicit-def $lr, implicit $lr, implicit $sp, pre-instr-symbol <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-setup CFI_INSTRUCTION llvm_set_ra_state 2, <mcsymbol >
; PAUTHLR-MIR-NEXT: early-clobber $x18 = frame-setup STRXpost $lr, $x18, 8
@@ -304,6 +309,7 @@ define i32 @leaf_sign_all_v83(i32 %x) "branch-protection-pauth-lr" "sign-return-
; PAUTHLR-MIR: bb.0 (%ir-block.0):
; PAUTHLR-MIR-NEXT: liveins: $w0
; PAUTHLR-MIR-NEXT: {{ $}}
+ ; PAUTHLR-MIR-NEXT: frame-setup EMITPAUTH
; PAUTHLR-MIR-NEXT: frame-setup PACIASPPC implicit-def $lr, implicit $lr, implicit $sp, pre-instr-symbol <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-setup CFI_INSTRUCTION llvm_set_ra_state 2, <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-destroy RETAASPPCi <mcsymbol >, implicit $lr, implicit $sp, implicit-def $lr, implicit killed $lr, implicit $sp
@@ -335,6 +341,7 @@ define fastcc void @spill_lr_and_tail_call(i64 %x) "branch-protection-pauth-lr"
; PAUTHLR-MIR: bb.0 (%ir-block.0):
; PAUTHLR-MIR-NEXT: liveins: $x0, $lr
; PAUTHLR-MIR-NEXT: {{ $}}
+ ; PAUTHLR-MIR-NEXT: frame-setup EMITPAUTH
; PAUTHLR-MIR-NEXT: frame-setup PACIASPPC implicit-def $lr, implicit $lr, implicit $sp, pre-instr-symbol <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-setup CFI_INSTRUCTION llvm_set_ra_state 2, <mcsymbol >
; PAUTHLR-MIR-NEXT: early-clobber $sp = frame-setup STRXpre killed $lr, $sp, -16 :: (store (s64) into %stack.0)
@@ -379,6 +386,7 @@ define i32 @leaf_sign_all_a_key(i32 %x) "branch-protection-pauth-lr" "sign-retur
; PAUTHLR-MIR: bb.0 (%ir-block.0):
; PAUTHLR-MIR-NEXT: liveins: $w0
; PAUTHLR-MIR-NEXT: {{ $}}
+ ; PAUTHLR-MIR-NEXT: frame-setup EMITPAUTH
; PAUTHLR-MIR-NEXT: frame-setup PACIASPPC implicit-def $lr, implicit $lr, implicit $sp, pre-instr-symbol <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-setup CFI_INSTRUCTION llvm_set_ra_state 2, <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-destroy RETAASPPCi <mcsymbol >, implicit $lr, implicit $sp, implicit-def $lr, implicit killed $lr, implicit $sp
@@ -418,6 +426,7 @@ define i32 @leaf_sign_all_b_key(i32 %x) "branch-protection-pauth-lr" "sign-retur
; PAUTHLR-MIR-NEXT: liveins: $w0
; PAUTHLR-MIR-NEXT: {{ $}}
; PAUTHLR-MIR-NEXT: frame-setup EMITBKEY
+ ; PAUTHLR-MIR-NEXT: frame-setup EMITPAUTH
; PAUTHLR-MIR-NEXT: frame-setup PACIBSPPC implicit-def $lr, implicit $lr, implicit $sp, pre-instr-symbol <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-setup CFI_INSTRUCTION llvm_set_ra_state 2, <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-destroy RETABSPPCi <mcsymbol >, implicit $lr, implicit $sp, implicit-def $lr, implicit killed $lr, implicit $sp
@@ -443,6 +452,7 @@ define i32 @leaf_sign_all_v83_b_key(i32 %x) "branch-protection-pauth-lr" "sign-r
; PAUTHLR-MIR-NEXT: liveins: $w0
; PAUTHLR-MIR-NEXT: {{ $}}
; PAUTHLR-MIR-NEXT: frame-setup EMITBKEY
+ ; PAUTHLR-MIR-NEXT: frame-setup EMITPAUTH
; PAUTHLR-MIR-NEXT: frame-setup PACIBSPPC implicit-def $lr, implicit $lr, implicit $sp, pre-instr-symbol <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-setup CFI_INSTRUCTION llvm_set_ra_state 2, <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-destroy RETABSPPCi <mcsymbol >, implicit $lr, implicit $sp, implicit-def $lr, implicit killed $lr, implicit $sp
@@ -479,6 +489,7 @@ define i32 @leaf_sign_all_a_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-r
; PAUTHLR-MIR: bb.0 (%ir-block.0):
; PAUTHLR-MIR-NEXT: liveins: $w0
; PAUTHLR-MIR-NEXT: {{ $}}
+ ; PAUTHLR-MIR-NEXT: frame-setup EMITPAUTH
; PAUTHLR-MIR-NEXT: frame-setup PACIASPPC implicit-def $lr, implicit $lr, implicit $sp, pre-instr-symbol <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-setup CFI_INSTRUCTION llvm_set_ra_state 2, <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-destroy RETAASPPCi <mcsymbol >, implicit $lr, implicit $sp, implicit-def $lr, implicit killed $lr, implicit $sp
@@ -518,6 +529,7 @@ define i32 @leaf_sign_all_b_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-r
; PAUTHLR-MIR-NEXT: liveins: $w0
; PAUTHLR-MIR-NEXT: {{ $}}
; PAUTHLR-MIR-NEXT: frame-setup EMITBKEY
+ ; PAUTHLR-MIR-NEXT: frame-setup EMITPAUTH
; PAUTHLR-MIR-NEXT: frame-setup PACIBSPPC implicit-def $lr, implicit $lr, implicit $sp, pre-instr-symbol <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-setup CFI_INSTRUCTION llvm_set_ra_state 2, <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-destroy RETABSPPCi <mcsymbol >, implicit $lr, implicit $sp, implicit-def $lr, implicit killed $lr, implicit $sp
@@ -543,6 +555,7 @@ define i32 @leaf_sign_all_v83_b_key_bti(i32 %x) "branch-protection-pauth-lr" "si
; PAUTHLR-MIR-NEXT: liveins: $w0
; PAUTHLR-MIR-NEXT: {{ $}}
; PAUTHLR-MIR-NEXT: frame-setup EMITBKEY
+ ; PAUTHLR-MIR-NEXT: frame-setup EMITPAUTH
; PAUTHLR-MIR-NEXT: frame-setup PACIBSPPC implicit-def $lr, implicit $lr, implicit $sp, pre-instr-symbol <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-setup CFI_INSTRUCTION llvm_set_ra_state 2, <mcsymbol >
; PAUTHLR-MIR-NEXT: frame-destroy RETABSPPCi <mcsymbol >, implicit $lr, implicit $sp, implicit-def $lr, implicit killed $lr, implicit $sp
diff --git a/llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll b/llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
index a4db0bcebe0e3..4c8200e4514a9 100644
--- a/llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
+++ b/llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
@@ -134,6 +134,7 @@ define i32 @leaf_sign_all(i32 %x) "branch-protection-pauth-lr" "sign-return-addr
;
; PAUTHLR-LABEL: leaf_sign_all:
; PAUTHLR: // %bb.0:
+; PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; PAUTHLR-NEXT: .Ltmp0:
; PAUTHLR-NEXT: paciasppc
; PAUTHLR-NEXT: .cfi_set_ra_state 2, .Ltmp0
@@ -187,6 +188,7 @@ define i32 @leaf_sign_all(i32 %x) "branch-protection-pauth-lr" "sign-return-addr
;
; NEGATE-PAUTHLR-LABEL: leaf_sign_all:
; NEGATE-PAUTHLR: // %bb.0:
+; NEGATE-PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; NEGATE-PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; NEGATE-PAUTHLR-NEXT: .Ltmp0:
; NEGATE-PAUTHLR-NEXT: paciasppc
@@ -234,6 +236,7 @@ define i64 @leaf_clobbers_lr(i64 %x) "branch-protection-pauth-lr" "sign-return-a
;
; PAUTHLR-LABEL: leaf_clobbers_lr:
; PAUTHLR: // %bb.0:
+; PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; PAUTHLR-NEXT: .Ltmp1:
; PAUTHLR-NEXT: paciasppc
; PAUTHLR-NEXT: .cfi_set_ra_state 2, .Ltmp1
@@ -322,6 +325,7 @@ define i64 @leaf_clobbers_lr(i64 %x) "branch-protection-pauth-lr" "sign-return-a
;
; NEGATE-PAUTHLR-LABEL: leaf_clobbers_lr:
; NEGATE-PAUTHLR: // %bb.0:
+; NEGATE-PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; NEGATE-PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; NEGATE-PAUTHLR-NEXT: .Ltmp1:
; NEGATE-PAUTHLR-NEXT: paciasppc
@@ -375,6 +379,7 @@ define i32 @non_leaf_sign_all(i32 %x) "branch-protection-pauth-lr" "sign-return-
;
; PAUTHLR-LABEL: non_leaf_sign_all:
; PAUTHLR: // %bb.0:
+; PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; PAUTHLR-NEXT: .Ltmp2:
; PAUTHLR-NEXT: paciasppc
; PAUTHLR-NEXT: .cfi_set_ra_state 2, .Ltmp2
@@ -453,6 +458,7 @@ define i32 @non_leaf_sign_all(i32 %x) "branch-protection-pauth-lr" "sign-return-
;
; NEGATE-PAUTHLR-LABEL: non_leaf_sign_all:
; NEGATE-PAUTHLR: // %bb.0:
+; NEGATE-PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; NEGATE-PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; NEGATE-PAUTHLR-NEXT: .Ltmp2:
; NEGATE-PAUTHLR-NEXT: paciasppc
@@ -502,6 +508,7 @@ define i32 @non_leaf_sign_non_leaf(i32 %x) "branch-protection-pauth-lr" "sign-re
;
; PAUTHLR-LABEL: non_leaf_sign_non_leaf:
; PAUTHLR: // %bb.0:
+; PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; PAUTHLR-NEXT: .Ltmp3:
; PAUTHLR-NEXT: paciasppc
; PAUTHLR-NEXT: .cfi_set_ra_state 2, .Ltmp3
@@ -580,6 +587,7 @@ define i32 @non_leaf_sign_non_leaf(i32 %x) "branch-protection-pauth-lr" "sign-re
;
; NEGATE-PAUTHLR-LABEL: non_leaf_sign_non_leaf:
; NEGATE-PAUTHLR: // %bb.0:
+; NEGATE-PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; NEGATE-PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; NEGATE-PAUTHLR-NEXT: .Ltmp3:
; NEGATE-PAUTHLR-NEXT: paciasppc
@@ -617,6 +625,7 @@ define i32 @non_leaf_scs(i32 %x) "branch-protection-pauth-lr" "sign-return-addre
;
; PAUTHLR-LABEL: non_leaf_scs:
; PAUTHLR: // %bb.0:
+; PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; PAUTHLR-NEXT: .Ltmp4:
; PAUTHLR-NEXT: paciasppc
; PAUTHLR-NEXT: .cfi_set_ra_state 2, .Ltmp4
@@ -673,6 +682,7 @@ define i32 @non_leaf_scs(i32 %x) "branch-protection-pauth-lr" "sign-return-addre
;
; NEGATE-PAUTHLR-LABEL: non_leaf_scs:
; NEGATE-PAUTHLR: // %bb.0:
+; NEGATE-PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; NEGATE-PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; NEGATE-PAUTHLR-NEXT: .Ltmp4:
; NEGATE-PAUTHLR-NEXT: paciasppc
@@ -704,6 +714,7 @@ define i32 @leaf_sign_all_v83(i32 %x) "branch-protection-pauth-lr" "sign-return-
;
; PAUTHLR-LABEL: leaf_sign_all_v83:
; PAUTHLR: // %bb.0:
+; PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; PAUTHLR-NEXT: .Ltmp5:
; PAUTHLR-NEXT: paciasppc
; PAUTHLR-NEXT: .cfi_set_ra_state 2, .Ltmp5
@@ -733,6 +744,7 @@ define i32 @leaf_sign_all_v83(i32 %x) "branch-protection-pauth-lr" "sign-return-
;
; NEGATE-PAUTHLR-LABEL: leaf_sign_all_v83:
; NEGATE-PAUTHLR: // %bb.0:
+; NEGATE-PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; NEGATE-PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; NEGATE-PAUTHLR-NEXT: .Ltmp5:
; NEGATE-PAUTHLR-NEXT: paciasppc
@@ -783,6 +795,7 @@ define fastcc void @spill_lr_and_tail_call(i64 %x) "branch-protection-pauth-lr"
;
; PAUTHLR-LABEL: spill_lr_and_tail_call:
; PAUTHLR: // %bb.0:
+; PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; PAUTHLR-NEXT: .Ltmp6:
; PAUTHLR-NEXT: paciasppc
; PAUTHLR-NEXT: .cfi_set_ra_state 2, .Ltmp6
@@ -874,6 +887,7 @@ define fastcc void @spill_lr_and_tail_call(i64 %x) "branch-protection-pauth-lr"
;
; NEGATE-PAUTHLR-LABEL: spill_lr_and_tail_call:
; NEGATE-PAUTHLR: // %bb.0:
+; NEGATE-PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; NEGATE-PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; NEGATE-PAUTHLR-NEXT: .Ltmp6:
; NEGATE-PAUTHLR-NEXT: paciasppc
@@ -917,6 +931,7 @@ define i32 @leaf_sign_all_a_key(i32 %x) "branch-protection-pauth-lr" "sign-retur
;
; PAUTHLR-LABEL: leaf_sign_all_a_key:
; PAUTHLR: // %bb.0:
+; PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; PAUTHLR-NEXT: .Ltmp7:
; PAUTHLR-NEXT: paciasppc
; PAUTHLR-NEXT: .cfi_set_ra_state 2, .Ltmp7
@@ -970,6 +985,7 @@ define i32 @leaf_sign_all_a_key(i32 %x) "branch-protection-pauth-lr" "sign-retur
;
; NEGATE-PAUTHLR-LABEL: leaf_sign_all_a_key:
; NEGATE-PAUTHLR: // %bb.0:
+; NEGATE-PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; NEGATE-PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; NEGATE-PAUTHLR-NEXT: .Ltmp7:
; NEGATE-PAUTHLR-NEXT: paciasppc
@@ -1006,6 +1022,7 @@ define i32 @leaf_sign_all_b_key(i32 %x) "branch-protection-pauth-lr" "sign-retur
; PAUTHLR-LABEL: leaf_sign_all_b_key:
; PAUTHLR: // %bb.0:
; PAUTHLR-NEXT: .cfi_b_key_frame
+; PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; PAUTHLR-NEXT: .Ltmp8:
; PAUTHLR-NEXT: pacibsppc
; PAUTHLR-NEXT: .cfi_set_ra_state 2, .Ltmp8
@@ -1064,6 +1081,7 @@ define i32 @leaf_sign_all_b_key(i32 %x) "branch-protection-pauth-lr" "sign-retur
; NEGATE-PAUTHLR-LABEL: leaf_sign_all_b_key:
; NEGATE-PAUTHLR: // %bb.0:
; NEGATE-PAUTHLR-NEXT: .cfi_b_key_frame
+; NEGATE-PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; NEGATE-PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; NEGATE-PAUTHLR-NEXT: .Ltmp8:
; NEGATE-PAUTHLR-NEXT: pacibsppc
@@ -1087,6 +1105,7 @@ define i32 @leaf_sign_all_v83_b_key(i32 %x) "branch-protection-pauth-lr" "sign-r
; PAUTHLR-LABEL: leaf_sign_all_v83_b_key:
; PAUTHLR: // %bb.0:
; PAUTHLR-NEXT: .cfi_b_key_frame
+; PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; PAUTHLR-NEXT: .Ltmp9:
; PAUTHLR-NEXT: pacibsppc
; PAUTHLR-NEXT: .cfi_set_ra_state 2, .Ltmp9
@@ -1119,6 +1138,7 @@ define i32 @leaf_sign_all_v83_b_key(i32 %x) "branch-protection-pauth-lr" "sign-r
; NEGATE-PAUTHLR-LABEL: leaf_sign_all_v83_b_key:
; NEGATE-PAUTHLR: // %bb.0:
; NEGATE-PAUTHLR-NEXT: .cfi_b_key_frame
+; NEGATE-PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; NEGATE-PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; NEGATE-PAUTHLR-NEXT: .Ltmp9:
; NEGATE-PAUTHLR-NEXT: pacibsppc
@@ -1156,6 +1176,7 @@ define i32 @leaf_sign_all_a_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-r
; PAUTHLR-LABEL: leaf_sign_all_a_key_bti:
; PAUTHLR: // %bb.0:
; PAUTHLR-NEXT: bti c
+; PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; PAUTHLR-NEXT: .Ltmp10:
; PAUTHLR-NEXT: paciasppc
; PAUTHLR-NEXT: .cfi_set_ra_state 2, .Ltmp10
@@ -1213,8 +1234,9 @@ define i32 @leaf_sign_all_a_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-r
;
; NEGATE-PAUTHLR-LABEL: leaf_sign_all_a_key_bti:
; NEGATE-PAUTHLR: // %bb.0:
-; NEGATE-PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; NEGATE-PAUTHLR-NEXT: bti c
+; NEGATE-PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
+; NEGATE-PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; NEGATE-PAUTHLR-NEXT: .Ltmp10:
; NEGATE-PAUTHLR-NEXT: paciasppc
; NEGATE-PAUTHLR-NEXT: retaasppc .Ltmp10
@@ -1254,6 +1276,7 @@ define i32 @leaf_sign_all_b_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-r
; PAUTHLR: // %bb.0:
; PAUTHLR-NEXT: .cfi_b_key_frame
; PAUTHLR-NEXT: bti c
+; PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; PAUTHLR-NEXT: .Ltmp11:
; PAUTHLR-NEXT: pacibsppc
; PAUTHLR-NEXT: .cfi_set_ra_state 2, .Ltmp11
@@ -1316,8 +1339,9 @@ define i32 @leaf_sign_all_b_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-r
; NEGATE-PAUTHLR-LABEL: leaf_sign_all_b_key_bti:
; NEGATE-PAUTHLR: // %bb.0:
; NEGATE-PAUTHLR-NEXT: .cfi_b_key_frame
-; NEGATE-PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; NEGATE-PAUTHLR-NEXT: bti c
+; NEGATE-PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
+; NEGATE-PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; NEGATE-PAUTHLR-NEXT: .Ltmp11:
; NEGATE-PAUTHLR-NEXT: pacibsppc
; NEGATE-PAUTHLR-NEXT: retabsppc .Ltmp11
@@ -1343,6 +1367,7 @@ define i32 @leaf_sign_all_v83_b_key_bti(i32 %x) "branch-protection-pauth-lr" "si
; PAUTHLR: // %bb.0:
; PAUTHLR-NEXT: .cfi_b_key_frame
; PAUTHLR-NEXT: bti c
+; PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; PAUTHLR-NEXT: .Ltmp12:
; PAUTHLR-NEXT: pacibsppc
; PAUTHLR-NEXT: .cfi_set_ra_state 2, .Ltmp12
@@ -1377,8 +1402,9 @@ define i32 @leaf_sign_all_v83_b_key_bti(i32 %x) "branch-protection-pauth-lr" "si
; NEGATE-PAUTHLR-LABEL: leaf_sign_all_v83_b_key_bti:
; NEGATE-PAUTHLR: // %bb.0:
; NEGATE-PAUTHLR-NEXT: .cfi_b_key_frame
-; NEGATE-PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; NEGATE-PAUTHLR-NEXT: bti c
+; NEGATE-PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
+; NEGATE-PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; NEGATE-PAUTHLR-NEXT: .Ltmp12:
; NEGATE-PAUTHLR-NEXT: pacibsppc
; NEGATE-PAUTHLR-NEXT: retabsppc .Ltmp12
diff --git a/llvm/test/CodeGen/AArch64/sign-return-address-pauthlr-slh.ll b/llvm/test/CodeGen/AArch64/sign-return-address-pauthlr-slh.ll
index 6f3a1f8f90af5..afd33f2f11764 100644
--- a/llvm/test/CodeGen/AArch64/sign-return-address-pauthlr-slh.ll
+++ b/llvm/test/CodeGen/AArch64/sign-return-address-pauthlr-slh.ll
@@ -52,6 +52,7 @@ define i32 @f() #0 {
; CHECK-PAUTHLR: // %bb.0: // %entry
; CHECK-PAUTHLR-NEXT: cmp sp, #0
; CHECK-PAUTHLR-NEXT: csetm x16, ne
+; CHECK-PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; CHECK-PAUTHLR-NEXT: .Ltmp0:
; CHECK-PAUTHLR-NEXT: paciasppc
; CHECK-PAUTHLR-NEXT: .cfi_set_ra_state 2, .Ltmp0
@@ -75,6 +76,7 @@ define i32 @f() #0 {
; CHECK-PAUTH-PAUTHLR: // %bb.0: // %entry
; CHECK-PAUTH-PAUTHLR-NEXT: cmp sp, #0
; CHECK-PAUTH-PAUTHLR-NEXT: csetm x16, ne
+; CHECK-PAUTH-PAUTHLR-NEXT: .cfi_non_hint_pauth_frame
; CHECK-PAUTH-PAUTHLR-NEXT: .Ltmp0:
; CHECK-PAUTH-PAUTHLR-NEXT: paciasppc
; CHECK-PAUTH-PAUTHLR-NEXT: .cfi_set_ra_state 2, .Ltmp0
diff --git a/llvm/test/CodeGen/AArch64/swifttail-ptrauth.ll b/llvm/test/CodeGen/AArch64/swifttail-ptrauth.ll
index 54191b3e4b6e7..5de168bae79fb 100644
--- a/llvm/test/CodeGen/AArch64/swifttail-ptrauth.ll
+++ b/llvm/test/CodeGen/AArch64/swifttail-ptrauth.ll
@@ -35,6 +35,7 @@ define swifttailcc void @caller_to0_from0() "branch-protection-pauth-lr" "sign-r
; V83A-NEXT: paciasp
; V83A-NEXT: .cfi_set_ra_state 2, .Ltmp0
+; V9A-NEXT: .cfi_non_hint_pauth_frame
; V9A-NEXT: .Ltmp0:
; V9A-NEXT: paciasppc
; V9A-NEXT: .cfi_set_ra_state 2, .Ltmp0
@@ -103,6 +104,7 @@ define swifttailcc void @caller_to0_from8([8 x i64], i64) "branch-protection-pau
; V83A-NEXT: paciasp
; V83A-NEXT: .cfi_set_ra_state 2, .Ltmp1
+; V9A-NEXT: .cfi_non_hint_pauth_frame
; V9A-NEXT: .Ltmp1:
; V9A-NEXT: paciasppc
; V9A-NEXT: .cfi_set_ra_state 2, .Ltmp1
@@ -177,6 +179,7 @@ define swifttailcc void @caller_to8_from0() "branch-protection-pauth-lr" "sign-r
; V83A-NEXT: paciasp
; V83A-NEXT: .cfi_set_ra_state 2, .Ltmp2
+; V9A-NEXT: .cfi_non_hint_pauth_frame
; V9A-NEXT: .Ltmp2:
; V9A-NEXT: paciasppc
; V9A-NEXT: .cfi_set_ra_state 2, .Ltmp2
@@ -252,6 +255,7 @@ define swifttailcc void @crash_tc(i1 %c, [8 x i64] %pad, i64 %x) "branch-protect
; V83A-NEXT: paciasp
; V83A-NEXT: .cfi_set_ra_state 2, .Ltmp3
+; V9A-NEXT: .cfi_non_hint_pauth_frame
; V9A-NEXT: .Ltmp3:
; V9A-NEXT: paciasppc
; V9A-NEXT: .cfi_set_ra_state 2, .Ltmp3
diff --git a/llvm/test/MC/AArch64/directives-case_insensitive.s b/llvm/test/MC/AArch64/directives-case_insensitive.s
index ee9087b846db2..369bb146b19ba 100644
--- a/llvm/test/MC/AArch64/directives-case_insensitive.s
+++ b/llvm/test/MC/AArch64/directives-case_insensitive.s
@@ -34,12 +34,14 @@ fred .REQ x5
.CFI_NEGATE_RA_STATE
.CFI_NEGATE_RA_STATE_WITH_PC
.CFI_SET_RA_STATE 2, 0
+.CFI_NON_HINT_PAUTH_FRAME
.CFI_B_KEY_FRAME
.CFI_ENDPROC
// CHECK: .cfi_startproc
// CHECK: .cfi_negate_ra_state
// CHECK: .cfi_negate_ra_state_with_pc
// CHECK: .cfi_set_ra_state 2, 0
+// CHECK: .cfi_non_hint_pauth_frame
// CHECK: .cfi_b_key_frame
// CHECK: .cfi_endproc
diff --git a/llvm/test/MC/ELF/AArch64/cfi.s b/llvm/test/MC/ELF/AArch64/cfi.s
index 7047f92bab8fe..7808ca960a58b 100644
--- a/llvm/test/MC/ELF/AArch64/cfi.s
+++ b/llvm/test/MC/ELF/AArch64/cfi.s
@@ -226,6 +226,13 @@ f37:
nop
.cfi_endproc
+f38:
+ .cfi_startproc
+ .cfi_non_hint_pauth_frame
+ .cfi_lsda 0x3, bar
+ nop
+ .cfi_endproc
+
// CHECK: Section {
// CHECK: Name: .eh_frame
// CHECK-NEXT: Type: SHT_PROGBITS (0x1)
@@ -233,8 +240,8 @@ f37:
// CHECK-NEXT: SHF_ALLOC (0x2)
// CHECK-NEXT: ]
// CHECK-NEXT: Address: 0x0
-// CHECK-NEXT: Offset: 0xD0
-// CHECK-NEXT: Size: 1760
+// CHECK-NEXT: Offset: 0xD8
+// CHECK-NEXT: Size: 1808
// CHECK-NEXT: Link: 0
// CHECK-NEXT: Info: 0
// CHECK-NEXT: AddressAlignment: 8
@@ -245,113 +252,116 @@ f37:
// CHECK-NEXT: 0000: 10000000 00000000 017A5200 017C1E01 |.........zR..|..|
// CHECK-NEXT: 0010: 1B000000 10000000 18000000 00000000 |................|
// CHECK-NEXT: 0020: 04000000 00000000 14000000 00000000 |................|
-// CHECK-NEXT: 0030: 017A4C52 4700017C 1E02031B 0C1F0000 |.zLRG..|........|
+// CHECK-NEXT: 0030: 017A4C52 4E00017C 1E02031B 0C1F0000 |.zLRN..|........|
// CHECK-NEXT: 0040: 14000000 1C000000 00000000 04000000 |................|
// CHECK-NEXT: 0050: 04000000 00000000 14000000 00000000 |................|
-// CHECK-NEXT: 0060: 017A4C52 4200017C 1E02031B 0C1F0000 |.zLRB..|........|
+// CHECK-NEXT: 0060: 017A4C52 4700017C 1E02031B 0C1F0000 |.zLRG..|........|
// CHECK-NEXT: 0070: 14000000 1C000000 00000000 04000000 |................|
-// CHECK-NEXT: 0080: 04000000 00000000 1C000000 00000000 |................|
-// CHECK-NEXT: 0090: 017A504C 5200017C 1E0B0000 00000000 |.zPLR..|........|
-// CHECK-NEXT: 00A0: 00000002 1B0C1F00 10000000 24000000 |............$...|
-// CHECK-NEXT: 00B0: 00000000 04000000 02000000 1C000000 |................|
-// CHECK-NEXT: 00C0: 00000000 017A504C 5200017C 1E0B0000 |.....zPLR..|....|
-// CHECK-NEXT: 00D0: 00000000 00000003 1B0C1F00 14000000 |................|
-// CHECK-NEXT: 00E0: 24000000 00000000 04000000 04000000 |$...............|
-// CHECK-NEXT: 00F0: 00000000 14000000 00000000 017A5052 |.............zPR|
-// CHECK-NEXT: 0100: 00017C1E 04020000 1B0C1F00 10000000 |..|.............|
-// CHECK-NEXT: 0110: 1C000000 00000000 04000000 00000000 |................|
-// CHECK-NEXT: 0120: 18000000 00000000 017A5052 00017C1E |.........zPR..|.|
-// CHECK-NEXT: 0130: 06030000 00001B0C 1F000000 10000000 |................|
-// CHECK-NEXT: 0140: 20000000 00000000 04000000 00000000 | ...............|
-// CHECK-NEXT: 0150: 1C000000 00000000 017A5052 00017C1E |.........zPR..|.|
-// CHECK-NEXT: 0160: 0A040000 00000000 00001B0C 1F000000 |................|
-// CHECK-NEXT: 0170: 10000000 24000000 00000000 04000000 |....$...........|
-// CHECK-NEXT: 0180: 00000000 1C000000 00000000 017A5052 |.............zPR|
-// CHECK-NEXT: 0190: 00017C1E 0A080000 00000000 00001B0C |..|.............|
-// CHECK-NEXT: 01A0: 1F000000 10000000 24000000 00000000 |........$.......|
-// CHECK-NEXT: 01B0: 04000000 00000000 14000000 00000000 |................|
-// CHECK-NEXT: 01C0: 017A5052 00017C1E 040A0000 1B0C1F00 |.zPR..|.........|
-// CHECK-NEXT: 01D0: 10000000 1C000000 00000000 04000000 |................|
-// CHECK-NEXT: 01E0: 00000000 18000000 00000000 017A5052 |.............zPR|
-// CHECK-NEXT: 01F0: 00017C1E 060B0000 00001B0C 1F000000 |..|.............|
-// CHECK-NEXT: 0200: 10000000 20000000 00000000 04000000 |.... ...........|
-// CHECK-NEXT: 0210: 00000000 1C000000 00000000 017A5052 |.............zPR|
-// CHECK-NEXT: 0220: 00017C1E 0A0C0000 00000000 00001B0C |..|.............|
-// CHECK-NEXT: 0230: 1F000000 10000000 24000000 00000000 |........$.......|
-// CHECK-NEXT: 0240: 04000000 00000000 1C000000 00000000 |................|
-// CHECK-NEXT: 0250: 017A5052 00017C1E 0A100000 00000000 |.zPR..|.........|
-// CHECK-NEXT: 0260: 00001B0C 1F000000 10000000 24000000 |............$...|
-// CHECK-NEXT: 0270: 00000000 04000000 00000000 14000000 |................|
-// CHECK-NEXT: 0280: 00000000 017A5052 00017C1E 04120000 |.....zPR..|.....|
-// CHECK-NEXT: 0290: 1B0C1F00 10000000 1C000000 00000000 |................|
-// CHECK-NEXT: 02A0: 04000000 00000000 18000000 00000000 |................|
-// CHECK-NEXT: 02B0: 017A5052 00017C1E 06130000 00001B0C |.zPR..|.........|
-// CHECK-NEXT: 02C0: 1F000000 10000000 20000000 00000000 |........ .......|
-// CHECK-NEXT: 02D0: 04000000 00000000 1C000000 00000000 |................|
-// CHECK-NEXT: 02E0: 017A5052 00017C1E 0A140000 00000000 |.zPR..|.........|
-// CHECK-NEXT: 02F0: 00001B0C 1F000000 10000000 24000000 |............$...|
-// CHECK-NEXT: 0300: 00000000 04000000 00000000 1C000000 |................|
-// CHECK-NEXT: 0310: 00000000 017A5052 00017C1E 0A180000 |.....zPR..|.....|
-// CHECK-NEXT: 0320: 00000000 00001B0C 1F000000 10000000 |................|
-// CHECK-NEXT: 0330: 24000000 00000000 04000000 00000000 |$...............|
-// CHECK-NEXT: 0340: 14000000 00000000 017A5052 00017C1E |.........zPR..|.|
-// CHECK-NEXT: 0350: 041A0000 1B0C1F00 10000000 1C000000 |................|
-// CHECK-NEXT: 0360: 00000000 04000000 00000000 18000000 |................|
-// CHECK-NEXT: 0370: 00000000 017A5052 00017C1E 061B0000 |.....zPR..|.....|
-// CHECK-NEXT: 0380: 00001B0C 1F000000 10000000 20000000 |............ ...|
-// CHECK-NEXT: 0390: 00000000 04000000 00000000 1C000000 |................|
-// CHECK-NEXT: 03A0: 00000000 017A5052 00017C1E 0A1C0000 |.....zPR..|.....|
-// CHECK-NEXT: 03B0: 00000000 00001B0C 1F000000 10000000 |................|
-// CHECK-NEXT: 03C0: 24000000 00000000 04000000 00000000 |$...............|
-// CHECK-NEXT: 03D0: 1C000000 00000000 017A5052 00017C1E |.........zPR..|.|
-// CHECK-NEXT: 03E0: 0A800000 00000000 00001B0C 1F000000 |................|
-// CHECK-NEXT: 03F0: 10000000 24000000 00000000 04000000 |....$...........|
-// CHECK-NEXT: 0400: 00000000 14000000 00000000 017A5052 |.............zPR|
-// CHECK-NEXT: 0410: 00017C1E 04820000 1B0C1F00 10000000 |..|.............|
-// CHECK-NEXT: 0420: 1C000000 00000000 04000000 00000000 |................|
-// CHECK-NEXT: 0430: 18000000 00000000 017A5052 00017C1E |.........zPR..|.|
-// CHECK-NEXT: 0440: 06830000 00001B0C 1F000000 10000000 |................|
-// CHECK-NEXT: 0450: 20000000 00000000 04000000 00000000 | ...............|
-// CHECK-NEXT: 0460: 1C000000 00000000 017A5052 00017C1E |.........zPR..|.|
-// CHECK-NEXT: 0470: 0A840000 00000000 00001B0C 1F000000 |................|
-// CHECK-NEXT: 0480: 10000000 24000000 00000000 04000000 |....$...........|
-// CHECK-NEXT: 0490: 00000000 1C000000 00000000 017A5052 |.............zPR|
-// CHECK-NEXT: 04A0: 00017C1E 0A880000 00000000 00001B0C |..|.............|
-// CHECK-NEXT: 04B0: 1F000000 10000000 24000000 00000000 |........$.......|
-// CHECK-NEXT: 04C0: 04000000 00000000 14000000 00000000 |................|
-// CHECK-NEXT: 04D0: 017A5052 00017C1E 048A0000 1B0C1F00 |.zPR..|.........|
-// CHECK-NEXT: 04E0: 10000000 1C000000 00000000 04000000 |................|
-// CHECK-NEXT: 04F0: 00000000 18000000 00000000 017A5052 |.............zPR|
-// CHECK-NEXT: 0500: 00017C1E 068B0000 00001B0C 1F000000 |..|.............|
-// CHECK-NEXT: 0510: 10000000 20000000 00000000 04000000 |.... ...........|
-// CHECK-NEXT: 0520: 00000000 1C000000 00000000 017A5052 |.............zPR|
-// CHECK-NEXT: 0530: 00017C1E 0A8C0000 00000000 00001B0C |..|.............|
-// CHECK-NEXT: 0540: 1F000000 10000000 24000000 00000000 |........$.......|
-// CHECK-NEXT: 0550: 04000000 00000000 1C000000 00000000 |................|
-// CHECK-NEXT: 0560: 017A5052 00017C1E 0A900000 00000000 |.zPR..|.........|
-// CHECK-NEXT: 0570: 00001B0C 1F000000 10000000 24000000 |............$...|
-// CHECK-NEXT: 0580: 00000000 04000000 00000000 14000000 |................|
-// CHECK-NEXT: 0590: 00000000 017A5052 00017C1E 04920000 |.....zPR..|.....|
-// CHECK-NEXT: 05A0: 1B0C1F00 10000000 1C000000 00000000 |................|
-// CHECK-NEXT: 05B0: 04000000 00000000 18000000 00000000 |................|
-// CHECK-NEXT: 05C0: 017A5052 00017C1E 06930000 00001B0C |.zPR..|.........|
-// CHECK-NEXT: 05D0: 1F000000 10000000 20000000 00000000 |........ .......|
-// CHECK-NEXT: 05E0: 04000000 00000000 1C000000 00000000 |................|
-// CHECK-NEXT: 05F0: 017A5052 00017C1E 0A940000 00000000 |.zPR..|.........|
-// CHECK-NEXT: 0600: 00001B0C 1F000000 10000000 24000000 |............$...|
-// CHECK-NEXT: 0610: 00000000 04000000 00000000 1C000000 |................|
-// CHECK-NEXT: 0620: 00000000 017A5052 00017C1E 0A980000 |.....zPR..|.....|
-// CHECK-NEXT: 0630: 00000000 00001B0C 1F000000 10000000 |................|
-// CHECK-NEXT: 0640: 24000000 00000000 04000000 00000000 |$...............|
-// CHECK-NEXT: 0650: 14000000 00000000 017A5052 00017C1E |.........zPR..|.|
-// CHECK-NEXT: 0660: 049A0000 1B0C1F00 10000000 1C000000 |................|
-// CHECK-NEXT: 0670: 00000000 04000000 00000000 18000000 |................|
-// CHECK-NEXT: 0680: 00000000 017A5052 00017C1E 069B0000 |.....zPR..|.....|
-// CHECK-NEXT: 0690: 00001B0C 1F000000 10000000 20000000 |............ ...|
-// CHECK-NEXT: 06A0: 00000000 04000000 00000000 1C000000 |................|
-// CHECK-NEXT: 06B0: 00000000 017A5052 00017C1E 0A9C0000 |.....zPR..|.....|
-// CHECK-NEXT: 06C0: 00000000 00001B0C 1F000000 10000000 |................|
-// CHECK-NEXT: 06D0: 24000000 00000000 04000000 00000000 |$...............|
+// CHECK-NEXT: 0080: 04000000 00000000 14000000 00000000 |................|
+// CHECK-NEXT: 0090: 017A4C52 4200017C 1E02031B 0C1F0000 |.zLRB..|........|
+// CHECK-NEXT: 00A0: 14000000 1C000000 00000000 04000000 |................|
+// CHECK-NEXT: 00B0: 04000000 00000000 1C000000 00000000 |................|
+// CHECK-NEXT: 00C0: 017A504C 5200017C 1E0B0000 00000000 |.zPLR..|........|
+// CHECK-NEXT: 00D0: 00000002 1B0C1F00 10000000 24000000 |............$...|
+// CHECK-NEXT: 00E0: 00000000 04000000 02000000 1C000000 |................|
+// CHECK-NEXT: 00F0: 00000000 017A504C 5200017C 1E0B0000 |.....zPLR..|....|
+// CHECK-NEXT: 0100: 00000000 00000003 1B0C1F00 14000000 |................|
+// CHECK-NEXT: 0110: 24000000 00000000 04000000 04000000 |$...............|
+// CHECK-NEXT: 0120: 00000000 14000000 00000000 017A5052 |.............zPR|
+// CHECK-NEXT: 0130: 00017C1E 04020000 1B0C1F00 10000000 |..|.............|
+// CHECK-NEXT: 0140: 1C000000 00000000 04000000 00000000 |................|
+// CHECK-NEXT: 0150: 18000000 00000000 017A5052 00017C1E |.........zPR..|.|
+// CHECK-NEXT: 0160: 06030000 00001B0C 1F000000 10000000 |................|
+// CHECK-NEXT: 0170: 20000000 00000000 04000000 00000000 | ...............|
+// CHECK-NEXT: 0180: 1C000000 00000000 017A5052 00017C1E |.........zPR..|.|
+// CHECK-NEXT: 0190: 0A040000 00000000 00001B0C 1F000000 |................|
+// CHECK-NEXT: 01A0: 10000000 24000000 00000000 04000000 |....$...........|
+// CHECK-NEXT: 01B0: 00000000 1C000000 00000000 017A5052 |.............zPR|
+// CHECK-NEXT: 01C0: 00017C1E 0A080000 00000000 00001B0C |..|.............|
+// CHECK-NEXT: 01D0: 1F000000 10000000 24000000 00000000 |........$.......|
+// CHECK-NEXT: 01E0: 04000000 00000000 14000000 00000000 |................|
+// CHECK-NEXT: 01F0: 017A5052 00017C1E 040A0000 1B0C1F00 |.zPR..|.........|
+// CHECK-NEXT: 0200: 10000000 1C000000 00000000 04000000 |................|
+// CHECK-NEXT: 0210: 00000000 18000000 00000000 017A5052 |.............zPR|
+// CHECK-NEXT: 0220: 00017C1E 060B0000 00001B0C 1F000000 |..|.............|
+// CHECK-NEXT: 0230: 10000000 20000000 00000000 04000000 |.... ...........|
+// CHECK-NEXT: 0240: 00000000 1C000000 00000000 017A5052 |.............zPR|
+// CHECK-NEXT: 0250: 00017C1E 0A0C0000 00000000 00001B0C |..|.............|
+// CHECK-NEXT: 0260: 1F000000 10000000 24000000 00000000 |........$.......|
+// CHECK-NEXT: 0270: 04000000 00000000 1C000000 00000000 |................|
+// CHECK-NEXT: 0280: 017A5052 00017C1E 0A100000 00000000 |.zPR..|.........|
+// CHECK-NEXT: 0290: 00001B0C 1F000000 10000000 24000000 |............$...|
+// CHECK-NEXT: 02A0: 00000000 04000000 00000000 14000000 |................|
+// CHECK-NEXT: 02B0: 00000000 017A5052 00017C1E 04120000 |.....zPR..|.....|
+// CHECK-NEXT: 02C0: 1B0C1F00 10000000 1C000000 00000000 |................|
+// CHECK-NEXT: 02D0: 04000000 00000000 18000000 00000000 |................|
+// CHECK-NEXT: 02E0: 017A5052 00017C1E 06130000 00001B0C |.zPR..|.........|
+// CHECK-NEXT: 02F0: 1F000000 10000000 20000000 00000000 |........ .......|
+// CHECK-NEXT: 0300: 04000000 00000000 1C000000 00000000 |................|
+// CHECK-NEXT: 0310: 017A5052 00017C1E 0A140000 00000000 |.zPR..|.........|
+// CHECK-NEXT: 0320: 00001B0C 1F000000 10000000 24000000 |............$...|
+// CHECK-NEXT: 0330: 00000000 04000000 00000000 1C000000 |................|
+// CHECK-NEXT: 0340: 00000000 017A5052 00017C1E 0A180000 |.....zPR..|.....|
+// CHECK-NEXT: 0350: 00000000 00001B0C 1F000000 10000000 |................|
+// CHECK-NEXT: 0360: 24000000 00000000 04000000 00000000 |$...............|
+// CHECK-NEXT: 0370: 14000000 00000000 017A5052 00017C1E |.........zPR..|.|
+// CHECK-NEXT: 0380: 041A0000 1B0C1F00 10000000 1C000000 |................|
+// CHECK-NEXT: 0390: 00000000 04000000 00000000 18000000 |................|
+// CHECK-NEXT: 03A0: 00000000 017A5052 00017C1E 061B0000 |.....zPR..|.....|
+// CHECK-NEXT: 03B0: 00001B0C 1F000000 10000000 20000000 |............ ...|
+// CHECK-NEXT: 03C0: 00000000 04000000 00000000 1C000000 |................|
+// CHECK-NEXT: 03D0: 00000000 017A5052 00017C1E 0A1C0000 |.....zPR..|.....|
+// CHECK-NEXT: 03E0: 00000000 00001B0C 1F000000 10000000 |................|
+// CHECK-NEXT: 03F0: 24000000 00000000 04000000 00000000 |$...............|
+// CHECK-NEXT: 0400: 1C000000 00000000 017A5052 00017C1E |.........zPR..|.|
+// CHECK-NEXT: 0410: 0A800000 00000000 00001B0C 1F000000 |................|
+// CHECK-NEXT: 0420: 10000000 24000000 00000000 04000000 |....$...........|
+// CHECK-NEXT: 0430: 00000000 14000000 00000000 017A5052 |.............zPR|
+// CHECK-NEXT: 0440: 00017C1E 04820000 1B0C1F00 10000000 |..|.............|
+// CHECK-NEXT: 0450: 1C000000 00000000 04000000 00000000 |................|
+// CHECK-NEXT: 0460: 18000000 00000000 017A5052 00017C1E |.........zPR..|.|
+// CHECK-NEXT: 0470: 06830000 00001B0C 1F000000 10000000 |................|
+// CHECK-NEXT: 0480: 20000000 00000000 04000000 00000000 | ...............|
+// CHECK-NEXT: 0490: 1C000000 00000000 017A5052 00017C1E |.........zPR..|.|
+// CHECK-NEXT: 04A0: 0A840000 00000000 00001B0C 1F000000 |................|
+// CHECK-NEXT: 04B0: 10000000 24000000 00000000 04000000 |....$...........|
+// CHECK-NEXT: 04C0: 00000000 1C000000 00000000 017A5052 |.............zPR|
+// CHECK-NEXT: 04D0: 00017C1E 0A880000 00000000 00001B0C |..|.............|
+// CHECK-NEXT: 04E0: 1F000000 10000000 24000000 00000000 |........$.......|
+// CHECK-NEXT: 04F0: 04000000 00000000 14000000 00000000 |................|
+// CHECK-NEXT: 0500: 017A5052 00017C1E 048A0000 1B0C1F00 |.zPR..|.........|
+// CHECK-NEXT: 0510: 10000000 1C000000 00000000 04000000 |................|
+// CHECK-NEXT: 0520: 00000000 18000000 00000000 017A5052 |.............zPR|
+// CHECK-NEXT: 0530: 00017C1E 068B0000 00001B0C 1F000000 |..|.............|
+// CHECK-NEXT: 0540: 10000000 20000000 00000000 04000000 |.... ...........|
+// CHECK-NEXT: 0550: 00000000 1C000000 00000000 017A5052 |.............zPR|
+// CHECK-NEXT: 0560: 00017C1E 0A8C0000 00000000 00001B0C |..|.............|
+// CHECK-NEXT: 0570: 1F000000 10000000 24000000 00000000 |........$.......|
+// CHECK-NEXT: 0580: 04000000 00000000 1C000000 00000000 |................|
+// CHECK-NEXT: 0590: 017A5052 00017C1E 0A900000 00000000 |.zPR..|.........|
+// CHECK-NEXT: 05A0: 00001B0C 1F000000 10000000 24000000 |............$...|
+// CHECK-NEXT: 05B0: 00000000 04000000 00000000 14000000 |................|
+// CHECK-NEXT: 05C0: 00000000 017A5052 00017C1E 04920000 |.....zPR..|.....|
+// CHECK-NEXT: 05D0: 1B0C1F00 10000000 1C000000 00000000 |................|
+// CHECK-NEXT: 05E0: 04000000 00000000 18000000 00000000 |................|
+// CHECK-NEXT: 05F0: 017A5052 00017C1E 06930000 00001B0C |.zPR..|.........|
+// CHECK-NEXT: 0600: 1F000000 10000000 20000000 00000000 |........ .......|
+// CHECK-NEXT: 0610: 04000000 00000000 1C000000 00000000 |................|
+// CHECK-NEXT: 0620: 017A5052 00017C1E 0A940000 00000000 |.zPR..|.........|
+// CHECK-NEXT: 0630: 00001B0C 1F000000 10000000 24000000 |............$...|
+// CHECK-NEXT: 0640: 00000000 04000000 00000000 1C000000 |................|
+// CHECK-NEXT: 0650: 00000000 017A5052 00017C1E 0A980000 |.....zPR..|.....|
+// CHECK-NEXT: 0660: 00000000 00001B0C 1F000000 10000000 |................|
+// CHECK-NEXT: 0670: 24000000 00000000 04000000 00000000 |$...............|
+// CHECK-NEXT: 0680: 14000000 00000000 017A5052 00017C1E |.........zPR..|.|
+// CHECK-NEXT: 0690: 049A0000 1B0C1F00 10000000 1C000000 |................|
+// CHECK-NEXT: 06A0: 00000000 04000000 00000000 18000000 |................|
+// CHECK-NEXT: 06B0: 00000000 017A5052 00017C1E 069B0000 |.....zPR..|.....|
+// CHECK-NEXT: 06C0: 00001B0C 1F000000 10000000 20000000 |............ ...|
+// CHECK-NEXT: 06D0: 00000000 04000000 00000000 1C000000 |................|
+// CHECK-NEXT: 06E0: 00000000 017A5052 00017C1E 0A9C0000 |.....zPR..|.....|
+// CHECK-NEXT: 06F0: 00000000 00001B0C 1F000000 10000000 |................|
+// CHECK-NEXT: 0700: 24000000 00000000 04000000 00000000 |$...............|
// CHECK-NEXT: )
// CHECK-NEXT: }
// CHECK: Section {
@@ -361,198 +371,203 @@ f37:
// CHECK-NEXT: SHF_INFO_LINK (0x40)
// CHECK-NEXT: ]
// CHECK-NEXT: Address: 0x0
-// CHECK-NEXT: Offset: 0xBA0
-// CHECK-NEXT: Size: 1752
+// CHECK-NEXT: Offset: 0xBF0
+// CHECK-NEXT: Size: 1800
// CHECK-NEXT: Link: 5
// CHECK-NEXT: Info: 3
// CHECK-NEXT: AddressAlignment: 8
// CHECK-NEXT: EntrySize: 24
// CHECK-NEXT: Relocations [
// CHECK-NEXT: 0x1C R_AARCH64_PREL32 .text 0x8C
-// CHECK-NEXT: 0x48 R_AARCH64_PREL32 .text 0x8
+// CHECK-NEXT: 0x48 R_AARCH64_PREL32 .text 0x90
// CHECK-NEXT: 0x51 R_AARCH64_ABS32 bar 0x0
-// CHECK-NEXT: 0x78 R_AARCH64_PREL32 .text 0x0
+// CHECK-NEXT: 0x78 R_AARCH64_PREL32 .text 0x8
// CHECK-NEXT: 0x81 R_AARCH64_ABS32 bar 0x0
-// CHECK-NEXT: 0x9B R_AARCH64_ABS64 foo 0x0
-// CHECK-NEXT: 0xB0 R_AARCH64_PREL32 .text 0xC
-// CHECK-NEXT: 0xB9 R_AARCH64_ABS16 bar 0x0
-// CHECK-NEXT: 0xCF R_AARCH64_ABS64 foo 0x0
-// CHECK-NEXT: 0xE4 R_AARCH64_PREL32 .text 0x4
-// CHECK-NEXT: 0xED R_AARCH64_ABS32 bar 0x0
-// CHECK-NEXT: 0x106 R_AARCH64_ABS16 foo 0x0
-// CHECK-NEXT: 0x114 R_AARCH64_PREL32 .text 0x10
-// CHECK-NEXT: 0x132 R_AARCH64_ABS32 foo 0x0
-// CHECK-NEXT: 0x144 R_AARCH64_PREL32 .text 0x14
-// CHECK-NEXT: 0x162 R_AARCH64_ABS64 foo 0x0
-// CHECK-NEXT: 0x178 R_AARCH64_PREL32 .text 0x18
-// CHECK-NEXT: 0x196 R_AARCH64_ABS64 foo 0x0
-// CHECK-NEXT: 0x1AC R_AARCH64_PREL32 .text 0x28
-// CHECK-NEXT: 0x1CA R_AARCH64_ABS16 foo 0x0
-// CHECK-NEXT: 0x1D8 R_AARCH64_PREL32 .text 0x1C
-// CHECK-NEXT: 0x1F6 R_AARCH64_ABS32 foo 0x0
-// CHECK-NEXT: 0x208 R_AARCH64_PREL32 .text 0x20
-// CHECK-NEXT: 0x226 R_AARCH64_ABS64 foo 0x0
-// CHECK-NEXT: 0x23C R_AARCH64_PREL32 .text 0x24
-// CHECK-NEXT: 0x25A R_AARCH64_PREL64 foo 0x0
-// CHECK-NEXT: 0x270 R_AARCH64_PREL32 .text 0x2C
-// CHECK-NEXT: 0x28E R_AARCH64_PREL16 foo 0x0
-// CHECK-NEXT: 0x29C R_AARCH64_PREL32 .text 0x30
-// CHECK-NEXT: 0x2BA R_AARCH64_PREL32 foo 0x0
-// CHECK-NEXT: 0x2CC R_AARCH64_PREL32 .text 0x34
-// CHECK-NEXT: 0x2EA R_AARCH64_PREL64 foo 0x0
-// CHECK-NEXT: 0x300 R_AARCH64_PREL32 .text 0x38
-// CHECK-NEXT: 0x31E R_AARCH64_PREL64 foo 0x0
-// CHECK-NEXT: 0x334 R_AARCH64_PREL32 .text 0x48
-// CHECK-NEXT: 0x352 R_AARCH64_PREL16 foo 0x0
-// CHECK-NEXT: 0x360 R_AARCH64_PREL32 .text 0x3C
-// CHECK-NEXT: 0x37E R_AARCH64_PREL32 foo 0x0
-// CHECK-NEXT: 0x390 R_AARCH64_PREL32 .text 0x40
-// CHECK-NEXT: 0x3AE R_AARCH64_PREL64 foo 0x0
-// CHECK-NEXT: 0x3C4 R_AARCH64_PREL32 .text 0x44
-// CHECK-NEXT: 0x3E2 R_AARCH64_ABS64 foo 0x0
-// CHECK-NEXT: 0x3F8 R_AARCH64_PREL32 .text 0x4C
-// CHECK-NEXT: 0x416 R_AARCH64_ABS16 foo 0x0
-// CHECK-NEXT: 0x424 R_AARCH64_PREL32 .text 0x50
-// CHECK-NEXT: 0x442 R_AARCH64_ABS32 foo 0x0
-// CHECK-NEXT: 0x454 R_AARCH64_PREL32 .text 0x54
-// CHECK-NEXT: 0x472 R_AARCH64_ABS64 foo 0x0
-// CHECK-NEXT: 0x488 R_AARCH64_PREL32 .text 0x58
-// CHECK-NEXT: 0x4A6 R_AARCH64_ABS64 foo 0x0
-// CHECK-NEXT: 0x4BC R_AARCH64_PREL32 .text 0x68
-// CHECK-NEXT: 0x4DA R_AARCH64_ABS16 foo 0x0
-// CHECK-NEXT: 0x4E8 R_AARCH64_PREL32 .text 0x5C
-// CHECK-NEXT: 0x506 R_AARCH64_ABS32 foo 0x0
-// CHECK-NEXT: 0x518 R_AARCH64_PREL32 .text 0x60
-// CHECK-NEXT: 0x536 R_AARCH64_ABS64 foo 0x0
-// CHECK-NEXT: 0x54C R_AARCH64_PREL32 .text 0x64
-// CHECK-NEXT: 0x56A R_AARCH64_PREL64 foo 0x0
-// CHECK-NEXT: 0x580 R_AARCH64_PREL32 .text 0x6C
-// CHECK-NEXT: 0x59E R_AARCH64_PREL16 foo 0x0
-// CHECK-NEXT: 0x5AC R_AARCH64_PREL32 .text 0x70
-// CHECK-NEXT: 0x5CA R_AARCH64_PREL32 foo 0x0
-// CHECK-NEXT: 0x5DC R_AARCH64_PREL32 .text 0x74
-// CHECK-NEXT: 0x5FA R_AARCH64_PREL64 foo 0x0
-// CHECK-NEXT: 0x610 R_AARCH64_PREL32 .text 0x78
-// CHECK-NEXT: 0x62E R_AARCH64_PREL64 foo 0x0
-// CHECK-NEXT: 0x644 R_AARCH64_PREL32 .text 0x88
-// CHECK-NEXT: 0x662 R_AARCH64_PREL16 foo 0x0
-// CHECK-NEXT: 0x670 R_AARCH64_PREL32 .text 0x7C
-// CHECK-NEXT: 0x68E R_AARCH64_PREL32 foo 0x0
-// CHECK-NEXT: 0x6A0 R_AARCH64_PREL32 .text 0x80
-// CHECK-NEXT: 0x6BE R_AARCH64_PREL64 foo 0x0
-// CHECK-NEXT: 0x6D4 R_AARCH64_PREL32 .text 0x84
+// CHECK-NEXT: 0xA8 R_AARCH64_PREL32 .text 0x0
+// CHECK-NEXT: 0xB1 R_AARCH64_ABS32 bar 0x0
+// CHECK-NEXT: 0xCB R_AARCH64_ABS64 foo 0x0
+// CHECK-NEXT: 0xE0 R_AARCH64_PREL32 .text 0xC
+// CHECK-NEXT: 0xE9 R_AARCH64_ABS16 bar 0x0
+// CHECK-NEXT: 0xFF R_AARCH64_ABS64 foo 0x0
+// CHECK-NEXT: 0x114 R_AARCH64_PREL32 .text 0x4
+// CHECK-NEXT: 0x11D R_AARCH64_ABS32 bar 0x0
+// CHECK-NEXT: 0x136 R_AARCH64_ABS16 foo 0x0
+// CHECK-NEXT: 0x144 R_AARCH64_PREL32 .text 0x10
+// CHECK-NEXT: 0x162 R_AARCH64_ABS32 foo 0x0
+// CHECK-NEXT: 0x174 R_AARCH64_PREL32 .text 0x14
+// CHECK-NEXT: 0x192 R_AARCH64_ABS64 foo 0x0
+// CHECK-NEXT: 0x1A8 R_AARCH64_PREL32 .text 0x18
+// CHECK-NEXT: 0x1C6 R_AARCH64_ABS64 foo 0x0
+// CHECK-NEXT: 0x1DC R_AARCH64_PREL32 .text 0x28
+// CHECK-NEXT: 0x1FA R_AARCH64_ABS16 foo 0x0
+// CHECK-NEXT: 0x208 R_AARCH64_PREL32 .text 0x1C
+// CHECK-NEXT: 0x226 R_AARCH64_ABS32 foo 0x0
+// CHECK-NEXT: 0x238 R_AARCH64_PREL32 .text 0x20
+// CHECK-NEXT: 0x256 R_AARCH64_ABS64 foo 0x0
+// CHECK-NEXT: 0x26C R_AARCH64_PREL32 .text 0x24
+// CHECK-NEXT: 0x28A R_AARCH64_PREL64 foo 0x0
+// CHECK-NEXT: 0x2A0 R_AARCH64_PREL32 .text 0x2C
+// CHECK-NEXT: 0x2BE R_AARCH64_PREL16 foo 0x0
+// CHECK-NEXT: 0x2CC R_AARCH64_PREL32 .text 0x30
+// CHECK-NEXT: 0x2EA R_AARCH64_PREL32 foo 0x0
+// CHECK-NEXT: 0x2FC R_AARCH64_PREL32 .text 0x34
+// CHECK-NEXT: 0x31A R_AARCH64_PREL64 foo 0x0
+// CHECK-NEXT: 0x330 R_AARCH64_PREL32 .text 0x38
+// CHECK-NEXT: 0x34E R_AARCH64_PREL64 foo 0x0
+// CHECK-NEXT: 0x364 R_AARCH64_PREL32 .text 0x48
+// CHECK-NEXT: 0x382 R_AARCH64_PREL16 foo 0x0
+// CHECK-NEXT: 0x390 R_AARCH64_PREL32 .text 0x3C
+// CHECK-NEXT: 0x3AE R_AARCH64_PREL32 foo 0x0
+// CHECK-NEXT: 0x3C0 R_AARCH64_PREL32 .text 0x40
+// CHECK-NEXT: 0x3DE R_AARCH64_PREL64 foo 0x0
+// CHECK-NEXT: 0x3F4 R_AARCH64_PREL32 .text 0x44
+// CHECK-NEXT: 0x412 R_AARCH64_ABS64 foo 0x0
+// CHECK-NEXT: 0x428 R_AARCH64_PREL32 .text 0x4C
+// CHECK-NEXT: 0x446 R_AARCH64_ABS16 foo 0x0
+// CHECK-NEXT: 0x454 R_AARCH64_PREL32 .text 0x50
+// CHECK-NEXT: 0x472 R_AARCH64_ABS32 foo 0x0
+// CHECK-NEXT: 0x484 R_AARCH64_PREL32 .text 0x54
+// CHECK-NEXT: 0x4A2 R_AARCH64_ABS64 foo 0x0
+// CHECK-NEXT: 0x4B8 R_AARCH64_PREL32 .text 0x58
+// CHECK-NEXT: 0x4D6 R_AARCH64_ABS64 foo 0x0
+// CHECK-NEXT: 0x4EC R_AARCH64_PREL32 .text 0x68
+// CHECK-NEXT: 0x50A R_AARCH64_ABS16 foo 0x0
+// CHECK-NEXT: 0x518 R_AARCH64_PREL32 .text 0x5C
+// CHECK-NEXT: 0x536 R_AARCH64_ABS32 foo 0x0
+// CHECK-NEXT: 0x548 R_AARCH64_PREL32 .text 0x60
+// CHECK-NEXT: 0x566 R_AARCH64_ABS64 foo 0x0
+// CHECK-NEXT: 0x57C R_AARCH64_PREL32 .text 0x64
+// CHECK-NEXT: 0x59A R_AARCH64_PREL64 foo 0x0
+// CHECK-NEXT: 0x5B0 R_AARCH64_PREL32 .text 0x6C
+// CHECK-NEXT: 0x5CE R_AARCH64_PREL16 foo 0x0
+// CHECK-NEXT: 0x5DC R_AARCH64_PREL32 .text 0x70
+// CHECK-NEXT: 0x5FA R_AARCH64_PREL32 foo 0x0
+// CHECK-NEXT: 0x60C R_AARCH64_PREL32 .text 0x74
+// CHECK-NEXT: 0x62A R_AARCH64_PREL64 foo 0x0
+// CHECK-NEXT: 0x640 R_AARCH64_PREL32 .text 0x78
+// CHECK-NEXT: 0x65E R_AARCH64_PREL64 foo 0x0
+// CHECK-NEXT: 0x674 R_AARCH64_PREL32 .text 0x88
+// CHECK-NEXT: 0x692 R_AARCH64_PREL16 foo 0x0
+// CHECK-NEXT: 0x6A0 R_AARCH64_PREL32 .text 0x7C
+// CHECK-NEXT: 0x6BE R_AARCH64_PREL32 foo 0x0
+// CHECK-NEXT: 0x6D0 R_AARCH64_PREL32 .text 0x80
+// CHECK-NEXT: 0x6EE R_AARCH64_PREL64 foo 0x0
+// CHECK-NEXT: 0x704 R_AARCH64_PREL32 .text 0x84
// CHECK-NEXT: ]
// CHECK-NEXT: SectionData (
// CHECK-NEXT: 0000: 1C000000 00000000 05010000 01000000 |................|
// CHECK-NEXT: 0010: 8C000000 00000000 48000000 00000000 |........H.......|
-// CHECK-NEXT: 0020: 05010000 01000000 08000000 00000000 |................|
-// CHECK-NEXT: 0030: 51000000 00000000 02010000 28000000 |Q...........(...|
+// CHECK-NEXT: 0020: 05010000 01000000 90000000 00000000 |................|
+// CHECK-NEXT: 0030: 51000000 00000000 02010000 29000000 |Q...........)...|
// CHECK-NEXT: 0040: 00000000 00000000 78000000 00000000 |........x.......|
-// CHECK-NEXT: 0050: 05010000 01000000 00000000 00000000 |................|
-// CHECK-NEXT: 0060: 81000000 00000000 02010000 28000000 |............(...|
-// CHECK-NEXT: 0070: 00000000 00000000 9B000000 00000000 |................|
-// CHECK-NEXT: 0080: 01010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 0090: B0000000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 00A0: 0C000000 00000000 B9000000 00000000 |................|
-// CHECK-NEXT: 00B0: 03010000 28000000 00000000 00000000 |....(...........|
-// CHECK-NEXT: 00C0: CF000000 00000000 01010000 29000000 |............)...|
-// CHECK-NEXT: 00D0: 00000000 00000000 E4000000 00000000 |................|
-// CHECK-NEXT: 00E0: 05010000 01000000 04000000 00000000 |................|
-// CHECK-NEXT: 00F0: ED000000 00000000 02010000 28000000 |............(...|
-// CHECK-NEXT: 0100: 00000000 00000000 06010000 00000000 |................|
-// CHECK-NEXT: 0110: 03010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 0120: 14010000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 0130: 10000000 00000000 32010000 00000000 |........2.......|
-// CHECK-NEXT: 0140: 02010000 29000000 00000000 00000000 |....)...........|
+// CHECK-NEXT: 0050: 05010000 01000000 08000000 00000000 |................|
+// CHECK-NEXT: 0060: 81000000 00000000 02010000 29000000 |............)...|
+// CHECK-NEXT: 0070: 00000000 00000000 A8000000 00000000 |................|
+// CHECK-NEXT: 0080: 05010000 01000000 00000000 00000000 |................|
+// CHECK-NEXT: 0090: B1000000 00000000 02010000 29000000 |............)...|
+// CHECK-NEXT: 00A0: 00000000 00000000 CB000000 00000000 |................|
+// CHECK-NEXT: 00B0: 01010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 00C0: E0000000 00000000 05010000 01000000 |................|
+// CHECK-NEXT: 00D0: 0C000000 00000000 E9000000 00000000 |................|
+// CHECK-NEXT: 00E0: 03010000 29000000 00000000 00000000 |....)...........|
+// CHECK-NEXT: 00F0: FF000000 00000000 01010000 2A000000 |............*...|
+// CHECK-NEXT: 0100: 00000000 00000000 14010000 00000000 |................|
+// CHECK-NEXT: 0110: 05010000 01000000 04000000 00000000 |................|
+// CHECK-NEXT: 0120: 1D010000 00000000 02010000 29000000 |............)...|
+// CHECK-NEXT: 0130: 00000000 00000000 36010000 00000000 |........6.......|
+// CHECK-NEXT: 0140: 03010000 2A000000 00000000 00000000 |....*...........|
// CHECK-NEXT: 0150: 44010000 00000000 05010000 01000000 |D...............|
-// CHECK-NEXT: 0160: 14000000 00000000 62010000 00000000 |........b.......|
-// CHECK-NEXT: 0170: 01010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 0180: 78010000 00000000 05010000 01000000 |x...............|
-// CHECK-NEXT: 0190: 18000000 00000000 96010000 00000000 |................|
-// CHECK-NEXT: 01A0: 01010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 01B0: AC010000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 01C0: 28000000 00000000 CA010000 00000000 |(...............|
-// CHECK-NEXT: 01D0: 03010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 01E0: D8010000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 01F0: 1C000000 00000000 F6010000 00000000 |................|
-// CHECK-NEXT: 0200: 02010000 29000000 00000000 00000000 |....)...........|
+// CHECK-NEXT: 0160: 10000000 00000000 62010000 00000000 |........b.......|
+// CHECK-NEXT: 0170: 02010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 0180: 74010000 00000000 05010000 01000000 |t...............|
+// CHECK-NEXT: 0190: 14000000 00000000 92010000 00000000 |................|
+// CHECK-NEXT: 01A0: 01010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 01B0: A8010000 00000000 05010000 01000000 |................|
+// CHECK-NEXT: 01C0: 18000000 00000000 C6010000 00000000 |................|
+// CHECK-NEXT: 01D0: 01010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 01E0: DC010000 00000000 05010000 01000000 |................|
+// CHECK-NEXT: 01F0: 28000000 00000000 FA010000 00000000 |(...............|
+// CHECK-NEXT: 0200: 03010000 2A000000 00000000 00000000 |....*...........|
// CHECK-NEXT: 0210: 08020000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 0220: 20000000 00000000 26020000 00000000 | .......&.......|
-// CHECK-NEXT: 0230: 01010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 0240: 3C020000 00000000 05010000 01000000 |<...............|
-// CHECK-NEXT: 0250: 24000000 00000000 5A020000 00000000 |$.......Z.......|
-// CHECK-NEXT: 0260: 04010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 0270: 70020000 00000000 05010000 01000000 |p...............|
-// CHECK-NEXT: 0280: 2C000000 00000000 8E020000 00000000 |,...............|
-// CHECK-NEXT: 0290: 06010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 02A0: 9C020000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 02B0: 30000000 00000000 BA020000 00000000 |0...............|
-// CHECK-NEXT: 02C0: 05010000 29000000 00000000 00000000 |....)...........|
+// CHECK-NEXT: 0220: 1C000000 00000000 26020000 00000000 |........&.......|
+// CHECK-NEXT: 0230: 02010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 0240: 38020000 00000000 05010000 01000000 |8...............|
+// CHECK-NEXT: 0250: 20000000 00000000 56020000 00000000 | .......V.......|
+// CHECK-NEXT: 0260: 01010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 0270: 6C020000 00000000 05010000 01000000 |l...............|
+// CHECK-NEXT: 0280: 24000000 00000000 8A020000 00000000 |$...............|
+// CHECK-NEXT: 0290: 04010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 02A0: A0020000 00000000 05010000 01000000 |................|
+// CHECK-NEXT: 02B0: 2C000000 00000000 BE020000 00000000 |,...............|
+// CHECK-NEXT: 02C0: 06010000 2A000000 00000000 00000000 |....*...........|
// CHECK-NEXT: 02D0: CC020000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 02E0: 34000000 00000000 EA020000 00000000 |4...............|
-// CHECK-NEXT: 02F0: 04010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 0300: 00030000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 0310: 38000000 00000000 1E030000 00000000 |8...............|
-// CHECK-NEXT: 0320: 04010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 0330: 34030000 00000000 05010000 01000000 |4...............|
-// CHECK-NEXT: 0340: 48000000 00000000 52030000 00000000 |H.......R.......|
-// CHECK-NEXT: 0350: 06010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 0360: 60030000 00000000 05010000 01000000 |`...............|
-// CHECK-NEXT: 0370: 3C000000 00000000 7E030000 00000000 |<.......~.......|
-// CHECK-NEXT: 0380: 05010000 29000000 00000000 00000000 |....)...........|
+// CHECK-NEXT: 02E0: 30000000 00000000 EA020000 00000000 |0...............|
+// CHECK-NEXT: 02F0: 05010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 0300: FC020000 00000000 05010000 01000000 |................|
+// CHECK-NEXT: 0310: 34000000 00000000 1A030000 00000000 |4...............|
+// CHECK-NEXT: 0320: 04010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 0330: 30030000 00000000 05010000 01000000 |0...............|
+// CHECK-NEXT: 0340: 38000000 00000000 4E030000 00000000 |8.......N.......|
+// CHECK-NEXT: 0350: 04010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 0360: 64030000 00000000 05010000 01000000 |d...............|
+// CHECK-NEXT: 0370: 48000000 00000000 82030000 00000000 |H...............|
+// CHECK-NEXT: 0380: 06010000 2A000000 00000000 00000000 |....*...........|
// CHECK-NEXT: 0390: 90030000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 03A0: 40000000 00000000 AE030000 00000000 |@...............|
-// CHECK-NEXT: 03B0: 04010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 03C0: C4030000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 03D0: 44000000 00000000 E2030000 00000000 |D...............|
-// CHECK-NEXT: 03E0: 01010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 03F0: F8030000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 0400: 4C000000 00000000 16040000 00000000 |L...............|
-// CHECK-NEXT: 0410: 03010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 0420: 24040000 00000000 05010000 01000000 |$...............|
-// CHECK-NEXT: 0430: 50000000 00000000 42040000 00000000 |P.......B.......|
-// CHECK-NEXT: 0440: 02010000 29000000 00000000 00000000 |....)...........|
+// CHECK-NEXT: 03A0: 3C000000 00000000 AE030000 00000000 |<...............|
+// CHECK-NEXT: 03B0: 05010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 03C0: C0030000 00000000 05010000 01000000 |................|
+// CHECK-NEXT: 03D0: 40000000 00000000 DE030000 00000000 |@...............|
+// CHECK-NEXT: 03E0: 04010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 03F0: F4030000 00000000 05010000 01000000 |................|
+// CHECK-NEXT: 0400: 44000000 00000000 12040000 00000000 |D...............|
+// CHECK-NEXT: 0410: 01010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 0420: 28040000 00000000 05010000 01000000 |(...............|
+// CHECK-NEXT: 0430: 4C000000 00000000 46040000 00000000 |L.......F.......|
+// CHECK-NEXT: 0440: 03010000 2A000000 00000000 00000000 |....*...........|
// CHECK-NEXT: 0450: 54040000 00000000 05010000 01000000 |T...............|
-// CHECK-NEXT: 0460: 54000000 00000000 72040000 00000000 |T.......r.......|
-// CHECK-NEXT: 0470: 01010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 0480: 88040000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 0490: 58000000 00000000 A6040000 00000000 |X...............|
-// CHECK-NEXT: 04A0: 01010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 04B0: BC040000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 04C0: 68000000 00000000 DA040000 00000000 |h...............|
-// CHECK-NEXT: 04D0: 03010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 04E0: E8040000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 04F0: 5C000000 00000000 06050000 00000000 |\...............|
-// CHECK-NEXT: 0500: 02010000 29000000 00000000 00000000 |....)...........|
+// CHECK-NEXT: 0460: 50000000 00000000 72040000 00000000 |P.......r.......|
+// CHECK-NEXT: 0470: 02010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 0480: 84040000 00000000 05010000 01000000 |................|
+// CHECK-NEXT: 0490: 54000000 00000000 A2040000 00000000 |T...............|
+// CHECK-NEXT: 04A0: 01010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 04B0: B8040000 00000000 05010000 01000000 |................|
+// CHECK-NEXT: 04C0: 58000000 00000000 D6040000 00000000 |X...............|
+// CHECK-NEXT: 04D0: 01010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 04E0: EC040000 00000000 05010000 01000000 |................|
+// CHECK-NEXT: 04F0: 68000000 00000000 0A050000 00000000 |h...............|
+// CHECK-NEXT: 0500: 03010000 2A000000 00000000 00000000 |....*...........|
// CHECK-NEXT: 0510: 18050000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 0520: 60000000 00000000 36050000 00000000 |`.......6.......|
-// CHECK-NEXT: 0530: 01010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 0540: 4C050000 00000000 05010000 01000000 |L...............|
-// CHECK-NEXT: 0550: 64000000 00000000 6A050000 00000000 |d.......j.......|
-// CHECK-NEXT: 0560: 04010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 0570: 80050000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 0580: 6C000000 00000000 9E050000 00000000 |l...............|
-// CHECK-NEXT: 0590: 06010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 05A0: AC050000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 05B0: 70000000 00000000 CA050000 00000000 |p...............|
-// CHECK-NEXT: 05C0: 05010000 29000000 00000000 00000000 |....)...........|
+// CHECK-NEXT: 0520: 5C000000 00000000 36050000 00000000 |\.......6.......|
+// CHECK-NEXT: 0530: 02010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 0540: 48050000 00000000 05010000 01000000 |H...............|
+// CHECK-NEXT: 0550: 60000000 00000000 66050000 00000000 |`.......f.......|
+// CHECK-NEXT: 0560: 01010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 0570: 7C050000 00000000 05010000 01000000 ||...............|
+// CHECK-NEXT: 0580: 64000000 00000000 9A050000 00000000 |d...............|
+// CHECK-NEXT: 0590: 04010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 05A0: B0050000 00000000 05010000 01000000 |................|
+// CHECK-NEXT: 05B0: 6C000000 00000000 CE050000 00000000 |l...............|
+// CHECK-NEXT: 05C0: 06010000 2A000000 00000000 00000000 |....*...........|
// CHECK-NEXT: 05D0: DC050000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 05E0: 74000000 00000000 FA050000 00000000 |t...............|
-// CHECK-NEXT: 05F0: 04010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 0600: 10060000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 0610: 78000000 00000000 2E060000 00000000 |x...............|
-// CHECK-NEXT: 0620: 04010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 0630: 44060000 00000000 05010000 01000000 |D...............|
-// CHECK-NEXT: 0640: 88000000 00000000 62060000 00000000 |........b.......|
-// CHECK-NEXT: 0650: 06010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 0660: 70060000 00000000 05010000 01000000 |p...............|
-// CHECK-NEXT: 0670: 7C000000 00000000 8E060000 00000000 ||...............|
-// CHECK-NEXT: 0680: 05010000 29000000 00000000 00000000 |....)...........|
+// CHECK-NEXT: 05E0: 70000000 00000000 FA050000 00000000 |p...............|
+// CHECK-NEXT: 05F0: 05010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 0600: 0C060000 00000000 05010000 01000000 |................|
+// CHECK-NEXT: 0610: 74000000 00000000 2A060000 00000000 |t.......*.......|
+// CHECK-NEXT: 0620: 04010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 0630: 40060000 00000000 05010000 01000000 |@...............|
+// CHECK-NEXT: 0640: 78000000 00000000 5E060000 00000000 |x.......^.......|
+// CHECK-NEXT: 0650: 04010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 0660: 74060000 00000000 05010000 01000000 |t...............|
+// CHECK-NEXT: 0670: 88000000 00000000 92060000 00000000 |................|
+// CHECK-NEXT: 0680: 06010000 2A000000 00000000 00000000 |....*...........|
// CHECK-NEXT: 0690: A0060000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 06A0: 80000000 00000000 BE060000 00000000 |................|
-// CHECK-NEXT: 06B0: 04010000 29000000 00000000 00000000 |....)...........|
-// CHECK-NEXT: 06C0: D4060000 00000000 05010000 01000000 |................|
-// CHECK-NEXT: 06D0: 84000000 00000000 |........|
+// CHECK-NEXT: 06A0: 7C000000 00000000 BE060000 00000000 ||...............|
+// CHECK-NEXT: 06B0: 05010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 06C0: D0060000 00000000 05010000 01000000 |................|
+// CHECK-NEXT: 06D0: 80000000 00000000 EE060000 00000000 |................|
+// CHECK-NEXT: 06E0: 04010000 2A000000 00000000 00000000 |....*...........|
+// CHECK-NEXT: 06F0: 04070000 00000000 05010000 01000000 |................|
+// CHECK-NEXT: 0700: 84000000 00000000 |........|
// CHECK-NEXT: )
// CHECK-NEXT: }
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