[clang] d05c46c - [clang][CIR] Add tests for SVE NAND intrinsics (#233173)
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Sun Oct 18 08:02:24 PDT 2026
Author: Vicky Nguyen
Date: 2026-10-18T08:02:19-07:00
New Revision: d05c46c7c5955196eb01f16d6bf16b9047ffa6e8
URL: https://github.com/llvm/llvm-project/commit/d05c46c7c5955196eb01f16d6bf16b9047ffa6e8
DIFF: https://github.com/llvm/llvm-project/commit/d05c46c7c5955196eb01f16d6bf16b9047ffa6e8.diff
LOG: [clang][CIR] Add tests for SVE NAND intrinsics (#233173)
Tests for plain SVE `svnand`
(https://developer.arm.com/architectures/instruction-sets/intrinsics/#q=svnand).
Port: `clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nand.c` to
`clang/test/CodeGen/AArch64/sve/nand.c`
Part of https://github.com/llvm/llvm-project/issues/223963.
Added:
clang/test/CodeGen/AArch64/sve/nand.c
Modified:
Removed:
clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nand.c
################################################################################
diff --git a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nand.c b/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nand.c
deleted file mode 100644
index 5b8bede05af7d3..00000000000000
--- a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nand.c
+++ /dev/null
@@ -1,38 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
-// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
-// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
-// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
-
-#include <arm_sve.h>
-
-#if defined __ARM_FEATURE_SME
-#define MODE_ATTR __arm_streaming
-#else
-#define MODE_ATTR
-#endif
-
-#ifdef SVE_OVERLOADED_FORMS
-// A simple used,unused... macro, long enough to represent any SVE builtin.
-#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
-#else
-#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
-#endif
-
-// CHECK-LABEL: @test_svnand_b_z(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.nand.z.nxv16i1(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP2:%.*]])
-// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
-//
-// CPP-CHECK-LABEL: @_Z15test_svnand_b_zu10__SVBool_tS_S_(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.nand.z.nxv16i1(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP2:%.*]])
-// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
-//
-svbool_t test_svnand_b_z(svbool_t pg, svbool_t op1, svbool_t op2) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svnand,_b,_z,)(pg, op1, op2);
-}
diff --git a/clang/test/CodeGen/AArch64/sve/nand.c b/clang/test/CodeGen/AArch64/sve/nand.c
new file mode 100644
index 00000000000000..80ca2b70a5e123
--- /dev/null
+++ b/clang/test/CodeGen/AArch64/sve/nand.c
@@ -0,0 +1,49 @@
+// REQUIRES: aarch64-registered-target
+
+// DEFINE: %{optimize} = opt -passes=mem2reg -S
+
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -fclangir -emit-cir -disable-O0-optnone -o - %s | FileCheck %s --check-prefixes=C,CIR %}
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-cir -disable-O0-optnone -o - %s | FileCheck %s --check-prefixes=C,CIR %}
+
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -fclangir -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM %}
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM %}
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-llvm -disable-O0-optnone -o - -x c++ %s | %{optimize} | FileCheck %s --check-prefixes=CPP,LLVM %}
+
+// RUN: %clang_cc1_cg_arm64_sve -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM
+// RUN: %clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM
+// RUN: %clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -emit-llvm -disable-O0-optnone -o - -x c++ %s | %{optimize} | FileCheck %s --check-prefixes=CPP,LLVM
+
+// RUN: %clang_cc1_cg_arm64_sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
+
+//=============================================================================
+// NOTES
+//
+// Tests for SVE NAND intrinsics
+//=============================================================================
+
+#include <arm_sve.h>
+
+#if defined __ARM_FEATURE_SME
+#define MODE_ATTR __arm_streaming
+#else
+#define MODE_ATTR
+#endif
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+// C-LABEL: @test_svnand_b_z(
+// CPP-LABEL: @_Z15test_svnand_b_zu10__SVBool_tS_S_(
+svbool_t test_svnand_b_z(svbool_t pg, svbool_t op1, svbool_t op2) MODE_ATTR
+{
+// CIR: cir.call_llvm_intrinsic "aarch64.sve.nand.z" %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<[16] x !cir.int<u, 1>>, !cir.vector<[16] x !cir.int<u, 1>>, !cir.vector<[16] x !cir.int<u, 1>>) -> !cir.vector<[16] x !cir.int<u, 1>>
+
+// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP2:%.*]])
+// LLVM: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.nand.z.nxv16i1(<vscale x 16 x i1> [[PG]], <vscale x 16 x i1> [[OP1]], <vscale x 16 x i1> [[OP2]])
+// LLVM: ret <vscale x 16 x i1> [[TMP0]]
+ return SVE_ACLE_FUNC(svnand,_b,_z,)(pg, op1, op2);
+}
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