[clang] [llvm] [AMDGPU] Hardwire SRAMECC ON for gfx12.5 (PR #232985)
via cfe-commits
cfe-commits at lists.llvm.org
Fri Oct 16 16:48:21 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clang-driver
Author: Chinmay Deshpande (chinmaydd)
<details>
<summary>Changes</summary>
---
Patch is 146.99 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/232985.diff
9 Files Affected:
- (modified) clang/test/Driver/amdgpu-xnack-sramecc-flags.c (+10-5)
- (modified) llvm/docs/AMDGPUUsage.rst (+8-8)
- (modified) llvm/lib/Target/AMDGPU/GCNFeatures.td (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/atomic-load-store-16-sramecc.ll (-64)
- (modified) llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll (+7)
- (modified) llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll (-1555)
- (modified) llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-any.ll (+4-3)
- (modified) llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-disabled.ll (+4)
- (modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+20-3)
``````````diff
diff --git a/clang/test/Driver/amdgpu-xnack-sramecc-flags.c b/clang/test/Driver/amdgpu-xnack-sramecc-flags.c
index 0936234903f0d..169c38b4e9807 100644
--- a/clang/test/Driver/amdgpu-xnack-sramecc-flags.c
+++ b/clang/test/Driver/amdgpu-xnack-sramecc-flags.c
@@ -17,11 +17,16 @@
// RUN: FileCheck -check-prefix=SRAMECC-OFF %s
// SRAMECC-OFF: "-mno-sramecc"
-// SRAMECC remains selectable on gfx12.5 even though XNACK is hardwired on.
-// RUN: %clang -### --target=amdgcn-amd-amdhsa -mcpu=gfx1250:sramecc+ %s 2>&1 | \
-// RUN: FileCheck -check-prefix=SRAMECC-ON %s
-// RUN: %clang -### --target=amdgcn-amd-amdhsa -mcpu=gfx1250:sramecc- %s 2>&1 | \
-// RUN: FileCheck -check-prefix=SRAMECC-OFF %s
+// SRAMECC is hardwired on for gfx12.5, so the modifier is rejected.
+// RUN: not %clang -### --target=amdgcn-amd-amdhsa -mcpu=gfx1250:sramecc+ %s 2>&1 | \
+// RUN: FileCheck -check-prefix=GFX1250-SRAMECC-ON %s
+// GFX1250-SRAMECC-ON: error: invalid target ID 'gfx1250:sramecc+'
+// RUN: not %clang -### --target=amdgcn-amd-amdhsa -mcpu=gfx1251:sramecc- %s 2>&1 | \
+// RUN: FileCheck -check-prefix=GFX1251-SRAMECC-OFF %s
+// GFX1251-SRAMECC-OFF: error: invalid target ID 'gfx1251:sramecc-'
+// RUN: not %clang -### --target=amdgcn-amd-amdhsa -mcpu=gfx12-5-generic:sramecc- %s 2>&1 | \
+// RUN: FileCheck -check-prefix=GFX12-5-GENERIC-SRAMECC-OFF %s
+// GFX12-5-GENERIC-SRAMECC-OFF: error: invalid target ID 'gfx12-5-generic:sramecc-'
// Test that target ID takes precedence over explicit flags
// RUN: %clang -### --target=amdgcn-amd-amdhsa -mcpu=gfx90a:xnack+ -mno-xnack %s 2>&1 | \
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 46e2bebb060b7..88b9874bf868d 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -670,8 +670,8 @@ Every processor supports every OS ABI (see :ref:`amdgpu-os`) with the following
work-item
IDs
- ``gfx1250-strict`` ``amdgpu12.50s`` dGPU - sramecc - Architected *TBA*
- - xnack flat
+ ``gfx1250-strict`` ``amdgpu12.50s`` dGPU - xnack - Architected *TBA*
+ flat
scratch .. TODO::
- Packed
work-item Add product
@@ -682,8 +682,8 @@ Every processor supports every OS ABI (see :ref:`amdgpu-os`) with the following
- Workgroup
Clusters
- ``gfx1250`` ``amdgpu12.50`` APU - sramecc - Architected *TBA*
- - xnack flat
+ ``gfx1250`` ``amdgpu12.50`` APU - xnack - Architected *TBA*
+ flat
scratch .. TODO::
- Packed
work-item Add product
@@ -694,8 +694,8 @@ Every processor supports every OS ABI (see :ref:`amdgpu-os`) with the following
- Workgroup
Clusters
- ``gfx1251`` ``amdgpu12.51`` APU - sramecc - Architected *TBA*
- - xnack flat
+ ``gfx1251`` ``amdgpu12.51`` APU - xnack - Architected *TBA*
+ flat
scratch .. TODO::
- Packed
work-item Add product
@@ -831,8 +831,8 @@ Generic processor code objects are versioned. See :ref:`amdgpu-generic-processor
work-item
IDs
- ``gfx12-5-generic`` ``amdgpu12.5`` - ``gfx1250`` - sramecc - Architected Functionally equivalent to
- - ``gfx1251`` - xnack flat scratch gfx1250.
+ ``gfx12-5-generic`` ``amdgpu12.5`` - ``gfx1250`` - xnack - Architected Functionally equivalent to
+ - ``gfx1251`` flat scratch gfx1250.
- Packed
work-item
IDs
diff --git a/llvm/lib/Target/AMDGPU/GCNFeatures.td b/llvm/lib/Target/AMDGPU/GCNFeatures.td
index 09083dcf604d6..59cda13cb2cf6 100644
--- a/llvm/lib/Target/AMDGPU/GCNFeatures.td
+++ b/llvm/lib/Target/AMDGPU/GCNFeatures.td
@@ -2523,7 +2523,7 @@ def FeatureISAVersion12_50_Common : FeatureSet<
FeaturePrngInst,
FeaturePermlane16Swap,
FeatureAshrPkInsts,
- FeatureSRAMECCOnOffModes,
+ FeatureSupportsSRAMECC,
FeatureMaxHardClauseLength63,
FeatureWaitXcnt,
FeatureAsynccnt,
diff --git a/llvm/test/CodeGen/AMDGPU/atomic-load-store-16-sramecc.ll b/llvm/test/CodeGen/AMDGPU/atomic-load-store-16-sramecc.ll
index 8512cd50990e3..e1ea520f5f28c 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic-load-store-16-sramecc.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic-load-store-16-sramecc.ll
@@ -1,18 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: sed 's/SRAMECC/0/' %s | llc -mtriple=amdgpu12.50 -mattr=+real-true16 | FileCheck -check-prefix=SRAMECC-OFF %s
; RUN: sed 's/SRAMECC/1/' %s | llc -mtriple=amdgpu12.50 -mattr=+real-true16 | FileCheck -check-prefix=SRAMECC-ON %s
-; RUN: sed 's/SRAMECC/0/' %s | llc -global-isel -mtriple=amdgpu12.50 -mattr=+real-true16 | FileCheck -check-prefix=SRAMECC-OFF %s
; RUN: sed 's/SRAMECC/1/' %s | llc -global-isel -mtriple=amdgpu12.50 -mattr=+real-true16 | FileCheck -check-prefix=SRAMECC-ON %s
define i16 @atomic_load_i16_global(ptr addrspace(1) %p) {
-; SRAMECC-OFF-LABEL: atomic_load_i16_global:
-; SRAMECC-OFF: ; %bb.0:
-; SRAMECC-OFF-NEXT: s_wait_loadcnt_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_wait_kmcnt 0x0
-; SRAMECC-OFF-NEXT: global_load_d16_b16 v0, v[0:1], off scope:SCOPE_SYS
-; SRAMECC-OFF-NEXT: s_wait_loadcnt 0x0
-; SRAMECC-OFF-NEXT: s_set_pc_i64 s[30:31]
-;
; SRAMECC-ON-LABEL: atomic_load_i16_global:
; SRAMECC-ON: ; %bb.0:
; SRAMECC-ON-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -25,14 +15,6 @@ define i16 @atomic_load_i16_global(ptr addrspace(1) %p) {
}
define half @atomic_load_f16_global(ptr addrspace(1) %p) {
-; SRAMECC-OFF-LABEL: atomic_load_f16_global:
-; SRAMECC-OFF: ; %bb.0:
-; SRAMECC-OFF-NEXT: s_wait_loadcnt_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_wait_kmcnt 0x0
-; SRAMECC-OFF-NEXT: global_load_d16_b16 v0, v[0:1], off scope:SCOPE_SYS
-; SRAMECC-OFF-NEXT: s_wait_loadcnt 0x0
-; SRAMECC-OFF-NEXT: s_set_pc_i64 s[30:31]
-;
; SRAMECC-ON-LABEL: atomic_load_f16_global:
; SRAMECC-ON: ; %bb.0:
; SRAMECC-ON-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -45,14 +27,6 @@ define half @atomic_load_f16_global(ptr addrspace(1) %p) {
}
define bfloat @atomic_load_bf16_global(ptr addrspace(1) %p) {
-; SRAMECC-OFF-LABEL: atomic_load_bf16_global:
-; SRAMECC-OFF: ; %bb.0:
-; SRAMECC-OFF-NEXT: s_wait_loadcnt_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_wait_kmcnt 0x0
-; SRAMECC-OFF-NEXT: global_load_d16_b16 v0, v[0:1], off scope:SCOPE_SYS
-; SRAMECC-OFF-NEXT: s_wait_loadcnt 0x0
-; SRAMECC-OFF-NEXT: s_set_pc_i64 s[30:31]
-;
; SRAMECC-ON-LABEL: atomic_load_bf16_global:
; SRAMECC-ON: ; %bb.0:
; SRAMECC-ON-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -65,14 +39,6 @@ define bfloat @atomic_load_bf16_global(ptr addrspace(1) %p) {
}
define i16 @atomic_load_i16_flat(ptr %p) {
-; SRAMECC-OFF-LABEL: atomic_load_i16_flat:
-; SRAMECC-OFF: ; %bb.0:
-; SRAMECC-OFF-NEXT: s_wait_loadcnt_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_wait_kmcnt 0x0
-; SRAMECC-OFF-NEXT: flat_load_d16_b16 v0, v[0:1] scope:SCOPE_SYS
-; SRAMECC-OFF-NEXT: s_wait_loadcnt_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_set_pc_i64 s[30:31]
-;
; SRAMECC-ON-LABEL: atomic_load_i16_flat:
; SRAMECC-ON: ; %bb.0:
; SRAMECC-ON-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -85,14 +51,6 @@ define i16 @atomic_load_i16_flat(ptr %p) {
}
define half @atomic_load_f16_local(ptr addrspace(3) %p) {
-; SRAMECC-OFF-LABEL: atomic_load_f16_local:
-; SRAMECC-OFF: ; %bb.0:
-; SRAMECC-OFF-NEXT: s_wait_loadcnt_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_wait_kmcnt 0x0
-; SRAMECC-OFF-NEXT: ds_load_u16_d16 v0, v0
-; SRAMECC-OFF-NEXT: s_wait_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_set_pc_i64 s[30:31]
-;
; SRAMECC-ON-LABEL: atomic_load_f16_local:
; SRAMECC-ON: ; %bb.0:
; SRAMECC-ON-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -105,13 +63,6 @@ define half @atomic_load_f16_local(ptr addrspace(3) %p) {
}
define void @atomic_store_i16_global(ptr addrspace(1) %p, i16 %v) {
-; SRAMECC-OFF-LABEL: atomic_store_i16_global:
-; SRAMECC-OFF: ; %bb.0:
-; SRAMECC-OFF-NEXT: s_wait_loadcnt_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_wait_kmcnt 0x0
-; SRAMECC-OFF-NEXT: global_store_b16 v[0:1], v2, off scope:SCOPE_SYS
-; SRAMECC-OFF-NEXT: s_set_pc_i64 s[30:31]
-;
; SRAMECC-ON-LABEL: atomic_store_i16_global:
; SRAMECC-ON: ; %bb.0:
; SRAMECC-ON-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -123,13 +74,6 @@ define void @atomic_store_i16_global(ptr addrspace(1) %p, i16 %v) {
}
define void @atomic_store_f16_global(ptr addrspace(1) %p, half %v) {
-; SRAMECC-OFF-LABEL: atomic_store_f16_global:
-; SRAMECC-OFF: ; %bb.0:
-; SRAMECC-OFF-NEXT: s_wait_loadcnt_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_wait_kmcnt 0x0
-; SRAMECC-OFF-NEXT: global_store_b16 v[0:1], v2, off scope:SCOPE_SYS
-; SRAMECC-OFF-NEXT: s_set_pc_i64 s[30:31]
-;
; SRAMECC-ON-LABEL: atomic_store_f16_global:
; SRAMECC-ON: ; %bb.0:
; SRAMECC-ON-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -141,14 +85,6 @@ define void @atomic_store_f16_global(ptr addrspace(1) %p, half %v) {
}
define void @atomic_store_bf16_local(ptr addrspace(3) %p, bfloat %v) {
-; SRAMECC-OFF-LABEL: atomic_store_bf16_local:
-; SRAMECC-OFF: ; %bb.0:
-; SRAMECC-OFF-NEXT: s_wait_loadcnt_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_wait_kmcnt 0x0
-; SRAMECC-OFF-NEXT: ds_store_b16 v0, v1
-; SRAMECC-OFF-NEXT: s_wait_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_set_pc_i64 s[30:31]
-;
; SRAMECC-ON-LABEL: atomic_store_bf16_local:
; SRAMECC-ON: ; %bb.0:
; SRAMECC-ON-NEXT: s_wait_loadcnt_dscnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll b/llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
index 2b7a0363f1755..3b621eb97fb89 100644
--- a/llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
+++ b/llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
@@ -17,6 +17,7 @@
; RUN: llc -filetype=obj -mtriple=amdgpu12.50 < %s | llvm-readobj --file-header - | FileCheck --check-prefix=SRAM-ECC-GFX1250 %s
; RUN: llc -filetype=obj -mtriple=amdgpu12.50 -amdgpu-sramecc=1 < %s | llvm-readobj --file-header - | FileCheck --check-prefix=SRAM-ECC-GFX1250 %s
+; RUN: llc -filetype=obj -mtriple=amdgpu12.50-amd-amdhsa -amdgpu-sramecc=0 < %s | llvm-readobj --file-header - | FileCheck --check-prefix=HSA-GFX1250 %s
; RUN: llc -filetype=obj -mtriple=amdgpu12.51 < %s | llvm-readobj --file-header - | FileCheck --check-prefix=SRAM-ECC-GFX1251 %s
; RUN: llc -filetype=obj -mtriple=amdgpu12.51 -amdgpu-sramecc=1 < %s | llvm-readobj --file-header - | FileCheck --check-prefix=SRAM-ECC-GFX1251 %s
@@ -66,6 +67,12 @@
; SRAM-ECC-GFX1250: EF_AMDGPU_MACH_AMDGCN_GFX1250 (0x49)
; SRAM-ECC-GFX1250: ]
+; Hardwired-on SRAMECC is not an ELF mode; -amdgpu-sramecc=0 is ignored.
+; HSA-GFX1250: Flags [
+; HSA-GFX1250-NEXT: EF_AMDGPU_FEATURE_XNACK_ANY_V4 (0x100)
+; HSA-GFX1250-NEXT: EF_AMDGPU_MACH_AMDGCN_GFX1250 (0x49)
+; HSA-GFX1250-NEXT: ]
+
; SRAM-ECC-GFX1251: Flags [
; SRAM-ECC-GFX1251: EF_AMDGPU_FEATURE_SRAMECC_V3 (0x200)
; SRAM-ECC-GFX1251: EF_AMDGPU_MACH_AMDGCN_GFX1251 (0x5A)
diff --git a/llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll b/llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
index d0d95d19189c3..eae0e325e22e3 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
@@ -4,9 +4,6 @@
; RUN: llc -global-isel=0 -mtriple=amdgpu12.50-mesa-mesa3d -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG,GFX1250-SDAG-TRUE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgpu12.50-mesa-mesa3d -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL,GFX1250-GISEL-TRUE16 %s
-; RUN: llc -mtriple=amdgpu12.50-mesa-mesa3d -mattr=+real-true16 --amdgpu-sramecc=false < %s | FileCheck -check-prefixes=GFX1250,GFX1250-NOECC,GFX1250-NOECC-SDAG-TRUE16 %s
-; RUN: llc -mtriple=amdgpu12.50-mesa-mesa3d -mattr=-real-true16 --amdgpu-sramecc=false < %s | FileCheck -check-prefixes=GFX1250,GFX1250-NOECC,GFX1250-NOECC-SDAG-FAKE16 %s
-
; Test using saddr addressing mode of flat_*load_* instructions.
; --------------------------------------------------------------------------------
@@ -153,19 +150,6 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0xFFFFFFFF(ptr inreg %sbase) {
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_0xFFFFFFFF:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_add_co_u32 v0, s0, 0xff800000, s2
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_co_ci_u32_e64 v1, null, 0, s3, s0
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1] offset:8388607
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 4294967295
%load = load i8, ptr %gep0
%zext = zext i8 %load to i32
@@ -199,18 +183,6 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0x100000000(ptr inreg %sbase)
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_0x100000000:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NOECC-NEXT: s_add_co_i32 s3, s3, 1
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v0, s[2:3]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 4294967296
%load = load i8, ptr %gep0
%zext = zext i8 %load to i32
@@ -245,19 +217,6 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0x100000001(ptr inreg %sbase)
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_0x100000001:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_add_co_u32 v0, s0, 0, s2
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_co_ci_u32_e64 v1, null, 1, s3, s0
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1] offset:1
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 4294967297
%load = load i8, ptr %gep0
%zext = zext i8 %load to i32
@@ -292,19 +251,6 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0x100000FFF(ptr inreg %sbase)
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_0x100000FFF:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_add_co_u32 v0, s0, 0, s2
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_co_ci_u32_e64 v1, null, 1, s3, s0
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1] offset:4095
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 4294971391
%load = load i8, ptr %gep0
%zext = zext i8 %load to i32
@@ -339,19 +285,6 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0x100001000(ptr inreg %sbase)
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_0x100001000:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_add_co_u32 v0, s0, 0, s2
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_co_ci_u32_e64 v1, null, 1, s3, s0
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1] offset:4096
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 4294971392
%load = load i8, ptr %gep0
%zext = zext i8 %load to i32
@@ -386,19 +319,6 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_neg0xFFFFFFFF(ptr inreg %sbase
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_neg0xFFFFFFFF:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/232985
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