[clang] [llvm] [AMDGPU] Hardwire SRAMECC ON for gfx12.5 (PR #232985)
Chinmay Deshpande via cfe-commits
cfe-commits at lists.llvm.org
Fri Oct 16 16:47:46 PDT 2026
https://github.com/chinmaydd created https://github.com/llvm/llvm-project/pull/232985
None
>From 8b8e1c3c39ff205dda6b3d90a5a8c90f96c6b30f Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Fri, 16 Oct 2026 19:40:23 -0400
Subject: [PATCH] [AMDGPU] Hardwire SRAMECC on for gfx12.5
ECC on gfx12.5 cannot be disabled, so sramecc is not a selectable
target ID feature. Accepting sramecc- produced code relying on D16
loads preserving unused bits, which the loader then rejects.
Change-Id: I331b5d42e80cc6de8d084047f2b84fc2ef9349cb
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
---
.../test/Driver/amdgpu-xnack-sramecc-flags.c | 15 +-
llvm/docs/AMDGPUUsage.rst | 16 +-
llvm/lib/Target/AMDGPU/GCNFeatures.td | 2 +-
.../AMDGPU/atomic-load-store-16-sramecc.ll | 64 -
.../AMDGPU/elf-header-flags-sramecc.ll | 7 +
llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll | 1555 -----------------
.../AMDGPU/sramecc-subtarget-feature-any.ll | 7 +-
.../sramecc-subtarget-feature-disabled.ll | 4 +
.../TargetParser/TargetParserTest.cpp | 23 +-
9 files changed, 54 insertions(+), 1639 deletions(-)
diff --git a/clang/test/Driver/amdgpu-xnack-sramecc-flags.c b/clang/test/Driver/amdgpu-xnack-sramecc-flags.c
index 0936234903f0d..169c38b4e9807 100644
--- a/clang/test/Driver/amdgpu-xnack-sramecc-flags.c
+++ b/clang/test/Driver/amdgpu-xnack-sramecc-flags.c
@@ -17,11 +17,16 @@
// RUN: FileCheck -check-prefix=SRAMECC-OFF %s
// SRAMECC-OFF: "-mno-sramecc"
-// SRAMECC remains selectable on gfx12.5 even though XNACK is hardwired on.
-// RUN: %clang -### --target=amdgcn-amd-amdhsa -mcpu=gfx1250:sramecc+ %s 2>&1 | \
-// RUN: FileCheck -check-prefix=SRAMECC-ON %s
-// RUN: %clang -### --target=amdgcn-amd-amdhsa -mcpu=gfx1250:sramecc- %s 2>&1 | \
-// RUN: FileCheck -check-prefix=SRAMECC-OFF %s
+// SRAMECC is hardwired on for gfx12.5, so the modifier is rejected.
+// RUN: not %clang -### --target=amdgcn-amd-amdhsa -mcpu=gfx1250:sramecc+ %s 2>&1 | \
+// RUN: FileCheck -check-prefix=GFX1250-SRAMECC-ON %s
+// GFX1250-SRAMECC-ON: error: invalid target ID 'gfx1250:sramecc+'
+// RUN: not %clang -### --target=amdgcn-amd-amdhsa -mcpu=gfx1251:sramecc- %s 2>&1 | \
+// RUN: FileCheck -check-prefix=GFX1251-SRAMECC-OFF %s
+// GFX1251-SRAMECC-OFF: error: invalid target ID 'gfx1251:sramecc-'
+// RUN: not %clang -### --target=amdgcn-amd-amdhsa -mcpu=gfx12-5-generic:sramecc- %s 2>&1 | \
+// RUN: FileCheck -check-prefix=GFX12-5-GENERIC-SRAMECC-OFF %s
+// GFX12-5-GENERIC-SRAMECC-OFF: error: invalid target ID 'gfx12-5-generic:sramecc-'
// Test that target ID takes precedence over explicit flags
// RUN: %clang -### --target=amdgcn-amd-amdhsa -mcpu=gfx90a:xnack+ -mno-xnack %s 2>&1 | \
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 46e2bebb060b7..88b9874bf868d 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -670,8 +670,8 @@ Every processor supports every OS ABI (see :ref:`amdgpu-os`) with the following
work-item
IDs
- ``gfx1250-strict`` ``amdgpu12.50s`` dGPU - sramecc - Architected *TBA*
- - xnack flat
+ ``gfx1250-strict`` ``amdgpu12.50s`` dGPU - xnack - Architected *TBA*
+ flat
scratch .. TODO::
- Packed
work-item Add product
@@ -682,8 +682,8 @@ Every processor supports every OS ABI (see :ref:`amdgpu-os`) with the following
- Workgroup
Clusters
- ``gfx1250`` ``amdgpu12.50`` APU - sramecc - Architected *TBA*
- - xnack flat
+ ``gfx1250`` ``amdgpu12.50`` APU - xnack - Architected *TBA*
+ flat
scratch .. TODO::
- Packed
work-item Add product
@@ -694,8 +694,8 @@ Every processor supports every OS ABI (see :ref:`amdgpu-os`) with the following
- Workgroup
Clusters
- ``gfx1251`` ``amdgpu12.51`` APU - sramecc - Architected *TBA*
- - xnack flat
+ ``gfx1251`` ``amdgpu12.51`` APU - xnack - Architected *TBA*
+ flat
scratch .. TODO::
- Packed
work-item Add product
@@ -831,8 +831,8 @@ Generic processor code objects are versioned. See :ref:`amdgpu-generic-processor
work-item
IDs
- ``gfx12-5-generic`` ``amdgpu12.5`` - ``gfx1250`` - sramecc - Architected Functionally equivalent to
- - ``gfx1251`` - xnack flat scratch gfx1250.
+ ``gfx12-5-generic`` ``amdgpu12.5`` - ``gfx1250`` - xnack - Architected Functionally equivalent to
+ - ``gfx1251`` flat scratch gfx1250.
- Packed
work-item
IDs
diff --git a/llvm/lib/Target/AMDGPU/GCNFeatures.td b/llvm/lib/Target/AMDGPU/GCNFeatures.td
index 09083dcf604d6..59cda13cb2cf6 100644
--- a/llvm/lib/Target/AMDGPU/GCNFeatures.td
+++ b/llvm/lib/Target/AMDGPU/GCNFeatures.td
@@ -2523,7 +2523,7 @@ def FeatureISAVersion12_50_Common : FeatureSet<
FeaturePrngInst,
FeaturePermlane16Swap,
FeatureAshrPkInsts,
- FeatureSRAMECCOnOffModes,
+ FeatureSupportsSRAMECC,
FeatureMaxHardClauseLength63,
FeatureWaitXcnt,
FeatureAsynccnt,
diff --git a/llvm/test/CodeGen/AMDGPU/atomic-load-store-16-sramecc.ll b/llvm/test/CodeGen/AMDGPU/atomic-load-store-16-sramecc.ll
index 8512cd50990e3..e1ea520f5f28c 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic-load-store-16-sramecc.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic-load-store-16-sramecc.ll
@@ -1,18 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: sed 's/SRAMECC/0/' %s | llc -mtriple=amdgpu12.50 -mattr=+real-true16 | FileCheck -check-prefix=SRAMECC-OFF %s
; RUN: sed 's/SRAMECC/1/' %s | llc -mtriple=amdgpu12.50 -mattr=+real-true16 | FileCheck -check-prefix=SRAMECC-ON %s
-; RUN: sed 's/SRAMECC/0/' %s | llc -global-isel -mtriple=amdgpu12.50 -mattr=+real-true16 | FileCheck -check-prefix=SRAMECC-OFF %s
; RUN: sed 's/SRAMECC/1/' %s | llc -global-isel -mtriple=amdgpu12.50 -mattr=+real-true16 | FileCheck -check-prefix=SRAMECC-ON %s
define i16 @atomic_load_i16_global(ptr addrspace(1) %p) {
-; SRAMECC-OFF-LABEL: atomic_load_i16_global:
-; SRAMECC-OFF: ; %bb.0:
-; SRAMECC-OFF-NEXT: s_wait_loadcnt_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_wait_kmcnt 0x0
-; SRAMECC-OFF-NEXT: global_load_d16_b16 v0, v[0:1], off scope:SCOPE_SYS
-; SRAMECC-OFF-NEXT: s_wait_loadcnt 0x0
-; SRAMECC-OFF-NEXT: s_set_pc_i64 s[30:31]
-;
; SRAMECC-ON-LABEL: atomic_load_i16_global:
; SRAMECC-ON: ; %bb.0:
; SRAMECC-ON-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -25,14 +15,6 @@ define i16 @atomic_load_i16_global(ptr addrspace(1) %p) {
}
define half @atomic_load_f16_global(ptr addrspace(1) %p) {
-; SRAMECC-OFF-LABEL: atomic_load_f16_global:
-; SRAMECC-OFF: ; %bb.0:
-; SRAMECC-OFF-NEXT: s_wait_loadcnt_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_wait_kmcnt 0x0
-; SRAMECC-OFF-NEXT: global_load_d16_b16 v0, v[0:1], off scope:SCOPE_SYS
-; SRAMECC-OFF-NEXT: s_wait_loadcnt 0x0
-; SRAMECC-OFF-NEXT: s_set_pc_i64 s[30:31]
-;
; SRAMECC-ON-LABEL: atomic_load_f16_global:
; SRAMECC-ON: ; %bb.0:
; SRAMECC-ON-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -45,14 +27,6 @@ define half @atomic_load_f16_global(ptr addrspace(1) %p) {
}
define bfloat @atomic_load_bf16_global(ptr addrspace(1) %p) {
-; SRAMECC-OFF-LABEL: atomic_load_bf16_global:
-; SRAMECC-OFF: ; %bb.0:
-; SRAMECC-OFF-NEXT: s_wait_loadcnt_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_wait_kmcnt 0x0
-; SRAMECC-OFF-NEXT: global_load_d16_b16 v0, v[0:1], off scope:SCOPE_SYS
-; SRAMECC-OFF-NEXT: s_wait_loadcnt 0x0
-; SRAMECC-OFF-NEXT: s_set_pc_i64 s[30:31]
-;
; SRAMECC-ON-LABEL: atomic_load_bf16_global:
; SRAMECC-ON: ; %bb.0:
; SRAMECC-ON-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -65,14 +39,6 @@ define bfloat @atomic_load_bf16_global(ptr addrspace(1) %p) {
}
define i16 @atomic_load_i16_flat(ptr %p) {
-; SRAMECC-OFF-LABEL: atomic_load_i16_flat:
-; SRAMECC-OFF: ; %bb.0:
-; SRAMECC-OFF-NEXT: s_wait_loadcnt_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_wait_kmcnt 0x0
-; SRAMECC-OFF-NEXT: flat_load_d16_b16 v0, v[0:1] scope:SCOPE_SYS
-; SRAMECC-OFF-NEXT: s_wait_loadcnt_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_set_pc_i64 s[30:31]
-;
; SRAMECC-ON-LABEL: atomic_load_i16_flat:
; SRAMECC-ON: ; %bb.0:
; SRAMECC-ON-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -85,14 +51,6 @@ define i16 @atomic_load_i16_flat(ptr %p) {
}
define half @atomic_load_f16_local(ptr addrspace(3) %p) {
-; SRAMECC-OFF-LABEL: atomic_load_f16_local:
-; SRAMECC-OFF: ; %bb.0:
-; SRAMECC-OFF-NEXT: s_wait_loadcnt_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_wait_kmcnt 0x0
-; SRAMECC-OFF-NEXT: ds_load_u16_d16 v0, v0
-; SRAMECC-OFF-NEXT: s_wait_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_set_pc_i64 s[30:31]
-;
; SRAMECC-ON-LABEL: atomic_load_f16_local:
; SRAMECC-ON: ; %bb.0:
; SRAMECC-ON-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -105,13 +63,6 @@ define half @atomic_load_f16_local(ptr addrspace(3) %p) {
}
define void @atomic_store_i16_global(ptr addrspace(1) %p, i16 %v) {
-; SRAMECC-OFF-LABEL: atomic_store_i16_global:
-; SRAMECC-OFF: ; %bb.0:
-; SRAMECC-OFF-NEXT: s_wait_loadcnt_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_wait_kmcnt 0x0
-; SRAMECC-OFF-NEXT: global_store_b16 v[0:1], v2, off scope:SCOPE_SYS
-; SRAMECC-OFF-NEXT: s_set_pc_i64 s[30:31]
-;
; SRAMECC-ON-LABEL: atomic_store_i16_global:
; SRAMECC-ON: ; %bb.0:
; SRAMECC-ON-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -123,13 +74,6 @@ define void @atomic_store_i16_global(ptr addrspace(1) %p, i16 %v) {
}
define void @atomic_store_f16_global(ptr addrspace(1) %p, half %v) {
-; SRAMECC-OFF-LABEL: atomic_store_f16_global:
-; SRAMECC-OFF: ; %bb.0:
-; SRAMECC-OFF-NEXT: s_wait_loadcnt_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_wait_kmcnt 0x0
-; SRAMECC-OFF-NEXT: global_store_b16 v[0:1], v2, off scope:SCOPE_SYS
-; SRAMECC-OFF-NEXT: s_set_pc_i64 s[30:31]
-;
; SRAMECC-ON-LABEL: atomic_store_f16_global:
; SRAMECC-ON: ; %bb.0:
; SRAMECC-ON-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -141,14 +85,6 @@ define void @atomic_store_f16_global(ptr addrspace(1) %p, half %v) {
}
define void @atomic_store_bf16_local(ptr addrspace(3) %p, bfloat %v) {
-; SRAMECC-OFF-LABEL: atomic_store_bf16_local:
-; SRAMECC-OFF: ; %bb.0:
-; SRAMECC-OFF-NEXT: s_wait_loadcnt_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_wait_kmcnt 0x0
-; SRAMECC-OFF-NEXT: ds_store_b16 v0, v1
-; SRAMECC-OFF-NEXT: s_wait_dscnt 0x0
-; SRAMECC-OFF-NEXT: s_set_pc_i64 s[30:31]
-;
; SRAMECC-ON-LABEL: atomic_store_bf16_local:
; SRAMECC-ON: ; %bb.0:
; SRAMECC-ON-NEXT: s_wait_loadcnt_dscnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll b/llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
index 2b7a0363f1755..3b621eb97fb89 100644
--- a/llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
+++ b/llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
@@ -17,6 +17,7 @@
; RUN: llc -filetype=obj -mtriple=amdgpu12.50 < %s | llvm-readobj --file-header - | FileCheck --check-prefix=SRAM-ECC-GFX1250 %s
; RUN: llc -filetype=obj -mtriple=amdgpu12.50 -amdgpu-sramecc=1 < %s | llvm-readobj --file-header - | FileCheck --check-prefix=SRAM-ECC-GFX1250 %s
+; RUN: llc -filetype=obj -mtriple=amdgpu12.50-amd-amdhsa -amdgpu-sramecc=0 < %s | llvm-readobj --file-header - | FileCheck --check-prefix=HSA-GFX1250 %s
; RUN: llc -filetype=obj -mtriple=amdgpu12.51 < %s | llvm-readobj --file-header - | FileCheck --check-prefix=SRAM-ECC-GFX1251 %s
; RUN: llc -filetype=obj -mtriple=amdgpu12.51 -amdgpu-sramecc=1 < %s | llvm-readobj --file-header - | FileCheck --check-prefix=SRAM-ECC-GFX1251 %s
@@ -66,6 +67,12 @@
; SRAM-ECC-GFX1250: EF_AMDGPU_MACH_AMDGCN_GFX1250 (0x49)
; SRAM-ECC-GFX1250: ]
+; Hardwired-on SRAMECC is not an ELF mode; -amdgpu-sramecc=0 is ignored.
+; HSA-GFX1250: Flags [
+; HSA-GFX1250-NEXT: EF_AMDGPU_FEATURE_XNACK_ANY_V4 (0x100)
+; HSA-GFX1250-NEXT: EF_AMDGPU_MACH_AMDGCN_GFX1250 (0x49)
+; HSA-GFX1250-NEXT: ]
+
; SRAM-ECC-GFX1251: Flags [
; SRAM-ECC-GFX1251: EF_AMDGPU_FEATURE_SRAMECC_V3 (0x200)
; SRAM-ECC-GFX1251: EF_AMDGPU_MACH_AMDGCN_GFX1251 (0x5A)
diff --git a/llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll b/llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
index d0d95d19189c3..eae0e325e22e3 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
@@ -4,9 +4,6 @@
; RUN: llc -global-isel=0 -mtriple=amdgpu12.50-mesa-mesa3d -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG,GFX1250-SDAG-TRUE16 %s
; RUN: llc -global-isel=1 -mtriple=amdgpu12.50-mesa-mesa3d -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL,GFX1250-GISEL-TRUE16 %s
-; RUN: llc -mtriple=amdgpu12.50-mesa-mesa3d -mattr=+real-true16 --amdgpu-sramecc=false < %s | FileCheck -check-prefixes=GFX1250,GFX1250-NOECC,GFX1250-NOECC-SDAG-TRUE16 %s
-; RUN: llc -mtriple=amdgpu12.50-mesa-mesa3d -mattr=-real-true16 --amdgpu-sramecc=false < %s | FileCheck -check-prefixes=GFX1250,GFX1250-NOECC,GFX1250-NOECC-SDAG-FAKE16 %s
-
; Test using saddr addressing mode of flat_*load_* instructions.
; --------------------------------------------------------------------------------
@@ -153,19 +150,6 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0xFFFFFFFF(ptr inreg %sbase) {
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_0xFFFFFFFF:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_add_co_u32 v0, s0, 0xff800000, s2
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_co_ci_u32_e64 v1, null, 0, s3, s0
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1] offset:8388607
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 4294967295
%load = load i8, ptr %gep0
%zext = zext i8 %load to i32
@@ -199,18 +183,6 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0x100000000(ptr inreg %sbase)
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_0x100000000:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NOECC-NEXT: s_add_co_i32 s3, s3, 1
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v0, s[2:3]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 4294967296
%load = load i8, ptr %gep0
%zext = zext i8 %load to i32
@@ -245,19 +217,6 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0x100000001(ptr inreg %sbase)
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_0x100000001:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_add_co_u32 v0, s0, 0, s2
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_co_ci_u32_e64 v1, null, 1, s3, s0
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1] offset:1
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 4294967297
%load = load i8, ptr %gep0
%zext = zext i8 %load to i32
@@ -292,19 +251,6 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0x100000FFF(ptr inreg %sbase)
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_0x100000FFF:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_add_co_u32 v0, s0, 0, s2
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_co_ci_u32_e64 v1, null, 1, s3, s0
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1] offset:4095
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 4294971391
%load = load i8, ptr %gep0
%zext = zext i8 %load to i32
@@ -339,19 +285,6 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0x100001000(ptr inreg %sbase)
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_0x100001000:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_add_co_u32 v0, s0, 0, s2
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_co_ci_u32_e64 v1, null, 1, s3, s0
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1] offset:4096
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 4294971392
%load = load i8, ptr %gep0
%zext = zext i8 %load to i32
@@ -386,19 +319,6 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_neg0xFFFFFFFF(ptr inreg %sbase
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_neg0xFFFFFFFF:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_add_co_u32 v0, s0, 0x800000, s2
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s3, s0
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1] offset:-8388607
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 -4294967295
%load = load i8, ptr %gep0
%zext = zext i8 %load to i32
@@ -432,18 +352,6 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_neg0x100000000(ptr inreg %sbas
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_neg0x100000000:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NOECC-NEXT: s_add_co_i32 s3, s3, -1
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v0, s[2:3]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 -4294967296
%load = load i8, ptr %gep0
%zext = zext i8 %load to i32
@@ -478,19 +386,6 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_neg0x100000001(ptr inreg %sbas
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_neg0x100000001:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_add_co_u32 v0, s0, 0, s2
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s3, s0
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1] offset:-1
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 -4294967297
%load = load i8, ptr %gep0
%zext = zext i8 %load to i32
@@ -530,19 +425,6 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr(ptr inreg %sbase, i32 %voff
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_zext_vgpr:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i8, ptr %gep0
@@ -579,19 +461,6 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_offset_8388607(ptr inreg %s
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1] offset:8388607
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_zext_vgpr_offset_8388607:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1] offset:8388607
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 8388607
@@ -635,22 +504,6 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_offset_8388608(ptr inreg %s
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_zext_vgpr_offset_8388608:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 8388608
@@ -688,19 +541,6 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_offset_neg8388608(ptr inreg
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1] offset:-8388608
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_zext_vgpr_offset_neg8388608:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1] offset:-8388608
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -8388608
@@ -738,19 +578,6 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_offset_neg8388607(ptr inreg
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1] offset:-8388607
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_zext_vgpr_offset_neg8388607:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1] offset:-8388607
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -8388607
@@ -787,19 +614,6 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_offset_8388607_gep_order(pt
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1] offset:8388607
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_zext_vgpr_offset_8388607_gep_order:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1] offset:8388607
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 8388607
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 %zext.offset
@@ -837,19 +651,6 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_ptrtoint(ptr inreg %sbase,
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_zext_vgpr_ptrtoint:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%sbase.as.int = ptrtoint ptr %sbase to i64
%add = add i64 %sbase.as.int, %zext.offset
@@ -888,19 +689,6 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_ptrtoint_commute_add(ptr in
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_zext_vgpr_ptrtoint_commute_add:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%sbase.as.int = ptrtoint ptr %sbase to i64
%add = add i64 %zext.offset, %sbase.as.int
@@ -943,20 +731,6 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_of
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_offset0:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], 0x80, v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%sbase.as.int = ptrtoint ptr %sbase to i64
%add = add i64 %zext.offset, %sbase.as.int
@@ -1000,20 +774,6 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_of
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_offset1:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], 0x80, v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%sbase.as.int = ptrtoint ptr %sbase to i64
%add.immoffset = add i64 %sbase.as.int, 128
@@ -1062,20 +822,6 @@ define amdgpu_ps float @flat_load_saddr_uniform_ptr_in_vgprs(i32 %voffset) {
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_uniform_ptr_in_vgprs:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: ds_load_b64 v[2:3], v1
-; GFX1250-NOECC-NEXT: s_wait_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], v[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%sbase = load ptr, ptr addrspace(3) @ptr.in.lds
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -1116,20 +862,6 @@ define amdgpu_ps float @flat_load_saddr_uniform_ptr_in_vgprs_immoffset(i32 %voff
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1] offset:42
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_uniform_ptr_in_vgprs_immoffset:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: ds_load_b64 v[2:3], v1
-; GFX1250-NOECC-NEXT: s_wait_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], v[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1] offset:42
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%sbase = load ptr, ptr addrspace(3) @ptr.in.lds
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -1168,20 +900,6 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_uniform_offset(ptr inreg %sbase,
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v0, s[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_zext_uniform_offset:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NOECC-NEXT: s_mov_b32 s5, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NOECC-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[4:5]
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v0, s[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %soffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i8, ptr %gep0
@@ -1218,20 +936,6 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_uniform_offset_immoffset(ptr inr
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v0, s[0:1] offset:-24
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_zext_uniform_offset_immoffset:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NOECC-NEXT: s_mov_b32 s5, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NOECC-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[4:5]
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v0, s[0:1] offset:-24
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %soffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -24
@@ -1269,20 +973,6 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_sgpr_ptrtoint_commute_add(ptr in
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v0, s[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_zext_sgpr_ptrtoint_commute_add:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NOECC-NEXT: s_mov_b32 s5, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NOECC-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[2:3]
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v0, s[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %soffset to i64
%sbase.as.int = ptrtoint ptr %sbase to i64
%add = add i64 %zext.offset, %sbase.as.int
@@ -1321,20 +1011,6 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_sgpr_ptrtoint_commute_add_imm_of
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v0, s[0:1] offset:128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i8_zext_sgpr_ptrtoint_commute_add_imm_offset0:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NOECC-NEXT: s_mov_b32 s5, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NOECC-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[2:3]
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v0, s[0:1] offset:128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %soffset to i64
%sbase.as.int = ptrtoint ptr %sbase to i64
%add = add i64 %zext.offset, %sbase.as.int
@@ -1376,19 +1052,6 @@ define amdgpu_ps float @flat_load_i8_vgpr64_sgpr32(ptr %vbase, i32 inreg %soffse
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_i8_vgpr64_sgpr32:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: s_mov_b32 s3, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %soffset to i64
%gep0 = getelementptr inbounds i8, ptr %vbase, i64 %zext.offset
%load = load i8, ptr %gep0
@@ -1427,19 +1090,6 @@ define amdgpu_ps float @flat_load_i8_vgpr64_sgpr32_offset_8388607(ptr %vbase, i3
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1] offset:8388607
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_i8_vgpr64_sgpr32_offset_8388607:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: s_mov_b32 s3, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1] offset:8388607
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %soffset to i64
%gep0 = getelementptr inbounds i8, ptr %vbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 8388607
@@ -1508,21 +1158,6 @@ define amdgpu_ps float @flat_load_saddr_f32_natural_addressing_immoffset(ptr inr
; GFX1250-GISEL-NEXT: flat_load_b32 v0, v[2:3] offset:128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_f32_natural_addressing_immoffset:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: flat_load_b32 v2, v[0:1]
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v3, 0
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[2:3]
-; GFX1250-NOECC-NEXT: flat_load_b32 v0, v[2:3] offset:128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%voffset = load i32, ptr %voffset.ptr
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -1564,21 +1199,6 @@ define amdgpu_ps float @flat_load_f32_saddr_zext_vgpr_range(ptr inreg %sbase, pt
; GFX1250-GISEL-NEXT: flat_load_b32 v0, v[2:3]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_f32_saddr_zext_vgpr_range:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: flat_load_b32 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 2, v0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[2:3]
-; GFX1250-NOECC-NEXT: flat_load_b32 v0, v[2:3]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%voffset = load i32, ptr %voffset.ptr, !range !0, !noundef !{}
%zext.offset = zext i32 %voffset to i64
%gep = getelementptr inbounds float, ptr %sbase, i64 %zext.offset
@@ -1619,21 +1239,6 @@ define amdgpu_ps float @flat_load_f32_saddr_zext_vgpr_range_imm_offset(ptr inreg
; GFX1250-GISEL-NEXT: flat_load_b32 v0, v[2:3] offset:400
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_f32_saddr_zext_vgpr_range_imm_offset:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: flat_load_b32 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 2, v0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[2:3]
-; GFX1250-NOECC-NEXT: flat_load_b32 v0, v[2:3] offset:400
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%voffset = load i32, ptr %voffset.ptr, !range !0, !noundef !{}
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds float, ptr %sbase, i64 %zext.offset
@@ -1707,32 +1312,6 @@ define amdgpu_ps half @flat_load_saddr_i16(ptr inreg %sbase, i32 %voffset) {
; GFX1250-GISEL-TRUE16-NEXT: flat_load_u16 v0, v[2:3]
; GFX1250-GISEL-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-SDAG-TRUE16-LABEL: flat_load_saddr_i16:
-; GFX1250-NOECC-SDAG-TRUE16: ; %bb.0:
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_nop
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: flat_load_d16_b16 v0, v[0:1]
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-SDAG-FAKE16-LABEL: flat_load_saddr_i16:
-; GFX1250-NOECC-SDAG-FAKE16: ; %bb.0:
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_nop
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: flat_load_u16 v0, v[0:1]
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i16, ptr %gep0
@@ -1781,32 +1360,6 @@ define amdgpu_ps half @flat_load_saddr_i16_immneg128(ptr inreg %sbase, i32 %voff
; GFX1250-GISEL-TRUE16-NEXT: flat_load_u16 v0, v[2:3] offset:-128
; GFX1250-GISEL-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-SDAG-TRUE16-LABEL: flat_load_saddr_i16_immneg128:
-; GFX1250-NOECC-SDAG-TRUE16: ; %bb.0:
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_nop
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: flat_load_d16_b16 v0, v[0:1] offset:-128
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-SDAG-FAKE16-LABEL: flat_load_saddr_i16_immneg128:
-; GFX1250-NOECC-SDAG-FAKE16: ; %bb.0:
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_nop
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: flat_load_u16 v0, v[0:1] offset:-128
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -1842,32 +1395,6 @@ define amdgpu_ps half @flat_load_saddr_f16(ptr inreg %sbase, i32 %voffset) {
; GFX1250-GISEL-NEXT: flat_load_u16 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-SDAG-TRUE16-LABEL: flat_load_saddr_f16:
-; GFX1250-NOECC-SDAG-TRUE16: ; %bb.0:
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_nop
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: flat_load_d16_b16 v0, v[0:1]
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-SDAG-FAKE16-LABEL: flat_load_saddr_f16:
-; GFX1250-NOECC-SDAG-FAKE16: ; %bb.0:
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_nop
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: flat_load_u16 v0, v[0:1]
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load half, ptr %gep0
@@ -1901,32 +1428,6 @@ define amdgpu_ps half @flat_load_saddr_f16_immneg128(ptr inreg %sbase, i32 %voff
; GFX1250-GISEL-NEXT: flat_load_u16 v0, v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-SDAG-TRUE16-LABEL: flat_load_saddr_f16_immneg128:
-; GFX1250-NOECC-SDAG-TRUE16: ; %bb.0:
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_nop
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: flat_load_d16_b16 v0, v[0:1] offset:-128
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-SDAG-FAKE16-LABEL: flat_load_saddr_f16_immneg128:
-; GFX1250-NOECC-SDAG-FAKE16: ; %bb.0:
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_nop
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: flat_load_u16 v0, v[0:1] offset:-128
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -1961,19 +1462,6 @@ define amdgpu_ps float @flat_load_saddr_i32(ptr inreg %sbase, i32 %voffset) {
; GFX1250-GISEL-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i32:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b32 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i32, ptr %gep0
@@ -2008,19 +1496,6 @@ define amdgpu_ps float @flat_load_saddr_i32_immneg128(ptr inreg %sbase, i32 %vof
; GFX1250-GISEL-NEXT: flat_load_b32 v0, v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i32_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b32 v0, v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -2056,19 +1531,6 @@ define amdgpu_ps float @flat_load_saddr_f32(ptr inreg %sbase, i32 %voffset) {
; GFX1250-GISEL-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_f32:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b32 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load float, ptr %gep0
@@ -2102,19 +1564,6 @@ define amdgpu_ps float @flat_load_saddr_f32_immneg128(ptr inreg %sbase, i32 %vof
; GFX1250-GISEL-NEXT: flat_load_b32 v0, v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_f32_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b32 v0, v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -2149,19 +1598,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_v2i16(ptr inreg %sbase, i32 %voffse
; GFX1250-GISEL-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v2i16:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b32 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load <2 x i16>, ptr %gep0
@@ -2196,19 +1632,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_v2i16_immneg128(ptr inreg %sbase, i
; GFX1250-GISEL-NEXT: flat_load_b32 v0, v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v2i16_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b32 v0, v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -2244,19 +1667,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_v2f16(ptr inreg %sbase, i32 %voffse
; GFX1250-GISEL-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v2f16:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b32 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load <2 x half>, ptr %gep0
@@ -2290,19 +1700,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_v2f16_immneg128(ptr inreg %sbase, i
; GFX1250-GISEL-NEXT: flat_load_b32 v0, v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v2f16_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b32 v0, v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -2337,19 +1734,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_p3(ptr inreg %sbase, i32 %voffset)
; GFX1250-GISEL-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_p3:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b32 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load ptr addrspace(3), ptr %gep0
@@ -2385,19 +1769,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_p3_immneg128(ptr inreg %sbase, i32
; GFX1250-GISEL-NEXT: flat_load_b32 v0, v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_p3_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b32 v0, v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -2434,19 +1805,6 @@ define amdgpu_ps <2 x float> @flat_load_saddr_f64(ptr inreg %sbase, i32 %voffset
; GFX1250-GISEL-NEXT: flat_load_b64 v[0:1], v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_f64:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b64 v[0:1], v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load double, ptr %gep0
@@ -2481,19 +1839,6 @@ define amdgpu_ps <2 x float> @flat_load_saddr_f64_immneg128(ptr inreg %sbase, i3
; GFX1250-GISEL-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_f64_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -2529,19 +1874,6 @@ define amdgpu_ps <2 x float> @flat_load_saddr_i64(ptr inreg %sbase, i32 %voffset
; GFX1250-GISEL-NEXT: flat_load_b64 v[0:1], v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i64:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b64 v[0:1], v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i64, ptr %gep0
@@ -2576,19 +1908,6 @@ define amdgpu_ps <2 x float> @flat_load_saddr_i64_immneg128(ptr inreg %sbase, i3
; GFX1250-GISEL-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i64_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -2624,19 +1943,6 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v2f32(ptr inreg %sbase, i32 %voffs
; GFX1250-GISEL-NEXT: flat_load_b64 v[0:1], v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v2f32:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b64 v[0:1], v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load <2 x float>, ptr %gep0
@@ -2670,19 +1976,6 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v2f32_immneg128(ptr inreg %sbase,
; GFX1250-GISEL-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v2f32_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -2717,19 +2010,6 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v2i32(ptr inreg %sbase, i32 %voffs
; GFX1250-GISEL-NEXT: flat_load_b64 v[0:1], v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v2i32:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b64 v[0:1], v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load <2 x i32>, ptr %gep0
@@ -2764,19 +2044,6 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v2i32_immneg128(ptr inreg %sbase,
; GFX1250-GISEL-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v2i32_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -2812,19 +2079,6 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v4i16(ptr inreg %sbase, i32 %voffs
; GFX1250-GISEL-NEXT: flat_load_b64 v[0:1], v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v4i16:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b64 v[0:1], v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load <4 x i16>, ptr %gep0
@@ -2859,19 +2113,6 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v4i16_immneg128(ptr inreg %sbase,
; GFX1250-GISEL-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v4i16_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -2907,19 +2148,6 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v4f16(ptr inreg %sbase, i32 %voffs
; GFX1250-GISEL-NEXT: flat_load_b64 v[0:1], v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v4f16:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b64 v[0:1], v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load <4 x half>, ptr %gep0
@@ -2954,19 +2182,6 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v4f16_immneg128(ptr inreg %sbase,
; GFX1250-GISEL-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v4f16_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -3002,19 +2217,6 @@ define amdgpu_ps <2 x float> @flat_load_saddr_p1(ptr inreg %sbase, i32 %voffset)
; GFX1250-GISEL-NEXT: flat_load_b64 v[0:1], v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_p1:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b64 v[0:1], v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load ptr, ptr %gep0
@@ -3050,19 +2252,6 @@ define amdgpu_ps <2 x float> @flat_load_saddr_p1_immneg128(ptr inreg %sbase, i32
; GFX1250-GISEL-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_p1_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -3099,19 +2288,6 @@ define amdgpu_ps <3 x float> @flat_load_saddr_v3f32(ptr inreg %sbase, i32 %voffs
; GFX1250-GISEL-NEXT: flat_load_b96 v[0:2], v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v3f32:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b96 v[0:2], v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load <3 x float>, ptr %gep0
@@ -3145,19 +2321,6 @@ define amdgpu_ps <3 x float> @flat_load_saddr_v3f32_immneg128(ptr inreg %sbase,
; GFX1250-GISEL-NEXT: flat_load_b96 v[0:2], v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v3f32_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b96 v[0:2], v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -3192,19 +2355,6 @@ define amdgpu_ps <3 x float> @flat_load_saddr_v3i32(ptr inreg %sbase, i32 %voffs
; GFX1250-GISEL-NEXT: flat_load_b96 v[0:2], v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v3i32:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b96 v[0:2], v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load <3 x i32>, ptr %gep0
@@ -3239,19 +2389,6 @@ define amdgpu_ps <3 x float> @flat_load_saddr_v3i32_immneg128(ptr inreg %sbase,
; GFX1250-GISEL-NEXT: flat_load_b96 v[0:2], v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v3i32_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b96 v[0:2], v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -3287,19 +2424,6 @@ define amdgpu_ps <6 x half> @flat_load_saddr_v6f16(ptr inreg %sbase, i32 %voffse
; GFX1250-GISEL-NEXT: flat_load_b96 v[0:2], v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v6f16:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b96 v[0:2], v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load <6 x half>, ptr %gep0
@@ -3333,19 +2457,6 @@ define amdgpu_ps <6 x half> @flat_load_saddr_v6f16_immneg128(ptr inreg %sbase, i
; GFX1250-GISEL-NEXT: flat_load_b96 v[0:2], v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v6f16_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b96 v[0:2], v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -3380,19 +2491,6 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v4f32(ptr inreg %sbase, i32 %voffs
; GFX1250-GISEL-NEXT: flat_load_b128 v[0:3], v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v4f32:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b128 v[0:3], v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load <4 x float>, ptr %gep0
@@ -3426,19 +2524,6 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v4f32_immneg128(ptr inreg %sbase,
; GFX1250-GISEL-NEXT: flat_load_b128 v[0:3], v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v4f32_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b128 v[0:3], v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -3473,19 +2558,6 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v4i32(ptr inreg %sbase, i32 %voffs
; GFX1250-GISEL-NEXT: flat_load_b128 v[0:3], v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v4i32:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b128 v[0:3], v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load <4 x i32>, ptr %gep0
@@ -3520,19 +2592,6 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v4i32_immneg128(ptr inreg %sbase,
; GFX1250-GISEL-NEXT: flat_load_b128 v[0:3], v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v4i32_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b128 v[0:3], v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -3568,19 +2627,6 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v2i64(ptr inreg %sbase, i32 %voffs
; GFX1250-GISEL-NEXT: flat_load_b128 v[0:3], v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v2i64:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b128 v[0:3], v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load <2 x i64>, ptr %gep0
@@ -3615,19 +2661,6 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v2i64_immneg128(ptr inreg %sbase,
; GFX1250-GISEL-NEXT: flat_load_b128 v[0:3], v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v2i64_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b128 v[0:3], v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -3663,19 +2696,6 @@ define amdgpu_ps <4 x float> @flat_load_saddr_i128(ptr inreg %sbase, i32 %voffse
; GFX1250-GISEL-NEXT: flat_load_b128 v[0:3], v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b128 v[0:3], v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i128, ptr %gep0
@@ -3710,19 +2730,6 @@ define amdgpu_ps <4 x float> @flat_load_saddr_i128_immneg128(ptr inreg %sbase, i
; GFX1250-GISEL-NEXT: flat_load_b128 v[0:3], v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i128_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b128 v[0:3], v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -3758,19 +2765,6 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v2p1(ptr inreg %sbase, i32 %voffse
; GFX1250-GISEL-NEXT: flat_load_b128 v[0:3], v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v2p1:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b128 v[0:3], v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load <2 x ptr>, ptr %gep0
@@ -3806,19 +2800,6 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v2p1_immneg128(ptr inreg %sbase, i
; GFX1250-GISEL-NEXT: flat_load_b128 v[0:3], v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v2p1_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b128 v[0:3], v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -3855,19 +2836,6 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v4p3(ptr inreg %sbase, i32 %voffse
; GFX1250-GISEL-NEXT: flat_load_b128 v[0:3], v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v4p3:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b128 v[0:3], v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load <4 x ptr addrspace(3)>, ptr %gep0
@@ -3903,19 +2871,6 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v4p3_immneg128(ptr inreg %sbase, i
; GFX1250-GISEL-NEXT: flat_load_b128 v[0:3], v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_v4p3_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b128 v[0:3], v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -3956,19 +2911,6 @@ define amdgpu_ps float @flat_sextload_saddr_i8(ptr inreg %sbase, i32 %voffset) {
; GFX1250-GISEL-NEXT: flat_load_i8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_sextload_saddr_i8:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_i8 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i8, ptr %gep0
@@ -4004,19 +2946,6 @@ define amdgpu_ps float @flat_sextload_saddr_i8_immneg128(ptr inreg %sbase, i32 %
; GFX1250-GISEL-NEXT: flat_load_i8 v0, v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_sextload_saddr_i8_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_i8 v0, v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -4053,19 +2982,6 @@ define amdgpu_ps float @flat_sextload_saddr_i16(ptr inreg %sbase, i32 %voffset)
; GFX1250-GISEL-NEXT: flat_load_i16 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_sextload_saddr_i16:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_i16 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i16, ptr %gep0
@@ -4101,19 +3017,6 @@ define amdgpu_ps float @flat_sextload_saddr_i16_immneg128(ptr inreg %sbase, i32
; GFX1250-GISEL-NEXT: flat_load_i16 v0, v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_sextload_saddr_i16_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_i16 v0, v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -4150,19 +3053,6 @@ define amdgpu_ps float @flat_zextload_saddr_i8(ptr inreg %sbase, i32 %voffset) {
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_zextload_saddr_i8:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i8, ptr %gep0
@@ -4198,19 +3088,6 @@ define amdgpu_ps float @flat_zextload_saddr_i8_immneg128(ptr inreg %sbase, i32 %
; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_zextload_saddr_i8_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_u8 v0, v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -4247,19 +3124,6 @@ define amdgpu_ps float @flat_zextload_saddr_i16(ptr inreg %sbase, i32 %voffset)
; GFX1250-GISEL-NEXT: flat_load_u16 v0, v[0:1]
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_zextload_saddr_i16:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_u16 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i16, ptr %gep0
@@ -4295,19 +3159,6 @@ define amdgpu_ps float @flat_zextload_saddr_i16_immneg128(ptr inreg %sbase, i32
; GFX1250-GISEL-NEXT: flat_load_u16 v0, v[0:1] offset:-128
; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_zextload_saddr_i16_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_u16 v0, v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -4352,21 +3203,6 @@ define amdgpu_ps float @atomic_flat_load_saddr_i32(ptr inreg %sbase, i32 %voffse
; GFX1250-GISEL-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: atomic_flat_load_saddr_i32:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b32 v0, v[0:1] scope:SCOPE_SYS
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NOECC-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load atomic i32, ptr %gep0 seq_cst, align 4
@@ -4405,21 +3241,6 @@ define amdgpu_ps float @atomic_flat_load_saddr_i32_immneg128(ptr inreg %sbase, i
; GFX1250-GISEL-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: atomic_flat_load_saddr_i32_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b32 v0, v[0:1] offset:-128 scope:SCOPE_SYS
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NOECC-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -4459,21 +3280,6 @@ define amdgpu_ps <2 x float> @atomic_flat_load_saddr_i64(ptr inreg %sbase, i32 %
; GFX1250-GISEL-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: atomic_flat_load_saddr_i64:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b64 v[0:1], v[0:1] scope:SCOPE_SYS
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NOECC-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load atomic i64, ptr %gep0 seq_cst, align 8
@@ -4512,21 +3318,6 @@ define amdgpu_ps <2 x float> @atomic_flat_load_saddr_i64_immneg128(ptr inreg %sb
; GFX1250-GISEL-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: atomic_flat_load_saddr_i64_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128 scope:SCOPE_SYS
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NOECC-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -4583,19 +3374,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_undef_hi(ptr inreg %sbase
; GFX1250-GISEL-TRUE16-NEXT: flat_load_u16 v0, v[0:1]
; GFX1250-GISEL-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_undef_hi:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_d16_b16 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i16, ptr %gep0
@@ -4648,19 +3426,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_undef_hi_immneg128(ptr in
; GFX1250-GISEL-TRUE16-NEXT: flat_load_u16 v0, v[0:1] offset:-128
; GFX1250-GISEL-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_undef_hi_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_d16_b16 v0, v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -4728,20 +3493,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zero_hi(ptr inreg %sbase,
; GFX1250-GISEL-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: v_cvt_u32_u16_e32 v0, v0.l
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_zero_hi:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_d16_b16 v1, v[2:3]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, v1
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i16, ptr %gep0
@@ -4808,20 +3559,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zero_hi_immneg128(ptr inr
; GFX1250-GISEL-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: v_cvt_u32_u16_e32 v0, v0.l
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_zero_hi_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_d16_b16 v1, v[2:3] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, v1
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -4874,20 +3611,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_reg_hi(ptr inreg %sbase,
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.h
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_reg_hi:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_d16_b16 v2, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, v2
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i16, ptr %gep0
@@ -4939,20 +3662,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_reg_hi_immneg128(ptr inre
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.h
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_reg_hi_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_d16_b16 v2, v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, v2
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -5005,20 +3714,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zexti8_reg_hi(ptr inreg %
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.h
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_zexti8_reg_hi:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_d16_u8 v2, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, v2
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i8, ptr %gep0
@@ -5071,20 +3766,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zexti8_reg_hi_immneg128(p
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.h
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_zexti8_reg_hi_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_d16_u8 v2, v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, v2
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -5157,20 +3838,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_sexti8_reg_hi(ptr inreg %
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT: v_and_or_b32 v0, v1, 0xffff0000, v0
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_sexti8_reg_hi:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_d16_i8 v2, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, v2
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i8, ptr %gep0
@@ -5242,20 +3909,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_sexti8_reg_hi_immneg128(p
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT: v_and_or_b32 v0, v1, 0xffff0000, v0
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_sexti8_reg_hi_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_d16_i8 v2, v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, v2
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -5329,19 +3982,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_undef_hi(ptr inreg %sbase
; GFX1250-GISEL-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_undef_hi:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_d16_hi_b16 v0, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i16, ptr %gep0
@@ -5409,19 +4049,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_undef_hi_immneg128(ptr in
; GFX1250-GISEL-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_undef_hi_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_d16_hi_b16 v0, v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -5474,34 +4101,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zero_hi(ptr inreg %sbase,
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-SDAG-TRUE16-LABEL: flat_load_saddr_i16_d16hi_zero_hi:
-; GFX1250-NOECC-SDAG-TRUE16: ; %bb.0:
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_nop
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[0:1]
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: flat_load_d16_hi_b16 v0, v[2:3]
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-SDAG-FAKE16-LABEL: flat_load_saddr_i16_d16hi_zero_hi:
-; GFX1250-NOECC-SDAG-FAKE16: ; %bb.0:
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_nop
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[0:1]
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: flat_load_d16_hi_b16 v1, v[2:3]
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, v1
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i16, ptr %gep0
@@ -5553,34 +4152,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zero_hi_immneg128(ptr inr
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-SDAG-TRUE16-LABEL: flat_load_saddr_i16_d16hi_zero_hi_immneg128:
-; GFX1250-NOECC-SDAG-TRUE16: ; %bb.0:
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_nop
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[0:1]
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: flat_load_d16_hi_b16 v0, v[2:3] offset:-128
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-SDAG-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-SDAG-FAKE16-LABEL: flat_load_saddr_i16_d16hi_zero_hi_immneg128:
-; GFX1250-NOECC-SDAG-FAKE16: ; %bb.0:
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_nop
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[0:1]
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: flat_load_d16_hi_b16 v1, v[2:3] offset:-128
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, v1
-; GFX1250-NOECC-SDAG-FAKE16-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -5636,20 +4207,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_reg_hi(ptr inreg %sbase,
; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l
; GFX1250-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_reg_hi:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_d16_hi_b16 v2, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, v2
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i16, ptr %gep0
@@ -5704,20 +4261,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_reg_hi_immneg128(ptr inre
; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l
; GFX1250-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_reg_hi_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_d16_hi_b16 v2, v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, v2
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -5773,20 +4316,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zexti8_reg_hi(ptr inreg %
; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l
; GFX1250-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_zexti8_reg_hi:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_d16_hi_u8 v2, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, v2
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i8, ptr %gep0
@@ -5842,20 +4371,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128(p
; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l
; GFX1250-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_d16_hi_u8 v2, v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, v2
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -5931,20 +4446,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_sexti8_reg_hi(ptr inreg %
; GFX1250-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1250-GISEL-TRUE16-NEXT: v_and_or_b32 v0, v1, 0xffff, v0
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_sexti8_reg_hi:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_d16_hi_i8 v2, v[0:1]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, v2
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i8, ptr %gep0
@@ -6019,20 +4520,6 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128(p
; GFX1250-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1250-GISEL-TRUE16-NEXT: v_and_or_b32 v0, v1, 0xffff, v0
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0
-; GFX1250-NOECC-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NOECC-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-NOECC-NEXT: flat_load_d16_hi_i8 v2, v[0:1] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, v2
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -6135,26 +4622,6 @@ define amdgpu_ps void @flat_addr_64bit_lsr_iv(ptr inreg %arg) {
; GFX1250-GISEL-NEXT: s_cbranch_scc0 .LBB117_1
; GFX1250-GISEL-NEXT: ; %bb.2: ; %bb2
; GFX1250-GISEL-NEXT: s_endpgm
-;
-; GFX1250-NOECC-LABEL: flat_addr_64bit_lsr_iv:
-; GFX1250-NOECC: ; %bb.0: ; %bb
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NOECC-NEXT: s_movk_i32 s0, 0x100
-; GFX1250-NOECC-NEXT: .LBB117_1: ; %bb3
-; GFX1250-NOECC-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1250-NOECC-NEXT: s_wait_dscnt 0x0
-; GFX1250-NOECC-NEXT: flat_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
-; GFX1250-NOECC-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NOECC-NEXT: s_add_co_i32 s0, s0, -1
-; GFX1250-NOECC-NEXT: s_add_nc_u64 s[2:3], s[2:3], 4
-; GFX1250-NOECC-NEXT: s_cmp_eq_u32 s0, 0
-; GFX1250-NOECC-NEXT: s_cbranch_scc0 .LBB117_1
-; GFX1250-NOECC-NEXT: ; %bb.2: ; %bb2
-; GFX1250-NOECC-NEXT: s_endpgm
bb:
br label %bb3
@@ -6218,28 +4685,6 @@ define amdgpu_ps void @flat_addr_64bit_lsr_iv_multiload(ptr inreg %arg, ptr inre
; GFX1250-GISEL-NEXT: s_cbranch_scc0 .LBB118_1
; GFX1250-GISEL-NEXT: ; %bb.2: ; %bb2
; GFX1250-GISEL-NEXT: s_endpgm
-;
-; GFX1250-NOECC-LABEL: flat_addr_64bit_lsr_iv_multiload:
-; GFX1250-NOECC: ; %bb.0: ; %bb
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NOECC-NEXT: v_nop
-; GFX1250-NOECC-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NOECC-NEXT: s_movk_i32 s0, 0x100
-; GFX1250-NOECC-NEXT: .LBB118_1: ; %bb3
-; GFX1250-NOECC-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1250-NOECC-NEXT: s_wait_dscnt 0x0
-; GFX1250-NOECC-NEXT: flat_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: flat_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
-; GFX1250-NOECC-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NOECC-NEXT: s_add_co_i32 s0, s0, -1
-; GFX1250-NOECC-NEXT: s_add_nc_u64 s[2:3], s[2:3], 4
-; GFX1250-NOECC-NEXT: s_cmp_eq_u32 s0, 0
-; GFX1250-NOECC-NEXT: s_cbranch_scc0 .LBB118_1
-; GFX1250-NOECC-NEXT: ; %bb.2: ; %bb2
-; GFX1250-NOECC-NEXT: s_endpgm
bb:
br label %bb3
diff --git a/llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-any.ll b/llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-any.ll
index 8a301f983eb6d..ec336d21ee5de 100644
--- a/llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-any.ll
+++ b/llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-any.ll
@@ -1,14 +1,15 @@
; RUN: llc -mtriple=amdgpu7.00 -debug-only=gcn-subtarget -o - %s 2>&1 | FileCheck --check-prefix=NOT-SUPPORTED %s
; RUN: llc -mtriple=amdgpu9.06 -debug-only=gcn-subtarget -o - %s 2>&1 | FileCheck --check-prefix=ANY %s
; RUN: llc -mtriple=amdgpu9.08 -debug-only=gcn-subtarget -o - %s 2>&1 | FileCheck --check-prefix=ANY %s
-; RUN: llc -mtriple=amdgpu12.50 -debug-only=gcn-subtarget -o - %s 2>&1 | FileCheck --check-prefix=ANY %s
-; RUN: llc -mtriple=amdgpu12.51 -debug-only=gcn-subtarget -o - %s 2>&1 | FileCheck --check-prefix=ANY %s
-; RUN: llc -mtriple=amdgpu12.5 -debug-only=gcn-subtarget -o - %s 2>&1 | FileCheck --check-prefix=ANY %s
+; RUN: llc -mtriple=amdgpu12.50 -debug-only=gcn-subtarget -o - %s 2>&1 | FileCheck --check-prefix=ON %s
+; RUN: llc -mtriple=amdgpu12.51 -debug-only=gcn-subtarget -o - %s 2>&1 | FileCheck --check-prefix=ON %s
+; RUN: llc -mtriple=amdgpu12.5 -debug-only=gcn-subtarget -o - %s 2>&1 | FileCheck --check-prefix=ON %s
; REQUIRES: asserts
; NOT-SUPPORTED: sramecc setting for subtarget: Unsupported
; ANY: sramecc setting for subtarget: Any
+; ON: sramecc setting for subtarget: On
define void @sramecc-subtarget-feature-default() #0 {
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-disabled.ll b/llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-disabled.ll
index 0c6ba648bd9cf..45e352921e7cb 100644
--- a/llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-disabled.ll
+++ b/llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-disabled.ll
@@ -1,9 +1,13 @@
; RUN: llc -mtriple=amdgpu9.06 -debug-only=gcn-subtarget -o - %s 2>&1 | FileCheck --check-prefix=OFF %s
; RUN: llc -mtriple=amdgpu9.08 -debug-only=gcn-subtarget -o - %s 2>&1 | FileCheck --check-prefix=OFF %s
+; SRAMECC is hardwired on for gfx12.5; the module flag is ignored.
+; RUN: llc -mtriple=amdgpu12.50 -debug-only=gcn-subtarget -o - %s 2>&1 | FileCheck --check-prefix=ON %s
+
; REQUIRES: asserts
; OFF: sramecc setting for subtarget: Off
+; ON: sramecc setting for subtarget: On
define void @sramecc-subtarget-feature-disabled() #0 {
ret void
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index c32ec6a5b4f92..ccc863356fe72 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -3653,10 +3653,9 @@ TEST(TargetParserTest, testAMDGPUSramEccOnOffModes) {
using namespace AMDGPU;
// Existing SRAMECC targets retain their selectable modes, including generic
- // targets and gfx12.5, where XNACK is hardwired on.
+ // targets.
for (StringRef GPU :
- {"gfx906", "gfx908", "gfx90a", "gfx942", "gfx950", "gfx9-4-generic",
- "gfx1250-strict", "gfx1250", "gfx1251", "gfx12-5-generic"}) {
+ {"gfx906", "gfx908", "gfx90a", "gfx942", "gfx950", "gfx9-4-generic"}) {
SCOPED_TRACE(GPU);
GPUKind Kind = parseArchAMDGCN(GPU);
const AMDGPUFeatureBitset &Features = getFeatureBitset(Kind);
@@ -3703,6 +3702,24 @@ TEST(TargetParserTest, testAMDGPUSramEccOnOffModes) {
.getSramEccSetting(),
TargetIDSetting::Unsupported);
}
+
+ // gfx12.5 hardwires SRAMECC on, so the modifier is rejected.
+ for (StringRef GPU :
+ {"gfx1250-strict", "gfx1250", "gfx1251", "gfx12-5-generic"}) {
+ SCOPED_TRACE(GPU);
+ GPUKind Kind = parseArchAMDGCN(GPU);
+ const AMDGPUFeatureBitset &Features = getFeatureBitset(Kind);
+ EXPECT_TRUE(Features.test(FEAT_SRAMECC_SUPPORT));
+ EXPECT_FALSE(Features.test(FEAT_SRAMECC_ON_OFF_MODES));
+
+ Triple TT(getSubArchName(getSubArch(Kind)), "amd", "amdhsa");
+ EXPECT_EQ(TargetID(TT, "").getSramEccSetting(), TargetIDSetting::On);
+ EXPECT_FALSE(TargetID::parse(TT, ":sramecc+"));
+ EXPECT_FALSE(TargetID::parse(TT, ":sramecc-"));
+ EXPECT_EQ(TargetID::createFromSubtargetFeatures(TT, GPU, "-sramecc")
+ .getSramEccSetting(),
+ TargetIDSetting::On);
+ }
}
TEST(TargetParserTest, testAMDGPUTargetIDProvidesFor) {
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