[clang] [llvm] [AArch64][llvm] Armv9.8-A: Add support for FEAT_SVE_LRCPC (PR #231430)
Martin Wehking via cfe-commits
cfe-commits at lists.llvm.org
Fri Oct 16 05:32:56 PDT 2026
https://github.com/MartinWehking updated https://github.com/llvm/llvm-project/pull/231430
>From 61ad1d22a9bdeffb182f82398b4a3cf13c4f56d9 Mon Sep 17 00:00:00 2001
From: Martin Wehking <martin.wehking at arm.com>
Date: Mon, 14 Sep 2026 14:49:59 +0000
Subject: [PATCH 1/5] [AArch64][llvm] Armv9.8-A: Add support for FEAT_SVE_LRCPC
Add support for FEAT_SVE_LRCPC (Load-Acquire/Store-Release octaword
instructions), which are optional from Armv9.6 onwards.
---
clang/test/Driver/aarch64-v98a.c | 4 ++
.../print-supported-extensions-aarch64.c | 1 +
llvm/lib/Target/AArch64/AArch64Features.td | 4 ++
.../lib/Target/AArch64/AArch64InstrFormats.td | 10 +++
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 2 +
.../lib/Target/AArch64/AArch64SVEInstrInfo.td | 8 +++
.../AArch64/AsmParser/AArch64AsmParser.cpp | 4 ++
llvm/lib/Target/AArch64/SVEInstrFormats.td | 49 +++++++++++++++
.../MC/AArch64/SVE/ldapro-stlro-diagnostics.s | 19 ++++++
llvm/test/MC/AArch64/SVE/ldapro-stlro.s | 62 +++++++++++++++++++
.../MC/AArch64/SVE2/directive-arch-negative.s | 6 ++
llvm/test/MC/AArch64/SVE2/directive-arch.s | 4 ++
.../SVE2/directive-arch_extension-negative.s | 6 ++
.../AArch64/SVE2/directive-arch_extension.s | 4 ++
.../TargetParser/TargetParserTest.cpp | 25 +++++++-
15 files changed, 207 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/MC/AArch64/SVE/ldapro-stlro-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/SVE/ldapro-stlro.s
diff --git a/clang/test/Driver/aarch64-v98a.c b/clang/test/Driver/aarch64-v98a.c
index 30e2cd9e84d100..7233e694211ca8 100644
--- a/clang/test/Driver/aarch64-v98a.c
+++ b/clang/test/Driver/aarch64-v98a.c
@@ -25,3 +25,7 @@
// RUN: %clang -target aarch64 -march=armv9.8a+lsc64b -### -c %s 2>&1 | FileCheck -check-prefix=V98A-LSC64B %s
// RUN: %clang -target aarch64 -march=armv9.8-a+lsc64b -### -c %s 2>&1 | FileCheck -check-prefix=V98A-LSC64B %s
// V98A-LSC64B: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.8a"{{.*}} "-target-feature" "+lsc64b"
+//
+// RUN: %clang -target aarch64 -march=armv9.8a+sve-lrcpc -### -c %s 2>&1 | FileCheck -check-prefix=V98A-SVE-LRCPC %s
+// RUN: %clang -target aarch64 -march=armv9.8-a+sve-lrcpc -### -c %s 2>&1 | FileCheck -check-prefix=V98A-SVE-LRCPC %s
+// V98A-SVE-LRCPC: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.8a"{{.*}} "-target-feature" "+sve-lrcpc"
diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c b/clang/test/Driver/print-supported-extensions-aarch64.c
index c35b1e080b21ac..9d2e00670f7420 100644
--- a/clang/test/Driver/print-supported-extensions-aarch64.c
+++ b/clang/test/Driver/print-supported-extensions-aarch64.c
@@ -105,6 +105,7 @@
// CHECK-NEXT: sve-bfscale FEAT_SVE_BFSCALE Enable Armv9.6-A SVE BFloat16 scaling instructions
// CHECK-NEXT: sve-bitperm FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
// CHECK-NEXT: sve-f16f32mm FEAT_SVE_F16F32MM Enable Armv9.6-A FP16 to FP32 Matrix Multiply
+// CHECK-NEXT: sve-lrcpc FEAT_SVE_LRCPC Enable Armv9.8-A SVE weaker Release Consistency processor consistent (RCpc) model
// CHECK-NEXT: sve-sha3 FEAT_SVE_SHA3 Enable SVE SHA3 instructions
// CHECK-NEXT: sve-sm4 FEAT_SVE_SM4 Enable SVE SM4 instructions
// CHECK-NEXT: sve2 FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index d70bdb44d34f55..fa23c2f43f6c97 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -627,6 +627,10 @@ def FeatureCFLT : ExtensionWithMArch<"cflt", "CFLT", "FEAT_CFLT",
def FeatureLSC64B : ExtensionWithMArch<"lsc64b", "LSC64B", "FEAT_LSC64B",
"Enable Armv9.8-A Single-copy atomic 64-byte load/store consistency extension", [FeatureLSCP]>;
+def FeatureSVE_LRCPC: ExtensionWithMArch<"sve-lrcpc", "SVE_LRCPC", "FEAT_SVE_LRCPC",
+ "Enable Armv9.8-A SVE weaker Release Consistency processor consistent (RCpc) model",
+ [FeatureSVE2, FeatureRCPC3]>;
+
//===----------------------------------------------------------------------===//
// Future Architecture Technologies
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 1b334a605b6004..3df66fa00fc282 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -737,6 +737,16 @@ def uimm6s16 : Operand<i64>, ImmLeaf<i64,
let OperandType = "OPERAND_IMMEDIATE";
}
+// uimm8sN predicate - True if the immediate is a multiple of N in the range
+// [0 * N, 255 * N].
+def UImm8s32Operand : UImmScaledMemoryIndexed<8, 32>;
+def uimm8s32 : Operand<i64>, ImmLeaf<i64,
+[{ return Imm >= 0 && Imm < (256*32) && ((Imm % 32) == 0); }]> {
+ let PrintMethod = "printImmScale<32>";
+ let ParserMatchClass = UImm8s32Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
+}
+
def SImmS2XForm : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getSExtValue() / 2, SDLoc(N), MVT::i64);
}]>;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index f03ba085246f19..f61576ef66e026 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -241,6 +241,8 @@ def HasCFLT : Predicate<"Subtarget->hasCFLT()">,
AssemblerPredicateWithAll<(all_of FeatureCFLT), "cflt">;
def HasLSC64B : Predicate<"Subtarget->hasLSC64B()">,
AssemblerPredicateWithAll<(all_of FeatureLSC64B), "lsc64b">;
+def HasSVE_LRCPC : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE_LRCPC()">,
+ AssemblerPredicateWithAll<(all_of FeatureSVE_LRCPC), "sve-lrcpc">;
// A subset of SVE(2) instructions are legal in Streaming SVE execution mode,
// they should be enabled if either has been specified.
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 74668943eb9d45..537fe185d7c231 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -5326,3 +5326,11 @@ let Predicates = [HasSVE, HasCPA] in {
// Multiply-add vectors, writing addend
def MLA_CPA : sve_int_mla_cpa<"mlapt">;
}
+
+//===----------------------------------------------------------------------===//
+// Load-Acquire/Store-Release octaword (FEAT_SVE_LRCPC)
+//===----------------------------------------------------------------------===//
+let Predicates = [HasSVE_LRCPC] in {
+ defm LDAPRO_ZXI : sve_mem_z_acq_fill<"ldapro">;
+ defm STLRO_ZXI : sve_mem_z_rel_spill<"stlro">;
+}
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index f93638caee3ba4..41a850a36af7b3 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3764,6 +3764,7 @@ constexpr EnumStringDef<FeatureBitset> ExtensionDefs[] = {
{{"wfxt"}, {AArch64::FeatureWFxT}},
{{"cflt"}, {AArch64::FeatureCFLT}},
{{"lsc64b"}, {AArch64::FeatureLSC64B}},
+ {{"sve-lrcpc"}, {AArch64::FeatureSVE_LRCPC}},
};
constexpr auto ExtensionMap = BUILD_ENUM_STRINGS(ExtensionDefs);
@@ -6037,6 +6038,8 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
return Error(Loc, "index must be a multiple of 8 in range [0, 504].");
case Match_InvalidMemoryIndexed16UImm6:
return Error(Loc, "index must be a multiple of 16 in range [0, 1008].");
+ case Match_InvalidMemoryIndexed32UImm8:
+ return Error(Loc, "index must be a multiple of 32 in range [0, 8160].");
case Match_InvalidMemoryIndexed4UImm6:
return Error(Loc, "index must be a multiple of 4 in range [0, 252].");
case Match_InvalidMemoryIndexed2UImm6:
@@ -6884,6 +6887,7 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidMemoryIndexed4UImm6:
case Match_InvalidMemoryIndexed8UImm6:
case Match_InvalidMemoryIndexed16UImm6:
+ case Match_InvalidMemoryIndexed32UImm8:
case Match_InvalidMemoryIndexedSImm6:
case Match_InvalidMemoryIndexedSImm5:
case Match_InvalidMemoryIndexedSImm8:
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index e45bc5fd19c735..7b1aade4cc004a 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -11590,3 +11590,52 @@ multiclass sve2_int_to_fp_upcvt<string asm, bits<2> U, SDPatternOperator op> {
def : SVE_1_Op_Pat<nxv4f32, op, nxv8i16, !cast<Instruction>(NAME # _HtoS)>;
def : SVE_1_Op_Pat<nxv2f64, op, nxv4i32, !cast<Instruction>(NAME # _StoD)>;
}
+
+//===----------------------------------------------------------------------===//
+// SVE ordered load/store
+//===----------------------------------------------------------------------===//
+class sve_mem_z_acq_fill_inst<string mnemonic> :
+ I<(outs ZPRAny:$Zt), (ins GPR64sp:$Rn, uimm8s32:$imm), mnemonic,
+ "\t$Zt, [$Rn, $imm]", "", []>, Sched<[]> {
+ bits<5> Zt;
+ bits<5> Rn;
+ bits<8> imm;
+ let Inst{31-21} = 0b10000101100;
+ let Inst{20-16} = imm{7-3};
+ let Inst{15-13} = 0b011;
+ let Inst{12-10} = imm{2-0};
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Zt;
+
+ let mayLoad = 1;
+}
+
+class sve_mem_z_rel_spill_inst<string mnemonic> :
+ I<(outs ), (ins ZPRAny:$Zt, GPR64sp:$Rn, uimm8s32:$imm), mnemonic,
+ "\t$Zt, [$Rn, $imm]", "", []>, Sched<[]> {
+ bits<5> Zt;
+ bits<5> Rn;
+ bits<8> imm;
+ let Inst{31-21} = 0b11100101110;
+ let Inst{20-16} = imm{7-3};
+ let Inst{15-13} = 0b000;
+ let Inst{12-10} = imm{2-0};
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Zt;
+
+ let mayStore = 1;
+}
+
+multiclass sve_mem_z_acq_fill<string mnemonic> {
+ def NAME : sve_mem_z_acq_fill_inst<mnemonic>;
+
+ def : InstAlias<mnemonic # "\t$Zt, [$Rn]",
+ (!cast<Instruction>(NAME) ZPRAny:$Zt, GPR64sp:$Rn, 0), 1>;
+}
+
+multiclass sve_mem_z_rel_spill<string mnemonic> {
+ def NAME : sve_mem_z_rel_spill_inst<mnemonic>;
+
+ def : InstAlias<mnemonic # "\t$Zt, [$Rn]",
+ (!cast<Instruction>(NAME) ZPRAny:$Zt, GPR64sp:$Rn, 0), 1>;
+}
diff --git a/llvm/test/MC/AArch64/SVE/ldapro-stlro-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldapro-stlro-diagnostics.s
new file mode 100644
index 00000000000000..09ee27afb020fe
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ldapro-stlro-diagnostics.s
@@ -0,0 +1,19 @@
+// RUN: not llvm-mc -triple=aarch64 -mattr=+sve,+sve-lrcpc < %s 2>&1 | FileCheck %s
+
+ldapro z2, [x6, #177]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [0, 8160].
+
+stlro z2, [x6, #177]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [0, 8160].
+
+ldapro z2, [x6, #8161]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [0, 8160].
+
+stlro z2, [x6, #8161]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [0, 8160].
+
+ldapro z2, [x6, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [0, 8160].
+
+stlro z2, [x6, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [0, 8160].
diff --git a/llvm/test/MC/AArch64/SVE/ldapro-stlro.s b/llvm/test/MC/AArch64/SVE/ldapro-stlro.s
new file mode 100644
index 00000000000000..7443899e2f5b7f
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ldapro-stlro.s
@@ -0,0 +1,62 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve,+sve-lrcpc < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve,+sve-lrcpc < %s \
+// RUN: | llvm-objdump -d --mattr=+sve,+sve-lrcpc --no-print-imm-hex - \
+// RUN: | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve,+sve-lrcpc < %s \
+// RUN: | llvm-objdump -d --mattr=+sve,-sve-lrcpc --no-print-imm-hex - \
+// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve,+sve-lrcpc < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve,+sve-lrcpc -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+ldapro z0, [x0]
+// CHECK-INST: ldapro z0, [x0]
+// CHECK-ENCODING: encoding: [0x00,0x60,0x80,0x85]
+// CHECK-ERROR: instruction requires: sve-lrcpc
+// CHECK-UNKNOWN: 85806000 <unknown>
+
+ldapro z31, [x0, #0]
+// CHECK-INST: ldapro z31, [x0]
+// CHECK-ENCODING: encoding: [0x1f,0x60,0x80,0x85]
+// CHECK-ERROR: instruction requires: sve-lrcpc
+// CHECK-UNKNOWN: 8580601f <unknown>
+
+ldapro z0, [sp, #2720]
+// CHECK-INST: ldapro z0, [sp, #2720]
+// CHECK-ENCODING: encoding: [0xe0,0x77,0x8a,0x85]
+// CHECK-ERROR: instruction requires: sve-lrcpc
+// CHECK-UNKNOWN: 858a77e0 <unknown>
+
+ldapro z31, [sp, #8160]
+// CHECK-INST: ldapro z31, [sp, #8160]
+// CHECK-ENCODING: encoding: [0xff,0x7f,0x9f,0x85]
+// CHECK-ERROR: instruction requires: sve-lrcpc
+// CHECK-UNKNOWN: 859f7fff <unknown>
+
+stlro z0, [x0]
+// CHECK-INST: stlro z0, [x0]
+// CHECK-ENCODING: encoding: [0x00,0x00,0xc0,0xe5]
+// CHECK-ERROR: instruction requires: sve-lrcpc
+// CHECK-UNKNOWN: e5c00000 <unknown>
+
+stlro z31, [x0, #0]
+// CHECK-INST: stlro z31, [x0]
+// CHECK-ENCODING: encoding: [0x1f,0x00,0xc0,0xe5]
+// CHECK-ERROR: instruction requires: sve-lrcpc
+// CHECK-UNKNOWN: e5c0001f <unknown>
+
+stlro z0, [sp, #2720]
+// CHECK-INST: stlro z0, [sp, #2720]
+// CHECK-ENCODING: encoding: [0xe0,0x17,0xca,0xe5]
+// CHECK-ERROR: instruction requires: sve-lrcpc
+// CHECK-UNKNOWN: e5ca17e0 <unknown>
+
+stlro z31, [sp, #8160]
+// CHECK-INST: stlro z31, [sp, #8160]
+// CHECK-ENCODING: encoding: [0xff,0x1f,0xdf,0xe5]
+// CHECK-ERROR: instruction requires: sve-lrcpc
+// CHECK-UNKNOWN: e5df1fff <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s b/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
index b20fed789a8ed5..6410c394d92067 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
@@ -64,3 +64,9 @@ fmmla z23.s, z13.h, z8.h
bfscale z0.h, p0/m, z0.h, z0.h
// CHECK: error: instruction requires: sve-bfscale
// CHECK-NEXT: bfscale z0.h, p0/m, z0.h, z0.h
+
+.arch armv9.6-a+sve-lrcpc
+.arch armv9.6-a+nosve-lrcpc
+ldapro z0, [x0]
+// CHECK: error: instruction requires: sve-lrcpc
+// CHECK-NEXT: ldapro z0, [x0]
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch.s b/llvm/test/MC/AArch64/SVE2/directive-arch.s
index 203541a09ad373..4eb4e144f059f6 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch.s
@@ -43,3 +43,7 @@ fmmla z23.s, z13.h, z8.h
.arch armv9-a+sve-bfscale
bfscale z0.h, p0/m, z0.h, z0.h
// CHECK: bfscale z0.h, p0/m, z0.h, z0.h
+
+.arch armv9.6-a+sve-lrcpc
+ldapro z0, [x0]
+// CHECK: ldapro z0, [x0]
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
index 73114e57fc18ad..712644136c8ac7 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
@@ -60,3 +60,9 @@ fmmla z23.s, z13.h, z8.h
bfscale z0.h, p0/m, z0.h, z0.h
// CHECK: error: instruction requires: sve-bfscale
// CHECK-NEXT: bfscale z0.h, p0/m, z0.h, z0.h
+
+.arch_extension sve-lrcpc
+.arch_extension nosve-lrcpc
+ldapro z0, [x0]
+// CHECK: error: instruction requires: sve-lrcpc
+// CHECK-NEXT: ldapro z0, [x0]
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s b/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
index e45e1f9881422e..34e1182b329011 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
@@ -39,3 +39,7 @@ fmmla z23.s, z13.h, z8.h
.arch_extension sve-bfscale
bfscale z0.h, p0/m, z0.h, z0.h
// CHECK: bfscale z0.h, p0/m, z0.h, z0.h
+
+.arch_extension sve-lrcpc
+ldapro z0, [x0]
+// CHECK: ldapro z0, [x0]
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 569e253cf9ba15..2b6e36cd46a16f 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1509,6 +1509,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_POPS, AArch64::AEK_SVESM4,
AArch64::AEK_MTETC, AArch64::AEK_HINTE,
AArch64::AEK_CFLT, AArch64::AEK_LSC64B,
+ AArch64::AEK_SVE_LRCPC,
};
std::vector<StringRef> Features;
@@ -1635,6 +1636,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
EXPECT_TRUE(llvm::is_contained(Features, "+hinte"));
EXPECT_TRUE(llvm::is_contained(Features, "+cflt"));
EXPECT_TRUE(llvm::is_contained(Features, "+lsc64b"));
+ EXPECT_TRUE(llvm::is_contained(Features, "+sve-lrcpc"));
// Assuming we listed every extension above, this should produce the same
// result.
@@ -1818,6 +1820,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
{"hinte", "nohinte", "+hinte", "-hinte"},
{"cflt", "nocflt", "+cflt", "-cflt"},
{"lsc64b", "nolsc64b", "+lsc64b", "-lsc64b"},
+ {"sve-lrcpc", "nosve-lrcpc", "+sve-lrcpc", "-sve-lrcpc"},
};
for (unsigned i = 0; i < std::size(ArchExt); i++) {
@@ -2124,7 +2127,8 @@ AArch64ExtensionDependenciesBaseArchTestParams
{AArch64::ARMV8A, {"noaes", "sve-aes"}, {"aes", "sve-aes"}, {}},
{AArch64::ARMV8A, {"sve-aes", "noaes"}, {}, {"aes", "sve-aes"}},
- // sve2 -> {sve2p1, sve2-bitperm, sve2-sha3, sve2-sm4, sve2-aes}
+ // sve2 ->
+ // {sve2p1, sve2-bitperm, sve2-sha3, sve2-sm4, sve2-aes, sve-lrcpc}
{AArch64::ARMV8A, {"nosve2", "sve2p1"}, {"sve2", "sve2p1"}, {}},
{AArch64::ARMV8A, {"sve2p1", "nosve2"}, {}, {"sve2", "sve2p1"}},
{AArch64::ARMV8A,
@@ -2150,6 +2154,15 @@ AArch64ExtensionDependenciesBaseArchTestParams
{AArch64::ARMV8A, {"nosve2", "sve2-aes"}, {"sve2", "sve2-aes"}, {}},
{AArch64::ARMV8A, {"sve2-aes", "nosve2"}, {}, {"sve2", "sve2-aes"}},
+ {AArch64::ARMV8A,
+ {"nosve2", "sve-lrcpc"},
+ {"sve2", "sve-lrcpc"},
+ {}},
+ {AArch64::ARMV8A,
+ {"sve-lrcpc", "nosve2"},
+ {},
+ {"sve2", "sve-lrcpc"}},
+
// sve-b16b16 -> {sme-b16b16}
{AArch64::ARMV9_4A,
{"nosve-b16b16", "sme-b16b16"},
@@ -2287,6 +2300,16 @@ AArch64ExtensionDependenciesBaseArchTestParams
{AArch64::ARMV8A, {"norcpc", "rcpc3"}, {"rcpc", "rcpc3"}, {}},
{AArch64::ARMV8A, {"rcpc3", "norcpc"}, {}, {"rcpc", "rcpc3"}},
+ // rcpc3 -> sve-lrcpc
+ {AArch64::ARMV8A,
+ {"norcpc3", "sve-lrcpc"},
+ {"rcpc3", "sve-lrcpc"},
+ {}},
+ {AArch64::ARMV8A,
+ {"sve-lrcpc", "norcpc3"},
+ {},
+ {"rcpc3", "sve-lrcpc"}},
+
// sve-aes -> {ssve-aes, sve2-aes}
{AArch64::ARMV9_6A,
{"nosve-aes", "ssve-aes"},
>From d7e23bf95f9d159ccad71f7f882769dc316f0320 Mon Sep 17 00:00:00 2001
From: Martin Wehking <martin.wehking at arm.com>
Date: Tue, 13 Oct 2026 15:40:42 +0000
Subject: [PATCH 2/5] fixup! Change extension name + combine classes
sve-lrcpc -> sve_rcpc
Combine ordered load/store into one class + multiclass.
---
clang/test/Driver/aarch64-v98a.c | 6 +--
.../print-supported-extensions-aarch64.c | 2 +-
llvm/lib/Target/AArch64/AArch64Features.td | 2 +-
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 4 +-
.../lib/Target/AArch64/AArch64SVEInstrInfo.td | 10 +++--
.../AArch64/AsmParser/AArch64AsmParser.cpp | 2 +-
llvm/lib/Target/AArch64/SVEInstrFormats.td | 43 +++++--------------
.../MC/AArch64/SVE/ldapro-stlro-diagnostics.s | 2 +-
llvm/test/MC/AArch64/SVE/ldapro-stlro.s | 30 ++++++-------
.../MC/AArch64/SVE2/directive-arch-negative.s | 6 +--
llvm/test/MC/AArch64/SVE2/directive-arch.s | 2 +-
.../SVE2/directive-arch_extension-negative.s | 6 +--
.../AArch64/SVE2/directive-arch_extension.s | 2 +-
.../TargetParser/TargetParserTest.cpp | 26 +++++------
14 files changed, 63 insertions(+), 80 deletions(-)
diff --git a/clang/test/Driver/aarch64-v98a.c b/clang/test/Driver/aarch64-v98a.c
index 7233e694211ca8..1a41a97610e595 100644
--- a/clang/test/Driver/aarch64-v98a.c
+++ b/clang/test/Driver/aarch64-v98a.c
@@ -26,6 +26,6 @@
// RUN: %clang -target aarch64 -march=armv9.8-a+lsc64b -### -c %s 2>&1 | FileCheck -check-prefix=V98A-LSC64B %s
// V98A-LSC64B: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.8a"{{.*}} "-target-feature" "+lsc64b"
//
-// RUN: %clang -target aarch64 -march=armv9.8a+sve-lrcpc -### -c %s 2>&1 | FileCheck -check-prefix=V98A-SVE-LRCPC %s
-// RUN: %clang -target aarch64 -march=armv9.8-a+sve-lrcpc -### -c %s 2>&1 | FileCheck -check-prefix=V98A-SVE-LRCPC %s
-// V98A-SVE-LRCPC: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.8a"{{.*}} "-target-feature" "+sve-lrcpc"
+// RUN: %clang -target aarch64 -march=armv9.8a+sve-rcpc -### -c %s 2>&1 | FileCheck -check-prefix=V98A-SVE-RCPC %s
+// RUN: %clang -target aarch64 -march=armv9.8-a+sve-rcpc -### -c %s 2>&1 | FileCheck -check-prefix=V98A-SVE-RCPC %s
+// V98A-SVE-RCPC: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.8a"{{.*}} "-target-feature" "+sve-rcpc"
diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c b/clang/test/Driver/print-supported-extensions-aarch64.c
index 9d2e00670f7420..e334d2e8dcee00 100644
--- a/clang/test/Driver/print-supported-extensions-aarch64.c
+++ b/clang/test/Driver/print-supported-extensions-aarch64.c
@@ -105,7 +105,7 @@
// CHECK-NEXT: sve-bfscale FEAT_SVE_BFSCALE Enable Armv9.6-A SVE BFloat16 scaling instructions
// CHECK-NEXT: sve-bitperm FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
// CHECK-NEXT: sve-f16f32mm FEAT_SVE_F16F32MM Enable Armv9.6-A FP16 to FP32 Matrix Multiply
-// CHECK-NEXT: sve-lrcpc FEAT_SVE_LRCPC Enable Armv9.8-A SVE weaker Release Consistency processor consistent (RCpc) model
+// CHECK-NEXT: sve-rcpc FEAT_SVE_LRCPC Enable Armv9.8-A SVE weaker Release Consistency processor consistent (RCpc) model
// CHECK-NEXT: sve-sha3 FEAT_SVE_SHA3 Enable SVE SHA3 instructions
// CHECK-NEXT: sve-sm4 FEAT_SVE_SM4 Enable SVE SM4 instructions
// CHECK-NEXT: sve2 FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index fa23c2f43f6c97..0434ec5d26ee85 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -627,7 +627,7 @@ def FeatureCFLT : ExtensionWithMArch<"cflt", "CFLT", "FEAT_CFLT",
def FeatureLSC64B : ExtensionWithMArch<"lsc64b", "LSC64B", "FEAT_LSC64B",
"Enable Armv9.8-A Single-copy atomic 64-byte load/store consistency extension", [FeatureLSCP]>;
-def FeatureSVE_LRCPC: ExtensionWithMArch<"sve-lrcpc", "SVE_LRCPC", "FEAT_SVE_LRCPC",
+def FeatureSVE_RCPC: ExtensionWithMArch<"sve-rcpc", "SVE_RCPC", "FEAT_SVE_LRCPC",
"Enable Armv9.8-A SVE weaker Release Consistency processor consistent (RCpc) model",
[FeatureSVE2, FeatureRCPC3]>;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index f61576ef66e026..07d8d79555b84a 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -241,8 +241,8 @@ def HasCFLT : Predicate<"Subtarget->hasCFLT()">,
AssemblerPredicateWithAll<(all_of FeatureCFLT), "cflt">;
def HasLSC64B : Predicate<"Subtarget->hasLSC64B()">,
AssemblerPredicateWithAll<(all_of FeatureLSC64B), "lsc64b">;
-def HasSVE_LRCPC : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE_LRCPC()">,
- AssemblerPredicateWithAll<(all_of FeatureSVE_LRCPC), "sve-lrcpc">;
+def HasSVE_RCPC : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE_RCPC()">,
+ AssemblerPredicateWithAll<(all_of FeatureSVE_RCPC), "sve-rcpc">;
// A subset of SVE(2) instructions are legal in Streaming SVE execution mode,
// they should be enabled if either has been specified.
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 537fe185d7c231..9662d7a0cb9f97 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -5330,7 +5330,11 @@ let Predicates = [HasSVE, HasCPA] in {
//===----------------------------------------------------------------------===//
// Load-Acquire/Store-Release octaword (FEAT_SVE_LRCPC)
//===----------------------------------------------------------------------===//
-let Predicates = [HasSVE_LRCPC] in {
- defm LDAPRO_ZXI : sve_mem_z_acq_fill<"ldapro">;
- defm STLRO_ZXI : sve_mem_z_rel_spill<"stlro">;
+let Predicates = [HasSVE_RCPC] in {
+ defm LDAPRO_ZXI : sve_mem_z_ordered<"ldapro", (outs ZPRAny:$Zt),
+ (ins GPR64sp:$Rn, uimm8s32:$imm),
+ 0b10000101100, 0b011, 1>;
+ defm STLRO_ZXI : sve_mem_z_ordered<"stlro", (outs),
+ (ins ZPRAny:$Zt, GPR64sp:$Rn, uimm8s32:$imm),
+ 0b11100101110, 0b000, 0>;
}
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 41a850a36af7b3..ce50ff30f14cba 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3764,7 +3764,7 @@ constexpr EnumStringDef<FeatureBitset> ExtensionDefs[] = {
{{"wfxt"}, {AArch64::FeatureWFxT}},
{{"cflt"}, {AArch64::FeatureCFLT}},
{{"lsc64b"}, {AArch64::FeatureLSC64B}},
- {{"sve-lrcpc"}, {AArch64::FeatureSVE_LRCPC}},
+ {{"sve-rcpc"}, {AArch64::FeatureSVE_RCPC}},
};
constexpr auto ExtensionMap = BUILD_ENUM_STRINGS(ExtensionDefs);
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 7b1aade4cc004a..2ebae0a431f93f 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -11594,47 +11594,26 @@ multiclass sve2_int_to_fp_upcvt<string asm, bits<2> U, SDPatternOperator op> {
//===----------------------------------------------------------------------===//
// SVE ordered load/store
//===----------------------------------------------------------------------===//
-class sve_mem_z_acq_fill_inst<string mnemonic> :
- I<(outs ZPRAny:$Zt), (ins GPR64sp:$Rn, uimm8s32:$imm), mnemonic,
- "\t$Zt, [$Rn, $imm]", "", []>, Sched<[]> {
+class sve_mem_z_ordered_inst<string mnemonic, dag oops, dag iops,
+ bits<11> opc, bits<3> opc2> :
+ I<oops, iops, mnemonic, "\t$Zt, [$Rn, $imm]", "", []>, Sched<[]> {
bits<5> Zt;
bits<5> Rn;
bits<8> imm;
- let Inst{31-21} = 0b10000101100;
+ let Inst{31-21} = opc;
let Inst{20-16} = imm{7-3};
- let Inst{15-13} = 0b011;
+ let Inst{15-13} = opc2;
let Inst{12-10} = imm{2-0};
let Inst{9-5} = Rn;
let Inst{4-0} = Zt;
-
- let mayLoad = 1;
}
-class sve_mem_z_rel_spill_inst<string mnemonic> :
- I<(outs ), (ins ZPRAny:$Zt, GPR64sp:$Rn, uimm8s32:$imm), mnemonic,
- "\t$Zt, [$Rn, $imm]", "", []>, Sched<[]> {
- bits<5> Zt;
- bits<5> Rn;
- bits<8> imm;
- let Inst{31-21} = 0b11100101110;
- let Inst{20-16} = imm{7-3};
- let Inst{15-13} = 0b000;
- let Inst{12-10} = imm{2-0};
- let Inst{9-5} = Rn;
- let Inst{4-0} = Zt;
-
- let mayStore = 1;
-}
-
-multiclass sve_mem_z_acq_fill<string mnemonic> {
- def NAME : sve_mem_z_acq_fill_inst<mnemonic>;
-
- def : InstAlias<mnemonic # "\t$Zt, [$Rn]",
- (!cast<Instruction>(NAME) ZPRAny:$Zt, GPR64sp:$Rn, 0), 1>;
-}
-
-multiclass sve_mem_z_rel_spill<string mnemonic> {
- def NAME : sve_mem_z_rel_spill_inst<mnemonic>;
+multiclass sve_mem_z_ordered<string mnemonic, dag oops, dag iops,
+ bits<11> opc, bits<3> opc2, bit isLoad> {
+ def NAME : sve_mem_z_ordered_inst<mnemonic, oops, iops, opc, opc2> {
+ let mayLoad = isLoad;
+ let mayStore = !not(isLoad);
+ }
def : InstAlias<mnemonic # "\t$Zt, [$Rn]",
(!cast<Instruction>(NAME) ZPRAny:$Zt, GPR64sp:$Rn, 0), 1>;
diff --git a/llvm/test/MC/AArch64/SVE/ldapro-stlro-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldapro-stlro-diagnostics.s
index 09ee27afb020fe..562fa8ecabd252 100644
--- a/llvm/test/MC/AArch64/SVE/ldapro-stlro-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ldapro-stlro-diagnostics.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -triple=aarch64 -mattr=+sve,+sve-lrcpc < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple=aarch64 -mattr=+sve,+sve-rcpc < %s 2>&1 | FileCheck %s
ldapro z2, [x6, #177]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [0, 8160].
diff --git a/llvm/test/MC/AArch64/SVE/ldapro-stlro.s b/llvm/test/MC/AArch64/SVE/ldapro-stlro.s
index 7443899e2f5b7f..05b2903907d83a 100644
--- a/llvm/test/MC/AArch64/SVE/ldapro-stlro.s
+++ b/llvm/test/MC/AArch64/SVE/ldapro-stlro.s
@@ -1,62 +1,62 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve,+sve-lrcpc < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve,+sve-rcpc < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve,+sve-lrcpc < %s \
-// RUN: | llvm-objdump -d --mattr=+sve,+sve-lrcpc --no-print-imm-hex - \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve,+sve-rcpc < %s \
+// RUN: | llvm-objdump -d --mattr=+sve,+sve-rcpc --no-print-imm-hex - \
// RUN: | FileCheck %s --check-prefix=CHECK-INST
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve,+sve-lrcpc < %s \
-// RUN: | llvm-objdump -d --mattr=+sve,-sve-lrcpc --no-print-imm-hex - \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve,+sve-rcpc < %s \
+// RUN: | llvm-objdump -d --mattr=+sve,-sve-rcpc --no-print-imm-hex - \
// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve,+sve-lrcpc < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve,+sve-rcpc < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
-// RUN: | llvm-mc -triple=aarch64 -mattr=+sve,+sve-lrcpc -disassemble -show-encoding \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve,+sve-rcpc -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
ldapro z0, [x0]
// CHECK-INST: ldapro z0, [x0]
// CHECK-ENCODING: encoding: [0x00,0x60,0x80,0x85]
-// CHECK-ERROR: instruction requires: sve-lrcpc
+// CHECK-ERROR: instruction requires: sve-rcpc
// CHECK-UNKNOWN: 85806000 <unknown>
ldapro z31, [x0, #0]
// CHECK-INST: ldapro z31, [x0]
// CHECK-ENCODING: encoding: [0x1f,0x60,0x80,0x85]
-// CHECK-ERROR: instruction requires: sve-lrcpc
+// CHECK-ERROR: instruction requires: sve-rcpc
// CHECK-UNKNOWN: 8580601f <unknown>
ldapro z0, [sp, #2720]
// CHECK-INST: ldapro z0, [sp, #2720]
// CHECK-ENCODING: encoding: [0xe0,0x77,0x8a,0x85]
-// CHECK-ERROR: instruction requires: sve-lrcpc
+// CHECK-ERROR: instruction requires: sve-rcpc
// CHECK-UNKNOWN: 858a77e0 <unknown>
ldapro z31, [sp, #8160]
// CHECK-INST: ldapro z31, [sp, #8160]
// CHECK-ENCODING: encoding: [0xff,0x7f,0x9f,0x85]
-// CHECK-ERROR: instruction requires: sve-lrcpc
+// CHECK-ERROR: instruction requires: sve-rcpc
// CHECK-UNKNOWN: 859f7fff <unknown>
stlro z0, [x0]
// CHECK-INST: stlro z0, [x0]
// CHECK-ENCODING: encoding: [0x00,0x00,0xc0,0xe5]
-// CHECK-ERROR: instruction requires: sve-lrcpc
+// CHECK-ERROR: instruction requires: sve-rcpc
// CHECK-UNKNOWN: e5c00000 <unknown>
stlro z31, [x0, #0]
// CHECK-INST: stlro z31, [x0]
// CHECK-ENCODING: encoding: [0x1f,0x00,0xc0,0xe5]
-// CHECK-ERROR: instruction requires: sve-lrcpc
+// CHECK-ERROR: instruction requires: sve-rcpc
// CHECK-UNKNOWN: e5c0001f <unknown>
stlro z0, [sp, #2720]
// CHECK-INST: stlro z0, [sp, #2720]
// CHECK-ENCODING: encoding: [0xe0,0x17,0xca,0xe5]
-// CHECK-ERROR: instruction requires: sve-lrcpc
+// CHECK-ERROR: instruction requires: sve-rcpc
// CHECK-UNKNOWN: e5ca17e0 <unknown>
stlro z31, [sp, #8160]
// CHECK-INST: stlro z31, [sp, #8160]
// CHECK-ENCODING: encoding: [0xff,0x1f,0xdf,0xe5]
-// CHECK-ERROR: instruction requires: sve-lrcpc
+// CHECK-ERROR: instruction requires: sve-rcpc
// CHECK-UNKNOWN: e5df1fff <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s b/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
index 6410c394d92067..f0d47664f08a79 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
@@ -65,8 +65,8 @@ bfscale z0.h, p0/m, z0.h, z0.h
// CHECK: error: instruction requires: sve-bfscale
// CHECK-NEXT: bfscale z0.h, p0/m, z0.h, z0.h
-.arch armv9.6-a+sve-lrcpc
-.arch armv9.6-a+nosve-lrcpc
+.arch armv9.6-a+sve-rcpc
+.arch armv9.6-a+nosve-rcpc
ldapro z0, [x0]
-// CHECK: error: instruction requires: sve-lrcpc
+// CHECK: error: instruction requires: sve-rcpc
// CHECK-NEXT: ldapro z0, [x0]
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch.s b/llvm/test/MC/AArch64/SVE2/directive-arch.s
index 4eb4e144f059f6..5f042ca3866230 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch.s
@@ -44,6 +44,6 @@ fmmla z23.s, z13.h, z8.h
bfscale z0.h, p0/m, z0.h, z0.h
// CHECK: bfscale z0.h, p0/m, z0.h, z0.h
-.arch armv9.6-a+sve-lrcpc
+.arch armv9.6-a+sve-rcpc
ldapro z0, [x0]
// CHECK: ldapro z0, [x0]
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
index 712644136c8ac7..c03e7deb6490b0 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
@@ -61,8 +61,8 @@ bfscale z0.h, p0/m, z0.h, z0.h
// CHECK: error: instruction requires: sve-bfscale
// CHECK-NEXT: bfscale z0.h, p0/m, z0.h, z0.h
-.arch_extension sve-lrcpc
-.arch_extension nosve-lrcpc
+.arch_extension sve-rcpc
+.arch_extension nosve-rcpc
ldapro z0, [x0]
-// CHECK: error: instruction requires: sve-lrcpc
+// CHECK: error: instruction requires: sve-rcpc
// CHECK-NEXT: ldapro z0, [x0]
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s b/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
index 34e1182b329011..940d7f179f5e20 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
@@ -40,6 +40,6 @@ fmmla z23.s, z13.h, z8.h
bfscale z0.h, p0/m, z0.h, z0.h
// CHECK: bfscale z0.h, p0/m, z0.h, z0.h
-.arch_extension sve-lrcpc
+.arch_extension sve-rcpc
ldapro z0, [x0]
// CHECK: ldapro z0, [x0]
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 2b6e36cd46a16f..bb557e98a5e7db 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1509,7 +1509,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_POPS, AArch64::AEK_SVESM4,
AArch64::AEK_MTETC, AArch64::AEK_HINTE,
AArch64::AEK_CFLT, AArch64::AEK_LSC64B,
- AArch64::AEK_SVE_LRCPC,
+ AArch64::AEK_SVE_RCPC,
};
std::vector<StringRef> Features;
@@ -1636,7 +1636,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
EXPECT_TRUE(llvm::is_contained(Features, "+hinte"));
EXPECT_TRUE(llvm::is_contained(Features, "+cflt"));
EXPECT_TRUE(llvm::is_contained(Features, "+lsc64b"));
- EXPECT_TRUE(llvm::is_contained(Features, "+sve-lrcpc"));
+ EXPECT_TRUE(llvm::is_contained(Features, "+sve-rcpc"));
// Assuming we listed every extension above, this should produce the same
// result.
@@ -1820,7 +1820,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
{"hinte", "nohinte", "+hinte", "-hinte"},
{"cflt", "nocflt", "+cflt", "-cflt"},
{"lsc64b", "nolsc64b", "+lsc64b", "-lsc64b"},
- {"sve-lrcpc", "nosve-lrcpc", "+sve-lrcpc", "-sve-lrcpc"},
+ {"sve-rcpc", "nosve-rcpc", "+sve-rcpc", "-sve-rcpc"},
};
for (unsigned i = 0; i < std::size(ArchExt); i++) {
@@ -2128,7 +2128,7 @@ AArch64ExtensionDependenciesBaseArchTestParams
{AArch64::ARMV8A, {"sve-aes", "noaes"}, {}, {"aes", "sve-aes"}},
// sve2 ->
- // {sve2p1, sve2-bitperm, sve2-sha3, sve2-sm4, sve2-aes, sve-lrcpc}
+ // {sve2p1, sve2-bitperm, sve2-sha3, sve2-sm4, sve2-aes, sve-rcpc}
{AArch64::ARMV8A, {"nosve2", "sve2p1"}, {"sve2", "sve2p1"}, {}},
{AArch64::ARMV8A, {"sve2p1", "nosve2"}, {}, {"sve2", "sve2p1"}},
{AArch64::ARMV8A,
@@ -2155,13 +2155,13 @@ AArch64ExtensionDependenciesBaseArchTestParams
{AArch64::ARMV8A, {"sve2-aes", "nosve2"}, {}, {"sve2", "sve2-aes"}},
{AArch64::ARMV8A,
- {"nosve2", "sve-lrcpc"},
- {"sve2", "sve-lrcpc"},
+ {"nosve2", "sve-rcpc"},
+ {"sve2", "sve-rcpc"},
{}},
{AArch64::ARMV8A,
- {"sve-lrcpc", "nosve2"},
+ {"sve-rcpc", "nosve2"},
{},
- {"sve2", "sve-lrcpc"}},
+ {"sve2", "sve-rcpc"}},
// sve-b16b16 -> {sme-b16b16}
{AArch64::ARMV9_4A,
@@ -2300,15 +2300,15 @@ AArch64ExtensionDependenciesBaseArchTestParams
{AArch64::ARMV8A, {"norcpc", "rcpc3"}, {"rcpc", "rcpc3"}, {}},
{AArch64::ARMV8A, {"rcpc3", "norcpc"}, {}, {"rcpc", "rcpc3"}},
- // rcpc3 -> sve-lrcpc
+ // rcpc3 -> sve-rcpc
{AArch64::ARMV8A,
- {"norcpc3", "sve-lrcpc"},
- {"rcpc3", "sve-lrcpc"},
+ {"norcpc3", "sve-rcpc"},
+ {"rcpc3", "sve-rcpc"},
{}},
{AArch64::ARMV8A,
- {"sve-lrcpc", "norcpc3"},
+ {"sve-rcpc", "norcpc3"},
{},
- {"rcpc3", "sve-lrcpc"}},
+ {"rcpc3", "sve-rcpc"}},
// sve-aes -> {ssve-aes, sve2-aes}
{AArch64::ARMV9_6A,
>From cd5a26aeecc729fb6662505af576ed712e8c3e1e Mon Sep 17 00:00:00 2001
From: Martin Wehking <martin.wehking at arm.com>
Date: Wed, 14 Oct 2026 08:08:14 +0000
Subject: [PATCH 3/5] fixup! Format touched lines in d7e23bf95f9d
---
.../TargetParser/TargetParserTest.cpp | 20 ++++---------------
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index bb557e98a5e7db..ca977888ed3f76 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -2154,14 +2154,8 @@ AArch64ExtensionDependenciesBaseArchTestParams
{AArch64::ARMV8A, {"nosve2", "sve2-aes"}, {"sve2", "sve2-aes"}, {}},
{AArch64::ARMV8A, {"sve2-aes", "nosve2"}, {}, {"sve2", "sve2-aes"}},
- {AArch64::ARMV8A,
- {"nosve2", "sve-rcpc"},
- {"sve2", "sve-rcpc"},
- {}},
- {AArch64::ARMV8A,
- {"sve-rcpc", "nosve2"},
- {},
- {"sve2", "sve-rcpc"}},
+ {AArch64::ARMV8A, {"nosve2", "sve-rcpc"}, {"sve2", "sve-rcpc"}, {}},
+ {AArch64::ARMV8A, {"sve-rcpc", "nosve2"}, {}, {"sve2", "sve-rcpc"}},
// sve-b16b16 -> {sme-b16b16}
{AArch64::ARMV9_4A,
@@ -2301,14 +2295,8 @@ AArch64ExtensionDependenciesBaseArchTestParams
{AArch64::ARMV8A, {"rcpc3", "norcpc"}, {}, {"rcpc", "rcpc3"}},
// rcpc3 -> sve-rcpc
- {AArch64::ARMV8A,
- {"norcpc3", "sve-rcpc"},
- {"rcpc3", "sve-rcpc"},
- {}},
- {AArch64::ARMV8A,
- {"sve-rcpc", "norcpc3"},
- {},
- {"rcpc3", "sve-rcpc"}},
+ {AArch64::ARMV8A, {"norcpc3", "sve-rcpc"}, {"rcpc3", "sve-rcpc"}, {}},
+ {AArch64::ARMV8A, {"sve-rcpc", "norcpc3"}, {}, {"rcpc3", "sve-rcpc"}},
// sve-aes -> {ssve-aes, sve2-aes}
{AArch64::ARMV9_6A,
>From 4eb44be46f29a1eab2620f9de00f4659cdb6b86f Mon Sep 17 00:00:00 2001
From: Martin Wehking <martin.wehking at arm.com>
Date: Thu, 15 Oct 2026 07:46:16 +0000
Subject: [PATCH 4/5] Revert "fixup! Change extension name + combine classes"
This reverts commit d7e23bf95f9d159ccad71f7f882769dc316f0320.
---
clang/test/Driver/aarch64-v98a.c | 6 ++--
.../print-supported-extensions-aarch64.c | 2 +-
llvm/lib/Target/AArch64/AArch64Features.td | 2 +-
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 4 +--
.../lib/Target/AArch64/AArch64SVEInstrInfo.td | 2 +-
.../AArch64/AsmParser/AArch64AsmParser.cpp | 2 +-
.../MC/AArch64/SVE/ldapro-stlro-diagnostics.s | 2 +-
llvm/test/MC/AArch64/SVE/ldapro-stlro.s | 30 +++++++++----------
.../MC/AArch64/SVE2/directive-arch-negative.s | 6 ++--
llvm/test/MC/AArch64/SVE2/directive-arch.s | 2 +-
.../SVE2/directive-arch_extension-negative.s | 6 ++--
.../AArch64/SVE2/directive-arch_extension.s | 2 +-
.../TargetParser/TargetParserTest.cpp | 18 +++++------
13 files changed, 42 insertions(+), 42 deletions(-)
diff --git a/clang/test/Driver/aarch64-v98a.c b/clang/test/Driver/aarch64-v98a.c
index 1a41a97610e595..7233e694211ca8 100644
--- a/clang/test/Driver/aarch64-v98a.c
+++ b/clang/test/Driver/aarch64-v98a.c
@@ -26,6 +26,6 @@
// RUN: %clang -target aarch64 -march=armv9.8-a+lsc64b -### -c %s 2>&1 | FileCheck -check-prefix=V98A-LSC64B %s
// V98A-LSC64B: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.8a"{{.*}} "-target-feature" "+lsc64b"
//
-// RUN: %clang -target aarch64 -march=armv9.8a+sve-rcpc -### -c %s 2>&1 | FileCheck -check-prefix=V98A-SVE-RCPC %s
-// RUN: %clang -target aarch64 -march=armv9.8-a+sve-rcpc -### -c %s 2>&1 | FileCheck -check-prefix=V98A-SVE-RCPC %s
-// V98A-SVE-RCPC: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.8a"{{.*}} "-target-feature" "+sve-rcpc"
+// RUN: %clang -target aarch64 -march=armv9.8a+sve-lrcpc -### -c %s 2>&1 | FileCheck -check-prefix=V98A-SVE-LRCPC %s
+// RUN: %clang -target aarch64 -march=armv9.8-a+sve-lrcpc -### -c %s 2>&1 | FileCheck -check-prefix=V98A-SVE-LRCPC %s
+// V98A-SVE-LRCPC: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.8a"{{.*}} "-target-feature" "+sve-lrcpc"
diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c b/clang/test/Driver/print-supported-extensions-aarch64.c
index e334d2e8dcee00..9d2e00670f7420 100644
--- a/clang/test/Driver/print-supported-extensions-aarch64.c
+++ b/clang/test/Driver/print-supported-extensions-aarch64.c
@@ -105,7 +105,7 @@
// CHECK-NEXT: sve-bfscale FEAT_SVE_BFSCALE Enable Armv9.6-A SVE BFloat16 scaling instructions
// CHECK-NEXT: sve-bitperm FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
// CHECK-NEXT: sve-f16f32mm FEAT_SVE_F16F32MM Enable Armv9.6-A FP16 to FP32 Matrix Multiply
-// CHECK-NEXT: sve-rcpc FEAT_SVE_LRCPC Enable Armv9.8-A SVE weaker Release Consistency processor consistent (RCpc) model
+// CHECK-NEXT: sve-lrcpc FEAT_SVE_LRCPC Enable Armv9.8-A SVE weaker Release Consistency processor consistent (RCpc) model
// CHECK-NEXT: sve-sha3 FEAT_SVE_SHA3 Enable SVE SHA3 instructions
// CHECK-NEXT: sve-sm4 FEAT_SVE_SM4 Enable SVE SM4 instructions
// CHECK-NEXT: sve2 FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index 0434ec5d26ee85..fa23c2f43f6c97 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -627,7 +627,7 @@ def FeatureCFLT : ExtensionWithMArch<"cflt", "CFLT", "FEAT_CFLT",
def FeatureLSC64B : ExtensionWithMArch<"lsc64b", "LSC64B", "FEAT_LSC64B",
"Enable Armv9.8-A Single-copy atomic 64-byte load/store consistency extension", [FeatureLSCP]>;
-def FeatureSVE_RCPC: ExtensionWithMArch<"sve-rcpc", "SVE_RCPC", "FEAT_SVE_LRCPC",
+def FeatureSVE_LRCPC: ExtensionWithMArch<"sve-lrcpc", "SVE_LRCPC", "FEAT_SVE_LRCPC",
"Enable Armv9.8-A SVE weaker Release Consistency processor consistent (RCpc) model",
[FeatureSVE2, FeatureRCPC3]>;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 07d8d79555b84a..f61576ef66e026 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -241,8 +241,8 @@ def HasCFLT : Predicate<"Subtarget->hasCFLT()">,
AssemblerPredicateWithAll<(all_of FeatureCFLT), "cflt">;
def HasLSC64B : Predicate<"Subtarget->hasLSC64B()">,
AssemblerPredicateWithAll<(all_of FeatureLSC64B), "lsc64b">;
-def HasSVE_RCPC : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE_RCPC()">,
- AssemblerPredicateWithAll<(all_of FeatureSVE_RCPC), "sve-rcpc">;
+def HasSVE_LRCPC : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE_LRCPC()">,
+ AssemblerPredicateWithAll<(all_of FeatureSVE_LRCPC), "sve-lrcpc">;
// A subset of SVE(2) instructions are legal in Streaming SVE execution mode,
// they should be enabled if either has been specified.
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 9662d7a0cb9f97..1ad615a4a81bad 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -5330,7 +5330,7 @@ let Predicates = [HasSVE, HasCPA] in {
//===----------------------------------------------------------------------===//
// Load-Acquire/Store-Release octaword (FEAT_SVE_LRCPC)
//===----------------------------------------------------------------------===//
-let Predicates = [HasSVE_RCPC] in {
+let Predicates = [HasSVE_LRCPC] in {
defm LDAPRO_ZXI : sve_mem_z_ordered<"ldapro", (outs ZPRAny:$Zt),
(ins GPR64sp:$Rn, uimm8s32:$imm),
0b10000101100, 0b011, 1>;
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index ce50ff30f14cba..41a850a36af7b3 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3764,7 +3764,7 @@ constexpr EnumStringDef<FeatureBitset> ExtensionDefs[] = {
{{"wfxt"}, {AArch64::FeatureWFxT}},
{{"cflt"}, {AArch64::FeatureCFLT}},
{{"lsc64b"}, {AArch64::FeatureLSC64B}},
- {{"sve-rcpc"}, {AArch64::FeatureSVE_RCPC}},
+ {{"sve-lrcpc"}, {AArch64::FeatureSVE_LRCPC}},
};
constexpr auto ExtensionMap = BUILD_ENUM_STRINGS(ExtensionDefs);
diff --git a/llvm/test/MC/AArch64/SVE/ldapro-stlro-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldapro-stlro-diagnostics.s
index 562fa8ecabd252..09ee27afb020fe 100644
--- a/llvm/test/MC/AArch64/SVE/ldapro-stlro-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ldapro-stlro-diagnostics.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -triple=aarch64 -mattr=+sve,+sve-rcpc < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple=aarch64 -mattr=+sve,+sve-lrcpc < %s 2>&1 | FileCheck %s
ldapro z2, [x6, #177]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [0, 8160].
diff --git a/llvm/test/MC/AArch64/SVE/ldapro-stlro.s b/llvm/test/MC/AArch64/SVE/ldapro-stlro.s
index 05b2903907d83a..7443899e2f5b7f 100644
--- a/llvm/test/MC/AArch64/SVE/ldapro-stlro.s
+++ b/llvm/test/MC/AArch64/SVE/ldapro-stlro.s
@@ -1,62 +1,62 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve,+sve-rcpc < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve,+sve-lrcpc < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve,+sve-rcpc < %s \
-// RUN: | llvm-objdump -d --mattr=+sve,+sve-rcpc --no-print-imm-hex - \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve,+sve-lrcpc < %s \
+// RUN: | llvm-objdump -d --mattr=+sve,+sve-lrcpc --no-print-imm-hex - \
// RUN: | FileCheck %s --check-prefix=CHECK-INST
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve,+sve-rcpc < %s \
-// RUN: | llvm-objdump -d --mattr=+sve,-sve-rcpc --no-print-imm-hex - \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve,+sve-lrcpc < %s \
+// RUN: | llvm-objdump -d --mattr=+sve,-sve-lrcpc --no-print-imm-hex - \
// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve,+sve-rcpc < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve,+sve-lrcpc < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
-// RUN: | llvm-mc -triple=aarch64 -mattr=+sve,+sve-rcpc -disassemble -show-encoding \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve,+sve-lrcpc -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
ldapro z0, [x0]
// CHECK-INST: ldapro z0, [x0]
// CHECK-ENCODING: encoding: [0x00,0x60,0x80,0x85]
-// CHECK-ERROR: instruction requires: sve-rcpc
+// CHECK-ERROR: instruction requires: sve-lrcpc
// CHECK-UNKNOWN: 85806000 <unknown>
ldapro z31, [x0, #0]
// CHECK-INST: ldapro z31, [x0]
// CHECK-ENCODING: encoding: [0x1f,0x60,0x80,0x85]
-// CHECK-ERROR: instruction requires: sve-rcpc
+// CHECK-ERROR: instruction requires: sve-lrcpc
// CHECK-UNKNOWN: 8580601f <unknown>
ldapro z0, [sp, #2720]
// CHECK-INST: ldapro z0, [sp, #2720]
// CHECK-ENCODING: encoding: [0xe0,0x77,0x8a,0x85]
-// CHECK-ERROR: instruction requires: sve-rcpc
+// CHECK-ERROR: instruction requires: sve-lrcpc
// CHECK-UNKNOWN: 858a77e0 <unknown>
ldapro z31, [sp, #8160]
// CHECK-INST: ldapro z31, [sp, #8160]
// CHECK-ENCODING: encoding: [0xff,0x7f,0x9f,0x85]
-// CHECK-ERROR: instruction requires: sve-rcpc
+// CHECK-ERROR: instruction requires: sve-lrcpc
// CHECK-UNKNOWN: 859f7fff <unknown>
stlro z0, [x0]
// CHECK-INST: stlro z0, [x0]
// CHECK-ENCODING: encoding: [0x00,0x00,0xc0,0xe5]
-// CHECK-ERROR: instruction requires: sve-rcpc
+// CHECK-ERROR: instruction requires: sve-lrcpc
// CHECK-UNKNOWN: e5c00000 <unknown>
stlro z31, [x0, #0]
// CHECK-INST: stlro z31, [x0]
// CHECK-ENCODING: encoding: [0x1f,0x00,0xc0,0xe5]
-// CHECK-ERROR: instruction requires: sve-rcpc
+// CHECK-ERROR: instruction requires: sve-lrcpc
// CHECK-UNKNOWN: e5c0001f <unknown>
stlro z0, [sp, #2720]
// CHECK-INST: stlro z0, [sp, #2720]
// CHECK-ENCODING: encoding: [0xe0,0x17,0xca,0xe5]
-// CHECK-ERROR: instruction requires: sve-rcpc
+// CHECK-ERROR: instruction requires: sve-lrcpc
// CHECK-UNKNOWN: e5ca17e0 <unknown>
stlro z31, [sp, #8160]
// CHECK-INST: stlro z31, [sp, #8160]
// CHECK-ENCODING: encoding: [0xff,0x1f,0xdf,0xe5]
-// CHECK-ERROR: instruction requires: sve-rcpc
+// CHECK-ERROR: instruction requires: sve-lrcpc
// CHECK-UNKNOWN: e5df1fff <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s b/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
index f0d47664f08a79..6410c394d92067 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
@@ -65,8 +65,8 @@ bfscale z0.h, p0/m, z0.h, z0.h
// CHECK: error: instruction requires: sve-bfscale
// CHECK-NEXT: bfscale z0.h, p0/m, z0.h, z0.h
-.arch armv9.6-a+sve-rcpc
-.arch armv9.6-a+nosve-rcpc
+.arch armv9.6-a+sve-lrcpc
+.arch armv9.6-a+nosve-lrcpc
ldapro z0, [x0]
-// CHECK: error: instruction requires: sve-rcpc
+// CHECK: error: instruction requires: sve-lrcpc
// CHECK-NEXT: ldapro z0, [x0]
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch.s b/llvm/test/MC/AArch64/SVE2/directive-arch.s
index 5f042ca3866230..4eb4e144f059f6 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch.s
@@ -44,6 +44,6 @@ fmmla z23.s, z13.h, z8.h
bfscale z0.h, p0/m, z0.h, z0.h
// CHECK: bfscale z0.h, p0/m, z0.h, z0.h
-.arch armv9.6-a+sve-rcpc
+.arch armv9.6-a+sve-lrcpc
ldapro z0, [x0]
// CHECK: ldapro z0, [x0]
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
index c03e7deb6490b0..712644136c8ac7 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
@@ -61,8 +61,8 @@ bfscale z0.h, p0/m, z0.h, z0.h
// CHECK: error: instruction requires: sve-bfscale
// CHECK-NEXT: bfscale z0.h, p0/m, z0.h, z0.h
-.arch_extension sve-rcpc
-.arch_extension nosve-rcpc
+.arch_extension sve-lrcpc
+.arch_extension nosve-lrcpc
ldapro z0, [x0]
-// CHECK: error: instruction requires: sve-rcpc
+// CHECK: error: instruction requires: sve-lrcpc
// CHECK-NEXT: ldapro z0, [x0]
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s b/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
index 940d7f179f5e20..34e1182b329011 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
@@ -40,6 +40,6 @@ fmmla z23.s, z13.h, z8.h
bfscale z0.h, p0/m, z0.h, z0.h
// CHECK: bfscale z0.h, p0/m, z0.h, z0.h
-.arch_extension sve-rcpc
+.arch_extension sve-lrcpc
ldapro z0, [x0]
// CHECK: ldapro z0, [x0]
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index ca977888ed3f76..58d9097377a107 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1509,7 +1509,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_POPS, AArch64::AEK_SVESM4,
AArch64::AEK_MTETC, AArch64::AEK_HINTE,
AArch64::AEK_CFLT, AArch64::AEK_LSC64B,
- AArch64::AEK_SVE_RCPC,
+ AArch64::AEK_SVE_LRCPC,
};
std::vector<StringRef> Features;
@@ -1636,7 +1636,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
EXPECT_TRUE(llvm::is_contained(Features, "+hinte"));
EXPECT_TRUE(llvm::is_contained(Features, "+cflt"));
EXPECT_TRUE(llvm::is_contained(Features, "+lsc64b"));
- EXPECT_TRUE(llvm::is_contained(Features, "+sve-rcpc"));
+ EXPECT_TRUE(llvm::is_contained(Features, "+sve-lrcpc"));
// Assuming we listed every extension above, this should produce the same
// result.
@@ -1820,7 +1820,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
{"hinte", "nohinte", "+hinte", "-hinte"},
{"cflt", "nocflt", "+cflt", "-cflt"},
{"lsc64b", "nolsc64b", "+lsc64b", "-lsc64b"},
- {"sve-rcpc", "nosve-rcpc", "+sve-rcpc", "-sve-rcpc"},
+ {"sve-lrcpc", "nosve-lrcpc", "+sve-lrcpc", "-sve-lrcpc"},
};
for (unsigned i = 0; i < std::size(ArchExt); i++) {
@@ -2128,7 +2128,7 @@ AArch64ExtensionDependenciesBaseArchTestParams
{AArch64::ARMV8A, {"sve-aes", "noaes"}, {}, {"aes", "sve-aes"}},
// sve2 ->
- // {sve2p1, sve2-bitperm, sve2-sha3, sve2-sm4, sve2-aes, sve-rcpc}
+ // {sve2p1, sve2-bitperm, sve2-sha3, sve2-sm4, sve2-aes, sve-lrcpc}
{AArch64::ARMV8A, {"nosve2", "sve2p1"}, {"sve2", "sve2p1"}, {}},
{AArch64::ARMV8A, {"sve2p1", "nosve2"}, {}, {"sve2", "sve2p1"}},
{AArch64::ARMV8A,
@@ -2154,8 +2154,8 @@ AArch64ExtensionDependenciesBaseArchTestParams
{AArch64::ARMV8A, {"nosve2", "sve2-aes"}, {"sve2", "sve2-aes"}, {}},
{AArch64::ARMV8A, {"sve2-aes", "nosve2"}, {}, {"sve2", "sve2-aes"}},
- {AArch64::ARMV8A, {"nosve2", "sve-rcpc"}, {"sve2", "sve-rcpc"}, {}},
- {AArch64::ARMV8A, {"sve-rcpc", "nosve2"}, {}, {"sve2", "sve-rcpc"}},
+ {AArch64::ARMV8A, {"nosve2", "sve-lrcpc"}, {"sve2", "sve-lrcpc"}, {}},
+ {AArch64::ARMV8A, {"sve-lrcpc", "nosve2"}, {}, {"sve2", "sve-lrcpc"}},
// sve-b16b16 -> {sme-b16b16}
{AArch64::ARMV9_4A,
@@ -2294,9 +2294,9 @@ AArch64ExtensionDependenciesBaseArchTestParams
{AArch64::ARMV8A, {"norcpc", "rcpc3"}, {"rcpc", "rcpc3"}, {}},
{AArch64::ARMV8A, {"rcpc3", "norcpc"}, {}, {"rcpc", "rcpc3"}},
- // rcpc3 -> sve-rcpc
- {AArch64::ARMV8A, {"norcpc3", "sve-rcpc"}, {"rcpc3", "sve-rcpc"}, {}},
- {AArch64::ARMV8A, {"sve-rcpc", "norcpc3"}, {}, {"rcpc3", "sve-rcpc"}},
+ // rcpc3 -> sve-lrcpc
+ {AArch64::ARMV8A, {"norcpc3", "sve-lrcpc"}, {"rcpc3", "sve-lrcpc"}, {}},
+ {AArch64::ARMV8A, {"sve-lrcpc", "norcpc3"}, {}, {"rcpc3", "sve-lrcpc"}},
// sve-aes -> {ssve-aes, sve2-aes}
{AArch64::ARMV9_6A,
>From af6fbb0309bffe9527c06d03a09c0a3eef22e58b Mon Sep 17 00:00:00 2001
From: Martin Wehking <martin.wehking at arm.com>
Date: Fri, 16 Oct 2026 12:03:53 +0000
Subject: [PATCH 5/5] fixup! Revert class split (d7e23bf9)
Keep the Tablegen classes for ldapro and stlro split similar to the existing sve
mem spill/fill classes.
---
.../lib/Target/AArch64/AArch64SVEInstrInfo.td | 8 +---
llvm/lib/Target/AArch64/SVEInstrFormats.td | 43 ++++++++++++++-----
2 files changed, 34 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 1ad615a4a81bad..537fe185d7c231 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -5331,10 +5331,6 @@ let Predicates = [HasSVE, HasCPA] in {
// Load-Acquire/Store-Release octaword (FEAT_SVE_LRCPC)
//===----------------------------------------------------------------------===//
let Predicates = [HasSVE_LRCPC] in {
- defm LDAPRO_ZXI : sve_mem_z_ordered<"ldapro", (outs ZPRAny:$Zt),
- (ins GPR64sp:$Rn, uimm8s32:$imm),
- 0b10000101100, 0b011, 1>;
- defm STLRO_ZXI : sve_mem_z_ordered<"stlro", (outs),
- (ins ZPRAny:$Zt, GPR64sp:$Rn, uimm8s32:$imm),
- 0b11100101110, 0b000, 0>;
+ defm LDAPRO_ZXI : sve_mem_z_acq_fill<"ldapro">;
+ defm STLRO_ZXI : sve_mem_z_rel_spill<"stlro">;
}
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 2ebae0a431f93f..7b1aade4cc004a 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -11594,26 +11594,47 @@ multiclass sve2_int_to_fp_upcvt<string asm, bits<2> U, SDPatternOperator op> {
//===----------------------------------------------------------------------===//
// SVE ordered load/store
//===----------------------------------------------------------------------===//
-class sve_mem_z_ordered_inst<string mnemonic, dag oops, dag iops,
- bits<11> opc, bits<3> opc2> :
- I<oops, iops, mnemonic, "\t$Zt, [$Rn, $imm]", "", []>, Sched<[]> {
+class sve_mem_z_acq_fill_inst<string mnemonic> :
+ I<(outs ZPRAny:$Zt), (ins GPR64sp:$Rn, uimm8s32:$imm), mnemonic,
+ "\t$Zt, [$Rn, $imm]", "", []>, Sched<[]> {
bits<5> Zt;
bits<5> Rn;
bits<8> imm;
- let Inst{31-21} = opc;
+ let Inst{31-21} = 0b10000101100;
let Inst{20-16} = imm{7-3};
- let Inst{15-13} = opc2;
+ let Inst{15-13} = 0b011;
let Inst{12-10} = imm{2-0};
let Inst{9-5} = Rn;
let Inst{4-0} = Zt;
+
+ let mayLoad = 1;
}
-multiclass sve_mem_z_ordered<string mnemonic, dag oops, dag iops,
- bits<11> opc, bits<3> opc2, bit isLoad> {
- def NAME : sve_mem_z_ordered_inst<mnemonic, oops, iops, opc, opc2> {
- let mayLoad = isLoad;
- let mayStore = !not(isLoad);
- }
+class sve_mem_z_rel_spill_inst<string mnemonic> :
+ I<(outs ), (ins ZPRAny:$Zt, GPR64sp:$Rn, uimm8s32:$imm), mnemonic,
+ "\t$Zt, [$Rn, $imm]", "", []>, Sched<[]> {
+ bits<5> Zt;
+ bits<5> Rn;
+ bits<8> imm;
+ let Inst{31-21} = 0b11100101110;
+ let Inst{20-16} = imm{7-3};
+ let Inst{15-13} = 0b000;
+ let Inst{12-10} = imm{2-0};
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Zt;
+
+ let mayStore = 1;
+}
+
+multiclass sve_mem_z_acq_fill<string mnemonic> {
+ def NAME : sve_mem_z_acq_fill_inst<mnemonic>;
+
+ def : InstAlias<mnemonic # "\t$Zt, [$Rn]",
+ (!cast<Instruction>(NAME) ZPRAny:$Zt, GPR64sp:$Rn, 0), 1>;
+}
+
+multiclass sve_mem_z_rel_spill<string mnemonic> {
+ def NAME : sve_mem_z_rel_spill_inst<mnemonic>;
def : InstAlias<mnemonic # "\t$Zt, [$Rn]",
(!cast<Instruction>(NAME) ZPRAny:$Zt, GPR64sp:$Rn, 0), 1>;
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