[clang] 78ed659 - [clang][CIR] Add tests for SVE MINNMV intrinsics (#232199)
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Thu Oct 15 18:57:32 PDT 2026
Author: Chibuoyim (Wilson) Ogbonna
Date: 2026-10-16T09:57:26+08:00
New Revision: 78ed659e5b5577d447f209e55c7c5bdd5f4461fa
URL: https://github.com/llvm/llvm-project/commit/78ed659e5b5577d447f209e55c7c5bdd5f4461fa
DIFF: https://github.com/llvm/llvm-project/commit/78ed659e5b5577d447f209e55c7c5bdd5f4461fa.diff
LOG: [clang][CIR] Add tests for SVE MINNMV intrinsics (#232199)
adds CIR tests for `svminnmv` (plain SVE) intrinsics.
Moves and adapts `sve-intrinsics/acle_sve_minnmv.c` to `sve/minnmv.c`
Part of #223963
Added:
clang/test/CodeGen/AArch64/sve/minnmv.c
Modified:
Removed:
clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnmv.c
################################################################################
diff --git a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnmv.c b/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnmv.c
deleted file mode 100644
index 58293685b16362..00000000000000
--- a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnmv.c
+++ /dev/null
@@ -1,75 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
-// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
-// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
-
-#include <arm_sve.h>
-
-
-#if defined __ARM_FEATURE_SME
-#define MODE_ATTR __arm_streaming
-#else
-#define MODE_ATTR
-#endif
-
-#ifdef SVE_OVERLOADED_FORMS
-// A simple used,unused... macro, long enough to represent any SVE builtin.
-#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
-#else
-#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
-#endif
-
-// CHECK-LABEL: @test_svminnmv_f16(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
-// CHECK-NEXT: [[TMP1:%.*]] = tail call half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
-// CHECK-NEXT: ret half [[TMP1]]
-//
-// CPP-CHECK-LABEL: @_Z17test_svminnmv_f16u10__SVBool_tu13__SVFloat16_t(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
-// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
-// CPP-CHECK-NEXT: ret half [[TMP1]]
-//
-float16_t test_svminnmv_f16(svbool_t pg, svfloat16_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svminnmv,_f16,,)(pg, op);
-}
-
-// CHECK-LABEL: @test_svminnmv_f32(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
-// CHECK-NEXT: [[TMP1:%.*]] = tail call float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
-// CHECK-NEXT: ret float [[TMP1]]
-//
-// CPP-CHECK-LABEL: @_Z17test_svminnmv_f32u10__SVBool_tu13__SVFloat32_t(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
-// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
-// CPP-CHECK-NEXT: ret float [[TMP1]]
-//
-float32_t test_svminnmv_f32(svbool_t pg, svfloat32_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svminnmv,_f32,,)(pg, op);
-}
-
-// CHECK-LABEL: @test_svminnmv_f64(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
-// CHECK-NEXT: [[TMP1:%.*]] = tail call double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
-// CHECK-NEXT: ret double [[TMP1]]
-//
-// CPP-CHECK-LABEL: @_Z17test_svminnmv_f64u10__SVBool_tu13__SVFloat64_t(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
-// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
-// CPP-CHECK-NEXT: ret double [[TMP1]]
-//
-float64_t test_svminnmv_f64(svbool_t pg, svfloat64_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svminnmv,_f64,,)(pg, op);
-}
diff --git a/clang/test/CodeGen/AArch64/sve/minnmv.c b/clang/test/CodeGen/AArch64/sve/minnmv.c
new file mode 100644
index 00000000000000..9432c3e050c84c
--- /dev/null
+++ b/clang/test/CodeGen/AArch64/sve/minnmv.c
@@ -0,0 +1,85 @@
+// REQUIRES: aarch64-registered-target
+
+// DEFINE: %{optimize} = opt -passes=mem2reg -S
+
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -fclangir -emit-cir -disable-O0-optnone -o - %s | FileCheck %s --check-prefixes=C,CIR %}
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-cir -disable-O0-optnone -o - %s | FileCheck %s --check-prefixes=C,CIR %}
+
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -fclangir -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM %}
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM %}
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-llvm -disable-O0-optnone -o - -x c++ %s | %{optimize} | FileCheck %s --check-prefixes=CPP,LLVM %}
+
+// RUN: %clang_cc1_cg_arm64_sve -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM
+// RUN: %clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM
+// RUN: %clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -emit-llvm -disable-O0-optnone -o - -x c++ %s | %{optimize} | FileCheck %s --check-prefixes=CPP,LLVM
+
+// RUN: %clang_cc1_cg_arm64_sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
+
+//=============================================================================
+// NOTES
+//
+// Tests for SVE MINNMV intrinsics
+//=============================================================================
+
+#include <arm_sve.h>
+
+#if defined __ARM_FEATURE_SME
+#define MODE_ATTR __arm_streaming
+#else
+#define MODE_ATTR
+#endif
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+// C-LABEL: @test_svminnmv_f16(
+// CPP-LABEL: @_Z17test_svminnmv_f16u10__SVBool_tu13__SVFloat16_t(
+float16_t test_svminnmv_f16(svbool_t pg, svfloat16_t op) MODE_ATTR
+{
+// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} :
+// CIR-SAME: -> !cir.vector<[8] x !cir.int<u, 1>>
+// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.fminnmv" %[[CONVERT_PG]], %{{.*}} :
+// CIR-SAME: -> !cir.f16
+
+// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 8 x half> [[OP:%.*]])
+// LLVM: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
+// LLVM: [[TMP1:%.*]] = call half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP]])
+// LLVM: ret half [[TMP1]]
+ return SVE_ACLE_FUNC(svminnmv,_f16,,)(pg, op);
+}
+
+// C-LABEL: @test_svminnmv_f32(
+// CPP-LABEL: @_Z17test_svminnmv_f32u10__SVBool_tu13__SVFloat32_t(
+float32_t test_svminnmv_f32(svbool_t pg, svfloat32_t op) MODE_ATTR
+{
+// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} :
+// CIR-SAME: -> !cir.vector<[4] x !cir.int<u, 1>>
+// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.fminnmv" %[[CONVERT_PG]], %{{.*}} :
+// CIR-SAME: -> !cir.float
+
+// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 4 x float> [[OP:%.*]])
+// LLVM: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
+// LLVM: [[TMP1:%.*]] = call float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP]])
+// LLVM: ret float [[TMP1]]
+ return SVE_ACLE_FUNC(svminnmv,_f32,,)(pg, op);
+}
+
+// C-LABEL: @test_svminnmv_f64(
+// CPP-LABEL: @_Z17test_svminnmv_f64u10__SVBool_tu13__SVFloat64_t(
+float64_t test_svminnmv_f64(svbool_t pg, svfloat64_t op) MODE_ATTR
+{
+// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} :
+// CIR-SAME: -> !cir.vector<[2] x !cir.int<u, 1>>
+// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.fminnmv" %[[CONVERT_PG]], %{{.*}} :
+// CIR-SAME: -> !cir.double
+
+// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 2 x double> [[OP:%.*]])
+// LLVM: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
+// LLVM: [[TMP1:%.*]] = call double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP]])
+// LLVM: ret double [[TMP1]]
+ return SVE_ACLE_FUNC(svminnmv,_f64,,)(pg, op);
+}
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