[clang] [CIR] Wire AMDGPU into the call-convention lowering pass (PR #220197)

[Andy Kaylor via cfe-commits]

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@@ -484,14 +484,37 @@ mlir::Value emitCoercionToMemory(mlir::OpBuilder &builder, mlir::Location loc,
                           dstTy == slotTy ? 0 : offset);
 }
 
+/// Cast \p src to \p dstTy when both are pointers to the same pointee, so only
+/// the address space changes.  Returns null when a real coercion is needed.
+static mlir::Value
+emitAddrSpaceCoercion(mlir::OpBuilder &builder, mlir::Location loc,
+                      mlir::Type dstTy, mlir::Value src,
+                      SmallPtrSetImpl<mlir::Operation *> &createdOps,
+                      unsigned offset) {
+  auto srcPtrTy = dyn_cast<cir::PointerType>(src.getType());
+  auto dstPtrTy = dyn_cast<cir::PointerType>(dstTy);
+  if (offset || !srcPtrTy || !dstPtrTy ||
+      srcPtrTy.getPointee() != dstPtrTy.getPointee())
+    return {};
+  auto cast = cir::CastOp::create(builder, loc, dstTy,
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andykaylor wrote:

Can you assert that the address spaces are different? I can't think of anything else that would reach here now, but I can imagine other differences that could be introduced in the future.

https://github.com/llvm/llvm-project/pull/220197