[clang] [llvm] [AArch64][GlobalISel] Do not run the Localizer at -O0 (attempt 2) (PR #231406)
Cullen Rhodes via cfe-commits
cfe-commits at lists.llvm.org
Tue Oct 13 01:08:43 PDT 2026
https://github.com/c-rhodes created https://github.com/llvm/llvm-project/pull/231406
This was disabled earlier this year (#177359) before being shortly reverted due
to two test failures which have since been fixed. The flaky LLDB issue was
fixed in #210050 and the libcxxabi test in #230518.
CTMark aarch64-O0-g geomean improves -0.97%. Code size regresses 2.70% but as
previously we think this is worth paying at O0 where compile-time and debug are
the biggest concern.
https://llvm-compile-time-tracker.com/compare.php?from=fc90bd3cfb0bab14a2bf7cbd33f5f1e904c7e133&to=071f3542ccb3b3c65032397550e862d7090f425f&stat=instructions:u
Assisted-by: codex
Co-authored-by: David Green (davemgreen)
>From 692fd15b1e9b4b237e377c3b86aef75c7bb22350 Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Mon, 12 Oct 2026 14:36:34 +0000
Subject: [PATCH] [AArch64][GlobalISel] Do not run the Localizer at -O0
---
bolt/test/AArch64/icp-inline.c | 4 +-
bolt/test/AArch64/jmp-table-unsupported.s | 2 +-
.../AArch64/instrumentation-ind-call.c | 4 +-
clang/test/CodeGen/memtag-globals-asm.cpp | 25 +--
.../Target/AArch64/AArch64TargetMachine.cpp | 1 -
.../AArch64/GlobalISel/arm64-atomic.ll | 55 +++---
.../atomic-anyextending-load-crash.ll | 4 +-
.../AArch64/GlobalISel/invoke-region.ll | 14 +-
.../AArch64/GlobalISel/legalize-exceptions.ll | 9 +-
.../AArch64/GlobalISel/localizer-arm64-tti.ll | 98 ++++-------
.../localizer-propagate-debug-loc.mir | 37 ++--
.../AArch64/GlobalISel/localizer-tls.ll | 16 +-
.../GlobalISel/select-fp-anyext-crash.ll | 22 +--
.../GlobalISel/translate-constant-dag.ll | 4 +-
llvm/test/CodeGen/AArch64/O0-pipeline.ll | 1 -
llvm/test/CodeGen/AArch64/O3-pipeline.ll | 1 -
.../CodeGen/AArch64/aarch64-fastcc-stackup.ll | 2 +-
llvm/test/CodeGen/AArch64/aarch64-tbz.ll | 12 +-
llvm/test/CodeGen/AArch64/cfguard-checks.ll | 4 +-
llvm/test/CodeGen/AArch64/cpa-globalisel.ll | 166 +++++++++---------
llvm/test/CodeGen/AArch64/large-stack.ll | 15 +-
llvm/test/CodeGen/AArch64/phi-dbg.ll | 3 +-
llvm/test/CodeGen/AArch64/popcount.ll | 38 ++--
llvm/test/CodeGen/AArch64/pr92062.ll | 2 +-
llvm/test/CodeGen/AArch64/vararg.ll | 16 +-
.../CodeGen/AArch64/win64_vararg_float.ll | 12 +-
.../CodeGen/AArch64/win64_vararg_float_cc.ll | 12 +-
llvm/test/Other/print-changed-machine.ll | 2 +-
28 files changed, 289 insertions(+), 292 deletions(-)
diff --git a/bolt/test/AArch64/icp-inline.c b/bolt/test/AArch64/icp-inline.c
index f2a4f47147eaa..97c407223af91 100644
--- a/bolt/test/AArch64/icp-inline.c
+++ b/bolt/test/AArch64/icp-inline.c
@@ -30,8 +30,8 @@ __attribute__((noinline)) int indirectTailCall(int Argc) {
__attribute__((musttail)) return Func(0);
}
-// FDATA: 1 indirectTailCall 28 1 foo 0 0 1
-// FDATA: 1 indirectTailCall 28 1 bar 0 0 2
+// FDATA: 1 indirectTailCall 2c 1 foo 0 0 1
+// FDATA: 1 indirectTailCall 2c 1 bar 0 0 2
int main(int Argc, char **Argv) {
(void)Argv;
diff --git a/bolt/test/AArch64/jmp-table-unsupported.s b/bolt/test/AArch64/jmp-table-unsupported.s
index 1228149430449..ad0f7cef838af 100644
--- a/bolt/test/AArch64/jmp-table-unsupported.s
+++ b/bolt/test/AArch64/jmp-table-unsupported.s
@@ -101,7 +101,7 @@ SECTIONS {
# JT-OBJDUMP-NORMAL: <handleOptionJumpTable>:
# JT-OBJDUMP-NORMAL: adrp
# JT-OBJDUMP-NORMAL-NEXT: add
-# JT-OBJDUMP-NORMAL-NEXT: ldr
+# JT-OBJDUMP-NORMAL: ldr
# JT-OBJDUMP-NORMAL-NEXT: blr
# RUN: llvm-bolt %t/jt_type_normal.exe --dyno-stats \
diff --git a/bolt/test/runtime/AArch64/instrumentation-ind-call.c b/bolt/test/runtime/AArch64/instrumentation-ind-call.c
index 8d9d1e13060f5..a0c1eed7e28bd 100644
--- a/bolt/test/runtime/AArch64/instrumentation-ind-call.c
+++ b/bolt/test/runtime/AArch64/instrumentation-ind-call.c
@@ -35,7 +35,7 @@ RUN: | FileCheck %s --check-prefix=CHECKINDIRECTREG
CHECKINDIRECTREG: mov w0, #0xa
CHECKINDIRECTREG-NEXT: mov w1, #0x14
-CHECKINDIRECTREG-NEXT: blr x8
+CHECKINDIRECTREG: blr x8
RUN: llvm-bolt %t.exe --instrument --instrumentation-file=%t.fdata \
RUN: -o %t.instrumented \
@@ -57,7 +57,7 @@ RUN: %t.instrumented | FileCheck %s --check-prefix=CHECK-INSTR-INDIR-CALL-FUNC
CHECK-MAIN: mov w0, #0xa
CHECK-MAIN-NEXT: mov w1, #0x14
// store current values
-CHECK-MAIN-NEXT: stp x0, x30, [sp
+CHECK-MAIN: stp x0, x30, [sp
// load callsite id
CHECK-MAIN-NEXT: mov x0,
CHECK-MAIN-NEXT: stp x8, x0, [sp
diff --git a/clang/test/CodeGen/memtag-globals-asm.cpp b/clang/test/CodeGen/memtag-globals-asm.cpp
index fb3958dd8bcb6..331939e49ac9d 100644
--- a/clang/test/CodeGen/memtag-globals-asm.cpp
+++ b/clang/test/CodeGen/memtag-globals-asm.cpp
@@ -248,32 +248,33 @@ int f(int x) {
global_my_class.virtual_func() +
local_my_class.virtual_func() +
local_const_string[0] +
+ // GOT pointers may be spilled before use at -O0.
// CHECK-Q-DAG: adrp [[REG_J:x[0-9]+]], :got:_ZL12local_string
- // CHECK-Q-DAG: ldr [[REG_J2:x[0-9]+]], [[[REG_J]], :got_lo12:_ZL12local_string]
- // CHECK-Q-DAG: ldrsb {{.*}}, [[[REG_J2]]]
+ // CHECK-Q-DAG: ldr {{x[0-9]+}}, [[[REG_J]], :got_lo12:_ZL12local_string]
+ // CHECK-Q-DAG: ldrsb {{.*}}, [{{x[0-9]+}}]
local_string[0] +
// CHECK-Q-DAG: adrp [[REG_K:x[0-9]+]], :got:_ZL16local_atomic_int
- // CHECK-Q-DAG: ldr [[REG_K2:x[0-9]+]], [[[REG_K]], :got_lo12:_ZL16local_atomic_int]
- // CHECK-Q-DAG: ldar {{.*}}, [[[REG_K2]]]
+ // CHECK-Q-DAG: ldr {{x[0-9]+}}, [[[REG_K]], :got_lo12:_ZL16local_atomic_int]
+ // CHECK-Q-DAG: ldar {{.*}}, [{{x[0-9]+}}]
local_atomic_int +
// CHECK-Q-DAG: adrp [[REG_L:x[0-9]+]], :got:global_atomic_int
- // CHECK-Q-DAG: ldr [[REG_L2:x[0-9]+]], [[[REG_L]], :got_lo12:global_atomic_int]
- // CHECK-Q-DAG: ldar {{.*}}, [[[REG_L2]]]
+ // CHECK-Q-DAG: ldr {{x[0-9]+}}, [[[REG_L]], :got_lo12:global_atomic_int]
+ // CHECK-Q-DAG: ldar {{.*}}, [{{x[0-9]+}}]
global_atomic_int +
// CHECK-Q-DAG: adrp [[REG_M:x[0-9]+]], :got:global_union
- // CHECK-Q-DAG: ldr [[REG_M2:x[0-9]+]], [[[REG_M]], :got_lo12:global_union]
- // CHECK-Q-DAG: ldr {{.*}}, [[[REG_M2]]]
+ // CHECK-Q-DAG: ldr {{x[0-9]+}}, [[[REG_M]], :got_lo12:global_union]
+ // CHECK-Q-DAG: ldr {{.*}}, [{{x[0-9]+}}]
global_union.i +
// CHECK-Q-DAG: adrp [[REG_N:x[0-9]+]], :got:_ZL11local_union
- // CHECK-Q-DAG: ldr [[REG_N2:x[0-9]+]], [[[REG_N]], :got_lo12:_ZL11local_union]
- // CHECK-Q-DAG: ldrsb {{.*}}, [[[REG_N2]]]
+ // CHECK-Q-DAG: ldr {{x[0-9]+}}, [[[REG_N]], :got_lo12:_ZL11local_union]
+ // CHECK-Q-DAG: ldrsb {{.*}}, [{{x[0-9]+}}]
local_union.c +
/// Global variables - ignore.
global_tls +
local_tls +
// CHECK-Q-DAG: adrp [[REG_O:x[0-9]+]], :got:_ZZ1fiE12function_int
- // CHECK-Q-DAG: ldr [[REG_O2:x[0-9]+]], [[[REG_O]], :got_lo12:_ZZ1fiE12function_int]
- // CHECK-Q-DAG: ldr {{.*}}, [[[REG_O2]]]
+ // CHECK-Q-DAG: ldr {{x[0-9]+}}, [[[REG_O]], :got_lo12:_ZZ1fiE12function_int]
+ // CHECK-Q-DAG: ldr {{.*}}, [{{x[0-9]+}}]
function_int;
}
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 59fb0e15649b8..5741535fe783b 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -618,7 +618,6 @@ bool AArch64PassConfig::addIRTranslator() {
void AArch64PassConfig::addPreLegalizeMachineIR() {
if (getAArch64TargetMachine().isGlobalISelOptNone()) {
addPass(createAArch64O0PreLegalizerCombiner());
- addPass(new LocalizerLegacy());
} else {
addPass(createAArch64PreLegalizerCombiner());
addPass(new LocalizerLegacy());
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
index 6da7795f8b5e8..56925d384995f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
@@ -762,6 +762,8 @@ define i32 @fetch_and_or(ptr %p) #0 {
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: mov w8, #5 ; =0x5
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #24] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: b LBB8_1
@@ -770,7 +772,7 @@ define i32 @fetch_and_or(ptr %p) #0 {
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB8_2 Depth 2
; CHECK-NOLSE-O0-NEXT: ldr w10, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: mov w8, #5 ; =0x5
+; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: orr w12, w10, w8
; CHECK-NOLSE-O0-NEXT: LBB8_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB8_1 Depth=1
@@ -1829,8 +1831,8 @@ define void @atomic_truncstore_relaxed_32(ptr %p, i32 %off32, i64 %inp1, i64 %in
; CHECK-NOLSE-O0-NEXT: str w8, [x0, w1, sxtw #2]
; CHECK-NOLSE-O0-NEXT: mov w8, w4
; CHECK-NOLSE-O0-NEXT: stur w8, [x0, #-256]
-; CHECK-NOLSE-O0-NEXT: mov w8, w5
; CHECK-NOLSE-O0-NEXT: add x9, x0, #291, lsl #12 ; =1191936
+; CHECK-NOLSE-O0-NEXT: mov w8, w5
; CHECK-NOLSE-O0-NEXT: str w8, [x9]
; CHECK-NOLSE-O0-NEXT: ret
;
@@ -1842,8 +1844,8 @@ define void @atomic_truncstore_relaxed_32(ptr %p, i32 %off32, i64 %inp1, i64 %in
; CHECK-OUTLINE-O0-NEXT: str w8, [x0, w1, sxtw #2]
; CHECK-OUTLINE-O0-NEXT: mov w8, w4
; CHECK-OUTLINE-O0-NEXT: stur w8, [x0, #-256]
-; CHECK-OUTLINE-O0-NEXT: mov w8, w5
; CHECK-OUTLINE-O0-NEXT: add x9, x0, #291, lsl #12 ; =1191936
+; CHECK-OUTLINE-O0-NEXT: mov w8, w5
; CHECK-OUTLINE-O0-NEXT: str w8, [x9]
; CHECK-OUTLINE-O0-NEXT: ret
;
@@ -1864,8 +1866,8 @@ define void @atomic_truncstore_relaxed_32(ptr %p, i32 %off32, i64 %inp1, i64 %in
; CHECK-LSE-O0-NEXT: str w8, [x0, w1, sxtw #2]
; CHECK-LSE-O0-NEXT: mov x8, x4
; CHECK-LSE-O0-NEXT: stur w8, [x0, #-256]
-; CHECK-LSE-O0-NEXT: mov x8, x5
; CHECK-LSE-O0-NEXT: add x9, x0, #291, lsl #12 ; =1191936
+; CHECK-LSE-O0-NEXT: mov x8, x5
; CHECK-LSE-O0-NEXT: str w8, [x9]
; CHECK-LSE-O0-NEXT: ret
%ptr_unsigned = getelementptr i32, ptr %p, i32 4095
@@ -2081,14 +2083,17 @@ define void @store_trunc(i32 %val, ptr %p8, ptr %p16, i64 %inp64) {
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: .cfi_offset w30, -8
; CHECK-NOLSE-O0-NEXT: .cfi_offset w29, -16
-; CHECK-NOLSE-O0-NEXT: stlrb w0, [x1]
-; CHECK-NOLSE-O0-NEXT: strh w0, [x2]
+; CHECK-NOLSE-O0-NEXT: mov w9, w0
+; CHECK-NOLSE-O0-NEXT: mov x10, x2
+; CHECK-NOLSE-O0-NEXT: mov x8, x3
+; CHECK-NOLSE-O0-NEXT: mov w11, #4 ; =0x4
+; CHECK-NOLSE-O0-NEXT: mov w0, w11
+; CHECK-NOLSE-O0-NEXT: mov w3, #5 ; =0x5
; CHECK-NOLSE-O0-NEXT: add x2, sp, #12
-; CHECK-NOLSE-O0-NEXT: mov w8, w3
+; CHECK-NOLSE-O0-NEXT: stlrb w9, [x1]
+; CHECK-NOLSE-O0-NEXT: strh w9, [x10]
+; CHECK-NOLSE-O0-NEXT: ; kill: def $w8 killed $w8 killed $x8
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12]
-; CHECK-NOLSE-O0-NEXT: mov w8, #4 ; =0x4
-; CHECK-NOLSE-O0-NEXT: mov w0, w8
-; CHECK-NOLSE-O0-NEXT: mov w3, #5 ; =0x5
; CHECK-NOLSE-O0-NEXT: bl ___atomic_store
; CHECK-NOLSE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
@@ -2101,14 +2106,17 @@ define void @store_trunc(i32 %val, ptr %p8, ptr %p16, i64 %inp64) {
; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
-; CHECK-OUTLINE-O0-NEXT: stlrb w0, [x1]
-; CHECK-OUTLINE-O0-NEXT: strh w0, [x2]
+; CHECK-OUTLINE-O0-NEXT: mov w9, w0
+; CHECK-OUTLINE-O0-NEXT: mov x10, x2
+; CHECK-OUTLINE-O0-NEXT: mov x8, x3
+; CHECK-OUTLINE-O0-NEXT: mov w11, #4 ; =0x4
+; CHECK-OUTLINE-O0-NEXT: mov w0, w11
+; CHECK-OUTLINE-O0-NEXT: mov w3, #5 ; =0x5
; CHECK-OUTLINE-O0-NEXT: add x2, sp, #12
-; CHECK-OUTLINE-O0-NEXT: mov w8, w3
+; CHECK-OUTLINE-O0-NEXT: stlrb w9, [x1]
+; CHECK-OUTLINE-O0-NEXT: strh w9, [x10]
+; CHECK-OUTLINE-O0-NEXT: ; kill: def $w8 killed $w8 killed $x8
; CHECK-OUTLINE-O0-NEXT: str w8, [sp, #12]
-; CHECK-OUTLINE-O0-NEXT: mov w8, #4 ; =0x4
-; CHECK-OUTLINE-O0-NEXT: mov w0, w8
-; CHECK-OUTLINE-O0-NEXT: mov w3, #5 ; =0x5
; CHECK-OUTLINE-O0-NEXT: bl ___atomic_store
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
@@ -2139,14 +2147,17 @@ define void @store_trunc(i32 %val, ptr %p8, ptr %p16, i64 %inp64) {
; CHECK-LSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-LSE-O0-NEXT: .cfi_offset w30, -8
; CHECK-LSE-O0-NEXT: .cfi_offset w29, -16
-; CHECK-LSE-O0-NEXT: stlrb w0, [x1]
-; CHECK-LSE-O0-NEXT: strh w0, [x2]
-; CHECK-LSE-O0-NEXT: add x2, sp, #12
+; CHECK-LSE-O0-NEXT: mov x9, x0
+; CHECK-LSE-O0-NEXT: mov x10, x2
; CHECK-LSE-O0-NEXT: mov x8, x3
-; CHECK-LSE-O0-NEXT: str w8, [sp, #12]
-; CHECK-LSE-O0-NEXT: mov w8, #4 ; =0x4
-; CHECK-LSE-O0-NEXT: mov x0, x8
+; CHECK-LSE-O0-NEXT: mov w11, #4 ; =0x4
+; CHECK-LSE-O0-NEXT: mov x0, x11
; CHECK-LSE-O0-NEXT: mov w3, #5 ; =0x5
+; CHECK-LSE-O0-NEXT: add x2, sp, #12
+; CHECK-LSE-O0-NEXT: stlrb w9, [x1]
+; CHECK-LSE-O0-NEXT: strh w9, [x10]
+; CHECK-LSE-O0-NEXT: ; kill: def $w8 killed $w8 killed $x8
+; CHECK-LSE-O0-NEXT: str w8, [sp, #12]
; CHECK-LSE-O0-NEXT: bl ___atomic_store
; CHECK-LSE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; CHECK-LSE-O0-NEXT: add sp, sp, #32
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/atomic-anyextending-load-crash.ll b/llvm/test/CodeGen/AArch64/GlobalISel/atomic-anyextending-load-crash.ll
index a3d57f05d9c60..2fa022d06da1f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/atomic-anyextending-load-crash.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/atomic-anyextending-load-crash.ll
@@ -11,10 +11,10 @@ define void @test(ptr %0) {
; CHECK-NEXT: .cfi_def_cfa_offset 144
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: ldar w8, [x0]
-; CHECK-NEXT: str w8, [sp, #116] ; 4-byte Spill
; CHECK-NEXT: mov x8, #0 ; =0x0
; CHECK-NEXT: str x8, [sp, #120] ; 8-byte Spill
+; CHECK-NEXT: ldar w9, [x0]
+; CHECK-NEXT: str w9, [sp, #116] ; 4-byte Spill
; CHECK-NEXT: blr x8
; CHECK-NEXT: ldr w11, [sp, #116] ; 4-byte Reload
; CHECK-NEXT: ldr x8, [sp, #120] ; 8-byte Reload
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll b/llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll
index 6efad350b4a96..9b404114f9913 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll
@@ -12,10 +12,10 @@ define i1 @test_lpad_phi_widen_into_pred() personality ptr @__gxx_personality_v0
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
- ; CHECK-NEXT: G_STORE [[C]](i32), [[GV]](p0) :: (store (i32) into @global_var)
+ ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[GV]](p0) :: (store (i32) into @global_var)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i16) = G_CONSTANT i16 1
; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol >
@@ -31,8 +31,7 @@ define i1 @test_lpad_phi_widen_into_pred() personality ptr @__gxx_personality_v0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[C1]](i32), %bb.1
; CHECK-NEXT: EH_LABEL <mcsymbol >
- ; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
- ; CHECK-NEXT: G_STORE [[PHI]](i32), [[GV1]](p0) :: (store (i32) into @global_var)
+ ; CHECK-NEXT: G_STORE [[PHI]](i32), [[GV]](p0) :: (store (i32) into @global_var)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i16) = G_CONSTANT i16 0
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
@@ -67,12 +66,12 @@ define i1 @test_lpad_phi_widen_into_pred_ext(ptr %ptr) personality ptr @__gxx_pe
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
; CHECK-NEXT: G_STORE [[C]](i32), [[GV]](p0) :: (store (i32) into @global_var)
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[COPY]](p0) :: (load (i8) from %ir.ptr)
; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i8) = G_ASSERT_ZEXT [[LOAD]], 1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i16) = G_ANYEXT [[ASSERT_ZEXT]](i8)
; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol >
@@ -88,8 +87,7 @@ define i1 @test_lpad_phi_widen_into_pred_ext(ptr %ptr) personality ptr @__gxx_pe
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[C1]](i32), %bb.1
; CHECK-NEXT: EH_LABEL <mcsymbol >
- ; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
- ; CHECK-NEXT: G_STORE [[PHI]](i32), [[GV1]](p0) :: (store (i32) into @global_var)
+ ; CHECK-NEXT: G_STORE [[PHI]](i32), [[GV]](p0) :: (store (i32) into @global_var)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i16) = G_CONSTANT i16 0
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
index cedc70d4a5357..eb77d7082ca9b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
@@ -13,10 +13,12 @@ define void @bar() personality ptr @__gxx_personality_v0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.exn.slot
+ ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.ehselector.slot
; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: BL @foo, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
@@ -32,9 +34,7 @@ define void @bar() personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY1]](p0)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](i64)
- ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.exn.slot
; CHECK-NEXT: G_STORE [[COPY]](p0), [[FRAME_INDEX]](p0) :: (store (p0) into %ir.exn.slot)
- ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.ehselector.slot
; CHECK-NEXT: G_STORE [[TRUNC]](i32), [[FRAME_INDEX1]](p0) :: (store (i32) into %ir.ehselector.slot)
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
@@ -42,8 +42,7 @@ define void @bar() personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: RET_ReallyLR
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.eh.resume:
- ; CHECK-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.exn.slot
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (load (p0) from %ir.exn.slot)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0) from %ir.exn.slot)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x0 = COPY [[LOAD]](p0)
; CHECK-NEXT: BL @_Unwind_Resume, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
index 4fa647223e9d0..2902d1dc73332 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -o - -verify-machineinstrs -O0 -global-isel -stop-after=localizer %s | FileCheck %s
+; RUN: llc -o - -verify-machineinstrs -O1 -global-isel -stop-after=localizer %s | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios5.0.0"
@@ -25,11 +25,11 @@ define i32 @foo() {
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[GV2]](p0) :: (load (i32) from @var1)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (i32) from @var1)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[LOAD]](i32), [[C3]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.2
- ; CHECK-NEXT: G_BR %bb.3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD]](i32), [[C3]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
@@ -43,7 +43,6 @@ define i32 @foo() {
; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3
; CHECK-NEXT: G_STORE [[C4]](i32), [[GV5]](p0) :: (store (i32) into @var3)
; CHECK-NEXT: G_STORE [[C5]](i32), [[GV4]](p0) :: (store (i32) into @var1)
- ; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.end:
; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
@@ -68,35 +67,29 @@ if.end:
define i32 @imm_cost_too_large_cost_of_2() {
; CHECK-LABEL: name: imm_cost_too_large_cost_of_2
; CHECK: bb.1.entry:
- ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[GV2]](p0) :: (load (i32) from @var1)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2228259
; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(i32) = G_CONSTANT_FOLD_BARRIER [[C1]]
+ ; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (i32) from @var1)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[LOAD]](i32), [[C2]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.2
- ; CHECK-NEXT: G_BR %bb.4
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD]](i32), [[C2]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](i32), [[GV3]](p0) :: (store (i32) into @var2)
- ; CHECK-NEXT: G_BR %bb.3
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.3.if.then2:
- ; CHECK-NEXT: successors: %bb.4(0x80000000)
- ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV4:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](i32), [[GV4]](p0) :: (store (i32) into @var1)
- ; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.4.if.end:
+ ; CHECK-NEXT: bb.3.if.end:
; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3
; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](i32), [[GV5]](p0) :: (store (i32) into @var3)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
@@ -124,35 +117,29 @@ if.end:
define i64 @imm_cost_too_large_cost_of_4() {
; CHECK-LABEL: name: imm_cost_too_large_cost_of_4
; CHECK: bb.1.entry:
- ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2_64
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[GV2]](p0) :: (load (i64) from @var1_64, align 4)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 -2228259
; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(i64) = G_CONSTANT_FOLD_BARRIER [[C1]]
+ ; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[GV2]](p0) :: (dereferenceable load (i64) from @var1_64, align 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[LOAD]](i64), [[C2]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.2
- ; CHECK-NEXT: G_BR %bb.4
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD]](i64), [[C2]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2_64
; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](i64), [[GV3]](p0) :: (store (i64) into @var2_64)
- ; CHECK-NEXT: G_BR %bb.3
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.3.if.then2:
- ; CHECK-NEXT: successors: %bb.4(0x80000000)
- ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV4:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](i64), [[GV4]](p0) :: (store (i64) into @var1_64)
- ; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.4.if.end:
+ ; CHECK-NEXT: bb.3.if.end:
; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](i64), [[GV5]](p0) :: (store (i64) into @var3_64)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
@@ -180,7 +167,7 @@ if.end:
define i64 @f64_imm_cost_too_high(double %a) {
; CHECK-LABEL: name: f64_imm_cost_too_high
; CHECK: bb.1.entry:
- ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e-02
@@ -188,27 +175,21 @@ define i64 @f64_imm_cost_too_high(double %a) {
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[GV2]](p0) :: (load (i64) from @var1_64, align 4)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[GV2]](p0) :: (dereferenceable load (i64) from @var1_64, align 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[LOAD]](i64), [[C2]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.2
- ; CHECK-NEXT: G_BR %bb.4
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD]](i64), [[C2]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2_64
; CHECK-NEXT: G_STORE [[C]](f64), [[GV3]](p0) :: (store (f64) into @var2_64)
- ; CHECK-NEXT: G_BR %bb.3
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.3.if.then2:
- ; CHECK-NEXT: successors: %bb.4(0x80000000)
- ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV4:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
; CHECK-NEXT: G_STORE [[C]](f64), [[GV4]](p0) :: (store (f64) into @var1_64)
- ; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.4.if.end:
+ ; CHECK-NEXT: bb.3.if.end:
; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
; CHECK-NEXT: G_STORE [[C]](f64), [[GV5]](p0) :: (store (f64) into @var3_64)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
@@ -235,7 +216,7 @@ if.end:
define i64 @f64_imm_cheap(double %a) {
; CHECK-LABEL: name: f64_imm_cheap
; CHECK: bb.1.entry:
- ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
@@ -243,11 +224,11 @@ define i64 @f64_imm_cheap(double %a) {
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[GV2]](p0) :: (load (i64) from @var1_64, align 4)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[GV2]](p0) :: (dereferenceable load (i64) from @var1_64, align 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[LOAD]](i64), [[C2]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.2
- ; CHECK-NEXT: G_BR %bb.4
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD]](i64), [[C2]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
@@ -255,22 +236,15 @@ define i64 @f64_imm_cheap(double %a) {
; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2_64
; CHECK-NEXT: [[C3:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
; CHECK-NEXT: G_STORE [[C3]](f64), [[GV3]](p0) :: (store (f64) into @var2_64)
- ; CHECK-NEXT: G_BR %bb.3
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.3.if.then2:
- ; CHECK-NEXT: successors: %bb.4(0x80000000)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
; CHECK-NEXT: [[GV4:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
- ; CHECK-NEXT: G_STORE [[C4]](f64), [[GV4]](p0) :: (store (f64) into @var1_64)
- ; CHECK-NEXT: G_BR %bb.4
+ ; CHECK-NEXT: G_STORE [[C3]](f64), [[GV4]](p0) :: (store (f64) into @var1_64)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.4.if.end:
+ ; CHECK-NEXT: bb.3.if.end:
; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
- ; CHECK-NEXT: G_STORE [[C5]](f64), [[GV5]](p0) :: (store (f64) into @var3_64)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: $x0 = COPY [[C6]](i64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
+ ; CHECK-NEXT: G_STORE [[C4]](f64), [[GV5]](p0) :: (store (f64) into @var3_64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: $x0 = COPY [[C5]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%0 = load i64, ptr @var1_64, align 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-propagate-debug-loc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-propagate-debug-loc.mir
index 6ced34daed680..e20aebb84be1d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-propagate-debug-loc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-propagate-debug-loc.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 %s -global-isel -start-before localizer \
-# RUN: -stop-after localizer -o - | FileCheck --check-prefix=CHECK %s
+# RUN: llc -run-pass=localizer %s -o - | FileCheck --check-prefix=CHECK %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-macosx12.0.0"
@@ -76,12 +75,12 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[C:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @C, debug-location !DILocation(line: 0, scope: !18)
- ; CHECK-NEXT: [[ADD_LOW:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP]](p0), target-flags(aarch64-pageoff, aarch64-nc) @C, debug-location !DILocation(line: 0, scope: !18)
- ; CHECK-NEXT: [[ADRP1:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @B, debug-location !DILocation(line: 0, scope: !14)
- ; CHECK-NEXT: [[ADD_LOW1:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP1]](p0), target-flags(aarch64-pageoff, aarch64-nc) @B, debug-location !DILocation(line: 0, scope: !14)
- ; CHECK-NEXT: [[ADRP2:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @A, debug-location !DILocation(line: 0, scope: !11)
- ; CHECK-NEXT: [[ADD_LOW2:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP2]](p0), target-flags(aarch64-pageoff, aarch64-nc) @A, debug-location !DILocation(line: 0, scope: !11)
+ ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @C, debug-location !DILocation(line: 0, scope: !18)
+ ; CHECK-NEXT: [[ADD_LOW:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP]](p0), target-flags(aarch64-pageoff, aarch64-nc) @C, debug-location !DILocation(line: 0, scope: !18)
+ ; CHECK-NEXT: [[ADRP1:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @B, debug-location !DILocation(line: 0, scope: !14)
+ ; CHECK-NEXT: [[ADD_LOW1:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP1]](p0), target-flags(aarch64-pageoff, aarch64-nc) @B, debug-location !DILocation(line: 0, scope: !14)
+ ; CHECK-NEXT: [[ADRP2:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @A, debug-location !DILocation(line: 0, scope: !11)
+ ; CHECK-NEXT: [[ADD_LOW2:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP2]](p0), target-flags(aarch64-pageoff, aarch64-nc) @A, debug-location !DILocation(line: 0, scope: !11)
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:gpr(p0) = G_FRAME_INDEX %stack.0
; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(i32) = COPY [[C1]](i32)
@@ -94,9 +93,9 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.5(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ADRP3:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @A, debug-location !10
- ; CHECK-NEXT: [[ADD_LOW3:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP3]](p0), target-flags(aarch64-pageoff, aarch64-nc) @A, debug-location !10
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:gpr(i32) = G_LOAD [[ADD_LOW3]](p0), debug-location !10 :: (dereferenceable load (i32))
+ ; CHECK-NEXT: [[ADRP3:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @A, debug-location !10
+ ; CHECK-NEXT: [[ADD_LOW3:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP3]](p0), target-flags(aarch64-pageoff, aarch64-nc) @A, debug-location !10
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:gpr(i32) = G_LOAD [[ADD_LOW3]](p0), debug-location !10 :: (dereferenceable load (i32))
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:gpr(p0) = G_FRAME_INDEX %stack.0
; CHECK-NEXT: G_STORE [[LOAD]](i32), [[FRAME_INDEX1]](p0) :: (volatile store (i32) into %ir.1)
; CHECK-NEXT: G_BR %bb.5
@@ -114,22 +113,22 @@ body: |
; CHECK-NEXT: bb.3:
; CHECK-NEXT: successors: %bb.5(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ADRP4:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @B, debug-location !DILocation(line: 0, scope: !14)
- ; CHECK-NEXT: [[ADD_LOW4:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP4]](p0), target-flags(aarch64-pageoff, aarch64-nc) @B, debug-location !DILocation(line: 0, scope: !14)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:gpr(i32) = G_LOAD [[ADD_LOW4]](p0), debug-location !13 :: (dereferenceable load (i32))
+ ; CHECK-NEXT: [[ADRP4:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @B, debug-location !DILocation(line: 0, scope: !14)
+ ; CHECK-NEXT: [[ADD_LOW4:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP4]](p0), target-flags(aarch64-pageoff, aarch64-nc) @B, debug-location !DILocation(line: 0, scope: !14)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:gpr(i32) = G_LOAD [[ADD_LOW4]](p0), debug-location !13 :: (dereferenceable load (i32))
; CHECK-NEXT: [[FRAME_INDEX2:%[0-9]+]]:gpr(p0) = G_FRAME_INDEX %stack.0
; CHECK-NEXT: G_STORE [[LOAD1]](i32), [[FRAME_INDEX2]](p0) :: (volatile store (i32) into %ir.1)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:gpr(i32) = G_LOAD [[ADD_LOW4]](p0), debug-location !16 :: (dereferenceable load (i32))
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:gpr(i32) = G_LOAD [[ADD_LOW4]](p0), debug-location !16 :: (dereferenceable load (i32))
; CHECK-NEXT: G_STORE [[LOAD2]](i32), [[FRAME_INDEX2]](p0) :: (volatile store (i32) into %ir.1)
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4:
; CHECK-NEXT: successors: %bb.5(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ADRP5:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @C, debug-location !17
- ; CHECK-NEXT: [[ADD_LOW5:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP5]](p0), target-flags(aarch64-pageoff, aarch64-nc) @C, debug-location !17
- ; CHECK-NEXT: [[C5:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 3, debug-location !17
- ; CHECK-NEXT: G_STORE [[C5]](i32), [[ADD_LOW5]](p0), debug-location !17 :: (store (i32) into @C)
+ ; CHECK-NEXT: [[ADRP5:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @C, debug-location !17
+ ; CHECK-NEXT: [[ADD_LOW5:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP5]](p0), target-flags(aarch64-pageoff, aarch64-nc) @C, debug-location !17
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 3, debug-location !17
+ ; CHECK-NEXT: G_STORE [[C5]](i32), [[ADD_LOW5]](p0), debug-location !17 :: (store (i32) into @C)
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-tls.ll b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-tls.ll
index b8f65310ae998..b2d2f4e17c327 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-tls.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-tls.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=arm64-apple-ios -o - -verify-machineinstrs -O0 -global-isel -stop-after=localizer %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-linux-gnu -o - -verify-machineinstrs -O0 -global-isel -stop-after=localizer %s | FileCheck %s
+; RUN: llc -mtriple=arm64-apple-ios -o - -verify-machineinstrs -O1 -global-isel -stop-after=localizer %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -o - -verify-machineinstrs -O1 -global-isel -stop-after=localizer %s | FileCheck %s
@var1 = common global i32 0, align 4
@var2 = common global i32 0, align 4
@@ -20,19 +20,18 @@ define i32 @tls() {
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[GV2]](p0) :: (load (i32) from @var1)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (i32) from @var1)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[LOAD]](i32), [[C1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.2
- ; CHECK-NEXT: G_BR %bb.3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[GV]](p0) :: (load (i32) from @tls_gv)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[GV]](p0) :: (dereferenceable load (i32) from @tls_gv)
; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
; CHECK-NEXT: G_STORE [[LOAD1]](i32), [[GV3]](p0) :: (store (i32) into @var2)
- ; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.end:
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
@@ -51,4 +50,3 @@ if.then:
if.end:
ret i32 0
}
-
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-anyext-crash.ll b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-anyext-crash.ll
index a63636e666e8f..4b57ef1d2d24f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-anyext-crash.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-anyext-crash.ll
@@ -13,19 +13,19 @@ define i32 @test() {
; CHECK-NEXT: .cfi_def_cfa_offset 80
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: mov x9, #0 ; =0x0
; CHECK-NEXT: mov x8, #0 ; =0x0
-; CHECK-NEXT: ldr s0, [x8]
+; CHECK-NEXT: mov w10, #0 ; =0x0
+; CHECK-NEXT: str w10, [sp, #60] ; 4-byte Spill
+; CHECK-NEXT: ldr s0, [x9]
; CHECK-NEXT: ; kill: def $d0 killed $s0
-; CHECK-NEXT: mov x8, sp
-; CHECK-NEXT: mov w9, #0 ; =0x0
-; CHECK-NEXT: str w9, [sp, #60] ; 4-byte Spill
-; CHECK-NEXT: str xzr, [x8]
-; CHECK-NEXT: str xzr, [x8, #8]
-; CHECK-NEXT: str xzr, [x8, #16]
-; CHECK-NEXT: str xzr, [x8, #24]
-; CHECK-NEXT: str d0, [x8, #32]
-; CHECK-NEXT: str xzr, [x8, #40]
-; CHECK-NEXT: mov x8, #0 ; =0x0
+; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: str xzr, [x9]
+; CHECK-NEXT: str xzr, [x9, #8]
+; CHECK-NEXT: str xzr, [x9, #16]
+; CHECK-NEXT: str xzr, [x9, #24]
+; CHECK-NEXT: str d0, [x9, #32]
+; CHECK-NEXT: str xzr, [x9, #40]
; CHECK-NEXT: mov x0, x8
; CHECK-NEXT: blr x8
; CHECK-NEXT: ldr w0, [sp, #60] ; 4-byte Reload
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/translate-constant-dag.ll b/llvm/test/CodeGen/AArch64/GlobalISel/translate-constant-dag.ll
index e7592fe49c863..11a768fcdbf47 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/translate-constant-dag.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/translate-constant-dag.ll
@@ -10,12 +10,12 @@ define void @test_const(ptr %dst) {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 10
- ; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 0 :: (store (i8) into %ir.dst)
; CHECK-NEXT: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 20
+ ; CHECK-NEXT: [[MOVi32imm2:%[0-9]+]]:gpr32 = MOVi32imm 50
+ ; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 0 :: (store (i8) into %ir.dst)
; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 1 :: (store (i8) into %ir.dst + 1)
; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 2 :: (store (i8) into %ir.dst + 2)
; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 3 :: (store (i8) into %ir.dst + 3)
- ; CHECK-NEXT: [[MOVi32imm2:%[0-9]+]]:gpr32 = MOVi32imm 50
; CHECK-NEXT: STRBBui [[MOVi32imm2]], [[COPY]], 4 :: (store (i8) into %ir.dst + 4)
; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 5 :: (store (i8) into %ir.dst + 5)
; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 6 :: (store (i8) into %ir.dst + 6)
diff --git a/llvm/test/CodeGen/AArch64/O0-pipeline.ll b/llvm/test/CodeGen/AArch64/O0-pipeline.ll
index fc068cd2e6cbd..109b0339b3de8 100644
--- a/llvm/test/CodeGen/AArch64/O0-pipeline.ll
+++ b/llvm/test/CodeGen/AArch64/O0-pipeline.ll
@@ -35,7 +35,6 @@
; CHECK-NEXT: Analysis containing CSE Info
; CHECK-NEXT: IRTranslator
; CHECK-NEXT: AArch64O0PreLegalizerCombiner
-; CHECK-NEXT: Localizer
; CHECK-NEXT: Analysis containing CSE Info
; CHECK-NEXT: Analysis for ComputingKnownBits
; CHECK-NEXT: Legalizer
diff --git a/llvm/test/CodeGen/AArch64/O3-pipeline.ll b/llvm/test/CodeGen/AArch64/O3-pipeline.ll
index 9a2f7b18e23f1..8d58fe7f3fe0e 100644
--- a/llvm/test/CodeGen/AArch64/O3-pipeline.ll
+++ b/llvm/test/CodeGen/AArch64/O3-pipeline.ll
@@ -118,7 +118,6 @@
; CHECK-NEXT: Function Alias Analysis Results
; CHECK-NEXT: IRTranslator
; CHECK-NEXT: AArch64O0PreLegalizerCombiner
-; CHECK-NEXT: Localizer
; CHECK-NEXT: Analysis containing CSE Info
; CHECK-NEXT: Analysis for ComputingKnownBits
; CHECK-NEXT: Legalizer
diff --git a/llvm/test/CodeGen/AArch64/aarch64-fastcc-stackup.ll b/llvm/test/CodeGen/AArch64/aarch64-fastcc-stackup.ll
index 3cfe10ed8a83d..f279485c2a4a6 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-fastcc-stackup.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-fastcc-stackup.ll
@@ -24,8 +24,8 @@ define fastcc i64 @baz() {
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16
-; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov x7, xzr
+; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: str xzr, [x8]
; CHECK-NEXT: mov x0, x7
; CHECK-NEXT: mov x1, x7
diff --git a/llvm/test/CodeGen/AArch64/aarch64-tbz.ll b/llvm/test/CodeGen/AArch64/aarch64-tbz.ll
index f895dabba5714..a6603130899a5 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-tbz.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-tbz.ll
@@ -223,17 +223,25 @@ define i32 @tbzfromextract(<8 x i8> %b) {
;
; CHECK-GIO0-LABEL: tbzfromextract:
; CHECK-GIO0: // %bb.0:
+; CHECK-GIO0-NEXT: sub sp, sp, #16
+; CHECK-GIO0-NEXT: .cfi_def_cfa_offset 16
; CHECK-GIO0-NEXT: fmov d1, d0
+; CHECK-GIO0-NEXT: mov w8, wzr
+; CHECK-GIO0-NEXT: str w8, [sp, #8] // 4-byte Spill
+; CHECK-GIO0-NEXT: mov w8, #1 // =0x1
+; CHECK-GIO0-NEXT: str w8, [sp, #12] // 4-byte Spill
; CHECK-GIO0-NEXT: // implicit-def: $q0
; CHECK-GIO0-NEXT: fmov d0, d1
; CHECK-GIO0-NEXT: umov w8, v0.b[0]
; CHECK-GIO0-NEXT: tbz w8, #31, .LBB4_1
; CHECK-GIO0-NEXT: b .LBB4_2
; CHECK-GIO0-NEXT: .LBB4_1: // %land.rhs
-; CHECK-GIO0-NEXT: mov w0, #1 // =0x1
+; CHECK-GIO0-NEXT: ldr w0, [sp, #12] // 4-byte Reload
+; CHECK-GIO0-NEXT: add sp, sp, #16
; CHECK-GIO0-NEXT: ret
; CHECK-GIO0-NEXT: .LBB4_2: // %land.end
-; CHECK-GIO0-NEXT: mov w0, wzr
+; CHECK-GIO0-NEXT: ldr w0, [sp, #8] // 4-byte Reload
+; CHECK-GIO0-NEXT: add sp, sp, #16
; CHECK-GIO0-NEXT: ret
%e = extractelement <8 x i8> %b, i32 0
%z = zext i8 %e to i32
diff --git a/llvm/test/CodeGen/AArch64/cfguard-checks.ll b/llvm/test/CodeGen/AArch64/cfguard-checks.ll
index 0b05b7422fb06..effe4e8d5797f 100644
--- a/llvm/test/CodeGen/AArch64/cfguard-checks.ll
+++ b/llvm/test/CodeGen/AArch64/cfguard-checks.ll
@@ -40,10 +40,10 @@ entry:
; CHECK-LABEL: func_optnone_cf
; CHECK: adrp x8, target_func
; CHECK-NEXT: add x8, x8, :lo12:target_func
+ ; CHECK-NEXT: adrp x9, __guard_check_icall_fptr
; CHECK-NEXT: str x8, [sp, #8]
; CHECK-NEXT: ldr x15, [sp, #8]
- ; CHECK-NEXT: adrp x8, __guard_check_icall_fptr
- ; CHECK-NEXT: ldr x8, [x8, :lo12:__guard_check_icall_fptr]
+ ; CHECK-NEXT: ldr x8, [x9, :lo12:__guard_check_icall_fptr]
; CHECK-NEXT: blr x8
; CHECK-NEXT: blr x15
}
diff --git a/llvm/test/CodeGen/AArch64/cpa-globalisel.ll b/llvm/test/CodeGen/AArch64/cpa-globalisel.ll
index 092c1d189b14a..f5d16dea085bb 100644
--- a/llvm/test/CodeGen/AArch64/cpa-globalisel.ll
+++ b/llvm/test/CodeGen/AArch64/cpa-globalisel.ll
@@ -51,16 +51,16 @@ entry:
define void @maddpt1(i32 %pos, ptr %val) {
; CHECK-CPA-O0-LABEL: maddpt1:
; CHECK-CPA-O0: // %bb.0: // %entry
+; CHECK-CPA-O0-NEXT: adrp x10, array2
+; CHECK-CPA-O0-NEXT: add x10, x10, :lo12:array2
+; CHECK-CPA-O0-NEXT: mov w8, #48 // =0x30
+; CHECK-CPA-O0-NEXT: mov w2, w8
; CHECK-CPA-O0-NEXT: // implicit-def: $x8
; CHECK-CPA-O0-NEXT: mov w8, w0
; CHECK-CPA-O0-NEXT: sxtw x8, w8
; CHECK-CPA-O0-NEXT: mov w9, #48 // =0x30
; CHECK-CPA-O0-NEXT: // kill: def $x9 killed $w9
-; CHECK-CPA-O0-NEXT: adrp x10, array2
-; CHECK-CPA-O0-NEXT: add x10, x10, :lo12:array2
; CHECK-CPA-O0-NEXT: maddpt x0, x8, x9, x10
-; CHECK-CPA-O0-NEXT: mov w8, #48 // =0x30
-; CHECK-CPA-O0-NEXT: mov w2, w8
; CHECK-CPA-O0-NEXT: b memcpy
;
; CHECK-CPA-O3-LABEL: maddpt1:
@@ -84,9 +84,9 @@ define void @maddpt1(i32 %pos, ptr %val) {
; CHECK-NOCPA-O0-NEXT: adrp x9, array2
; CHECK-NOCPA-O0-NEXT: add x9, x9, :lo12:array2
; CHECK-NOCPA-O0-NEXT: mov w8, #48 // =0x30
-; CHECK-NOCPA-O0-NEXT: smaddl x0, w0, w8, x9
-; CHECK-NOCPA-O0-NEXT: mov w8, #48 // =0x30
; CHECK-NOCPA-O0-NEXT: mov w2, w8
+; CHECK-NOCPA-O0-NEXT: mov w8, #48 // =0x30
+; CHECK-NOCPA-O0-NEXT: smaddl x0, w0, w8, x9
; CHECK-NOCPA-O0-NEXT: b memcpy
;
; CHECK-NOCPA-O3-LABEL: maddpt1:
@@ -112,22 +112,22 @@ entry:
define void @msubpt1(i32 %index, i32 %elem) {
; CHECK-CPA-O0-LABEL: msubpt1:
; CHECK-CPA-O0: // %bb.0: // %entry
-; CHECK-CPA-O0-NEXT: // implicit-def: $x8
-; CHECK-CPA-O0-NEXT: mov w8, w0
-; CHECK-CPA-O0-NEXT: sxtw x10, w8
-; CHECK-CPA-O0-NEXT: mov w8, #48 // =0x30
-; CHECK-CPA-O0-NEXT: mov w9, w8
-; CHECK-CPA-O0-NEXT: mov w8, #288 // =0x120
-; CHECK-CPA-O0-NEXT: mov w11, w8
; CHECK-CPA-O0-NEXT: adrp x8, array2
; CHECK-CPA-O0-NEXT: add x8, x8, :lo12:array2
-; CHECK-CPA-O0-NEXT: addpt x11, x8, x11
-; CHECK-CPA-O0-NEXT: msubpt x0, x9, x10, x11
-; CHECK-CPA-O0-NEXT: mov w9, #48 // =0x30
-; CHECK-CPA-O0-NEXT: mov w2, w9
+; CHECK-CPA-O0-NEXT: mov w9, #288 // =0x120
+; CHECK-CPA-O0-NEXT: // kill: def $x9 killed $w9
+; CHECK-CPA-O0-NEXT: addpt x10, x8, x9
; CHECK-CPA-O0-NEXT: mov w9, #96 // =0x60
; CHECK-CPA-O0-NEXT: // kill: def $x9 killed $w9
; CHECK-CPA-O0-NEXT: addpt x1, x8, x9
+; CHECK-CPA-O0-NEXT: mov w8, #48 // =0x30
+; CHECK-CPA-O0-NEXT: mov w2, w8
+; CHECK-CPA-O0-NEXT: // implicit-def: $x8
+; CHECK-CPA-O0-NEXT: mov w8, w0
+; CHECK-CPA-O0-NEXT: sxtw x9, w8
+; CHECK-CPA-O0-NEXT: mov w8, #48 // =0x30
+; CHECK-CPA-O0-NEXT: // kill: def $x8 killed $w8
+; CHECK-CPA-O0-NEXT: msubpt x0, x8, x9, x10
; CHECK-CPA-O0-NEXT: b memcpy
;
; CHECK-CPA-O3-LABEL: msubpt1:
@@ -148,19 +148,19 @@ define void @msubpt1(i32 %index, i32 %elem) {
;
; CHECK-NOCPA-O0-LABEL: msubpt1:
; CHECK-NOCPA-O0: // %bb.0: // %entry
-; CHECK-NOCPA-O0-NEXT: // implicit-def: $x8
-; CHECK-NOCPA-O0-NEXT: mov w8, w0
-; CHECK-NOCPA-O0-NEXT: sxtw x8, w8
-; CHECK-NOCPA-O0-NEXT: mov w9, #48 // =0x30
-; CHECK-NOCPA-O0-NEXT: // kill: def $x9 killed $w9
-; CHECK-NOCPA-O0-NEXT: mneg x10, x8, x9
-; CHECK-NOCPA-O0-NEXT: adrp x8, array2
-; CHECK-NOCPA-O0-NEXT: add x8, x8, :lo12:array2
-; CHECK-NOCPA-O0-NEXT: add x9, x8, #288
-; CHECK-NOCPA-O0-NEXT: add x0, x9, x10
+; CHECK-NOCPA-O0-NEXT: adrp x9, array2
+; CHECK-NOCPA-O0-NEXT: add x9, x9, :lo12:array2
+; CHECK-NOCPA-O0-NEXT: add x8, x9, #288
+; CHECK-NOCPA-O0-NEXT: add x1, x9, #96
; CHECK-NOCPA-O0-NEXT: mov w9, #48 // =0x30
; CHECK-NOCPA-O0-NEXT: mov w2, w9
-; CHECK-NOCPA-O0-NEXT: add x1, x8, #96
+; CHECK-NOCPA-O0-NEXT: // implicit-def: $x9
+; CHECK-NOCPA-O0-NEXT: mov w9, w0
+; CHECK-NOCPA-O0-NEXT: sxtw x9, w9
+; CHECK-NOCPA-O0-NEXT: mov w10, #48 // =0x30
+; CHECK-NOCPA-O0-NEXT: // kill: def $x10 killed $w10
+; CHECK-NOCPA-O0-NEXT: mneg x9, x9, x10
+; CHECK-NOCPA-O0-NEXT: add x0, x8, x9
; CHECK-NOCPA-O0-NEXT: b memcpy
;
; CHECK-NOCPA-O3-LABEL: msubpt1:
@@ -190,14 +190,14 @@ entry:
define void @subpt1(i32 %index, i32 %elem) {
; CHECK-CPA-O0-LABEL: subpt1:
; CHECK-CPA-O0: // %bb.0: // %entry
-; CHECK-CPA-O0-NEXT: mov w8, #-16 // =0xfffffff0
-; CHECK-CPA-O0-NEXT: smull x9, w0, w8
-; CHECK-CPA-O0-NEXT: adrp x8, array
-; CHECK-CPA-O0-NEXT: add x8, x8, :lo12:array
-; CHECK-CPA-O0-NEXT: ldr q0, [x8, #32]
-; CHECK-CPA-O0-NEXT: mov w10, #96 // =0x60
-; CHECK-CPA-O0-NEXT: // kill: def $x10 killed $w10
-; CHECK-CPA-O0-NEXT: addpt x8, x8, x10
+; CHECK-CPA-O0-NEXT: adrp x10, array
+; CHECK-CPA-O0-NEXT: add x10, x10, :lo12:array
+; CHECK-CPA-O0-NEXT: mov w8, #96 // =0x60
+; CHECK-CPA-O0-NEXT: // kill: def $x8 killed $w8
+; CHECK-CPA-O0-NEXT: addpt x8, x10, x8
+; CHECK-CPA-O0-NEXT: mov w9, #-16 // =0xfffffff0
+; CHECK-CPA-O0-NEXT: smull x9, w0, w9
+; CHECK-CPA-O0-NEXT: ldr q0, [x10, #32]
; CHECK-CPA-O0-NEXT: str q0, [x8, x9, lsl #4]
; CHECK-CPA-O0-NEXT: ret
;
@@ -214,12 +214,12 @@ define void @subpt1(i32 %index, i32 %elem) {
;
; CHECK-NOCPA-O0-LABEL: subpt1:
; CHECK-NOCPA-O0: // %bb.0: // %entry
-; CHECK-NOCPA-O0-NEXT: mov w8, #-16 // =0xfffffff0
-; CHECK-NOCPA-O0-NEXT: smull x9, w0, w8
-; CHECK-NOCPA-O0-NEXT: adrp x8, array
-; CHECK-NOCPA-O0-NEXT: add x8, x8, :lo12:array
-; CHECK-NOCPA-O0-NEXT: ldr q0, [x8, #32]
-; CHECK-NOCPA-O0-NEXT: add x8, x8, #96
+; CHECK-NOCPA-O0-NEXT: adrp x10, array
+; CHECK-NOCPA-O0-NEXT: add x10, x10, :lo12:array
+; CHECK-NOCPA-O0-NEXT: add x8, x10, #96
+; CHECK-NOCPA-O0-NEXT: mov w9, #-16 // =0xfffffff0
+; CHECK-NOCPA-O0-NEXT: smull x9, w0, w9
+; CHECK-NOCPA-O0-NEXT: ldr q0, [x10, #32]
; CHECK-NOCPA-O0-NEXT: str q0, [x8, x9, lsl #4]
; CHECK-NOCPA-O0-NEXT: ret
;
@@ -244,14 +244,14 @@ entry:
define void @subpt2(i32 %index, i32 %elem) {
; CHECK-CPA-O0-LABEL: subpt2:
; CHECK-CPA-O0: // %bb.0: // %entry
-; CHECK-CPA-O0-NEXT: mov x8, xzr
-; CHECK-CPA-O0-NEXT: subs x9, x8, w0, sxtw
-; CHECK-CPA-O0-NEXT: adrp x8, array
-; CHECK-CPA-O0-NEXT: add x8, x8, :lo12:array
-; CHECK-CPA-O0-NEXT: ldr q0, [x8, #32]
-; CHECK-CPA-O0-NEXT: mov w10, #96 // =0x60
-; CHECK-CPA-O0-NEXT: // kill: def $x10 killed $w10
-; CHECK-CPA-O0-NEXT: addpt x8, x8, x10
+; CHECK-CPA-O0-NEXT: mov x9, xzr
+; CHECK-CPA-O0-NEXT: adrp x10, array
+; CHECK-CPA-O0-NEXT: add x10, x10, :lo12:array
+; CHECK-CPA-O0-NEXT: mov w8, #96 // =0x60
+; CHECK-CPA-O0-NEXT: // kill: def $x8 killed $w8
+; CHECK-CPA-O0-NEXT: addpt x8, x10, x8
+; CHECK-CPA-O0-NEXT: subs x9, x9, w0, sxtw
+; CHECK-CPA-O0-NEXT: ldr q0, [x10, #32]
; CHECK-CPA-O0-NEXT: str q0, [x8, x9, lsl #4]
; CHECK-CPA-O0-NEXT: ret
;
@@ -268,12 +268,12 @@ define void @subpt2(i32 %index, i32 %elem) {
;
; CHECK-NOCPA-O0-LABEL: subpt2:
; CHECK-NOCPA-O0: // %bb.0: // %entry
-; CHECK-NOCPA-O0-NEXT: mov x8, xzr
-; CHECK-NOCPA-O0-NEXT: subs x9, x8, w0, sxtw
-; CHECK-NOCPA-O0-NEXT: adrp x8, array
-; CHECK-NOCPA-O0-NEXT: add x8, x8, :lo12:array
-; CHECK-NOCPA-O0-NEXT: ldr q0, [x8, #32]
-; CHECK-NOCPA-O0-NEXT: add x8, x8, #96
+; CHECK-NOCPA-O0-NEXT: mov x9, xzr
+; CHECK-NOCPA-O0-NEXT: adrp x10, array
+; CHECK-NOCPA-O0-NEXT: add x10, x10, :lo12:array
+; CHECK-NOCPA-O0-NEXT: add x8, x10, #96
+; CHECK-NOCPA-O0-NEXT: subs x9, x9, w0, sxtw
+; CHECK-NOCPA-O0-NEXT: ldr q0, [x10, #32]
; CHECK-NOCPA-O0-NEXT: str q0, [x8, x9, lsl #4]
; CHECK-NOCPA-O0-NEXT: ret
;
@@ -645,31 +645,35 @@ entry:
define hidden void @multidim() {
; CHECK-CPA-O0-LABEL: multidim:
; CHECK-CPA-O0: // %bb.0: // %entry
-; CHECK-CPA-O0-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-CPA-O0-NEXT: .cfi_def_cfa_offset 16
+; CHECK-CPA-O0-NEXT: sub sp, sp, #32
+; CHECK-CPA-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
+; CHECK-CPA-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-CPA-O0-NEXT: .cfi_offset w30, -16
-; CHECK-CPA-O0-NEXT: adrp x8, b
-; CHECK-CPA-O0-NEXT: ldrh w9, [x8, :lo12:b]
-; CHECK-CPA-O0-NEXT: mov w10, w9
-; CHECK-CPA-O0-NEXT: ldrh w8, [x8, :lo12:b]
-; CHECK-CPA-O0-NEXT: add w9, w8, #1
-; CHECK-CPA-O0-NEXT: mov w8, #2 // =0x2
-; CHECK-CPA-O0-NEXT: mov w11, w8
+; CHECK-CPA-O0-NEXT: adrp x9, b
; CHECK-CPA-O0-NEXT: adrp x8, a
; CHECK-CPA-O0-NEXT: add x8, x8, :lo12:a
-; CHECK-CPA-O0-NEXT: addpt x8, x8, x11
+; CHECK-CPA-O0-NEXT: mov w10, #2 // =0x2
+; CHECK-CPA-O0-NEXT: // kill: def $x10 killed $w10
+; CHECK-CPA-O0-NEXT: addpt x8, x8, x10
+; CHECK-CPA-O0-NEXT: adrp x10, .L.str
+; CHECK-CPA-O0-NEXT: add x10, x10, :lo12:.L.str
+; CHECK-CPA-O0-NEXT: str x10, [sp, #8] // 8-byte Spill
+; CHECK-CPA-O0-NEXT: ldrh w10, [x9, :lo12:b]
+; CHECK-CPA-O0-NEXT: // kill: def $x10 killed $w10
; CHECK-CPA-O0-NEXT: addpt x8, x8, x10, lsl #1
+; CHECK-CPA-O0-NEXT: ldrh w9, [x9, :lo12:b]
+; CHECK-CPA-O0-NEXT: add w9, w9, #1
; CHECK-CPA-O0-NEXT: ldrb w8, [x8, w9, sxtw]
; CHECK-CPA-O0-NEXT: uxtb w8, w8
; CHECK-CPA-O0-NEXT: cbnz w8, .LBB14_1
; CHECK-CPA-O0-NEXT: b .LBB14_2
; CHECK-CPA-O0-NEXT: .LBB14_1:
-; CHECK-CPA-O0-NEXT: adrp x0, .L.str
-; CHECK-CPA-O0-NEXT: add x0, x0, :lo12:.L.str
+; CHECK-CPA-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
; CHECK-CPA-O0-NEXT: bl printf
; CHECK-CPA-O0-NEXT: b .LBB14_2
; CHECK-CPA-O0-NEXT: .LBB14_2:
-; CHECK-CPA-O0-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-CPA-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-CPA-O0-NEXT: add sp, sp, #32
; CHECK-CPA-O0-NEXT: ret
;
; CHECK-CPA-O3-LABEL: multidim:
@@ -696,29 +700,33 @@ define hidden void @multidim() {
;
; CHECK-NOCPA-O0-LABEL: multidim:
; CHECK-NOCPA-O0: // %bb.0: // %entry
-; CHECK-NOCPA-O0-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NOCPA-O0-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NOCPA-O0-NEXT: sub sp, sp, #32
+; CHECK-NOCPA-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
+; CHECK-NOCPA-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOCPA-O0-NEXT: .cfi_offset w30, -16
-; CHECK-NOCPA-O0-NEXT: adrp x8, b
-; CHECK-NOCPA-O0-NEXT: ldrh w9, [x8, :lo12:b]
-; CHECK-NOCPA-O0-NEXT: mov w10, w9
-; CHECK-NOCPA-O0-NEXT: ldrh w8, [x8, :lo12:b]
-; CHECK-NOCPA-O0-NEXT: add w9, w8, #1
+; CHECK-NOCPA-O0-NEXT: adrp x9, b
; CHECK-NOCPA-O0-NEXT: adrp x8, a
; CHECK-NOCPA-O0-NEXT: add x8, x8, :lo12:a
; CHECK-NOCPA-O0-NEXT: add x8, x8, #2
+; CHECK-NOCPA-O0-NEXT: adrp x10, .L.str
+; CHECK-NOCPA-O0-NEXT: add x10, x10, :lo12:.L.str
+; CHECK-NOCPA-O0-NEXT: str x10, [sp, #8] // 8-byte Spill
+; CHECK-NOCPA-O0-NEXT: ldrh w10, [x9, :lo12:b]
+; CHECK-NOCPA-O0-NEXT: // kill: def $x10 killed $w10
; CHECK-NOCPA-O0-NEXT: add x8, x8, x10, lsl #1
+; CHECK-NOCPA-O0-NEXT: ldrh w9, [x9, :lo12:b]
+; CHECK-NOCPA-O0-NEXT: add w9, w9, #1
; CHECK-NOCPA-O0-NEXT: ldrb w8, [x8, w9, sxtw]
; CHECK-NOCPA-O0-NEXT: uxtb w8, w8
; CHECK-NOCPA-O0-NEXT: cbnz w8, .LBB14_1
; CHECK-NOCPA-O0-NEXT: b .LBB14_2
; CHECK-NOCPA-O0-NEXT: .LBB14_1:
-; CHECK-NOCPA-O0-NEXT: adrp x0, .L.str
-; CHECK-NOCPA-O0-NEXT: add x0, x0, :lo12:.L.str
+; CHECK-NOCPA-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
; CHECK-NOCPA-O0-NEXT: bl printf
; CHECK-NOCPA-O0-NEXT: b .LBB14_2
; CHECK-NOCPA-O0-NEXT: .LBB14_2:
-; CHECK-NOCPA-O0-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NOCPA-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-NOCPA-O0-NEXT: add sp, sp, #32
; CHECK-NOCPA-O0-NEXT: ret
;
; CHECK-NOCPA-O3-LABEL: multidim:
diff --git a/llvm/test/CodeGen/AArch64/large-stack.ll b/llvm/test/CodeGen/AArch64/large-stack.ll
index a177398e66e50..2f9c6384e7d1b 100644
--- a/llvm/test/CodeGen/AArch64/large-stack.ll
+++ b/llvm/test/CodeGen/AArch64/large-stack.ll
@@ -32,15 +32,16 @@ attributes #0 = { noinline optnone "frame-pointer"="all" uwtable }
; CHECK-NEXT: sub sp, sp, #[[STACK2:[0-9]+]], lsl #12
; CHECK-NEXT: sub sp, sp, #[[STACK3:[0-9]+]]
; CHECK: sub x[[INDEX:[0-9]+]], x[[FRAME]], #8
+; CHECK-NEXT: mov x[[ONE:[0-9]+]], #1
+; CHECK-NEXT: adrp x[[STR:[0-9]+]], .L.str
+; CHECK-NEXT: add x[[STR]], x[[STR]], :lo12:.L.str
+; CHECK-NEXT: add x[[ARRAY:[0-9]+]], sp, #8
; CHECK-NEXT: str x0, [x[[INDEX]]]
; CHECK-NEXT: ldr x[[VAL1:[0-9]+]], [x[[INDEX]]]
-; CHECK-NEXT: add x10, sp, #8
-; CHECK-NEXT: mov x11, #1 // =0x1
-; CHECK-NEXT: str x11, [x10, x9, lsl #3]
-; CHECK-NEXT: ldr x8, [x8]
-; CHECK-NEXT: ldr x1, [x10, x8, lsl #3]
-; CHECK-NEXT: adrp x0, .L.str
-; CHECK-NEXT: add x0, x0, :lo12:.L.str
+; CHECK-NEXT: str x[[ONE]], [x[[ARRAY]], x[[VAL1]], lsl #3]
+; CHECK-NEXT: ldr x[[VAL2:[0-9]+]], [x[[INDEX]]]
+; CHECK-NEXT: ldr x1, [x[[ARRAY]], x[[VAL2]], lsl #3]
+; CHECK-NEXT: mov x0, x[[STR]]
; CHECK: bl printf
; CHECK-COUNT-128: add sp, sp, #[[STACK1]], lsl #12
; CHECK-NEXT: add sp, sp, #[[STACK2]], lsl #12
diff --git a/llvm/test/CodeGen/AArch64/phi-dbg.ll b/llvm/test/CodeGen/AArch64/phi-dbg.ll
index 4f7c005f8026f..fba69ad7aaf68 100644
--- a/llvm/test/CodeGen/AArch64/phi-dbg.ll
+++ b/llvm/test/CodeGen/AArch64/phi-dbg.ll
@@ -28,8 +28,9 @@ bb2:
call void @llvm.dbg.value(metadata i32 12, i64 0, metadata !15, metadata !13), !dbg !16
br label %bb3, !dbg !20
-; CHECK: bb.2.bb2:
+; CHECK: bb.1.entry:
; CHECK: [[REG0:%[0-9]+]]:gpr32 = MOVi32imm 12
+; CHECK: bb.2.bb2:
; CHECK: [[PHIREG:%[0-9]+]]:gpr32 = COPY [[REG0]]
bb3:
diff --git a/llvm/test/CodeGen/AArch64/popcount.ll b/llvm/test/CodeGen/AArch64/popcount.ll
index bb81776a7f6d6..adbb0dfeb475d 100644
--- a/llvm/test/CodeGen/AArch64/popcount.ll
+++ b/llvm/test/CodeGen/AArch64/popcount.ll
@@ -768,27 +768,28 @@ Entry:
define i32 @ctpop_into_extract(ptr %p) {
; CHECKO0-LABEL: ctpop_into_extract:
; CHECKO0: // %bb.0:
-; CHECKO0-NEXT: mov w8, #-1 // =0xffffffff
+; CHECKO0-NEXT: mov x8, x0
+; CHECKO0-NEXT: mov w9, #-1 // =0xffffffff
; CHECKO0-NEXT: // implicit-def: $d2
-; CHECKO0-NEXT: fmov s2, w8
-; CHECKO0-NEXT: ldr d0, [x0]
+; CHECKO0-NEXT: fmov s2, w9
+; CHECKO0-NEXT: mov w0, wzr
+; CHECKO0-NEXT: ldr d0, [x8]
; CHECKO0-NEXT: // implicit-def: $q1
; CHECKO0-NEXT: fmov d1, d0
-; CHECKO0-NEXT: mov w8, v1.s[0]
-; CHECKO0-NEXT: mov w1, w8
+; CHECKO0-NEXT: mov w9, v1.s[0]
+; CHECKO0-NEXT: mov w1, w9
; CHECKO0-NEXT: fmov d1, x1
; CHECKO0-NEXT: cnt v1.8b, v1.8b
; CHECKO0-NEXT: uaddlv h1, v1.8b
; CHECKO0-NEXT: // kill: def $q1 killed $h1
; CHECKO0-NEXT: // kill: def $s1 killed $s1 killed $q1
-; CHECKO0-NEXT: fmov w8, s1
+; CHECKO0-NEXT: fmov w9, s1
; CHECKO0-NEXT: // implicit-def: $q1
; CHECKO0-NEXT: fmov d1, d2
-; CHECKO0-NEXT: mov v1.s[1], w8
+; CHECKO0-NEXT: mov v1.s[1], w9
; CHECKO0-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECKO0-NEXT: sub v0.2s, v0.2s, v1.2s
-; CHECKO0-NEXT: str d0, [x0]
-; CHECKO0-NEXT: mov w0, wzr
+; CHECKO0-NEXT: str d0, [x8]
; CHECKO0-NEXT: ret
;
; NEON-LABEL: ctpop_into_extract:
@@ -868,27 +869,28 @@ define i32 @ctpop_into_extract(ptr %p) {
;
; GISELO0-LABEL: ctpop_into_extract:
; GISELO0: // %bb.0:
-; GISELO0-NEXT: mov w8, #-1 // =0xffffffff
+; GISELO0-NEXT: mov x8, x0
+; GISELO0-NEXT: mov w9, #-1 // =0xffffffff
; GISELO0-NEXT: // implicit-def: $d2
-; GISELO0-NEXT: fmov s2, w8
-; GISELO0-NEXT: ldr d0, [x0]
+; GISELO0-NEXT: fmov s2, w9
+; GISELO0-NEXT: mov w0, wzr
+; GISELO0-NEXT: ldr d0, [x8]
; GISELO0-NEXT: // implicit-def: $q1
; GISELO0-NEXT: fmov d1, d0
-; GISELO0-NEXT: mov w8, v1.s[0]
-; GISELO0-NEXT: mov w1, w8
+; GISELO0-NEXT: mov w9, v1.s[0]
+; GISELO0-NEXT: mov w1, w9
; GISELO0-NEXT: fmov d1, x1
; GISELO0-NEXT: cnt v1.8b, v1.8b
; GISELO0-NEXT: uaddlv h1, v1.8b
; GISELO0-NEXT: // kill: def $q1 killed $h1
; GISELO0-NEXT: // kill: def $s1 killed $s1 killed $q1
-; GISELO0-NEXT: fmov w8, s1
+; GISELO0-NEXT: fmov w9, s1
; GISELO0-NEXT: // implicit-def: $q1
; GISELO0-NEXT: fmov d1, d2
-; GISELO0-NEXT: mov v1.s[1], w8
+; GISELO0-NEXT: mov v1.s[1], w9
; GISELO0-NEXT: // kill: def $d1 killed $d1 killed $q1
; GISELO0-NEXT: sub v0.2s, v0.2s, v1.2s
-; GISELO0-NEXT: str d0, [x0]
-; GISELO0-NEXT: mov w0, wzr
+; GISELO0-NEXT: str d0, [x8]
; GISELO0-NEXT: ret
%1 = load <2 x i32>, ptr %p, align 4
%2 = extractelement <2 x i32> %1, i64 0
diff --git a/llvm/test/CodeGen/AArch64/pr92062.ll b/llvm/test/CodeGen/AArch64/pr92062.ll
index 6111ee0fbe18f..c6f8922cc2a48 100644
--- a/llvm/test/CodeGen/AArch64/pr92062.ll
+++ b/llvm/test/CodeGen/AArch64/pr92062.ll
@@ -10,8 +10,8 @@ define void @foo() {
; CHECK: // %bb.0: // %bb
; CHECK-NEXT: adrp x8, :got:p
; CHECK-NEXT: ldr x8, [x8, :got_lo12:p]
-; CHECK-NEXT: ldr x8, [x8]
; CHECK-NEXT: mov x9, xzr
+; CHECK-NEXT: ldr x8, [x8]
; CHECK-NEXT: str x8, [x9]
; CHECK-NEXT: ret
bb:
diff --git a/llvm/test/CodeGen/AArch64/vararg.ll b/llvm/test/CodeGen/AArch64/vararg.ll
index 291eee2ddf706..33ac571b6d4c1 100644
--- a/llvm/test/CodeGen/AArch64/vararg.ll
+++ b/llvm/test/CodeGen/AArch64/vararg.ll
@@ -86,6 +86,8 @@ define i64 @vararg(...) #0 {
; CHECK-GI-NEXT: str q5, [sp, #96]
; CHECK-GI-NEXT: str q6, [sp, #112]
; CHECK-GI-NEXT: str q7, [sp, #128]
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: mov w0, w8
; CHECK-GI-NEXT: add x9, sp, #8
; CHECK-GI-NEXT: add x8, x29, #16
; CHECK-GI-NEXT: str x8, [x9]
@@ -97,8 +99,6 @@ define i64 @vararg(...) #0 {
; CHECK-GI-NEXT: str w8, [x9, #24]
; CHECK-GI-NEXT: mov w8, #-128 // =0xffffff80
; CHECK-GI-NEXT: str w8, [x9, #28]
-; CHECK-GI-NEXT: mov w8, #1 // =0x1
-; CHECK-GI-NEXT: mov w0, w8
; CHECK-GI-NEXT: .cfi_def_cfa wsp, 224
; CHECK-GI-NEXT: ldp x29, x30, [sp, #208] // 16-byte Folded Reload
; CHECK-GI-NEXT: add sp, sp, #224
@@ -171,6 +171,8 @@ define i64 @vararg_many_gpr(i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6
; CHECK-GI-NEXT: str q5, [sp, #96]
; CHECK-GI-NEXT: str q6, [sp, #112]
; CHECK-GI-NEXT: str q7, [sp, #128]
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: mov w0, w8
; CHECK-GI-NEXT: add x9, sp, #8
; CHECK-GI-NEXT: add x8, x29, #16
; CHECK-GI-NEXT: str x8, [x9]
@@ -182,8 +184,6 @@ define i64 @vararg_many_gpr(i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6
; CHECK-GI-NEXT: str w8, [x9, #24]
; CHECK-GI-NEXT: mov w8, #-128 // =0xffffff80
; CHECK-GI-NEXT: str w8, [x9, #28]
-; CHECK-GI-NEXT: mov w8, #1 // =0x1
-; CHECK-GI-NEXT: mov w0, w8
; CHECK-GI-NEXT: .cfi_def_cfa wsp, 176
; CHECK-GI-NEXT: ldp x29, x30, [sp, #160] // 16-byte Folded Reload
; CHECK-GI-NEXT: add sp, sp, #176
@@ -256,6 +256,8 @@ define i64 @vararg_many_float(float %a1, float %a2, float %a3, float %a4, float
; CHECK-GI-NEXT: str x6, [sp, #80]
; CHECK-GI-NEXT: str x7, [sp, #88]
; CHECK-GI-NEXT: str q7, [sp, #16]
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: mov w0, w8
; CHECK-GI-NEXT: add x9, sp, #8
; CHECK-GI-NEXT: add x8, x29, #16
; CHECK-GI-NEXT: str x8, [x9]
@@ -267,8 +269,6 @@ define i64 @vararg_many_float(float %a1, float %a2, float %a3, float %a4, float
; CHECK-GI-NEXT: str w8, [x9, #24]
; CHECK-GI-NEXT: mov w8, #-16 // =0xfffffff0
; CHECK-GI-NEXT: str w8, [x9, #28]
-; CHECK-GI-NEXT: mov w8, #1 // =0x1
-; CHECK-GI-NEXT: mov w0, w8
; CHECK-GI-NEXT: .cfi_def_cfa wsp, 112
; CHECK-GI-NEXT: ldp x29, x30, [sp, #96] // 16-byte Folded Reload
; CHECK-GI-NEXT: add sp, sp, #112
@@ -351,6 +351,8 @@ define i64 @gpr1_fpr1(i32 %i, float %f, ...) #0 {
; CHECK-GI-NEXT: str q5, [sp, #80]
; CHECK-GI-NEXT: str q6, [sp, #96]
; CHECK-GI-NEXT: str q7, [sp, #112]
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: mov w0, w8
; CHECK-GI-NEXT: add x9, sp, #8
; CHECK-GI-NEXT: add x8, x29, #16
; CHECK-GI-NEXT: str x8, [x9]
@@ -362,8 +364,6 @@ define i64 @gpr1_fpr1(i32 %i, float %f, ...) #0 {
; CHECK-GI-NEXT: str w8, [x9, #24]
; CHECK-GI-NEXT: mov w8, #-112 // =0xffffff90
; CHECK-GI-NEXT: str w8, [x9, #28]
-; CHECK-GI-NEXT: mov w8, #1 // =0x1
-; CHECK-GI-NEXT: mov w0, w8
; CHECK-GI-NEXT: .cfi_def_cfa wsp, 208
; CHECK-GI-NEXT: ldp x29, x30, [sp, #192] // 16-byte Folded Reload
; CHECK-GI-NEXT: add sp, sp, #208
diff --git a/llvm/test/CodeGen/AArch64/win64_vararg_float.ll b/llvm/test/CodeGen/AArch64/win64_vararg_float.ll
index a99b29fa3bef9..d3f9b45c6b687 100644
--- a/llvm/test/CodeGen/AArch64/win64_vararg_float.ll
+++ b/llvm/test/CodeGen/AArch64/win64_vararg_float.ll
@@ -118,12 +118,12 @@ define void @call_f_va() nounwind {
;
; GISEL-LABEL: call_f_va:
; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: fmov s0, #1.00000000
-; GISEL-NEXT: fmov w0, s0
+; GISEL-NEXT: fmov s1, #1.00000000
; GISEL-NEXT: mov w1, #2 // =0x2
; GISEL-NEXT: fmov d0, #3.00000000
-; GISEL-NEXT: fmov x2, d0
; GISEL-NEXT: mov w3, #4 // =0x4
+; GISEL-NEXT: fmov w0, s1
+; GISEL-NEXT: fmov x2, d0
; GISEL-NEXT: b other_f_va_fn
entry:
tail call void (float, i32, ...) @other_f_va_fn(float 1.000000e+00, i32 2, double 3.000000e+00, i32 4)
@@ -151,12 +151,12 @@ define void @call_d_va() nounwind {
;
; GISEL-LABEL: call_d_va:
; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: fmov d0, #1.00000000
-; GISEL-NEXT: fmov x0, d0
+; GISEL-NEXT: fmov d1, #1.00000000
; GISEL-NEXT: mov w1, #2 // =0x2
; GISEL-NEXT: fmov d0, #3.00000000
-; GISEL-NEXT: fmov x2, d0
; GISEL-NEXT: mov w3, #4 // =0x4
+; GISEL-NEXT: fmov x0, d1
+; GISEL-NEXT: fmov x2, d0
; GISEL-NEXT: b other_d_va_fn
entry:
tail call void (double, i32, ...) @other_d_va_fn(double 1.000000e+00, i32 2, double 3.000000e+00, i32 4)
diff --git a/llvm/test/CodeGen/AArch64/win64_vararg_float_cc.ll b/llvm/test/CodeGen/AArch64/win64_vararg_float_cc.ll
index 029d2da43b691..049cee9341417 100644
--- a/llvm/test/CodeGen/AArch64/win64_vararg_float_cc.ll
+++ b/llvm/test/CodeGen/AArch64/win64_vararg_float_cc.ll
@@ -138,12 +138,12 @@ define void @call_f_va() nounwind {
; GISEL-LABEL: call_f_va:
; GISEL: // %bb.0: // %entry
; GISEL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; GISEL-NEXT: fmov s0, #1.00000000
-; GISEL-NEXT: fmov w0, s0
+; GISEL-NEXT: fmov s1, #1.00000000
; GISEL-NEXT: mov w1, #2 // =0x2
; GISEL-NEXT: fmov d0, #3.00000000
-; GISEL-NEXT: fmov x2, d0
; GISEL-NEXT: mov w3, #4 // =0x4
+; GISEL-NEXT: fmov w0, s1
+; GISEL-NEXT: fmov x2, d0
; GISEL-NEXT: bl other_f_va_fn
; GISEL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; GISEL-NEXT: ret
@@ -180,12 +180,12 @@ define void @call_d_va() nounwind {
; GISEL-LABEL: call_d_va:
; GISEL: // %bb.0: // %entry
; GISEL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; GISEL-NEXT: fmov d0, #1.00000000
-; GISEL-NEXT: fmov x0, d0
+; GISEL-NEXT: fmov d1, #1.00000000
; GISEL-NEXT: mov w1, #2 // =0x2
; GISEL-NEXT: fmov d0, #3.00000000
-; GISEL-NEXT: fmov x2, d0
; GISEL-NEXT: mov w3, #4 // =0x4
+; GISEL-NEXT: fmov x0, d1
+; GISEL-NEXT: fmov x2, d0
; GISEL-NEXT: bl other_d_va_fn
; GISEL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; GISEL-NEXT: ret
diff --git a/llvm/test/Other/print-changed-machine.ll b/llvm/test/Other/print-changed-machine.ll
index 7b2b9b3c10d95..e2143d113a7f1 100644
--- a/llvm/test/Other/print-changed-machine.ll
+++ b/llvm/test/Other/print-changed-machine.ll
@@ -24,7 +24,7 @@
; QUIET: *** IR Dump After IRTranslator (ir-translator) on foo ***
; QUIET-NOT: ***
-; QUIET: *** IR Dump After Localizer (localizer) on foo ***
+; QUIET: *** IR Dump After Legalizer (legalizer) on foo ***
; RUN: llc -filetype=null -mtriple=aarch64 -O0 -print-changed -filter-passes=ir-translator,legalizer %s 2>&1 | \
; RUN: FileCheck %s --check-prefixes=VERBOSE-FILTER
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