[clang] 4a51cf1 - [RISCV][P-ext] Add scalar rev16 intrinsic (#230704)
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Mon Oct 12 22:07:14 PDT 2026
Author: Craig Topper
Date: 2026-10-13T05:07:07Z
New Revision: 4a51cf16b821f83df895aa66b82578c3a45fda7b
URL: https://github.com/llvm/llvm-project/commit/4a51cf16b821f83df895aa66b82578c3a45fda7b
DIFF: https://github.com/llvm/llvm-project/commit/4a51cf16b821f83df895aa66b82578c3a45fda7b.diff
LOG: [RISCV][P-ext] Add scalar rev16 intrinsic (#230704)
Assisted-by: Claude
Added:
Modified:
clang/include/clang/Basic/BuiltinsRISCV.td
clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
clang/lib/Headers/riscv_packed_simd.h
clang/test/CodeGen/RISCV/rvp-intrinsics.c
cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoP.td
llvm/test/CodeGen/RISCV/rv64p.ll
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td
index 001b93189870b..6f6dc52b29dae 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -261,6 +261,9 @@ def pmerge_u8x8 : RISCVBuiltin<"_Vector<8, unsigned char>(_Vector<8, unsigned ch
def pmerge_u16x4 : RISCVBuiltin<"_Vector<4, unsigned short>(_Vector<4, unsigned short>, _Vector<4, unsigned short>, _Vector<4, unsigned short>)">;
def pmerge_u32x2 : RISCVBuiltin<"_Vector<2, unsigned int>(_Vector<2, unsigned int>, _Vector<2, unsigned int>, _Vector<2, unsigned int>)">;
+// Scalar Bitmanip
+def rev16_64 : RISCVBuiltin<"uint64_t(uint64_t)", "64bit">;
+
// Scalar Averaging Addition and Subtraction
def aadd_i32 : RISCVBuiltin<"int32_t(int32_t, int32_t)">;
def aaddu_u32 : RISCVBuiltin<"uint32_t(uint32_t, uint32_t)">;
diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
index 71e72a713d8d5..a911b0f7b65f1 100644
--- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
@@ -1199,6 +1199,11 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
break;
}
+ // P extension scalar bitmanip
+ case RISCV::BI__builtin_riscv_rev16_64:
+ ID = Intrinsic::riscv_rev16_64;
+ break;
+
// Packed Widening Shifts
case RISCV::BI__builtin_riscv_pwsll_s_u16x4:
case RISCV::BI__builtin_riscv_pwsll_s_u32x2:
diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h
index af2bf7cbb77ce..c1b784e90165b 100644
--- a/clang/lib/Headers/riscv_packed_simd.h
+++ b/clang/lib/Headers/riscv_packed_simd.h
@@ -441,6 +441,7 @@ __packed_srx(srx_32, uint32_t)
#if __riscv_xlen == 64
__packed_cls(cls_64, int64_t, __builtin_clrsbll)
__packed_unary_builtin(rev_64, uint64_t, __builtin_bitreverse64)
+__packed_unary_builtin(rev16_64, uint64_t, __builtin_riscv_rev16_64)
__packed_slx(slx_64, uint64_t)
__packed_srx(srx_64, uint64_t)
#endif
diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
index 61dffaaa2058e..e693f52a54d80 100644
--- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c
+++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
@@ -105,6 +105,16 @@ uint64_t test_rev_64(uint64_t a) {
return __riscv_rev_64(a);
}
+// RV64-LABEL: define dso_local i64 @test_rev16_64(
+// RV64-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.rev16.64(i64 [[A]])
+// RV64-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_rev16_64(uint64_t a) {
+ return __riscv_rev16_64(a);
+}
+
// RV64-LABEL: define dso_local i64 @test_slx_64(
// RV64-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
// RV64-NEXT: [[ENTRY:.*:]]
diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
index 073ae94ac7111..75c5a1ff8b75d 100644
--- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
@@ -51,6 +51,10 @@ unsigned test_cls_64(int64_t a) { return __riscv_cls_64(a); }
// RV64: rev{{[[:space:]]}}
uint64_t test_rev_64(uint64_t a) { return __riscv_rev_64(a); }
+// RV64-LABEL: test_rev16_64:
+// RV64: rev16{{[[:space:]]}}
+uint64_t test_rev16_64(uint64_t a) { return __riscv_rev16_64(a); }
+
// RV64-LABEL: test_slx_64:
// RV64: slx{{[[:space:]]}}
uint64_t test_slx_64(uint64_t rd, uint64_t rs1, unsigned shamt) {
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index c0df519d02b19..8c8258cf7b12b 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -2140,6 +2140,10 @@ class RVPBinaryIntrinsic
[IntrNoMem, IntrSpeculatable]>;
def int_riscv_pmerge : RVPTernaryIntrinsic;
+ // Reverse the order of the 16-bit halfwords of a 64-bit value (RV64 only).
+ def int_riscv_rev16_64 : DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i64_ty],
+ [IntrNoMem, IntrSpeculatable]>;
+
// Packed Sign and Zero Extend.
class RVPExtIntrinsic
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 759f21952c93e..0ee01bdc4ab1f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -3180,6 +3180,7 @@ let append Predicates = [IsRV32] in {
let append Predicates = [IsRV64] in {
def : PatGpr<riscv_absw, ABSW>;
def : PatGpr<riscv_clsw, CLSW>;
+ def : PatGpr<int_riscv_rev16_64, REV16_RV64>;
def : PatGpr<bitreverse, REV_RV64>;
diff --git a/llvm/test/CodeGen/RISCV/rv64p.ll b/llvm/test/CodeGen/RISCV/rv64p.ll
index b4b0277d1b4f3..5ceae2996fe3d 100644
--- a/llvm/test/CodeGen/RISCV/rv64p.ll
+++ b/llvm/test/CodeGen/RISCV/rv64p.ll
@@ -1853,6 +1853,15 @@ define i32 @test_mulhrsu_i32(i32 %rs1, i32 %rs2) {
ret i32 %res
}
+define i64 @rev16_intrinsic(i64 %x) {
+; CHECK-LABEL: rev16_intrinsic:
+; CHECK: # %bb.0:
+; CHECK-NEXT: rev16 a0, a0
+; CHECK-NEXT: ret
+ %r = call i64 @llvm.riscv.rev16.64(i64 %x)
+ ret i64 %r
+}
+
define i32 @test_aadd_i32(i32 %a, i32 %b) {
; CHECK-LABEL: test_aadd_i32:
; CHECK: # %bb.0:
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