[clang] [CIR] Added Vector Reduce Op (PR #226546)

[Andy Kaylor via cfe-commits]

================
@@ -2425,42 +2425,48 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) {
   case X86::BI__builtin_ia32_reduce_fadd_ph512:
   case X86::BI__builtin_ia32_reduce_fadd_ph256:
   case X86::BI__builtin_ia32_reduce_fadd_ph128: {
-    assert(!cir::MissingFeatures::fastMathFlags());
-    return builder.emitIntrinsicCallOp(getLoc(expr->getExprLoc()),
-                                       "vector.reduce.fadd", ops[0].getType(),
-                                       mlir::ValueRange{ops[0], ops[1]});
+    CIRGenFPOptionsRAII FPOptsRAII(*this, expr);
+    cir::FastMathFlagsAttr fastMath =
+        getFastMathFlagsAttr(cir::FastMathFlags::reassoc);
----------------
andykaylor wrote:

I don't like the way you've implemented and named `getFastMathFlagsAttr` here. It reads like you're just getting an attribute with this one flag set. Compare this to the classic codegen implementation:

```
    IRBuilder<>::FastMathFlagGuard FMFGuard(Builder);
    Builder.getFastMathFlags().setAllowReassoc();
```
There it is clear that we are retrieving the current flags and adding `reassoc` to them.

https://github.com/llvm/llvm-project/pull/226546