[clang] Add synthetic inlined debug info for memset and memcpy (PR #229218)
via cfe-commits
cfe-commits at lists.llvm.org
Mon Oct 5 15:03:17 PDT 2026
https://github.com/mxms0 updated https://github.com/llvm/llvm-project/pull/229218
>From 498ecd2418a82de91b69e0298ecaed5a689b9eea Mon Sep 17 00:00:00 2001
From: mxms <mxms at google.com>
Date: Mon, 5 Oct 2026 16:29:38 -0400
Subject: [PATCH 1/2] Add synthetic inlined debug info for llvm.memset and
llvm.memcpy emitted by Clang CodeGen.
When list-initializers or aggregate initializations (such as `char array[24] = { 0 }`) are lowered to `llvm.memset` or `llvm.memcpy`, compiler optimizations can inline these memory operations into sequences stores. Without debug information attributing the generated machine instructions to an inlined `memset` or `memcpy` frame, sampling profilers attribute execution samples directly to the enclosing function at the variable declaration line, obscuring implicit initialization.
`CGBuilderTy::CreateMemSet` and `CGBuilderTy::CreateMemCpy` now rewrite the debug location of the emitted intrinsic call so it appears inlined from a synthetic artificial `memset`/`memcpy` subprogram at the builder's current location.
When the intrinsic is expanded into stores, DWARF contains `DW_TAG_inlined_subroutine` records, so profilers and debuggers attribute those stores to an inlined `memset` or `memcpy` frame at the source location.
The location is set after the instruction is created rather than in `CGBuilderInserter::InsertHelper`, because `IRBuilder` applies the current debug location after the inserter runs.
The OpenMP debug-info tests were regenerated with `update_cc_test_checks.py`.
---
clang/lib/CodeGen/CGBuilder.h | 27 +-
clang/lib/CodeGen/CGDebugInfo.cpp | 6 +
clang/lib/CodeGen/CGDebugInfo.h | 2 +-
clang/lib/CodeGen/CodeGenFunction.cpp | 13 +
.../test/CodeGen/memset-debuginfo-list-init.c | 39 +
.../CodeGenCXX/memset-debuginfo-list-init.cpp | 61 +
clang/test/DebugInfo/CXX/line.cpp | 4 +-
clang/test/OpenMP/error_codegen.cpp | 248 ++--
clang/test/OpenMP/single_codegen.cpp | 1252 ++++++++---------
.../OpenMP/target_parallel_debug_codegen.cpp | 716 +++++-----
.../target_parallel_for_debug_codegen.cpp | 954 ++++++-------
...target_parallel_generic_loop_codegen-3.cpp | 954 ++++++-------
12 files changed, 2210 insertions(+), 2066 deletions(-)
create mode 100644 clang/test/CodeGen/memset-debuginfo-list-init.c
create mode 100644 clang/test/CodeGenCXX/memset-debuginfo-list-init.cpp
diff --git a/clang/lib/CodeGen/CGBuilder.h b/clang/lib/CodeGen/CGBuilder.h
index 18e738f10ba3b..bef44fa8ee789 100644
--- a/clang/lib/CodeGen/CGBuilder.h
+++ b/clang/lib/CodeGen/CGBuilder.h
@@ -58,6 +58,14 @@ class CGBuilderTy : public CGBuilderBaseTy {
CodeGenFunction *getCGF() const { return getInserter().CGF; }
+ /// If debug info is enabled, rewrite the debug location of \p CI so that it
+ /// appears inlined from a synthetic artificial function named \p FuncName at
+ /// its current location. This lets profilers and debuggers attribute the
+ /// stores that implicit llvm.memset/llvm.memcpy calls are later expanded
+ /// into to a memset/memcpy frame instead of the enclosing function.
+ void attachSyntheticInlineDebugLoc(llvm::CallInst *CI,
+ llvm::StringRef FuncName);
+
llvm::Value *emitRawPointerFromAddress(Address Addr) const {
return Addr.getBasePointer();
}
@@ -398,15 +406,21 @@ class CGBuilderTy : public CGBuilderBaseTy {
bool IsVolatile = false) {
llvm::Value *DestPtr = emitRawPointerFromAddress(Dest);
llvm::Value *SrcPtr = emitRawPointerFromAddress(Src);
- return CreateMemCpy(DestPtr, Dest.getAlignment().getAsAlign(), SrcPtr,
- Src.getAlignment().getAsAlign(), Size, IsVolatile);
+ llvm::CallInst *CI =
+ CreateMemCpy(DestPtr, Dest.getAlignment().getAsAlign(), SrcPtr,
+ Src.getAlignment().getAsAlign(), Size, IsVolatile);
+ attachSyntheticInlineDebugLoc(CI, "memcpy");
+ return CI;
}
llvm::CallInst *CreateMemCpy(Address Dest, Address Src, uint64_t Size,
bool IsVolatile = false) {
llvm::Value *DestPtr = emitRawPointerFromAddress(Dest);
llvm::Value *SrcPtr = emitRawPointerFromAddress(Src);
- return CreateMemCpy(DestPtr, Dest.getAlignment().getAsAlign(), SrcPtr,
- Src.getAlignment().getAsAlign(), Size, IsVolatile);
+ llvm::CallInst *CI =
+ CreateMemCpy(DestPtr, Dest.getAlignment().getAsAlign(), SrcPtr,
+ Src.getAlignment().getAsAlign(), Size, IsVolatile);
+ attachSyntheticInlineDebugLoc(CI, "memcpy");
+ return CI;
}
using CGBuilderBaseTy::CreateMemCpyInline;
@@ -429,8 +443,11 @@ class CGBuilderTy : public CGBuilderBaseTy {
using CGBuilderBaseTy::CreateMemSet;
llvm::CallInst *CreateMemSet(Address Dest, llvm::Value *Value,
llvm::Value *Size, bool IsVolatile = false) {
- return CreateMemSet(emitRawPointerFromAddress(Dest), Value, Size,
+ llvm::CallInst *CI =
+ CreateMemSet(emitRawPointerFromAddress(Dest), Value, Size,
Dest.getAlignment().getAsAlign(), IsVolatile);
+ attachSyntheticInlineDebugLoc(CI, "memset");
+ return CI;
}
using CGBuilderBaseTy::CreateMemSetInline;
diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp b/clang/lib/CodeGen/CGDebugInfo.cpp
index 93428777b9b24..88908dbae2a61 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -4188,6 +4188,12 @@ llvm::DILocation *
CGDebugInfo::CreateSyntheticInlineAt(llvm::DebugLoc ParentLocation,
StringRef SynthFuncName,
llvm::DIFile *SynthFile) {
+ if (!ParentLocation)
+ return nullptr;
+ if (!SynthFile)
+ SynthFile = ParentLocation->getFile();
+ if (!SynthFile && TheCU)
+ SynthFile = TheCU->getFile();
llvm::DISubprogram *SP = createInlinedSubprogram(SynthFuncName, SynthFile);
return CreateSyntheticInlineAt(ParentLocation, SP);
}
diff --git a/clang/lib/CodeGen/CGDebugInfo.h b/clang/lib/CodeGen/CGDebugInfo.h
index 37520394812b4..59569ce96be90 100644
--- a/clang/lib/CodeGen/CGDebugInfo.h
+++ b/clang/lib/CodeGen/CGDebugInfo.h
@@ -685,7 +685,7 @@ class CGDebugInfo {
llvm::DISubprogram *SynthSubprogram);
llvm::DILocation *CreateSyntheticInlineAt(llvm::DebugLoc ParentLocation,
StringRef SynthFuncName,
- llvm::DIFile *SynthFile);
+ llvm::DIFile *SynthFile = nullptr);
/// Reset internal state.
void completeFunction();
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index 62dade6cf6f49..130b5a9717710 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2895,6 +2895,19 @@ void CGBuilderInserter::InsertHelper(
CGF->InsertHelper(I, Name, InsertPt);
}
+void CGBuilderTy::attachSyntheticInlineDebugLoc(llvm::CallInst *CI,
+ StringRef FuncName) {
+ // This can't be done from CGBuilderInserter::InsertHelper because IRBuilder
+ // sets the instruction's debug location after the inserter runs.
+ CodeGenFunction *CGF = getCGF();
+ CGDebugInfo *DI = CGF ? CGF->getDebugInfo() : nullptr;
+ if (!DI)
+ return;
+ if (llvm::DebugLoc DL = CI->getDebugLoc())
+ if (llvm::DILocation *SynthLoc = DI->CreateSyntheticInlineAt(DL, FuncName))
+ CI->setDebugLoc(SynthLoc);
+}
+
// Emits an error if we don't have a valid set of target features for the
// called function.
void CodeGenFunction::checkTargetFeatures(const CallExpr *E,
diff --git a/clang/test/CodeGen/memset-debuginfo-list-init.c b/clang/test/CodeGen/memset-debuginfo-list-init.c
new file mode 100644
index 0000000000000..d047067749d65
--- /dev/null
+++ b/clang/test/CodeGen/memset-debuginfo-list-init.c
@@ -0,0 +1,39 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -O0 -emit-llvm -debug-info-kind=limited %s -o - | FileCheck %s
+
+void use(void *);
+
+// CHECK-LABEL: define {{.*}}void @test_memset_zero_init()
+void test_memset_zero_init(void) {
+ // CHECK: call void @llvm.memset.{{.*}} !dbg ![[LOC_MEMSET:[0-9]+]]
+ char array[24] = { 0 };
+ use(array);
+}
+
+// CHECK-LABEL: define {{.*}}void @test_memcpy_init()
+void test_memcpy_init(void) {
+ // CHECK: call void @llvm.memcpy.{{.*}} !dbg ![[LOC_MEMCPY:[0-9]+]]
+ char array[24] = { 1, 2, 3 };
+ use(array);
+}
+
+struct Big {
+ int arr[20];
+};
+
+// CHECK-LABEL: define {{.*}}void @test_agg_memset()
+void test_agg_memset(void) {
+ // CHECK: call void @llvm.memset.{{.*}} !dbg ![[LOC_AGG:[0-9]+]]
+ struct Big b = { 0 };
+ use(&b);
+}
+
+// CHECK-DAG: ![[LOC_MEMSET]] = !DILocation(line: 0, scope: ![[SP_MEMSET:[0-9]+]], inlinedAt: ![[INLINED_MEMSET:[0-9]+]])
+// CHECK-DAG: ![[SP_MEMSET]] = distinct !DISubprogram(name: "memset", scope: ![[FILE:[0-9]+]], file: ![[FILE]], type: ![[SUBROUTINE_TYPE:[0-9]+]], flags: DIFlagArtificial, spFlags: DISPFlagDefinition, unit: ![[CU:[0-9]+]])
+// CHECK-DAG: ![[INLINED_MEMSET]] = !DILocation(line: [[#]], column: [[#]], scope: ![[SP_FUNC_ZERO:[0-9]+]])
+
+// CHECK-DAG: ![[LOC_MEMCPY]] = !DILocation(line: 0, scope: ![[SP_MEMCPY:[0-9]+]], inlinedAt: ![[INLINED_MEMCPY:[0-9]+]])
+// CHECK-DAG: ![[SP_MEMCPY]] = distinct !DISubprogram(name: "memcpy", scope: ![[FILE]], file: ![[FILE]], type: ![[SUBROUTINE_TYPE]], flags: DIFlagArtificial, spFlags: DISPFlagDefinition, unit: ![[CU]])
+// CHECK-DAG: ![[INLINED_MEMCPY]] = !DILocation(line: [[#]], column: [[#]], scope: ![[SP_FUNC_CPY:[0-9]+]])
+
+// CHECK-DAG: ![[LOC_AGG]] = !DILocation(line: 0, scope: ![[SP_MEMSET]], inlinedAt: ![[INLINED_AGG:[0-9]+]])
+
diff --git a/clang/test/CodeGenCXX/memset-debuginfo-list-init.cpp b/clang/test/CodeGenCXX/memset-debuginfo-list-init.cpp
new file mode 100644
index 0000000000000..580c1fcc5e4f4
--- /dev/null
+++ b/clang/test/CodeGenCXX/memset-debuginfo-list-init.cpp
@@ -0,0 +1,61 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -O0 -emit-llvm -debug-info-kind=limited %s -o - | FileCheck %s
+
+void use(void *);
+
+struct A {
+ char buf[64];
+};
+
+// CHECK-LABEL: define {{.*}}void @_Z18test_cpp_aggregatev()
+void test_cpp_aggregate() {
+ // CHECK: call void @llvm.memset.{{.*}} !dbg ![[LOC_AGG:[0-9]+]]
+ A a = { 0 };
+ use(&a);
+}
+
+// CHECK-LABEL: define {{.*}}void @_Z14test_cpp_arrayv()
+void test_cpp_array() {
+ // CHECK: call void @llvm.memset.{{.*}} !dbg ![[LOC_ARR:[0-9]+]]
+ char array[24] = { 0 };
+ use(array);
+}
+
+struct Base {
+ char buf[32];
+};
+struct Derived : Base {
+ int x;
+ Derived() : Base(), x(0) {}
+};
+
+void test_derived() {
+ Derived d;
+ use(&d);
+}
+
+// CHECK-LABEL: define {{.*}}void @_Z21test_cpp_empty_bracesv()
+void test_cpp_empty_braces() {
+ // CHECK: call void @llvm.memset.{{.*}} !dbg ![[LOC_EMPTY:[0-9]+]]
+ char array[24]{};
+ use(array);
+}
+
+// CHECK-LABEL: define {{.*}}void @_Z18test_cpp_array_newv()
+void test_cpp_array_new() {
+ // CHECK: call void @llvm.memset.{{.*}} !dbg ![[LOC_NEW:[0-9]+]]
+ char *p = new char[24]{};
+ use(p);
+}
+
+// CHECK-LABEL: define {{.*}}void @_ZN7DerivedC2Ev(
+// CHECK: call void @llvm.memset.{{.*}} !dbg ![[LOC_BASE:[0-9]+]]
+
+// CHECK-DAG: ![[LOC_AGG]] = !DILocation(line: 0, scope: ![[SP_MEMSET:[0-9]+]], inlinedAt: ![[INLINED_AGG:[0-9]+]])
+// CHECK-DAG: ![[SP_MEMSET]] = distinct !DISubprogram(name: "memset", scope: ![[FILE:[0-9]+]], file: ![[FILE]], type: ![[SUBROUTINE_TYPE:[0-9]+]], flags: DIFlagArtificial, spFlags: DISPFlagDefinition, unit: ![[CU:[0-9]+]])
+
+// CHECK-DAG: ![[LOC_ARR]] = !DILocation(line: 0, scope: ![[SP_MEMSET]], inlinedAt: ![[INLINED_ARR:[0-9]+]])
+// CHECK-DAG: ![[LOC_BASE]] = !DILocation(line: 0, scope: ![[SP_MEMSET]], inlinedAt: ![[INLINED_BASE:[0-9]+]])
+// CHECK-DAG: ![[LOC_EMPTY]] = !DILocation(line: 0, scope: ![[SP_MEMSET]], inlinedAt: ![[INLINED_EMPTY:[0-9]+]])
+// CHECK-DAG: ![[LOC_NEW]] = !DILocation(line: 0, scope: ![[SP_MEMSET]], inlinedAt: ![[INLINED_NEW:[0-9]+]])
+
+
diff --git a/clang/test/DebugInfo/CXX/line.cpp b/clang/test/DebugInfo/CXX/line.cpp
index 59568ed2469b7..1fb26d2d4af51 100644
--- a/clang/test/DebugInfo/CXX/line.cpp
+++ b/clang/test/DebugInfo/CXX/line.cpp
@@ -308,7 +308,9 @@ void f25() {
// CHECK: [[DBG_F3]] = !DILocation(line: 400,
// CHECK: [[DBG_F4]] = !DILocation(line: 500,
// CHECK: [[DBG_F5]] = !DILocation(line: 600,
-// CHECK: [[DBG_F6]] = !DILocation(line: 700,
+// CHECK: [[DBG_F6]] = !DILocation(line: 0, scope: [[DBG_F6_MEMCPY:![0-9]+]], inlinedAt: [[DBG_F6_INLINED_AT:![0-9]+]])
+// CHECK: [[DBG_F6_MEMCPY]] = distinct !DISubprogram(name: "memcpy",
+// CHECK: [[DBG_F6_INLINED_AT]] = !DILocation(line: 700,
// CHECK: [[DBG_F7]] = !DILocation(line: 800,
// CHECK: [[DBG_F8]] = !DILocation(line: 900,
// CHECK: [[DBG_F9]] = !DILocation(line: 1000,
diff --git a/clang/test/OpenMP/error_codegen.cpp b/clang/test/OpenMP/error_codegen.cpp
index def68ea020c63..6f5c947c17eac 100644
--- a/clang/test/OpenMP/error_codegen.cpp
+++ b/clang/test/OpenMP/error_codegen.cpp
@@ -545,23 +545,23 @@ int main (int argc, char **argv) {
// SIMD-NEXT: #dbg_declare(ptr [[F]], [[META46:![0-9]+]], !DIExpression(), [[META47:![0-9]+]])
// SIMD-NEXT: #dbg_declare(ptr [[G]], [[META48:![0-9]+]], !DIExpression(), [[META49:![0-9]+]])
// SIMD-NEXT: #dbg_declare(ptr [[STR1]], [[META50:![0-9]+]], !DIExpression(), [[META51:![0-9]+]])
-// SIMD-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR1]], ptr align 1 @__const.main.str1, i64 4, i1 false), !dbg [[META51]]
-// SIMD-NEXT: #dbg_declare(ptr [[STR2]], [[META52:![0-9]+]], !DIExpression(), [[META54:![0-9]+]])
-// SIMD-NEXT: store ptr @.str, ptr [[STR2]], align 8, !dbg [[META54]]
-// SIMD-NEXT: #dbg_declare(ptr [[STR3]], [[META55:![0-9]+]], !DIExpression(), [[META57:![0-9]+]])
-// SIMD-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR3]], ptr align 1 @__const.main.str3, i64 4, i1 false), !dbg [[META57]]
-// SIMD-NEXT: #dbg_declare(ptr [[STR4]], [[META58:![0-9]+]], !DIExpression(), [[META59:![0-9]+]])
-// SIMD-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0, !dbg [[DBG60:![0-9]+]]
-// SIMD-NEXT: store ptr [[ARRAYDECAY]], ptr [[STR4]], align 8, !dbg [[META59]]
-// SIMD-NEXT: #dbg_declare(ptr [[STR5]], [[META61:![0-9]+]], !DIExpression(), [[META63:![0-9]+]])
-// SIMD-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0, !dbg [[DBG64:![0-9]+]]
-// SIMD-NEXT: store ptr [[ARRAYDECAY1]], ptr [[STR5]], align 8, !dbg [[META63]]
-// SIMD-NEXT: store i32 2, ptr @_ZZ4mainE1a, align 4, !dbg [[DBG65:![0-9]+]]
-// SIMD-NEXT: call void @_Z3foov(), !dbg [[DBG66:![0-9]+]]
-// SIMD-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4, !dbg [[DBG67:![0-9]+]]
-// SIMD-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8, !dbg [[DBG68:![0-9]+]]
-// SIMD-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_PPc(i32 noundef [[TMP1]], ptr noundef [[TMP2]]), !dbg [[DBG69:![0-9]+]]
-// SIMD-NEXT: ret i32 0, !dbg [[DBG70:![0-9]+]]
+// SIMD-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR1]], ptr align 1 @__const.main.str1, i64 4, i1 false), !dbg [[DBG52:![0-9]+]]
+// SIMD-NEXT: #dbg_declare(ptr [[STR2]], [[META55:![0-9]+]], !DIExpression(), [[META57:![0-9]+]])
+// SIMD-NEXT: store ptr @.str, ptr [[STR2]], align 8, !dbg [[META57]]
+// SIMD-NEXT: #dbg_declare(ptr [[STR3]], [[META58:![0-9]+]], !DIExpression(), [[META60:![0-9]+]])
+// SIMD-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR3]], ptr align 1 @__const.main.str3, i64 4, i1 false), !dbg [[DBG61:![0-9]+]]
+// SIMD-NEXT: #dbg_declare(ptr [[STR4]], [[META62:![0-9]+]], !DIExpression(), [[META63:![0-9]+]])
+// SIMD-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0, !dbg [[DBG64:![0-9]+]]
+// SIMD-NEXT: store ptr [[ARRAYDECAY]], ptr [[STR4]], align 8, !dbg [[META63]]
+// SIMD-NEXT: #dbg_declare(ptr [[STR5]], [[META65:![0-9]+]], !DIExpression(), [[META67:![0-9]+]])
+// SIMD-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0, !dbg [[DBG68:![0-9]+]]
+// SIMD-NEXT: store ptr [[ARRAYDECAY1]], ptr [[STR5]], align 8, !dbg [[META67]]
+// SIMD-NEXT: store i32 2, ptr @_ZZ4mainE1a, align 4, !dbg [[DBG69:![0-9]+]]
+// SIMD-NEXT: call void @_Z3foov(), !dbg [[DBG70:![0-9]+]]
+// SIMD-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4, !dbg [[DBG71:![0-9]+]]
+// SIMD-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8, !dbg [[DBG72:![0-9]+]]
+// SIMD-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_PPc(i32 noundef [[TMP1]], ptr noundef [[TMP2]]), !dbg [[DBG73:![0-9]+]]
+// SIMD-NEXT: ret i32 0, !dbg [[DBG74:![0-9]+]]
//
//
// SIMD-LABEL: define linkonce_odr noundef i32 @_Z5tmainIiLi10EEiT_PPc(
@@ -583,49 +583,49 @@ int main (int argc, char **argv) {
// SIMD-NEXT: [[B3:%.*]] = alloca i32, align 4
// SIMD-NEXT: [[C4:%.*]] = alloca i32, align 4
// SIMD-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
-// SIMD-NEXT: #dbg_declare(ptr [[ARGC_ADDR]], [[META71:![0-9]+]], !DIExpression(), [[META72:![0-9]+]])
+// SIMD-NEXT: #dbg_declare(ptr [[ARGC_ADDR]], [[META75:![0-9]+]], !DIExpression(), [[META76:![0-9]+]])
// SIMD-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
-// SIMD-NEXT: #dbg_declare(ptr [[ARGV_ADDR]], [[META73:![0-9]+]], !DIExpression(), [[META74:![0-9]+]])
-// SIMD-NEXT: #dbg_declare(ptr [[B]], [[META75:![0-9]+]], !DIExpression(), [[META76:![0-9]+]])
-// SIMD-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4, !dbg [[DBG77:![0-9]+]]
-// SIMD-NEXT: store i32 [[TMP0]], ptr [[B]], align 4, !dbg [[META76]]
-// SIMD-NEXT: #dbg_declare(ptr [[C]], [[META78:![0-9]+]], !DIExpression(), [[META79:![0-9]+]])
-// SIMD-NEXT: #dbg_declare(ptr [[D]], [[META80:![0-9]+]], !DIExpression(), [[META81:![0-9]+]])
-// SIMD-NEXT: #dbg_declare(ptr [[E]], [[META82:![0-9]+]], !DIExpression(), [[META83:![0-9]+]])
-// SIMD-NEXT: #dbg_declare(ptr [[F]], [[META84:![0-9]+]], !DIExpression(), [[META85:![0-9]+]])
-// SIMD-NEXT: #dbg_declare(ptr [[G]], [[META86:![0-9]+]], !DIExpression(), [[META87:![0-9]+]])
-// SIMD-NEXT: #dbg_declare(ptr [[STR1]], [[META88:![0-9]+]], !DIExpression(), [[META89:![0-9]+]])
-// SIMD-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR1]], ptr align 1 @__const._Z5tmainIiLi10EEiT_PPc.str1, i64 4, i1 false), !dbg [[META89]]
-// SIMD-NEXT: #dbg_declare(ptr [[STR2]], [[META90:![0-9]+]], !DIExpression(), [[META91:![0-9]+]])
-// SIMD-NEXT: store ptr @.str, ptr [[STR2]], align 8, !dbg [[META91]]
-// SIMD-NEXT: #dbg_declare(ptr [[STR3]], [[META92:![0-9]+]], !DIExpression(), [[META93:![0-9]+]])
-// SIMD-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR3]], ptr align 1 @__const._Z5tmainIiLi10EEiT_PPc.str3, i64 4, i1 false), !dbg [[META93]]
-// SIMD-NEXT: #dbg_declare(ptr [[STR4]], [[META94:![0-9]+]], !DIExpression(), [[META95:![0-9]+]])
-// SIMD-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0, !dbg [[DBG96:![0-9]+]]
-// SIMD-NEXT: store ptr [[ARRAYDECAY]], ptr [[STR4]], align 8, !dbg [[META95]]
-// SIMD-NEXT: #dbg_declare(ptr [[STR5]], [[META97:![0-9]+]], !DIExpression(), [[META98:![0-9]+]])
-// SIMD-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0, !dbg [[DBG99:![0-9]+]]
-// SIMD-NEXT: store ptr [[ARRAYDECAY1]], ptr [[STR5]], align 8, !dbg [[META98]]
-// SIMD-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8, !dbg [[DBG100:![0-9]+]]
-// SIMD-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i64 0, !dbg [[DBG100]]
-// SIMD-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !dbg [[DBG100]]
-// SIMD-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[TMP2]], i64 0, !dbg [[DBG100]]
-// SIMD-NEXT: [[TMP3:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1, !dbg [[DBG100]]
-// SIMD-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32, !dbg [[DBG100]]
-// SIMD-NEXT: store i32 [[CONV]], ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4, !dbg [[DBG101:![0-9]+]]
-// SIMD-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4, !dbg [[DBG102:![0-9]+]]
-// SIMD-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1, !dbg [[DBG102]]
-// SIMD-NEXT: store i32 [[INC]], ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4, !dbg [[DBG102]]
-// SIMD-NEXT: #dbg_declare(ptr [[B3]], [[META103:![0-9]+]], !DIExpression(), [[META105:![0-9]+]])
-// SIMD-NEXT: store i32 10, ptr [[B3]], align 4, !dbg [[META105]]
-// SIMD-NEXT: #dbg_declare(ptr [[C4]], [[META106:![0-9]+]], !DIExpression(), [[META107:![0-9]+]])
-// SIMD-NEXT: store i32 100, ptr [[C4]], align 4, !dbg [[META107]]
-// SIMD-NEXT: [[TMP5:%.*]] = load i32, ptr [[B3]], align 4, !dbg [[DBG108:![0-9]+]]
-// SIMD-NEXT: [[TMP6:%.*]] = load i32, ptr [[C4]], align 4, !dbg [[DBG109:![0-9]+]]
-// SIMD-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP6]], !dbg [[DBG110:![0-9]+]]
-// SIMD-NEXT: store i32 [[ADD]], ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4, !dbg [[DBG111:![0-9]+]]
-// SIMD-NEXT: call void @_Z3foov(), !dbg [[DBG112:![0-9]+]]
-// SIMD-NEXT: ret i32 10, !dbg [[DBG113:![0-9]+]]
+// SIMD-NEXT: #dbg_declare(ptr [[ARGV_ADDR]], [[META77:![0-9]+]], !DIExpression(), [[META78:![0-9]+]])
+// SIMD-NEXT: #dbg_declare(ptr [[B]], [[META79:![0-9]+]], !DIExpression(), [[META80:![0-9]+]])
+// SIMD-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4, !dbg [[DBG81:![0-9]+]]
+// SIMD-NEXT: store i32 [[TMP0]], ptr [[B]], align 4, !dbg [[META80]]
+// SIMD-NEXT: #dbg_declare(ptr [[C]], [[META82:![0-9]+]], !DIExpression(), [[META83:![0-9]+]])
+// SIMD-NEXT: #dbg_declare(ptr [[D]], [[META84:![0-9]+]], !DIExpression(), [[META85:![0-9]+]])
+// SIMD-NEXT: #dbg_declare(ptr [[E]], [[META86:![0-9]+]], !DIExpression(), [[META87:![0-9]+]])
+// SIMD-NEXT: #dbg_declare(ptr [[F]], [[META88:![0-9]+]], !DIExpression(), [[META89:![0-9]+]])
+// SIMD-NEXT: #dbg_declare(ptr [[G]], [[META90:![0-9]+]], !DIExpression(), [[META91:![0-9]+]])
+// SIMD-NEXT: #dbg_declare(ptr [[STR1]], [[META92:![0-9]+]], !DIExpression(), [[META93:![0-9]+]])
+// SIMD-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR1]], ptr align 1 @__const._Z5tmainIiLi10EEiT_PPc.str1, i64 4, i1 false), !dbg [[DBG94:![0-9]+]]
+// SIMD-NEXT: #dbg_declare(ptr [[STR2]], [[META95:![0-9]+]], !DIExpression(), [[META96:![0-9]+]])
+// SIMD-NEXT: store ptr @.str, ptr [[STR2]], align 8, !dbg [[META96]]
+// SIMD-NEXT: #dbg_declare(ptr [[STR3]], [[META97:![0-9]+]], !DIExpression(), [[META98:![0-9]+]])
+// SIMD-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR3]], ptr align 1 @__const._Z5tmainIiLi10EEiT_PPc.str3, i64 4, i1 false), !dbg [[DBG99:![0-9]+]]
+// SIMD-NEXT: #dbg_declare(ptr [[STR4]], [[META100:![0-9]+]], !DIExpression(), [[META101:![0-9]+]])
+// SIMD-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0, !dbg [[DBG102:![0-9]+]]
+// SIMD-NEXT: store ptr [[ARRAYDECAY]], ptr [[STR4]], align 8, !dbg [[META101]]
+// SIMD-NEXT: #dbg_declare(ptr [[STR5]], [[META103:![0-9]+]], !DIExpression(), [[META104:![0-9]+]])
+// SIMD-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0, !dbg [[DBG105:![0-9]+]]
+// SIMD-NEXT: store ptr [[ARRAYDECAY1]], ptr [[STR5]], align 8, !dbg [[META104]]
+// SIMD-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8, !dbg [[DBG106:![0-9]+]]
+// SIMD-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i64 0, !dbg [[DBG106]]
+// SIMD-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !dbg [[DBG106]]
+// SIMD-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[TMP2]], i64 0, !dbg [[DBG106]]
+// SIMD-NEXT: [[TMP3:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1, !dbg [[DBG106]]
+// SIMD-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32, !dbg [[DBG106]]
+// SIMD-NEXT: store i32 [[CONV]], ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4, !dbg [[DBG107:![0-9]+]]
+// SIMD-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4, !dbg [[DBG108:![0-9]+]]
+// SIMD-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1, !dbg [[DBG108]]
+// SIMD-NEXT: store i32 [[INC]], ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4, !dbg [[DBG108]]
+// SIMD-NEXT: #dbg_declare(ptr [[B3]], [[META109:![0-9]+]], !DIExpression(), [[META111:![0-9]+]])
+// SIMD-NEXT: store i32 10, ptr [[B3]], align 4, !dbg [[META111]]
+// SIMD-NEXT: #dbg_declare(ptr [[C4]], [[META112:![0-9]+]], !DIExpression(), [[META113:![0-9]+]])
+// SIMD-NEXT: store i32 100, ptr [[C4]], align 4, !dbg [[META113]]
+// SIMD-NEXT: [[TMP5:%.*]] = load i32, ptr [[B3]], align 4, !dbg [[DBG114:![0-9]+]]
+// SIMD-NEXT: [[TMP6:%.*]] = load i32, ptr [[C4]], align 4, !dbg [[DBG115:![0-9]+]]
+// SIMD-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP6]], !dbg [[DBG116:![0-9]+]]
+// SIMD-NEXT: store i32 [[ADD]], ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4, !dbg [[DBG117:![0-9]+]]
+// SIMD-NEXT: call void @_Z3foov(), !dbg [[DBG118:![0-9]+]]
+// SIMD-NEXT: ret i32 10, !dbg [[DBG119:![0-9]+]]
//
//.
// SIMD: [[META0:![0-9]+]] = !DIGlobalVariableExpression(var: [[META1:![0-9]+]], expr: !DIExpression())
@@ -678,66 +678,72 @@ int main (int argc, char **argv) {
// SIMD: [[META49]] = !DILocation(line: 60, column: 29, scope: [[DBG2]])
// SIMD: [[META50]] = !DILocalVariable(name: "str1", scope: [[DBG2]], file: [[META3]], line: 62, type: [[META15]])
// SIMD: [[META51]] = !DILocation(line: 62, column: 14, scope: [[DBG2]])
-// SIMD: [[META52]] = !DILocalVariable(name: "str2", scope: [[DBG2]], file: [[META3]], line: 63, type: [[META53:![0-9]+]])
-// SIMD: [[META53]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: [[META16]], size: 64)
-// SIMD: [[META54]] = !DILocation(line: 63, column: 15, scope: [[DBG2]])
-// SIMD: [[META55]] = !DILocalVariable(name: "str3", scope: [[DBG2]], file: [[META3]], line: 64, type: [[META56:![0-9]+]])
-// SIMD: [[META56]] = !DICompositeType(tag: DW_TAG_array_type, baseType: [[META9]], size: 32, elements: [[META17]])
-// SIMD: [[META57]] = !DILocation(line: 64, column: 8, scope: [[DBG2]])
-// SIMD: [[META58]] = !DILocalVariable(name: "str4", scope: [[DBG2]], file: [[META3]], line: 65, type: [[META8]])
-// SIMD: [[META59]] = !DILocation(line: 65, column: 9, scope: [[DBG2]])
-// SIMD: [[DBG60]] = !DILocation(line: 65, column: 16, scope: [[DBG2]])
-// SIMD: [[META61]] = !DILocalVariable(name: "str5", scope: [[DBG2]], file: [[META3]], line: 66, type: [[META62:![0-9]+]])
-// SIMD: [[META62]] = !DIDerivedType(tag: DW_TAG_const_type, baseType: [[META8]])
-// SIMD: [[META63]] = !DILocation(line: 66, column: 16, scope: [[DBG2]])
-// SIMD: [[DBG64]] = !DILocation(line: 66, column: 23, scope: [[DBG2]])
-// SIMD: [[DBG65]] = !DILocation(line: 73, column: 5, scope: [[DBG2]])
-// SIMD: [[DBG66]] = !DILocation(line: 80, column: 3, scope: [[DBG2]])
-// SIMD: [[DBG67]] = !DILocation(line: 81, column: 18, scope: [[DBG2]])
-// SIMD: [[DBG68]] = !DILocation(line: 81, column: 24, scope: [[DBG2]])
-// SIMD: [[DBG69]] = !DILocation(line: 81, column: 3, scope: [[DBG2]])
-// SIMD: [[DBG70]] = !DILocation(line: 82, column: 1, scope: [[DBG2]])
-// SIMD: [[META71]] = !DILocalVariable(name: "argc", arg: 1, scope: [[DBG22]], file: [[META3]], line: 20, type: [[META6]])
-// SIMD: [[META72]] = !DILocation(line: 20, column: 13, scope: [[DBG22]])
-// SIMD: [[META73]] = !DILocalVariable(name: "argv", arg: 2, scope: [[DBG22]], file: [[META3]], line: 20, type: [[META7]])
-// SIMD: [[META74]] = !DILocation(line: 20, column: 26, scope: [[DBG22]])
-// SIMD: [[META75]] = !DILocalVariable(name: "b", scope: [[DBG22]], file: [[META3]], line: 21, type: [[META6]])
-// SIMD: [[META76]] = !DILocation(line: 21, column: 5, scope: [[DBG22]])
-// SIMD: [[DBG77]] = !DILocation(line: 21, column: 9, scope: [[DBG22]])
-// SIMD: [[META78]] = !DILocalVariable(name: "c", scope: [[DBG22]], file: [[META3]], line: 21, type: [[META6]])
-// SIMD: [[META79]] = !DILocation(line: 21, column: 15, scope: [[DBG22]])
-// SIMD: [[META80]] = !DILocalVariable(name: "d", scope: [[DBG22]], file: [[META3]], line: 21, type: [[META6]])
-// SIMD: [[META81]] = !DILocation(line: 21, column: 18, scope: [[DBG22]])
-// SIMD: [[META82]] = !DILocalVariable(name: "e", scope: [[DBG22]], file: [[META3]], line: 21, type: [[META6]])
-// SIMD: [[META83]] = !DILocation(line: 21, column: 21, scope: [[DBG22]])
-// SIMD: [[META84]] = !DILocalVariable(name: "f", scope: [[DBG22]], file: [[META3]], line: 21, type: [[META6]])
-// SIMD: [[META85]] = !DILocation(line: 21, column: 24, scope: [[DBG22]])
-// SIMD: [[META86]] = !DILocalVariable(name: "g", scope: [[DBG22]], file: [[META3]], line: 21, type: [[META6]])
-// SIMD: [[META87]] = !DILocation(line: 21, column: 27, scope: [[DBG22]])
-// SIMD: [[META88]] = !DILocalVariable(name: "str1", scope: [[DBG22]], file: [[META3]], line: 23, type: [[META15]])
-// SIMD: [[META89]] = !DILocation(line: 23, column: 14, scope: [[DBG22]])
-// SIMD: [[META90]] = !DILocalVariable(name: "str2", scope: [[DBG22]], file: [[META3]], line: 24, type: [[META53]])
-// SIMD: [[META91]] = !DILocation(line: 24, column: 15, scope: [[DBG22]])
-// SIMD: [[META92]] = !DILocalVariable(name: "str3", scope: [[DBG22]], file: [[META3]], line: 25, type: [[META56]])
-// SIMD: [[META93]] = !DILocation(line: 25, column: 8, scope: [[DBG22]])
-// SIMD: [[META94]] = !DILocalVariable(name: "str4", scope: [[DBG22]], file: [[META3]], line: 26, type: [[META8]])
-// SIMD: [[META95]] = !DILocation(line: 26, column: 9, scope: [[DBG22]])
-// SIMD: [[DBG96]] = !DILocation(line: 26, column: 16, scope: [[DBG22]])
-// SIMD: [[META97]] = !DILocalVariable(name: "str5", scope: [[DBG22]], file: [[META3]], line: 27, type: [[META62]])
-// SIMD: [[META98]] = !DILocation(line: 27, column: 16, scope: [[DBG22]])
-// SIMD: [[DBG99]] = !DILocation(line: 27, column: 23, scope: [[DBG22]])
-// SIMD: [[DBG100]] = !DILocation(line: 34, column: 7, scope: [[DBG22]])
-// SIMD: [[DBG101]] = !DILocation(line: 34, column: 5, scope: [[DBG22]])
-// SIMD: [[DBG102]] = !DILocation(line: 35, column: 3, scope: [[DBG22]])
-// SIMD: [[META103]] = !DILocalVariable(name: "b", scope: [[META104:![0-9]+]], file: [[META3]], line: 43, type: [[META6]])
-// SIMD: [[META104]] = distinct !DILexicalBlock(scope: [[DBG22]], file: [[META3]], line: 42, column: 3)
-// SIMD: [[META105]] = !DILocation(line: 43, column: 9, scope: [[META104]])
-// SIMD: [[META106]] = !DILocalVariable(name: "c", scope: [[META104]], file: [[META3]], line: 44, type: [[META6]])
-// SIMD: [[META107]] = !DILocation(line: 44, column: 7, scope: [[META104]])
-// SIMD: [[DBG108]] = !DILocation(line: 45, column: 9, scope: [[META104]])
-// SIMD: [[DBG109]] = !DILocation(line: 45, column: 13, scope: [[META104]])
-// SIMD: [[DBG110]] = !DILocation(line: 45, column: 11, scope: [[META104]])
-// SIMD: [[DBG111]] = !DILocation(line: 45, column: 7, scope: [[META104]])
-// SIMD: [[DBG112]] = !DILocation(line: 53, column: 3, scope: [[DBG22]])
-// SIMD: [[DBG113]] = !DILocation(line: 54, column: 1, scope: [[DBG22]])
+// SIMD: [[DBG52]] = !DILocation(line: 0, scope: [[META53:![0-9]+]], inlinedAt: [[META51]])
+// SIMD: [[META53]] = distinct !DISubprogram(name: "memcpy", scope: [[META3]], file: [[META3]], type: [[META54:![0-9]+]], flags: DIFlagArtificial, spFlags: DISPFlagDefinition, unit: [[META10]])
+// SIMD: [[META54]] = !DISubroutineType(types: null)
+// SIMD: [[META55]] = !DILocalVariable(name: "str2", scope: [[DBG2]], file: [[META3]], line: 63, type: [[META56:![0-9]+]])
+// SIMD: [[META56]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: [[META16]], size: 64)
+// SIMD: [[META57]] = !DILocation(line: 63, column: 15, scope: [[DBG2]])
+// SIMD: [[META58]] = !DILocalVariable(name: "str3", scope: [[DBG2]], file: [[META3]], line: 64, type: [[META59:![0-9]+]])
+// SIMD: [[META59]] = !DICompositeType(tag: DW_TAG_array_type, baseType: [[META9]], size: 32, elements: [[META17]])
+// SIMD: [[META60]] = !DILocation(line: 64, column: 8, scope: [[DBG2]])
+// SIMD: [[DBG61]] = !DILocation(line: 0, scope: [[META53]], inlinedAt: [[META60]])
+// SIMD: [[META62]] = !DILocalVariable(name: "str4", scope: [[DBG2]], file: [[META3]], line: 65, type: [[META8]])
+// SIMD: [[META63]] = !DILocation(line: 65, column: 9, scope: [[DBG2]])
+// SIMD: [[DBG64]] = !DILocation(line: 65, column: 16, scope: [[DBG2]])
+// SIMD: [[META65]] = !DILocalVariable(name: "str5", scope: [[DBG2]], file: [[META3]], line: 66, type: [[META66:![0-9]+]])
+// SIMD: [[META66]] = !DIDerivedType(tag: DW_TAG_const_type, baseType: [[META8]])
+// SIMD: [[META67]] = !DILocation(line: 66, column: 16, scope: [[DBG2]])
+// SIMD: [[DBG68]] = !DILocation(line: 66, column: 23, scope: [[DBG2]])
+// SIMD: [[DBG69]] = !DILocation(line: 73, column: 5, scope: [[DBG2]])
+// SIMD: [[DBG70]] = !DILocation(line: 80, column: 3, scope: [[DBG2]])
+// SIMD: [[DBG71]] = !DILocation(line: 81, column: 18, scope: [[DBG2]])
+// SIMD: [[DBG72]] = !DILocation(line: 81, column: 24, scope: [[DBG2]])
+// SIMD: [[DBG73]] = !DILocation(line: 81, column: 3, scope: [[DBG2]])
+// SIMD: [[DBG74]] = !DILocation(line: 82, column: 1, scope: [[DBG2]])
+// SIMD: [[META75]] = !DILocalVariable(name: "argc", arg: 1, scope: [[DBG22]], file: [[META3]], line: 20, type: [[META6]])
+// SIMD: [[META76]] = !DILocation(line: 20, column: 13, scope: [[DBG22]])
+// SIMD: [[META77]] = !DILocalVariable(name: "argv", arg: 2, scope: [[DBG22]], file: [[META3]], line: 20, type: [[META7]])
+// SIMD: [[META78]] = !DILocation(line: 20, column: 26, scope: [[DBG22]])
+// SIMD: [[META79]] = !DILocalVariable(name: "b", scope: [[DBG22]], file: [[META3]], line: 21, type: [[META6]])
+// SIMD: [[META80]] = !DILocation(line: 21, column: 5, scope: [[DBG22]])
+// SIMD: [[DBG81]] = !DILocation(line: 21, column: 9, scope: [[DBG22]])
+// SIMD: [[META82]] = !DILocalVariable(name: "c", scope: [[DBG22]], file: [[META3]], line: 21, type: [[META6]])
+// SIMD: [[META83]] = !DILocation(line: 21, column: 15, scope: [[DBG22]])
+// SIMD: [[META84]] = !DILocalVariable(name: "d", scope: [[DBG22]], file: [[META3]], line: 21, type: [[META6]])
+// SIMD: [[META85]] = !DILocation(line: 21, column: 18, scope: [[DBG22]])
+// SIMD: [[META86]] = !DILocalVariable(name: "e", scope: [[DBG22]], file: [[META3]], line: 21, type: [[META6]])
+// SIMD: [[META87]] = !DILocation(line: 21, column: 21, scope: [[DBG22]])
+// SIMD: [[META88]] = !DILocalVariable(name: "f", scope: [[DBG22]], file: [[META3]], line: 21, type: [[META6]])
+// SIMD: [[META89]] = !DILocation(line: 21, column: 24, scope: [[DBG22]])
+// SIMD: [[META90]] = !DILocalVariable(name: "g", scope: [[DBG22]], file: [[META3]], line: 21, type: [[META6]])
+// SIMD: [[META91]] = !DILocation(line: 21, column: 27, scope: [[DBG22]])
+// SIMD: [[META92]] = !DILocalVariable(name: "str1", scope: [[DBG22]], file: [[META3]], line: 23, type: [[META15]])
+// SIMD: [[META93]] = !DILocation(line: 23, column: 14, scope: [[DBG22]])
+// SIMD: [[DBG94]] = !DILocation(line: 0, scope: [[META53]], inlinedAt: [[META93]])
+// SIMD: [[META95]] = !DILocalVariable(name: "str2", scope: [[DBG22]], file: [[META3]], line: 24, type: [[META56]])
+// SIMD: [[META96]] = !DILocation(line: 24, column: 15, scope: [[DBG22]])
+// SIMD: [[META97]] = !DILocalVariable(name: "str3", scope: [[DBG22]], file: [[META3]], line: 25, type: [[META59]])
+// SIMD: [[META98]] = !DILocation(line: 25, column: 8, scope: [[DBG22]])
+// SIMD: [[DBG99]] = !DILocation(line: 0, scope: [[META53]], inlinedAt: [[META98]])
+// SIMD: [[META100]] = !DILocalVariable(name: "str4", scope: [[DBG22]], file: [[META3]], line: 26, type: [[META8]])
+// SIMD: [[META101]] = !DILocation(line: 26, column: 9, scope: [[DBG22]])
+// SIMD: [[DBG102]] = !DILocation(line: 26, column: 16, scope: [[DBG22]])
+// SIMD: [[META103]] = !DILocalVariable(name: "str5", scope: [[DBG22]], file: [[META3]], line: 27, type: [[META66]])
+// SIMD: [[META104]] = !DILocation(line: 27, column: 16, scope: [[DBG22]])
+// SIMD: [[DBG105]] = !DILocation(line: 27, column: 23, scope: [[DBG22]])
+// SIMD: [[DBG106]] = !DILocation(line: 34, column: 7, scope: [[DBG22]])
+// SIMD: [[DBG107]] = !DILocation(line: 34, column: 5, scope: [[DBG22]])
+// SIMD: [[DBG108]] = !DILocation(line: 35, column: 3, scope: [[DBG22]])
+// SIMD: [[META109]] = !DILocalVariable(name: "b", scope: [[META110:![0-9]+]], file: [[META3]], line: 43, type: [[META6]])
+// SIMD: [[META110]] = distinct !DILexicalBlock(scope: [[DBG22]], file: [[META3]], line: 42, column: 3)
+// SIMD: [[META111]] = !DILocation(line: 43, column: 9, scope: [[META110]])
+// SIMD: [[META112]] = !DILocalVariable(name: "c", scope: [[META110]], file: [[META3]], line: 44, type: [[META6]])
+// SIMD: [[META113]] = !DILocation(line: 44, column: 7, scope: [[META110]])
+// SIMD: [[DBG114]] = !DILocation(line: 45, column: 9, scope: [[META110]])
+// SIMD: [[DBG115]] = !DILocation(line: 45, column: 13, scope: [[META110]])
+// SIMD: [[DBG116]] = !DILocation(line: 45, column: 11, scope: [[META110]])
+// SIMD: [[DBG117]] = !DILocation(line: 45, column: 7, scope: [[META110]])
+// SIMD: [[DBG118]] = !DILocation(line: 53, column: 3, scope: [[DBG22]])
+// SIMD: [[DBG119]] = !DILocation(line: 54, column: 1, scope: [[DBG22]])
//.
diff --git a/clang/test/OpenMP/single_codegen.cpp b/clang/test/OpenMP/single_codegen.cpp
index 0b1e158664a38..5fa3e328db129 100644
--- a/clang/test/OpenMP/single_codegen.cpp
+++ b/clang/test/OpenMP/single_codegen.cpp
@@ -494,7 +494,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK1-NEXT: store double 0.000000e+00, ptr [[A]], align 8
// CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SST]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: store ptr [[A3]], ptr [[A2]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META2:![0-9]+]], !align [[META3:![0-9]+]]
// CHECK1-NEXT: [[TMP1:%.*]] = load double, ptr [[TMP0]], align 8
// CHECK1-NEXT: store double [[TMP1]], ptr [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -520,7 +520,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META2]], !align [[META3]]
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
@@ -532,7 +532,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0
// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META2]], !align [[META3]]
// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8
// CHECK1-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]])
// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
@@ -542,7 +542,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK1-NEXT: br label [[OMP_IF_END]]
// CHECK1: omp_if.end:
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0
-// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]]
+// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META2]], !align [[META3]]
// CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 8
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK1-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP3]], i64 8, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.5, i32 [[TMP11]])
@@ -568,7 +568,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 1
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !nonnull [[META3]], !align [[META4]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !nonnull [[META2]], !align [[META3]]
// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP3]], align 8
// CHECK1-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]])
// CHECK1-NEXT: ret void
@@ -602,12 +602,12 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META3]], !align [[META4]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META2]], !align [[META3]]
// CHECK1-NEXT: [[TMP4:%.*]] = load double, ptr [[TMP3]], align 8
// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00
// CHECK1-NEXT: store double [[INC]], ptr [[TMP3]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META3]], !align [[META4]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META2]], !align [[META3]]
// CHECK1-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8
// CHECK1-NEXT: store double [[TMP7]], ptr [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -632,7 +632,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META2]], !align [[META3]]
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
@@ -641,7 +641,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK1-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0
// CHECK1-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.then:
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META2]], !align [[META3]]
// CHECK1-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8
// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00
// CHECK1-NEXT: store double [[INC]], ptr [[TMP6]], align 8
@@ -650,7 +650,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK1-NEXT: br label [[OMP_IF_END]]
// CHECK1: omp_if.end:
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0
-// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META2]], !align [[META3]]
// CHECK1-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK1-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP3]], i64 8, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.6, i32 [[TMP10]])
@@ -697,7 +697,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK1-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0
// CHECK1-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4
// CHECK1-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META3]], !align [[META7:![0-9]+]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META2]], !align [[META6:![0-9]+]]
// CHECK1-NEXT: store ptr [[TMP0]], ptr [[C]], align 8
// CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: store ptr [[A3]], ptr [[A2]], align 8
@@ -708,16 +708,16 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK1-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32
// CHECK1-NEXT: store i32 [[BF_CAST]], ptr [[B4]], align 4
// CHECK1-NEXT: [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[C7]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
// CHECK1-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B4]], align 4
// CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
// CHECK1-NEXT: store i32 [[TMP8]], ptr [[C_CASTED]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[C_CASTED]], align 8
@@ -750,9 +750,9 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8
// CHECK1-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: store ptr [[TMP2]], ptr [[_TMP3]], align 8
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
@@ -764,12 +764,12 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 0
// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP7]], align 8
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1
-// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 2
// CHECK1-NEXT: store ptr [[B_ADDR]], ptr [[TMP10]], align 8
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 3
-// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8
// CHECK1-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]])
// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
@@ -779,12 +779,12 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK1-NEXT: br label [[OMP_IF_END]]
// CHECK1: omp_if.end:
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0
-// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1
// CHECK1-NEXT: store ptr [[B_ADDR]], ptr [[TMP15]], align 8
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2
-// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK1-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP4]], i64 24, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.7, i32 [[TMP18]])
@@ -809,32 +809,32 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK1-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
// CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1
// CHECK1-NEXT: store i32 [[DEC]], ptr [[TMP6]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3
-// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1
// CHECK1-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1
-// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4
// CHECK1-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4
// CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2
-// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
// CHECK1-NEXT: store i32 [[TMP17]], ptr [[B_CASTED]], align 4
// CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[B_CASTED]], align 8
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3
-// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
// CHECK1-NEXT: store i32 [[TMP21]], ptr [[C_CASTED]], align 4
// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[C_CASTED]], align 8
@@ -896,9 +896,9 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8
// CHECK1-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: store ptr [[TMP2]], ptr [[_TMP3]], align 8
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
@@ -907,14 +907,14 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK1-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
// CHECK1-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.then:
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK1-NEXT: store i32 [[INC]], ptr [[TMP7]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1
// CHECK1-NEXT: store i32 [[DEC]], ptr [[B_ADDR]], align 4
-// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1
// CHECK1-NEXT: store i32 [[DIV]], ptr [[TMP10]], align 4
@@ -923,12 +923,12 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK1-NEXT: br label [[OMP_IF_END]]
// CHECK1: omp_if.end:
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0
-// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1
// CHECK1-NEXT: store ptr [[B_ADDR]], ptr [[TMP14]], align 8
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2
-// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META7]]
+// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META2]], !align [[META6]]
// CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK1-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP4]], i64 24, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.8, i32 [[TMP17]])
@@ -1444,7 +1444,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK2-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0
// CHECK2-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4
// CHECK2-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2
-// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
+// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]]
// CHECK2-NEXT: store ptr [[TMP0]], ptr [[C]], align 8
// CHECK2-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0
// CHECK2-NEXT: store ptr [[A3]], ptr [[A2]], align 8
@@ -1455,16 +1455,16 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK2-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32
// CHECK2-NEXT: store i32 [[BF_CAST]], ptr [[B4]], align 4
// CHECK2-NEXT: [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2
-// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: store ptr [[TMP1]], ptr [[C7]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
// CHECK2-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[B4]], align 4
// CHECK2-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
// CHECK2-NEXT: store i32 [[TMP8]], ptr [[C_CASTED]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[C_CASTED]], align 8
@@ -1497,9 +1497,9 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK2-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8
// CHECK2-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: store ptr [[TMP2]], ptr [[_TMP3]], align 8
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
@@ -1511,12 +1511,12 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0
// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP7]], align 8
// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1
-// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8
// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 2
// CHECK2-NEXT: store ptr [[B_ADDR]], ptr [[TMP10]], align 8
// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 3
-// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8
// CHECK2-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]])
// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
@@ -1526,12 +1526,12 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK2-NEXT: br label [[OMP_IF_END]]
// CHECK2: omp_if.end:
// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0
-// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8
// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1
// CHECK2-NEXT: store ptr [[B_ADDR]], ptr [[TMP15]], align 8
// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2
-// CHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK2-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP4]], i64 24, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.5, i32 [[TMP18]])
@@ -1556,32 +1556,32 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 1
-// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK2-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 2
-// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
// CHECK2-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1
// CHECK2-NEXT: store i32 [[DEC]], ptr [[TMP6]], align 4
// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 3
-// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1
// CHECK2-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 1
-// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4
// CHECK2-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4
// CHECK2-NEXT: [[TMP14:%.*]] = load i64, ptr [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 2
-// CHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
// CHECK2-NEXT: store i32 [[TMP17]], ptr [[B_CASTED]], align 4
// CHECK2-NEXT: [[TMP18:%.*]] = load i64, ptr [[B_CASTED]], align 8
// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 3
-// CHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
// CHECK2-NEXT: store i32 [[TMP21]], ptr [[C_CASTED]], align 4
// CHECK2-NEXT: [[TMP22:%.*]] = load i64, ptr [[C_CASTED]], align 8
@@ -1643,9 +1643,9 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK2-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8
// CHECK2-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: store ptr [[TMP2]], ptr [[_TMP3]], align 8
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
@@ -1654,14 +1654,14 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK2-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
// CHECK2-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.then:
-// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK2-NEXT: store i32 [[INC]], ptr [[TMP7]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK2-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1
// CHECK2-NEXT: store i32 [[DEC]], ptr [[B_ADDR]], align 4
-// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1
// CHECK2-NEXT: store i32 [[DIV]], ptr [[TMP10]], align 4
@@ -1670,12 +1670,12 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK2-NEXT: br label [[OMP_IF_END]]
// CHECK2: omp_if.end:
// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0
-// CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1
// CHECK2-NEXT: store ptr [[B_ADDR]], ptr [[TMP14]], align 8
// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2
-// CHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK2-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP4]], i64 24, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.6, i32 [[TMP17]])
@@ -1724,7 +1724,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK2-NEXT: store double 0.000000e+00, ptr [[A]], align 8
// CHECK2-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SST]], ptr [[THIS1]], i32 0, i32 0
// CHECK2-NEXT: store ptr [[A3]], ptr [[A2]], align 8
-// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META5]], !align [[META7:![0-9]+]]
+// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META4]], !align [[META6:![0-9]+]]
// CHECK2-NEXT: [[TMP1:%.*]] = load double, ptr [[TMP0]], align 8
// CHECK2-NEXT: store double [[TMP1]], ptr [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -1750,7 +1750,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK2-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK2-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META7]]
+// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META4]], !align [[META6]]
// CHECK2-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
@@ -1762,7 +1762,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
-// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META7]]
+// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META4]], !align [[META6]]
// CHECK2-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8
// CHECK2-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]])
// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
@@ -1772,7 +1772,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK2-NEXT: br label [[OMP_IF_END]]
// CHECK2: omp_if.end:
// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0
-// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META7]]
+// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META4]], !align [[META6]]
// CHECK2-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 8
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK2-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP3]], i64 8, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.7, i32 [[TMP11]])
@@ -1798,7 +1798,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK2-NEXT: store ptr [[TMP1]], ptr [[TMP2]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1
// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1
-// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !nonnull [[META5]], !align [[META7]]
+// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !nonnull [[META4]], !align [[META6]]
// CHECK2-NEXT: store ptr [[TMP5]], ptr [[TMP3]], align 8
// CHECK2-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]])
// CHECK2-NEXT: ret void
@@ -1832,12 +1832,12 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1
-// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META5]], !align [[META7]]
+// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META4]], !align [[META6]]
// CHECK2-NEXT: [[TMP4:%.*]] = load double, ptr [[TMP3]], align 8
// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00
// CHECK2-NEXT: store double [[INC]], ptr [[TMP3]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1
-// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META5]], !align [[META7]]
+// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META4]], !align [[META6]]
// CHECK2-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8
// CHECK2-NEXT: store double [[TMP7]], ptr [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -1862,7 +1862,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK2-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK2-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META7]]
+// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META4]], !align [[META6]]
// CHECK2-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
@@ -1871,7 +1871,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK2-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0
// CHECK2-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.then:
-// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META7]]
+// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META4]], !align [[META6]]
// CHECK2-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8
// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00
// CHECK2-NEXT: store double [[INC]], ptr [[TMP6]], align 8
@@ -1880,7 +1880,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK2-NEXT: br label [[OMP_IF_END]]
// CHECK2: omp_if.end:
// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0
-// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META7]]
+// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META4]], !align [[META6]]
// CHECK2-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK2-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP3]], i64 8, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.8, i32 [[TMP10]])
@@ -2336,7 +2336,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK4-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0
// CHECK4-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4
// CHECK4-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2
-// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
+// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]]
// CHECK4-NEXT: store ptr [[TMP0]], ptr [[C]], align 8
// CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0
// CHECK4-NEXT: store ptr [[A3]], ptr [[A2]], align 8
@@ -2347,16 +2347,16 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK4-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32
// CHECK4-NEXT: store i32 [[BF_CAST]], ptr [[B4]], align 4
// CHECK4-NEXT: [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2
-// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: store ptr [[TMP1]], ptr [[C7]], align 8
-// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
// CHECK4-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[B4]], align 4
// CHECK4-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4
// CHECK4-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
// CHECK4-NEXT: store i32 [[TMP8]], ptr [[C_CASTED]], align 4
// CHECK4-NEXT: [[TMP9:%.*]] = load i64, ptr [[C_CASTED]], align 8
@@ -2389,9 +2389,9 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK4-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8
// CHECK4-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8
-// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8
-// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: store ptr [[TMP2]], ptr [[_TMP3]], align 8
// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
@@ -2403,12 +2403,12 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0
// CHECK4-NEXT: store ptr [[TMP0]], ptr [[TMP7]], align 8
// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1
-// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8
// CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 2
// CHECK4-NEXT: store ptr [[B_ADDR]], ptr [[TMP10]], align 8
// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 3
-// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8
// CHECK4-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]])
// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
@@ -2418,12 +2418,12 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK4-NEXT: br label [[OMP_IF_END]]
// CHECK4: omp_if.end:
// CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0
-// CHECK4-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8
// CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1
// CHECK4-NEXT: store ptr [[B_ADDR]], ptr [[TMP15]], align 8
// CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2
-// CHECK4-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8
// CHECK4-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK4-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP4]], i64 24, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.4, i32 [[TMP18]])
@@ -2448,32 +2448,32 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
// CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 1
-// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK4-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4
// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 2
-// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
// CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1
// CHECK4-NEXT: store i32 [[DEC]], ptr [[TMP6]], align 4
// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 3
-// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1
// CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4
// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 1
-// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4
// CHECK4-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP14:%.*]] = load i64, ptr [[A_CASTED]], align 8
// CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 2
-// CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
// CHECK4-NEXT: store i32 [[TMP17]], ptr [[B_CASTED]], align 4
// CHECK4-NEXT: [[TMP18:%.*]] = load i64, ptr [[B_CASTED]], align 8
// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 3
-// CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
// CHECK4-NEXT: store i32 [[TMP21]], ptr [[C_CASTED]], align 4
// CHECK4-NEXT: [[TMP22:%.*]] = load i64, ptr [[C_CASTED]], align 8
@@ -2535,9 +2535,9 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK4-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8
// CHECK4-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8
-// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8
-// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: store ptr [[TMP2]], ptr [[_TMP3]], align 8
// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
@@ -2546,14 +2546,14 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK4-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
// CHECK4-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK4: omp_if.then:
-// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK4-NEXT: store i32 [[INC]], ptr [[TMP7]], align 4
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1
// CHECK4-NEXT: store i32 [[DEC]], ptr [[B_ADDR]], align 4
-// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1
// CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP10]], align 4
@@ -2562,12 +2562,12 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK4-NEXT: br label [[OMP_IF_END]]
// CHECK4: omp_if.end:
// CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0
-// CHECK4-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
// CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1
// CHECK4-NEXT: store ptr [[B_ADDR]], ptr [[TMP14]], align 8
// CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2
-// CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK4-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8
// CHECK4-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK4-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP4]], i64 24, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.5, i32 [[TMP17]])
@@ -2616,7 +2616,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK4-NEXT: store double 0.000000e+00, ptr [[A]], align 8
// CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SST]], ptr [[THIS1]], i32 0, i32 0
// CHECK4-NEXT: store ptr [[A3]], ptr [[A2]], align 8
-// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META5]], !align [[META7:![0-9]+]]
+// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META4]], !align [[META6:![0-9]+]]
// CHECK4-NEXT: [[TMP1:%.*]] = load double, ptr [[TMP0]], align 8
// CHECK4-NEXT: store double [[TMP1]], ptr [[A_CASTED]], align 8
// CHECK4-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -2642,7 +2642,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK4-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK4-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8
-// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META7]]
+// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META4]], !align [[META6]]
// CHECK4-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8
// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
@@ -2654,7 +2654,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
// CHECK4-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 8
// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
-// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META7]]
+// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META4]], !align [[META6]]
// CHECK4-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8
// CHECK4-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]])
// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
@@ -2664,7 +2664,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK4-NEXT: br label [[OMP_IF_END]]
// CHECK4: omp_if.end:
// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0
-// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META7]]
+// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META4]], !align [[META6]]
// CHECK4-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 8
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK4-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP3]], i64 8, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.6, i32 [[TMP11]])
@@ -2690,7 +2690,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK4-NEXT: store ptr [[TMP1]], ptr [[TMP2]], align 8
// CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1
// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1
-// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !nonnull [[META5]], !align [[META7]]
+// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !nonnull [[META4]], !align [[META6]]
// CHECK4-NEXT: store ptr [[TMP5]], ptr [[TMP3]], align 8
// CHECK4-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]])
// CHECK4-NEXT: ret void
@@ -2724,12 +2724,12 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
// CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1
-// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META5]], !align [[META7]]
+// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META4]], !align [[META6]]
// CHECK4-NEXT: [[TMP4:%.*]] = load double, ptr [[TMP3]], align 8
// CHECK4-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00
// CHECK4-NEXT: store double [[INC]], ptr [[TMP3]], align 8
// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1
-// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META5]], !align [[META7]]
+// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META4]], !align [[META6]]
// CHECK4-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8
// CHECK4-NEXT: store double [[TMP7]], ptr [[A_CASTED]], align 8
// CHECK4-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -2754,7 +2754,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK4-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK4-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8
-// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META7]]
+// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META4]], !align [[META6]]
// CHECK4-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8
// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
@@ -2763,7 +2763,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK4-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0
// CHECK4-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK4: omp_if.then:
-// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META7]]
+// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META4]], !align [[META6]]
// CHECK4-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8
// CHECK4-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00
// CHECK4-NEXT: store double [[INC]], ptr [[TMP6]], align 8
@@ -2772,7 +2772,7 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK4-NEXT: br label [[OMP_IF_END]]
// CHECK4: omp_if.end:
// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0
-// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META7]]
+// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META4]], !align [[META6]]
// CHECK4-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK4-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP3]], i64 8, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.7, i32 [[TMP10]])
@@ -2806,222 +2806,222 @@ void array_func(int n, int a[n], St s[2]) {
//
//
// CHECK5-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_.
-// CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG6:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG5:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
-// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG10:![0-9]+]]
-// CHECK5-NEXT: call void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]), !dbg [[DBG11:![0-9]+]]
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG10]]
-// CHECK5-NEXT: ret ptr [[TMP2]], !dbg [[DBG10]]
+// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG9:![0-9]+]]
+// CHECK5-NEXT: call void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]), !dbg [[DBG10:![0-9]+]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG9]]
+// CHECK5-NEXT: ret ptr [[TMP2]], !dbg [[DBG9]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassC1Ev
-// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 !dbg [[DBG12:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 !dbg [[DBG11:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
-// CHECK5-NEXT: call void @_ZN9TestClassC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]), !dbg [[DBG13:![0-9]+]]
-// CHECK5-NEXT: ret void, !dbg [[DBG14:![0-9]+]]
+// CHECK5-NEXT: call void @_ZN9TestClassC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]), !dbg [[DBG12:![0-9]+]]
+// CHECK5-NEXT: ret void, !dbg [[DBG13:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_.
-// CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG15:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG14:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
-// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG16:![0-9]+]]
-// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP1]]) #[[ATTR3:[0-9]+]], !dbg [[DBG16]]
-// CHECK5-NEXT: ret void, !dbg [[DBG17:![0-9]+]]
+// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG15:![0-9]+]]
+// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP1]]) #[[ATTR3:[0-9]+]], !dbg [[DBG15]]
+// CHECK5-NEXT: ret void, !dbg [[DBG16:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev
-// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 !dbg [[DBG18:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 !dbg [[DBG17:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
-// CHECK5-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG19:![0-9]+]]
-// CHECK5-NEXT: ret void, !dbg [[DBG20:![0-9]+]]
+// CHECK5-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG18:![0-9]+]]
+// CHECK5-NEXT: ret void, !dbg [[DBG19:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@.__omp_threadprivate_init_.
-// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG21:![0-9]+]] {
+// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG20:![0-9]+]] {
// CHECK5-NEXT: entry:
-// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]), !dbg [[DBG22:![0-9]+]]
-// CHECK5-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @tc, ptr @.__kmpc_global_ctor_., ptr null, ptr @.__kmpc_global_dtor_.), !dbg [[DBG22]]
-// CHECK5-NEXT: ret void, !dbg [[DBG22]]
+// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]), !dbg [[DBG21:![0-9]+]]
+// CHECK5-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @tc, ptr @.__kmpc_global_ctor_., ptr null, ptr @.__kmpc_global_dtor_.), !dbg [[DBG21]]
+// CHECK5-NEXT: ret void, !dbg [[DBG21]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..1
-// CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" personality ptr @__gxx_personality_v0 !dbg [[DBG23:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" personality ptr @__gxx_personality_v0 !dbg [[DBG22:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
// CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
-// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG24:![0-9]+]]
-// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[CLASS_TESTCLASS:%.*]]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG25:![0-9]+]]
-// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN]], i64 2, !dbg [[DBG25]]
-// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]], !dbg [[DBG25]]
+// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG23:![0-9]+]]
+// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[CLASS_TESTCLASS:%.*]]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG24:![0-9]+]]
+// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN]], i64 2, !dbg [[DBG24]]
+// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]], !dbg [[DBG24]]
// CHECK5: arrayctor.loop:
-// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ], !dbg [[DBG25]]
+// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ], !dbg [[DBG24]]
// CHECK5-NEXT: invoke void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
-// CHECK5-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]], !dbg [[DBG25]]
+// CHECK5-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]], !dbg [[DBG24]]
// CHECK5: invoke.cont:
-// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYCTOR_CUR]], i64 1, !dbg [[DBG25]]
-// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]], !dbg [[DBG25]]
-// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]], !dbg [[DBG25]]
+// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYCTOR_CUR]], i64 1, !dbg [[DBG24]]
+// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]], !dbg [[DBG24]]
+// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]], !dbg [[DBG24]]
// CHECK5: arrayctor.cont:
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG24]]
-// CHECK5-NEXT: ret ptr [[TMP2]], !dbg [[DBG24]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG23]]
+// CHECK5-NEXT: ret ptr [[TMP2]], !dbg [[DBG23]]
// CHECK5: lpad:
// CHECK5-NEXT: [[TMP3:%.*]] = landingpad { ptr, i32 }
-// CHECK5-NEXT: cleanup, !dbg [[DBG26:![0-9]+]]
-// CHECK5-NEXT: [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 0, !dbg [[DBG26]]
-// CHECK5-NEXT: store ptr [[TMP4]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG26]]
-// CHECK5-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 1, !dbg [[DBG26]]
-// CHECK5-NEXT: store i32 [[TMP5]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG26]]
-// CHECK5-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[ARRAYCTOR_CUR]], !dbg [[DBG25]]
-// CHECK5-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG25]]
+// CHECK5-NEXT: cleanup, !dbg [[DBG25:![0-9]+]]
+// CHECK5-NEXT: [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 0, !dbg [[DBG25]]
+// CHECK5-NEXT: store ptr [[TMP4]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG25]]
+// CHECK5-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 1, !dbg [[DBG25]]
+// CHECK5-NEXT: store i32 [[TMP5]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG25]]
+// CHECK5-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[ARRAYCTOR_CUR]], !dbg [[DBG24]]
+// CHECK5-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG24]]
// CHECK5: arraydestroy.body:
-// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG25]]
-// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG25]]
-// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG25]]
-// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]], !dbg [[DBG25]]
-// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG25]]
+// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG24]]
+// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG24]]
+// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG24]]
+// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]], !dbg [[DBG24]]
+// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG24]]
// CHECK5: arraydestroy.done1:
-// CHECK5-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG25]]
+// CHECK5-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG24]]
// CHECK5: eh.resume:
-// CHECK5-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG25]]
-// CHECK5-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG25]]
-// CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG25]]
-// CHECK5-NEXT: [[LPAD_VAL2:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG25]]
-// CHECK5-NEXT: resume { ptr, i32 } [[LPAD_VAL2]], !dbg [[DBG25]]
+// CHECK5-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG24]]
+// CHECK5-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG24]]
+// CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG24]]
+// CHECK5-NEXT: [[LPAD_VAL2:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG24]]
+// CHECK5-NEXT: resume { ptr, i32 } [[LPAD_VAL2]], !dbg [[DBG24]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..2
-// CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG27:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG26:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
-// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG28:![0-9]+]]
-// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], ptr [[TMP1]], i64 2, !dbg [[DBG28]]
-// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG28]]
+// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG27:![0-9]+]]
+// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], ptr [[TMP1]], i64 2, !dbg [[DBG27]]
+// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG27]]
// CHECK5: arraydestroy.body:
-// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG28]]
-// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG28]]
-// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG28]]
-// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]], !dbg [[DBG28]]
-// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG28]]
+// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG27]]
+// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG27]]
+// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG27]]
+// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]], !dbg [[DBG27]]
+// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG27]]
// CHECK5: arraydestroy.done1:
-// CHECK5-NEXT: ret void, !dbg [[DBG29:![0-9]+]]
+// CHECK5-NEXT: ret void, !dbg [[DBG28:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@.__omp_threadprivate_init_..3
-// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG30:![0-9]+]] {
+// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG29:![0-9]+]] {
// CHECK5-NEXT: entry:
-// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]), !dbg [[DBG31:![0-9]+]]
-// CHECK5-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB3]], ptr @tc2, ptr @.__kmpc_global_ctor_..1, ptr null, ptr @.__kmpc_global_dtor_..2), !dbg [[DBG31]]
-// CHECK5-NEXT: ret void, !dbg [[DBG31]]
+// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]), !dbg [[DBG30:![0-9]+]]
+// CHECK5-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB3]], ptr @tc2, ptr @.__kmpc_global_ctor_..1, ptr null, ptr @.__kmpc_global_dtor_..2), !dbg [[DBG30]]
+// CHECK5-NEXT: ret void, !dbg [[DBG30]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init
-// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG32:![0-9]+]] {
+// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG31:![0-9]+]] {
// CHECK5-NEXT: entry:
-// CHECK5-NEXT: call void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @tc), !dbg [[DBG33:![0-9]+]]
-// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN9TestClassD1Ev, ptr @tc, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG35:![0-9]+]]
-// CHECK5-NEXT: ret void, !dbg [[DBG33]]
+// CHECK5-NEXT: call void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @tc), !dbg [[DBG32:![0-9]+]]
+// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN9TestClassD1Ev, ptr @tc, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG34:![0-9]+]]
+// CHECK5-NEXT: ret void, !dbg [[DBG32]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.4
-// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" personality ptr @__gxx_personality_v0 !dbg [[DBG36:![0-9]+]] {
+// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" personality ptr @__gxx_personality_v0 !dbg [[DBG35:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
-// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]], !dbg [[DBG37:![0-9]+]]
+// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]], !dbg [[DBG36:![0-9]+]]
// CHECK5: arrayctor.loop:
-// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ @tc2, [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ], !dbg [[DBG37]]
+// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ @tc2, [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ], !dbg [[DBG36]]
// CHECK5-NEXT: invoke void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
-// CHECK5-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]], !dbg [[DBG37]]
+// CHECK5-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]], !dbg [[DBG36]]
// CHECK5: invoke.cont:
-// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], ptr [[ARRAYCTOR_CUR]], i64 1, !dbg [[DBG37]]
-// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], getelementptr inbounds nuw (i8, ptr @tc2, i64 8), !dbg [[DBG37]]
-// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]], !dbg [[DBG37]]
+// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], ptr [[ARRAYCTOR_CUR]], i64 1, !dbg [[DBG36]]
+// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], getelementptr inbounds nuw (i8, ptr @tc2, i64 8), !dbg [[DBG36]]
+// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]], !dbg [[DBG36]]
// CHECK5: arrayctor.cont:
-// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG39:![0-9]+]]
-// CHECK5-NEXT: ret void, !dbg [[DBG39]]
+// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG38:![0-9]+]]
+// CHECK5-NEXT: ret void, !dbg [[DBG38]]
// CHECK5: lpad:
// CHECK5-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 }
-// CHECK5-NEXT: cleanup, !dbg [[DBG40:![0-9]+]]
-// CHECK5-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG40]]
-// CHECK5-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG40]]
-// CHECK5-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG40]]
-// CHECK5-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG40]]
-// CHECK5-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @tc2, [[ARRAYCTOR_CUR]], !dbg [[DBG37]]
-// CHECK5-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG37]]
+// CHECK5-NEXT: cleanup, !dbg [[DBG39:![0-9]+]]
+// CHECK5-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG39]]
+// CHECK5-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG39]]
+// CHECK5-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG39]]
+// CHECK5-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG39]]
+// CHECK5-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @tc2, [[ARRAYCTOR_CUR]], !dbg [[DBG36]]
+// CHECK5-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG36]]
// CHECK5: arraydestroy.body:
-// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG37]]
-// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG37]]
-// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG37]]
-// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2, !dbg [[DBG37]]
-// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG37]]
+// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG36]]
+// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG36]]
+// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG36]]
+// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2, !dbg [[DBG36]]
+// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG36]]
// CHECK5: arraydestroy.done1:
-// CHECK5-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG37]]
+// CHECK5-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG36]]
// CHECK5: eh.resume:
-// CHECK5-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG37]]
-// CHECK5-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG37]]
-// CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG37]]
-// CHECK5-NEXT: [[LPAD_VAL2:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG37]]
-// CHECK5-NEXT: resume { ptr, i32 } [[LPAD_VAL2]], !dbg [[DBG37]]
+// CHECK5-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG36]]
+// CHECK5-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG36]]
+// CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG36]]
+// CHECK5-NEXT: [[LPAD_VAL2:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG36]]
+// CHECK5-NEXT: resume { ptr, i32 } [[LPAD_VAL2]], !dbg [[DBG36]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
-// CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG41:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG40:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
-// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG42:![0-9]+]]
+// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG41:![0-9]+]]
// CHECK5: arraydestroy.body:
-// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds nuw (i8, ptr @tc2, i64 8), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG42]]
-// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG42]]
-// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG42]]
-// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2, !dbg [[DBG42]]
-// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG42]]
+// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds nuw (i8, ptr @tc2, i64 8), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG41]]
+// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG41]]
+// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG41]]
+// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2, !dbg [[DBG41]]
+// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG41]]
// CHECK5: arraydestroy.done1:
-// CHECK5-NEXT: ret void, !dbg [[DBG42]]
+// CHECK5-NEXT: ret void, !dbg [[DBG41]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassC2Ev
-// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG43:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG42:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
-// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG44:![0-9]+]]
-// CHECK5-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: ret void, !dbg [[DBG45:![0-9]+]]
+// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG43:![0-9]+]]
+// CHECK5-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG43]]
+// CHECK5-NEXT: ret void, !dbg [[DBG44:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev
-// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG46:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG45:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
-// CHECK5-NEXT: ret void, !dbg [[DBG47:![0-9]+]]
+// CHECK5-NEXT: ret void, !dbg [[DBG46:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_Z3foov
-// CHECK5-SAME: () #[[ATTR1]] !dbg [[DBG48:![0-9]+]] {
+// CHECK5-SAME: () #[[ATTR1]] !dbg [[DBG47:![0-9]+]] {
// CHECK5-NEXT: entry:
-// CHECK5-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG49:![0-9]+]]
-// CHECK5-NEXT: ret void, !dbg [[DBG50:![0-9]+]]
+// CHECK5-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG48:![0-9]+]]
+// CHECK5-NEXT: ret void, !dbg [[DBG49:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@main
-// CHECK5-SAME: () #[[ATTR5:[0-9]+]] personality ptr @__gxx_personality_v0 !dbg [[DBG51:![0-9]+]] {
+// CHECK5-SAME: () #[[ATTR5:[0-9]+]] personality ptr @__gxx_personality_v0 !dbg [[DBG50:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[A:%.*]] = alloca i8, align 1
@@ -3031,86 +3031,86 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK5-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8
// CHECK5-NEXT: [[DOTOMP_COPYPRIVATE_DID_IT:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_COPYPRIVATE_CPR_LIST:%.*]] = alloca [5 x ptr], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB5:[0-9]+]]), !dbg [[DBG52:![0-9]+]]
+// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB5:[0-9]+]]), !dbg [[DBG51:![0-9]+]]
// CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4
-// CHECK5-NEXT: store ptr @tc, ptr [[C]], align 8, !dbg [[DBG53:![0-9]+]]
-// CHECK5-NEXT: call void @_ZN3SSTIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[SST]]), !dbg [[DBG54:![0-9]+]]
-// CHECK5-NEXT: call void @_ZN2SSC1ERi(ptr noundef nonnull align 8 dereferenceable(16) [[SS]], ptr noundef nonnull align 4 dereferenceable(4) @tc), !dbg [[DBG55:![0-9]+]]
-// CHECK5-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB5]], i32 [[TMP0]]), !dbg [[DBG52]]
-// CHECK5-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG52]]
-// CHECK5-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG52]]
+// CHECK5-NEXT: store ptr @tc, ptr [[C]], align 8, !dbg [[DBG52:![0-9]+]]
+// CHECK5-NEXT: call void @_ZN3SSTIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[SST]]), !dbg [[DBG53:![0-9]+]]
+// CHECK5-NEXT: call void @_ZN2SSC1ERi(ptr noundef nonnull align 8 dereferenceable(16) [[SS]], ptr noundef nonnull align 4 dereferenceable(4) @tc), !dbg [[DBG54:![0-9]+]]
+// CHECK5-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB5]], i32 [[TMP0]]), !dbg [[DBG51]]
+// CHECK5-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG51]]
+// CHECK5-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG51]]
// CHECK5: omp_if.then:
-// CHECK5-NEXT: store i8 2, ptr [[A]], align 1, !dbg [[DBG56:![0-9]+]]
-// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB5]], i32 [[TMP0]]), !dbg [[DBG57:![0-9]+]]
-// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG57]]
+// CHECK5-NEXT: store i8 2, ptr [[A]], align 1, !dbg [[DBG55:![0-9]+]]
+// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB5]], i32 [[TMP0]]), !dbg [[DBG56:![0-9]+]]
+// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG56]]
// CHECK5: omp_if.end:
-// CHECK5-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB7:[0-9]+]], i32 [[TMP0]]), !dbg [[DBG58:![0-9]+]]
-// CHECK5-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0, !dbg [[DBG58]]
-// CHECK5-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN1:%.*]], label [[OMP_IF_END2:%.*]], !dbg [[DBG58]]
+// CHECK5-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB7:[0-9]+]], i32 [[TMP0]]), !dbg [[DBG57:![0-9]+]]
+// CHECK5-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0, !dbg [[DBG57]]
+// CHECK5-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN1:%.*]], label [[OMP_IF_END2:%.*]], !dbg [[DBG57]]
// CHECK5: omp_if.then1:
-// CHECK5-NEXT: store i8 2, ptr [[A]], align 1, !dbg [[DBG59:![0-9]+]]
-// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB7]], i32 [[TMP0]]), !dbg [[DBG60:![0-9]+]]
-// CHECK5-NEXT: br label [[OMP_IF_END2]], !dbg [[DBG60]]
+// CHECK5-NEXT: store i8 2, ptr [[A]], align 1, !dbg [[DBG58:![0-9]+]]
+// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB7]], i32 [[TMP0]]), !dbg [[DBG59:![0-9]+]]
+// CHECK5-NEXT: br label [[OMP_IF_END2]], !dbg [[DBG59]]
// CHECK5: omp_if.end2:
-// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB8:[0-9]+]], i32 [[TMP0]]), !dbg [[DBG61:![0-9]+]]
-// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG62:![0-9]+]]
-// CHECK5-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB10:[0-9]+]], i32 [[TMP0]]), !dbg [[DBG62]]
-// CHECK5-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0, !dbg [[DBG62]]
-// CHECK5-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN3:%.*]], label [[OMP_IF_END4:%.*]], !dbg [[DBG62]]
+// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB8:[0-9]+]], i32 [[TMP0]]), !dbg [[DBG60:![0-9]+]]
+// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG61:![0-9]+]]
+// CHECK5-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB10:[0-9]+]], i32 [[TMP0]]), !dbg [[DBG61]]
+// CHECK5-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0, !dbg [[DBG61]]
+// CHECK5-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN3:%.*]], label [[OMP_IF_END4:%.*]], !dbg [[DBG61]]
// CHECK5: omp_if.then3:
// CHECK5-NEXT: invoke void @_Z3foov()
-// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG63:![0-9]+]]
+// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG62:![0-9]+]]
// CHECK5: invoke.cont:
-// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB10]], i32 [[TMP0]]), !dbg [[DBG63]]
-// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG63]]
-// CHECK5-NEXT: br label [[OMP_IF_END4]], !dbg [[DBG63]]
+// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB10]], i32 [[TMP0]]), !dbg [[DBG62]]
+// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG62]]
+// CHECK5-NEXT: br label [[OMP_IF_END4]], !dbg [[DBG62]]
// CHECK5: omp_if.end4:
-// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0, !dbg [[DBG63]]
-// CHECK5-NEXT: store ptr [[A]], ptr [[TMP7]], align 8, !dbg [[DBG63]]
-// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1, !dbg [[DBG63]]
-// CHECK5-NEXT: store ptr @tc, ptr [[TMP8]], align 8, !dbg [[DBG63]]
-// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2, !dbg [[DBG63]]
-// CHECK5-NEXT: [[TMP10:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB12:[0-9]+]], i32 [[TMP0]], ptr @tc, i64 4, ptr @tc.cache.), !dbg [[DBG64:![0-9]+]]
-// CHECK5-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 8, !dbg [[DBG63]]
-// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 3, !dbg [[DBG63]]
-// CHECK5-NEXT: store ptr [[A2]], ptr [[TMP11]], align 8, !dbg [[DBG63]]
-// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 4, !dbg [[DBG63]]
-// CHECK5-NEXT: [[TMP13:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB14:[0-9]+]], i32 [[TMP0]], ptr @tc2, i64 8, ptr @tc2.cache.), !dbg [[DBG65:![0-9]+]]
-// CHECK5-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !dbg [[DBG63]]
-// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG63]]
-// CHECK5-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB10]], i32 [[TMP0]], i64 40, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func, i32 [[TMP14]]), !dbg [[DBG63]]
-// CHECK5-NEXT: [[TMP15:%.*]] = load i8, ptr [[A]], align 1, !dbg [[DBG66:![0-9]+]]
-// CHECK5-NEXT: [[CONV:%.*]] = sext i8 [[TMP15]] to i32, !dbg [[DBG66]]
-// CHECK5-NEXT: ret i32 [[CONV]], !dbg [[DBG67:![0-9]+]]
+// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0, !dbg [[DBG62]]
+// CHECK5-NEXT: store ptr [[A]], ptr [[TMP7]], align 8, !dbg [[DBG62]]
+// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1, !dbg [[DBG62]]
+// CHECK5-NEXT: store ptr @tc, ptr [[TMP8]], align 8, !dbg [[DBG62]]
+// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2, !dbg [[DBG62]]
+// CHECK5-NEXT: [[TMP10:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB12:[0-9]+]], i32 [[TMP0]], ptr @tc, i64 4, ptr @tc.cache.), !dbg [[DBG63:![0-9]+]]
+// CHECK5-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 8, !dbg [[DBG62]]
+// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 3, !dbg [[DBG62]]
+// CHECK5-NEXT: store ptr [[A2]], ptr [[TMP11]], align 8, !dbg [[DBG62]]
+// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 4, !dbg [[DBG62]]
+// CHECK5-NEXT: [[TMP13:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB14:[0-9]+]], i32 [[TMP0]], ptr @tc2, i64 8, ptr @tc2.cache.), !dbg [[DBG64:![0-9]+]]
+// CHECK5-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !dbg [[DBG62]]
+// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG62]]
+// CHECK5-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB10]], i32 [[TMP0]], i64 40, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func, i32 [[TMP14]]), !dbg [[DBG62]]
+// CHECK5-NEXT: [[TMP15:%.*]] = load i8, ptr [[A]], align 1, !dbg [[DBG65:![0-9]+]]
+// CHECK5-NEXT: [[CONV:%.*]] = sext i8 [[TMP15]] to i32, !dbg [[DBG65]]
+// CHECK5-NEXT: ret i32 [[CONV]], !dbg [[DBG66:![0-9]+]]
// CHECK5: terminate.lpad:
// CHECK5-NEXT: [[TMP16:%.*]] = landingpad { ptr, i32 }
-// CHECK5-NEXT: catch ptr null, !dbg [[DBG63]]
-// CHECK5-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP16]], 0, !dbg [[DBG63]]
-// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP17]]) #[[ATTR11:[0-9]+]], !dbg [[DBG63]]
-// CHECK5-NEXT: unreachable, !dbg [[DBG63]]
+// CHECK5-NEXT: catch ptr null, !dbg [[DBG62]]
+// CHECK5-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP16]], 0, !dbg [[DBG62]]
+// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP17]]) #[[ATTR11:[0-9]+]], !dbg [[DBG62]]
+// CHECK5-NEXT: unreachable, !dbg [[DBG62]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIdEC1Ev
-// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG68:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG67:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
-// CHECK5-NEXT: call void @_ZN3SSTIdEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]), !dbg [[DBG69:![0-9]+]]
-// CHECK5-NEXT: ret void, !dbg [[DBG70:![0-9]+]]
+// CHECK5-NEXT: call void @_ZN3SSTIdEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]), !dbg [[DBG68:![0-9]+]]
+// CHECK5-NEXT: ret void, !dbg [[DBG69:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC1ERi
-// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG71:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG70:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG72:![0-9]+]]
-// CHECK5-NEXT: call void @_ZN2SSC2ERi(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]]), !dbg [[DBG72]]
-// CHECK5-NEXT: ret void, !dbg [[DBG73:![0-9]+]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG71:![0-9]+]]
+// CHECK5-NEXT: call void @_ZN2SSC2ERi(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]]), !dbg [[DBG71]]
+// CHECK5-NEXT: ret void, !dbg [[DBG72:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate
@@ -3121,87 +3121,87 @@ void array_func(int n, int a[n], St s[2]) {
//
//
// CHECK5-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func
-// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8:[0-9]+]] !dbg [[DBG74:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8:[0-9]+]] !dbg [[DBG73:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
// CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG75:![0-9]+]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG75]]
-// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG75]]
-// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG75]]
-// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG75]]
-// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG75]]
-// CHECK5-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 1, !dbg [[DBG76:![0-9]+]]
-// CHECK5-NEXT: store i8 [[TMP8]], ptr [[TMP5]], align 1, !dbg [[DBG76]]
-// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG75]]
-// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8, !dbg [[DBG75]]
-// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[TMP3]], i64 0, i64 1, !dbg [[DBG75]]
-// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !dbg [[DBG75]]
-// CHECK5-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN9TestClassaSERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP10]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP12]]), !dbg [[DBG77:![0-9]+]]
-// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[TMP2]], i64 0, i64 2, !dbg [[DBG75]]
-// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8, !dbg [[DBG75]]
-// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[TMP3]], i64 0, i64 2, !dbg [[DBG75]]
-// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !dbg [[DBG75]]
-// CHECK5-NEXT: [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN9TestClassaSERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP14]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP16]]), !dbg [[DBG78:![0-9]+]]
-// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[TMP2]], i64 0, i64 3, !dbg [[DBG75]]
-// CHECK5-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8, !dbg [[DBG75]]
-// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[TMP3]], i64 0, i64 3, !dbg [[DBG75]]
-// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !dbg [[DBG75]]
-// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[TMP18]], ptr align 1 [[TMP20]], i64 2, i1 false), !dbg [[DBG75]]
-// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[TMP2]], i64 0, i64 4, !dbg [[DBG75]]
-// CHECK5-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8, !dbg [[DBG75]]
-// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[TMP3]], i64 0, i64 4, !dbg [[DBG75]]
-// CHECK5-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8, !dbg [[DBG75]]
-// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], ptr [[TMP22]], i64 2, !dbg [[DBG75]]
-// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP22]], [[TMP25]], !dbg [[DBG75]]
-// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]], !dbg [[DBG75]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG74:![0-9]+]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG74]]
+// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG74]]
+// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG74]]
+// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG74]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG74]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 1, !dbg [[DBG75:![0-9]+]]
+// CHECK5-NEXT: store i8 [[TMP8]], ptr [[TMP5]], align 1, !dbg [[DBG75]]
+// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG74]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8, !dbg [[DBG74]]
+// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[TMP3]], i64 0, i64 1, !dbg [[DBG74]]
+// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !dbg [[DBG74]]
+// CHECK5-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN9TestClassaSERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP10]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP12]]), !dbg [[DBG76:![0-9]+]]
+// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[TMP2]], i64 0, i64 2, !dbg [[DBG74]]
+// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8, !dbg [[DBG74]]
+// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[TMP3]], i64 0, i64 2, !dbg [[DBG74]]
+// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !dbg [[DBG74]]
+// CHECK5-NEXT: [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN9TestClassaSERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP14]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP16]]), !dbg [[DBG77:![0-9]+]]
+// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[TMP2]], i64 0, i64 3, !dbg [[DBG74]]
+// CHECK5-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8, !dbg [[DBG74]]
+// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[TMP3]], i64 0, i64 3, !dbg [[DBG74]]
+// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !dbg [[DBG74]]
+// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[TMP18]], ptr align 1 [[TMP20]], i64 2, i1 false), !dbg [[DBG78:![0-9]+]]
+// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[TMP2]], i64 0, i64 4, !dbg [[DBG74]]
+// CHECK5-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8, !dbg [[DBG74]]
+// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[TMP3]], i64 0, i64 4, !dbg [[DBG74]]
+// CHECK5-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8, !dbg [[DBG74]]
+// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], ptr [[TMP22]], i64 2, !dbg [[DBG74]]
+// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP22]], [[TMP25]], !dbg [[DBG74]]
+// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]], !dbg [[DBG74]]
// CHECK5: omp.arraycpy.body:
-// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ], !dbg [[DBG75]]
-// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ], !dbg [[DBG75]]
-// CHECK5-NEXT: [[CALL3:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN9TestClassaSERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]), !dbg [[DBG79:![0-9]+]]
-// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[CLASS_TESTCLASS]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1, !dbg [[DBG75]]
-// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[CLASS_TESTCLASS]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1, !dbg [[DBG75]]
-// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP25]], !dbg [[DBG75]]
-// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]], !dbg [[DBG75]]
+// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ], !dbg [[DBG74]]
+// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ], !dbg [[DBG74]]
+// CHECK5-NEXT: [[CALL3:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN9TestClassaSERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]), !dbg [[DBG81:![0-9]+]]
+// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[CLASS_TESTCLASS]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1, !dbg [[DBG74]]
+// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[CLASS_TESTCLASS]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1, !dbg [[DBG74]]
+// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP25]], !dbg [[DBG74]]
+// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]], !dbg [[DBG74]]
// CHECK5: omp.arraycpy.done4:
-// CHECK5-NEXT: ret void, !dbg [[DBG79]]
+// CHECK5-NEXT: ret void, !dbg [[DBG81]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassaSERKS_
-// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] align 2 !dbg [[DBG80:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] align 2 !dbg [[DBG82:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
-// CHECK5-NEXT: ret ptr [[THIS1]], !dbg [[DBG81:![0-9]+]]
+// CHECK5-NEXT: ret ptr [[THIS1]], !dbg [[DBG83:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIdEC2Ev
-// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG82:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG84:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A2:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
-// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG83:![0-9]+]]
-// CHECK5-NEXT: store double 0.000000e+00, ptr [[A]], align 8, !dbg [[DBG83]]
-// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SST]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG84:![0-9]+]]
-// CHECK5-NEXT: store ptr [[A3]], ptr [[A2]], align 8, !dbg [[DBG84]]
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8, !dbg [[DBG85:![0-9]+]], !nonnull [[META9:![0-9]+]], !align [[META86:![0-9]+]]
-// CHECK5-NEXT: [[TMP1:%.*]] = load double, ptr [[TMP0]], align 8, !dbg [[DBG87:![0-9]+]]
-// CHECK5-NEXT: store double [[TMP1]], ptr [[A_CASTED]], align 8, !dbg [[DBG87]]
-// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG87]]
-// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB18:[0-9]+]], i32 2, ptr @_ZN3SSTIdEC2Ev.omp_outlined, ptr [[THIS1]], i64 [[TMP2]]), !dbg [[DBG87]]
-// CHECK5-NEXT: ret void, !dbg [[DBG88:![0-9]+]]
+// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG85:![0-9]+]]
+// CHECK5-NEXT: store double 0.000000e+00, ptr [[A]], align 8, !dbg [[DBG85]]
+// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SST]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG86:![0-9]+]]
+// CHECK5-NEXT: store ptr [[A3]], ptr [[A2]], align 8, !dbg [[DBG86]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8, !dbg [[DBG87:![0-9]+]], !nonnull [[META8:![0-9]+]], !align [[META88:![0-9]+]]
+// CHECK5-NEXT: [[TMP1:%.*]] = load double, ptr [[TMP0]], align 8, !dbg [[DBG89:![0-9]+]]
+// CHECK5-NEXT: store double [[TMP1]], ptr [[A_CASTED]], align 8, !dbg [[DBG89]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG89]]
+// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB18:[0-9]+]], i32 2, ptr @_ZN3SSTIdEC2Ev.omp_outlined, ptr [[THIS1]], i64 [[TMP2]]), !dbg [[DBG89]]
+// CHECK5-NEXT: ret void, !dbg [[DBG90:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIdEC2Ev.omp_outlined
-// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) #[[ATTR10:[0-9]+]] personality ptr @__gxx_personality_v0 !dbg [[DBG89:![0-9]+]] {
+// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) #[[ATTR10:[0-9]+]] personality ptr @__gxx_personality_v0 !dbg [[DBG91:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -3216,45 +3216,45 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG90:![0-9]+]]
-// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG90]]
-// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG91:![0-9]+]], !nonnull [[META9]], !align [[META86]]
-// CHECK5-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8, !dbg [[DBG92:![0-9]+]]
-// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG92]]
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG92]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG92]]
-// CHECK5-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB16:[0-9]+]], i32 [[TMP3]]), !dbg [[DBG92]]
-// CHECK5-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0, !dbg [[DBG92]]
-// CHECK5-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG92]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG92:![0-9]+]]
+// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG92]]
+// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG93:![0-9]+]], !nonnull [[META8]], !align [[META88]]
+// CHECK5-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8, !dbg [[DBG94:![0-9]+]]
+// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG94]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG94]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG94]]
+// CHECK5-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB16:[0-9]+]], i32 [[TMP3]]), !dbg [[DBG94]]
+// CHECK5-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0, !dbg [[DBG94]]
+// CHECK5-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG94]]
// CHECK5: omp_if.then:
-// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG93:![0-9]+]]
-// CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 8, !dbg [[DBG93]]
-// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG93]]
-// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG94:![0-9]+]], !nonnull [[META9]], !align [[META86]]
-// CHECK5-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8, !dbg [[DBG93]]
+// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG95:![0-9]+]]
+// CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 8, !dbg [[DBG95]]
+// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG95]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG96:![0-9]+]], !nonnull [[META8]], !align [[META88]]
+// CHECK5-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8, !dbg [[DBG95]]
// CHECK5-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]])
-// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG93]]
+// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG95]]
// CHECK5: invoke.cont:
-// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB16]], i32 [[TMP3]]), !dbg [[DBG93]]
-// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG93]]
-// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG93]]
+// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB16]], i32 [[TMP3]]), !dbg [[DBG95]]
+// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG95]]
+// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG95]]
// CHECK5: omp_if.end:
-// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0, !dbg [[DBG93]]
-// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG95:![0-9]+]], !nonnull [[META9]], !align [[META86]]
-// CHECK5-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 8, !dbg [[DBG93]]
-// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG93]]
-// CHECK5-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB16]], i32 [[TMP3]], i64 8, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.5, i32 [[TMP11]]), !dbg [[DBG93]]
-// CHECK5-NEXT: ret void, !dbg [[DBG96:![0-9]+]]
+// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0, !dbg [[DBG95]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG97:![0-9]+]], !nonnull [[META8]], !align [[META88]]
+// CHECK5-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 8, !dbg [[DBG95]]
+// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG95]]
+// CHECK5-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB16]], i32 [[TMP3]], i64 8, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.5, i32 [[TMP11]]), !dbg [[DBG95]]
+// CHECK5-NEXT: ret void, !dbg [[DBG98:![0-9]+]]
// CHECK5: terminate.lpad:
// CHECK5-NEXT: [[TMP12:%.*]] = landingpad { ptr, i32 }
-// CHECK5-NEXT: catch ptr null, !dbg [[DBG93]]
-// CHECK5-NEXT: [[TMP13:%.*]] = extractvalue { ptr, i32 } [[TMP12]], 0, !dbg [[DBG93]]
-// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP13]]) #[[ATTR11]], !dbg [[DBG93]]
-// CHECK5-NEXT: unreachable, !dbg [[DBG93]]
+// CHECK5-NEXT: catch ptr null, !dbg [[DBG95]]
+// CHECK5-NEXT: [[TMP13:%.*]] = extractvalue { ptr, i32 } [[TMP12]], 0, !dbg [[DBG95]]
+// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP13]]) #[[ATTR11]], !dbg [[DBG95]]
+// CHECK5-NEXT: unreachable, !dbg [[DBG95]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_ZZN3SSTIdEC1EvENKUlvE_clEv
-// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR1]] align 2 !dbg [[DBG97:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR1]] align 2 !dbg [[DBG99:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
@@ -3262,36 +3262,36 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG98:![0-9]+]]
-// CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP2]], align 8, !dbg [[DBG98]]
-// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG98]]
-// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG99:![0-9]+]]
-// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG99]], !nonnull [[META9]], !align [[META86]]
-// CHECK5-NEXT: store ptr [[TMP5]], ptr [[TMP3]], align 8, !dbg [[DBG98]]
-// CHECK5-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]), !dbg [[DBG98]]
-// CHECK5-NEXT: ret void, !dbg [[DBG100:![0-9]+]]
+// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG100:![0-9]+]]
+// CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP2]], align 8, !dbg [[DBG100]]
+// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG100]]
+// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG101:![0-9]+]]
+// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG101]], !nonnull [[META8]], !align [[META88]]
+// CHECK5-NEXT: store ptr [[TMP5]], ptr [[TMP3]], align 8, !dbg [[DBG100]]
+// CHECK5-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]), !dbg [[DBG100]]
+// CHECK5-NEXT: ret void, !dbg [[DBG102:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.5
-// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8]] !dbg [[DBG101:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8]] !dbg [[DBG103:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
// CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG102:![0-9]+]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG102]]
-// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG102]]
-// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG102]]
-// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG102]]
-// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG102]]
-// CHECK5-NEXT: [[TMP8:%.*]] = load double, ptr [[TMP7]], align 8, !dbg [[DBG103:![0-9]+]]
-// CHECK5-NEXT: store double [[TMP8]], ptr [[TMP5]], align 8, !dbg [[DBG103]]
-// CHECK5-NEXT: ret void, !dbg [[DBG103]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG104:![0-9]+]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG104]]
+// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG104]]
+// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG104]]
+// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG104]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG104]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load double, ptr [[TMP7]], align 8, !dbg [[DBG105:![0-9]+]]
+// CHECK5-NEXT: store double [[TMP8]], ptr [[TMP5]], align 8, !dbg [[DBG105]]
+// CHECK5-NEXT: ret void, !dbg [[DBG105]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv
-// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR2]] align 2 !dbg [[DBG106:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR2]] align 2 !dbg [[DBG108:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
@@ -3299,22 +3299,22 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG107:![0-9]+]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG107]], !nonnull [[META9]], !align [[META86]]
-// CHECK5-NEXT: [[TMP4:%.*]] = load double, ptr [[TMP3]], align 8, !dbg [[DBG108:![0-9]+]]
-// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00, !dbg [[DBG108]]
-// CHECK5-NEXT: store double [[INC]], ptr [[TMP3]], align 8, !dbg [[DBG108]]
-// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG109:![0-9]+]]
-// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !dbg [[DBG109]], !nonnull [[META9]], !align [[META86]]
-// CHECK5-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8, !dbg [[DBG110:![0-9]+]]
-// CHECK5-NEXT: store double [[TMP7]], ptr [[A_CASTED]], align 8, !dbg [[DBG110]]
-// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG110]]
-// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB22:[0-9]+]], i32 2, ptr @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv.omp_outlined, ptr [[TMP1]], i64 [[TMP8]]), !dbg [[DBG110]]
-// CHECK5-NEXT: ret void, !dbg [[DBG111:![0-9]+]]
+// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG109:![0-9]+]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG109]], !nonnull [[META8]], !align [[META88]]
+// CHECK5-NEXT: [[TMP4:%.*]] = load double, ptr [[TMP3]], align 8, !dbg [[DBG110:![0-9]+]]
+// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00, !dbg [[DBG110]]
+// CHECK5-NEXT: store double [[INC]], ptr [[TMP3]], align 8, !dbg [[DBG110]]
+// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG111:![0-9]+]]
+// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !dbg [[DBG111]], !nonnull [[META8]], !align [[META88]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8, !dbg [[DBG112:![0-9]+]]
+// CHECK5-NEXT: store double [[TMP7]], ptr [[A_CASTED]], align 8, !dbg [[DBG112]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG112]]
+// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB22:[0-9]+]], i32 2, ptr @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv.omp_outlined, ptr [[TMP1]], i64 [[TMP8]]), !dbg [[DBG112]]
+// CHECK5-NEXT: ret void, !dbg [[DBG113:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv.omp_outlined
-// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) #[[ATTR10]] !dbg [[DBG112:![0-9]+]] {
+// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) #[[ATTR10]] !dbg [[DBG114:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -3328,53 +3328,53 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG113:![0-9]+]]
-// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG113]]
-// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG114:![0-9]+]], !nonnull [[META9]], !align [[META86]]
-// CHECK5-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8, !dbg [[DBG115:![0-9]+]]
-// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG115]]
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG115]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG115]]
-// CHECK5-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB20:[0-9]+]], i32 [[TMP3]]), !dbg [[DBG115]]
-// CHECK5-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0, !dbg [[DBG115]]
-// CHECK5-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG115]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG115:![0-9]+]]
+// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG115]]
+// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG116:![0-9]+]], !nonnull [[META8]], !align [[META88]]
+// CHECK5-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8, !dbg [[DBG117:![0-9]+]]
+// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG117]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG117]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG117]]
+// CHECK5-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB20:[0-9]+]], i32 [[TMP3]]), !dbg [[DBG117]]
+// CHECK5-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0, !dbg [[DBG117]]
+// CHECK5-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG117]]
// CHECK5: omp_if.then:
-// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG114]], !nonnull [[META9]], !align [[META86]]
-// CHECK5-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8, !dbg [[DBG116:![0-9]+]]
-// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00, !dbg [[DBG116]]
-// CHECK5-NEXT: store double [[INC]], ptr [[TMP6]], align 8, !dbg [[DBG116]]
-// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB20]], i32 [[TMP3]]), !dbg [[DBG116]]
-// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG116]]
-// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG116]]
+// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG116]], !nonnull [[META8]], !align [[META88]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8, !dbg [[DBG118:![0-9]+]]
+// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00, !dbg [[DBG118]]
+// CHECK5-NEXT: store double [[INC]], ptr [[TMP6]], align 8, !dbg [[DBG118]]
+// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB20]], i32 [[TMP3]]), !dbg [[DBG118]]
+// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG118]]
+// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG118]]
// CHECK5: omp_if.end:
-// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0, !dbg [[DBG116]]
-// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG117:![0-9]+]], !nonnull [[META9]], !align [[META86]]
-// CHECK5-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8, !dbg [[DBG116]]
-// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG116]]
-// CHECK5-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB20]], i32 [[TMP3]], i64 8, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.6, i32 [[TMP10]]), !dbg [[DBG116]]
-// CHECK5-NEXT: ret void, !dbg [[DBG118:![0-9]+]]
+// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0, !dbg [[DBG118]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG119:![0-9]+]], !nonnull [[META8]], !align [[META88]]
+// CHECK5-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8, !dbg [[DBG118]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG118]]
+// CHECK5-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB20]], i32 [[TMP3]], i64 8, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.6, i32 [[TMP10]]), !dbg [[DBG118]]
+// CHECK5-NEXT: ret void, !dbg [[DBG120:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.6
-// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8]] !dbg [[DBG119:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8]] !dbg [[DBG121:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
// CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG120:![0-9]+]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG120]]
-// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG120]]
-// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG120]]
-// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG120]]
-// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG120]]
-// CHECK5-NEXT: [[TMP8:%.*]] = load double, ptr [[TMP7]], align 8, !dbg [[DBG121:![0-9]+]]
-// CHECK5-NEXT: store double [[TMP8]], ptr [[TMP5]], align 8, !dbg [[DBG121]]
-// CHECK5-NEXT: ret void, !dbg [[DBG121]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG122:![0-9]+]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG122]]
+// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG122]]
+// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG122]]
+// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG122]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG122]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load double, ptr [[TMP7]], align 8, !dbg [[DBG123:![0-9]+]]
+// CHECK5-NEXT: store double [[TMP8]], ptr [[TMP5]], align 8, !dbg [[DBG123]]
+// CHECK5-NEXT: ret void, !dbg [[DBG123]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC2ERi
-// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG122:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG124:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
@@ -3387,44 +3387,44 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
-// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG123:![0-9]+]]
-// CHECK5-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG123]]
-// CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG124:![0-9]+]]
-// CHECK5-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4, !dbg [[DBG124]]
-// CHECK5-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16, !dbg [[DBG124]]
-// CHECK5-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0, !dbg [[DBG124]]
-// CHECK5-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4, !dbg [[DBG124]]
-// CHECK5-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG125:![0-9]+]]
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG126:![0-9]+]], !nonnull [[META9]], !align [[META127:![0-9]+]]
-// CHECK5-NEXT: store ptr [[TMP0]], ptr [[C]], align 8, !dbg [[DBG125]]
-// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG128:![0-9]+]]
-// CHECK5-NEXT: store ptr [[A3]], ptr [[A2]], align 8, !dbg [[DBG128]]
-// CHECK5-NEXT: [[B5:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG129:![0-9]+]]
-// CHECK5-NEXT: [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 4, !dbg [[DBG129]]
-// CHECK5-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4, !dbg [[DBG129]]
-// CHECK5-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4, !dbg [[DBG129]]
-// CHECK5-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32, !dbg [[DBG129]]
-// CHECK5-NEXT: store i32 [[BF_CAST]], ptr [[B4]], align 4, !dbg [[DBG129]]
-// CHECK5-NEXT: [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG130:![0-9]+]]
-// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8, !dbg [[DBG130]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: store ptr [[TMP1]], ptr [[C7]], align 8, !dbg [[DBG130]]
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8, !dbg [[DBG131:![0-9]+]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG132:![0-9]+]]
-// CHECK5-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4, !dbg [[DBG132]]
-// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG132]]
-// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[B4]], align 4, !dbg [[DBG132]]
-// CHECK5-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4, !dbg [[DBG132]]
-// CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8, !dbg [[DBG132]]
-// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8, !dbg [[DBG133:![0-9]+]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG132]]
-// CHECK5-NEXT: store i32 [[TMP8]], ptr [[C_CASTED]], align 4, !dbg [[DBG132]]
-// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[C_CASTED]], align 8, !dbg [[DBG132]]
-// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB26:[0-9]+]], i32 4, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]]), !dbg [[DBG132]]
-// CHECK5-NEXT: ret void, !dbg [[DBG134:![0-9]+]]
+// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG125:![0-9]+]]
+// CHECK5-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG125]]
+// CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG126:![0-9]+]]
+// CHECK5-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4, !dbg [[DBG126]]
+// CHECK5-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16, !dbg [[DBG126]]
+// CHECK5-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0, !dbg [[DBG126]]
+// CHECK5-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4, !dbg [[DBG126]]
+// CHECK5-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG127:![0-9]+]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG128:![0-9]+]], !nonnull [[META8]], !align [[META129:![0-9]+]]
+// CHECK5-NEXT: store ptr [[TMP0]], ptr [[C]], align 8, !dbg [[DBG127]]
+// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG130:![0-9]+]]
+// CHECK5-NEXT: store ptr [[A3]], ptr [[A2]], align 8, !dbg [[DBG130]]
+// CHECK5-NEXT: [[B5:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG131:![0-9]+]]
+// CHECK5-NEXT: [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 4, !dbg [[DBG131]]
+// CHECK5-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4, !dbg [[DBG131]]
+// CHECK5-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4, !dbg [[DBG131]]
+// CHECK5-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32, !dbg [[DBG131]]
+// CHECK5-NEXT: store i32 [[BF_CAST]], ptr [[B4]], align 4, !dbg [[DBG131]]
+// CHECK5-NEXT: [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG132:![0-9]+]]
+// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8, !dbg [[DBG132]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: store ptr [[TMP1]], ptr [[C7]], align 8, !dbg [[DBG132]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8, !dbg [[DBG133:![0-9]+]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG134:![0-9]+]]
+// CHECK5-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4, !dbg [[DBG134]]
+// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG134]]
+// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[B4]], align 4, !dbg [[DBG134]]
+// CHECK5-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4, !dbg [[DBG134]]
+// CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8, !dbg [[DBG134]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8, !dbg [[DBG135:![0-9]+]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG134]]
+// CHECK5-NEXT: store i32 [[TMP8]], ptr [[C_CASTED]], align 4, !dbg [[DBG134]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[C_CASTED]], align 8, !dbg [[DBG134]]
+// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB26:[0-9]+]], i32 4, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]]), !dbg [[DBG134]]
+// CHECK5-NEXT: ret void, !dbg [[DBG136:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined
-// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[C:%.*]]) #[[ATTR10]] personality ptr @__gxx_personality_v0 !dbg [[DBG135:![0-9]+]] {
+// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[C:%.*]]) #[[ATTR10]] personality ptr @__gxx_personality_v0 !dbg [[DBG137:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -3445,58 +3445,58 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK5-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
// CHECK5-NEXT: store i64 [[C]], ptr [[C_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG136:![0-9]+]]
-// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG136]]
-// CHECK5-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8, !dbg [[DBG136]]
-// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG137:![0-9]+]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8, !dbg [[DBG138:![0-9]+]]
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG139:![0-9]+]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: store ptr [[TMP2]], ptr [[_TMP3]], align 8, !dbg [[DBG138]]
-// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG138]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG138]]
-// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !dbg [[DBG138]]
-// CHECK5-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB24:[0-9]+]], i32 [[TMP4]]), !dbg [[DBG138]]
-// CHECK5-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0, !dbg [[DBG138]]
-// CHECK5-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG138]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG138:![0-9]+]]
+// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG138]]
+// CHECK5-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8, !dbg [[DBG138]]
+// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG139:![0-9]+]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8, !dbg [[DBG140:![0-9]+]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG141:![0-9]+]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: store ptr [[TMP2]], ptr [[_TMP3]], align 8, !dbg [[DBG140]]
+// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG140]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG140]]
+// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !dbg [[DBG140]]
+// CHECK5-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB24:[0-9]+]], i32 [[TMP4]]), !dbg [[DBG140]]
+// CHECK5-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0, !dbg [[DBG140]]
+// CHECK5-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG140]]
// CHECK5: omp_if.then:
-// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG140:![0-9]+]]
-// CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP7]], align 8, !dbg [[DBG140]]
-// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG140]]
-// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG141:![0-9]+]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8, !dbg [[DBG140]]
-// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 2, !dbg [[DBG140]]
-// CHECK5-NEXT: store ptr [[B_ADDR]], ptr [[TMP10]], align 8, !dbg [[DBG140]]
-// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 3, !dbg [[DBG140]]
-// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG141]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8, !dbg [[DBG140]]
+// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG142:![0-9]+]]
+// CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP7]], align 8, !dbg [[DBG142]]
+// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG142]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG143:![0-9]+]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8, !dbg [[DBG142]]
+// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 2, !dbg [[DBG142]]
+// CHECK5-NEXT: store ptr [[B_ADDR]], ptr [[TMP10]], align 8, !dbg [[DBG142]]
+// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 3, !dbg [[DBG142]]
+// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG143]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8, !dbg [[DBG142]]
// CHECK5-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]])
-// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG140]]
+// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG142]]
// CHECK5: invoke.cont:
-// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB24]], i32 [[TMP4]]), !dbg [[DBG140]]
-// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG140]]
-// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG140]]
+// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB24]], i32 [[TMP4]]), !dbg [[DBG142]]
+// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG142]]
+// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG142]]
// CHECK5: omp_if.end:
-// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0, !dbg [[DBG140]]
-// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG142:![0-9]+]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8, !dbg [[DBG140]]
-// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1, !dbg [[DBG140]]
-// CHECK5-NEXT: store ptr [[B_ADDR]], ptr [[TMP15]], align 8, !dbg [[DBG140]]
-// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2, !dbg [[DBG140]]
-// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG143:![0-9]+]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8, !dbg [[DBG140]]
-// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG140]]
-// CHECK5-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB24]], i32 [[TMP4]], i64 24, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.7, i32 [[TMP18]]), !dbg [[DBG140]]
-// CHECK5-NEXT: ret void, !dbg [[DBG144:![0-9]+]]
+// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0, !dbg [[DBG142]]
+// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG144:![0-9]+]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8, !dbg [[DBG142]]
+// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1, !dbg [[DBG142]]
+// CHECK5-NEXT: store ptr [[B_ADDR]], ptr [[TMP15]], align 8, !dbg [[DBG142]]
+// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2, !dbg [[DBG142]]
+// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG145:![0-9]+]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8, !dbg [[DBG142]]
+// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG142]]
+// CHECK5-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB24]], i32 [[TMP4]], i64 24, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.7, i32 [[TMP18]]), !dbg [[DBG142]]
+// CHECK5-NEXT: ret void, !dbg [[DBG146:![0-9]+]]
// CHECK5: terminate.lpad:
// CHECK5-NEXT: [[TMP19:%.*]] = landingpad { ptr, i32 }
-// CHECK5-NEXT: catch ptr null, !dbg [[DBG140]]
-// CHECK5-NEXT: [[TMP20:%.*]] = extractvalue { ptr, i32 } [[TMP19]], 0, !dbg [[DBG140]]
-// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP20]]) #[[ATTR11]], !dbg [[DBG140]]
-// CHECK5-NEXT: unreachable, !dbg [[DBG140]]
+// CHECK5-NEXT: catch ptr null, !dbg [[DBG142]]
+// CHECK5-NEXT: [[TMP20:%.*]] = extractvalue { ptr, i32 } [[TMP19]], 0, !dbg [[DBG142]]
+// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP20]]) #[[ATTR11]], !dbg [[DBG142]]
+// CHECK5-NEXT: unreachable, !dbg [[DBG142]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv
-// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2]] align 2 !dbg [[DBG145:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2]] align 2 !dbg [[DBG147:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
@@ -3506,72 +3506,72 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG146:![0-9]+]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG146]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !dbg [[DBG147:![0-9]+]]
-// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1, !dbg [[DBG147]]
-// CHECK5-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4, !dbg [[DBG147]]
-// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG148:![0-9]+]]
-// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !dbg [[DBG148]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4, !dbg [[DBG149:![0-9]+]]
-// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1, !dbg [[DBG149]]
-// CHECK5-NEXT: store i32 [[DEC]], ptr [[TMP6]], align 4, !dbg [[DBG149]]
-// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3, !dbg [[DBG150:![0-9]+]]
-// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !dbg [[DBG150]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4, !dbg [[DBG151:![0-9]+]]
-// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1, !dbg [[DBG151]]
-// CHECK5-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4, !dbg [[DBG151]]
-// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG152:![0-9]+]]
-// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !dbg [[DBG152]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG153:![0-9]+]]
-// CHECK5-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4, !dbg [[DBG153]]
-// CHECK5-NEXT: [[TMP14:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG153]]
-// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG154:![0-9]+]]
-// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !dbg [[DBG154]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4, !dbg [[DBG153]]
-// CHECK5-NEXT: store i32 [[TMP17]], ptr [[B_CASTED]], align 4, !dbg [[DBG153]]
-// CHECK5-NEXT: [[TMP18:%.*]] = load i64, ptr [[B_CASTED]], align 8, !dbg [[DBG153]]
-// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3, !dbg [[DBG155:![0-9]+]]
-// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !dbg [[DBG155]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4, !dbg [[DBG153]]
-// CHECK5-NEXT: store i32 [[TMP21]], ptr [[C_CASTED]], align 4, !dbg [[DBG153]]
-// CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[C_CASTED]], align 8, !dbg [[DBG153]]
-// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB30:[0-9]+]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP1]], i64 [[TMP14]], i64 [[TMP18]], i64 [[TMP22]]), !dbg [[DBG153]]
-// CHECK5-NEXT: ret void, !dbg [[DBG156:![0-9]+]]
+// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG148:![0-9]+]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG148]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !dbg [[DBG149:![0-9]+]]
+// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1, !dbg [[DBG149]]
+// CHECK5-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4, !dbg [[DBG149]]
+// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG150:![0-9]+]]
+// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !dbg [[DBG150]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4, !dbg [[DBG151:![0-9]+]]
+// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1, !dbg [[DBG151]]
+// CHECK5-NEXT: store i32 [[DEC]], ptr [[TMP6]], align 4, !dbg [[DBG151]]
+// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3, !dbg [[DBG152:![0-9]+]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !dbg [[DBG152]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4, !dbg [[DBG153:![0-9]+]]
+// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1, !dbg [[DBG153]]
+// CHECK5-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4, !dbg [[DBG153]]
+// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG154:![0-9]+]]
+// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !dbg [[DBG154]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG155:![0-9]+]]
+// CHECK5-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4, !dbg [[DBG155]]
+// CHECK5-NEXT: [[TMP14:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG155]]
+// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG156:![0-9]+]]
+// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !dbg [[DBG156]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4, !dbg [[DBG155]]
+// CHECK5-NEXT: store i32 [[TMP17]], ptr [[B_CASTED]], align 4, !dbg [[DBG155]]
+// CHECK5-NEXT: [[TMP18:%.*]] = load i64, ptr [[B_CASTED]], align 8, !dbg [[DBG155]]
+// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3, !dbg [[DBG157:![0-9]+]]
+// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !dbg [[DBG157]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4, !dbg [[DBG155]]
+// CHECK5-NEXT: store i32 [[TMP21]], ptr [[C_CASTED]], align 4, !dbg [[DBG155]]
+// CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[C_CASTED]], align 8, !dbg [[DBG155]]
+// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB30:[0-9]+]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP1]], i64 [[TMP14]], i64 [[TMP18]], i64 [[TMP22]]), !dbg [[DBG155]]
+// CHECK5-NEXT: ret void, !dbg [[DBG158:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.7
-// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8]] !dbg [[DBG157:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8]] !dbg [[DBG159:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
// CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG158:![0-9]+]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG158]]
-// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG158]]
-// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG158]]
-// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG158]]
-// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG158]]
-// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG159:![0-9]+]]
-// CHECK5-NEXT: store i32 [[TMP8]], ptr [[TMP5]], align 4, !dbg [[DBG159]]
-// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG158]]
-// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8, !dbg [[DBG158]]
-// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 1, !dbg [[DBG158]]
-// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !dbg [[DBG158]]
-// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG160:![0-9]+]]
-// CHECK5-NEXT: store i32 [[TMP13]], ptr [[TMP10]], align 4, !dbg [[DBG160]]
-// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 2, !dbg [[DBG158]]
-// CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8, !dbg [[DBG158]]
-// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 2, !dbg [[DBG158]]
-// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8, !dbg [[DBG158]]
-// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4, !dbg [[DBG161:![0-9]+]]
-// CHECK5-NEXT: store i32 [[TMP18]], ptr [[TMP15]], align 4, !dbg [[DBG161]]
-// CHECK5-NEXT: ret void, !dbg [[DBG161]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG160:![0-9]+]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG160]]
+// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG160]]
+// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG160]]
+// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG160]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG160]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG161:![0-9]+]]
+// CHECK5-NEXT: store i32 [[TMP8]], ptr [[TMP5]], align 4, !dbg [[DBG161]]
+// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG160]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8, !dbg [[DBG160]]
+// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 1, !dbg [[DBG160]]
+// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !dbg [[DBG160]]
+// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG162:![0-9]+]]
+// CHECK5-NEXT: store i32 [[TMP13]], ptr [[TMP10]], align 4, !dbg [[DBG162]]
+// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 2, !dbg [[DBG160]]
+// CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8, !dbg [[DBG160]]
+// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 2, !dbg [[DBG160]]
+// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8, !dbg [[DBG160]]
+// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4, !dbg [[DBG163:![0-9]+]]
+// CHECK5-NEXT: store i32 [[TMP18]], ptr [[TMP15]], align 4, !dbg [[DBG163]]
+// CHECK5-NEXT: ret void, !dbg [[DBG163]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined
-// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[C:%.*]]) #[[ATTR10]] !dbg [[DBG162:![0-9]+]] {
+// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[C:%.*]]) #[[ATTR10]] !dbg [[DBG164:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -3591,121 +3591,121 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK5-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
// CHECK5-NEXT: store i64 [[C]], ptr [[C_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG163:![0-9]+]]
-// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG163]]
-// CHECK5-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8, !dbg [[DBG163]]
-// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG164:![0-9]+]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8, !dbg [[DBG165:![0-9]+]]
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG166:![0-9]+]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: store ptr [[TMP2]], ptr [[_TMP3]], align 8, !dbg [[DBG165]]
-// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG165]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG165]]
-// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !dbg [[DBG165]]
-// CHECK5-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB28:[0-9]+]], i32 [[TMP4]]), !dbg [[DBG165]]
-// CHECK5-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0, !dbg [[DBG165]]
-// CHECK5-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG165]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG165:![0-9]+]]
+// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG165]]
+// CHECK5-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8, !dbg [[DBG165]]
+// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG166:![0-9]+]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8, !dbg [[DBG167:![0-9]+]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG168:![0-9]+]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: store ptr [[TMP2]], ptr [[_TMP3]], align 8, !dbg [[DBG167]]
+// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG167]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG167]]
+// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !dbg [[DBG167]]
+// CHECK5-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB28:[0-9]+]], i32 [[TMP4]]), !dbg [[DBG167]]
+// CHECK5-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0, !dbg [[DBG167]]
+// CHECK5-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG167]]
// CHECK5: omp_if.then:
-// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG164]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG167:![0-9]+]]
-// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1, !dbg [[DBG167]]
-// CHECK5-NEXT: store i32 [[INC]], ptr [[TMP7]], align 4, !dbg [[DBG167]]
-// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[B_ADDR]], align 4, !dbg [[DBG168:![0-9]+]]
-// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1, !dbg [[DBG168]]
-// CHECK5-NEXT: store i32 [[DEC]], ptr [[B_ADDR]], align 4, !dbg [[DBG168]]
-// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG166]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4, !dbg [[DBG169:![0-9]+]]
-// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1, !dbg [[DBG169]]
-// CHECK5-NEXT: store i32 [[DIV]], ptr [[TMP10]], align 4, !dbg [[DBG169]]
-// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB28]], i32 [[TMP4]]), !dbg [[DBG167]]
-// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG167]]
-// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG167]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG166]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG169:![0-9]+]]
+// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1, !dbg [[DBG169]]
+// CHECK5-NEXT: store i32 [[INC]], ptr [[TMP7]], align 4, !dbg [[DBG169]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[B_ADDR]], align 4, !dbg [[DBG170:![0-9]+]]
+// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1, !dbg [[DBG170]]
+// CHECK5-NEXT: store i32 [[DEC]], ptr [[B_ADDR]], align 4, !dbg [[DBG170]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG168]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4, !dbg [[DBG171:![0-9]+]]
+// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1, !dbg [[DBG171]]
+// CHECK5-NEXT: store i32 [[DIV]], ptr [[TMP10]], align 4, !dbg [[DBG171]]
+// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB28]], i32 [[TMP4]]), !dbg [[DBG169]]
+// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG169]]
+// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG169]]
// CHECK5: omp_if.end:
-// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0, !dbg [[DBG167]]
-// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG170:![0-9]+]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !dbg [[DBG167]]
-// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1, !dbg [[DBG167]]
-// CHECK5-NEXT: store ptr [[B_ADDR]], ptr [[TMP14]], align 8, !dbg [[DBG167]]
-// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2, !dbg [[DBG167]]
-// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG171:![0-9]+]], !nonnull [[META9]], !align [[META127]]
-// CHECK5-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8, !dbg [[DBG167]]
-// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG167]]
-// CHECK5-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB28]], i32 [[TMP4]], i64 24, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.8, i32 [[TMP17]]), !dbg [[DBG167]]
-// CHECK5-NEXT: ret void, !dbg [[DBG172:![0-9]+]]
+// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0, !dbg [[DBG169]]
+// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG172:![0-9]+]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !dbg [[DBG169]]
+// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1, !dbg [[DBG169]]
+// CHECK5-NEXT: store ptr [[B_ADDR]], ptr [[TMP14]], align 8, !dbg [[DBG169]]
+// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2, !dbg [[DBG169]]
+// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG173:![0-9]+]], !nonnull [[META8]], !align [[META129]]
+// CHECK5-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8, !dbg [[DBG169]]
+// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG169]]
+// CHECK5-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB28]], i32 [[TMP4]], i64 24, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.8, i32 [[TMP17]]), !dbg [[DBG169]]
+// CHECK5-NEXT: ret void, !dbg [[DBG174:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.8
-// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8]] !dbg [[DBG173:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8]] !dbg [[DBG175:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
// CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG174:![0-9]+]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG174]]
-// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG174]]
-// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG174]]
-// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG174]]
-// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG174]]
-// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG175:![0-9]+]]
-// CHECK5-NEXT: store i32 [[TMP8]], ptr [[TMP5]], align 4, !dbg [[DBG175]]
-// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG174]]
-// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8, !dbg [[DBG174]]
-// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 1, !dbg [[DBG174]]
-// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !dbg [[DBG174]]
-// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG176:![0-9]+]]
-// CHECK5-NEXT: store i32 [[TMP13]], ptr [[TMP10]], align 4, !dbg [[DBG176]]
-// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 2, !dbg [[DBG174]]
-// CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8, !dbg [[DBG174]]
-// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 2, !dbg [[DBG174]]
-// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8, !dbg [[DBG174]]
-// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4, !dbg [[DBG177:![0-9]+]]
-// CHECK5-NEXT: store i32 [[TMP18]], ptr [[TMP15]], align 4, !dbg [[DBG177]]
-// CHECK5-NEXT: ret void, !dbg [[DBG177]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG176:![0-9]+]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG176]]
+// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG176]]
+// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG176]]
+// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG176]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG176]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG177:![0-9]+]]
+// CHECK5-NEXT: store i32 [[TMP8]], ptr [[TMP5]], align 4, !dbg [[DBG177]]
+// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG176]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8, !dbg [[DBG176]]
+// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 1, !dbg [[DBG176]]
+// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !dbg [[DBG176]]
+// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG178:![0-9]+]]
+// CHECK5-NEXT: store i32 [[TMP13]], ptr [[TMP10]], align 4, !dbg [[DBG178]]
+// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 2, !dbg [[DBG176]]
+// CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8, !dbg [[DBG176]]
+// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 2, !dbg [[DBG176]]
+// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8, !dbg [[DBG176]]
+// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4, !dbg [[DBG179:![0-9]+]]
+// CHECK5-NEXT: store i32 [[TMP18]], ptr [[TMP15]], align 4, !dbg [[DBG179]]
+// CHECK5-NEXT: ret void, !dbg [[DBG179]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_Z15parallel_singlev
-// CHECK5-SAME: () #[[ATTR2]] !dbg [[DBG178:![0-9]+]] {
+// CHECK5-SAME: () #[[ATTR2]] !dbg [[DBG180:![0-9]+]] {
// CHECK5-NEXT: entry:
-// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB35:[0-9]+]], i32 0, ptr @_Z15parallel_singlev.omp_outlined), !dbg [[DBG179:![0-9]+]]
-// CHECK5-NEXT: ret void, !dbg [[DBG180:![0-9]+]]
+// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB35:[0-9]+]], i32 0, ptr @_Z15parallel_singlev.omp_outlined), !dbg [[DBG181:![0-9]+]]
+// CHECK5-NEXT: ret void, !dbg [[DBG182:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_Z15parallel_singlev.omp_outlined
-// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR10]] personality ptr @__gxx_personality_v0 !dbg [[DBG181:![0-9]+]] {
+// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR10]] personality ptr @__gxx_personality_v0 !dbg [[DBG183:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG182:![0-9]+]]
-// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG182]]
-// CHECK5-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB32:[0-9]+]], i32 [[TMP1]]), !dbg [[DBG182]]
-// CHECK5-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0, !dbg [[DBG182]]
-// CHECK5-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG182]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG184:![0-9]+]]
+// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG184]]
+// CHECK5-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB32:[0-9]+]], i32 [[TMP1]]), !dbg [[DBG184]]
+// CHECK5-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0, !dbg [[DBG184]]
+// CHECK5-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG184]]
// CHECK5: omp_if.then:
// CHECK5-NEXT: invoke void @_Z3foov()
-// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG183:![0-9]+]]
+// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG185:![0-9]+]]
// CHECK5: invoke.cont:
-// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB32]], i32 [[TMP1]]), !dbg [[DBG183]]
-// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG183]]
+// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB32]], i32 [[TMP1]]), !dbg [[DBG185]]
+// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG185]]
// CHECK5: omp_if.end:
-// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB33:[0-9]+]], i32 [[TMP1]]), !dbg [[DBG184:![0-9]+]]
-// CHECK5-NEXT: ret void, !dbg [[DBG184]]
+// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB33:[0-9]+]], i32 [[TMP1]]), !dbg [[DBG186:![0-9]+]]
+// CHECK5-NEXT: ret void, !dbg [[DBG186]]
// CHECK5: terminate.lpad:
// CHECK5-NEXT: [[TMP4:%.*]] = landingpad { ptr, i32 }
-// CHECK5-NEXT: catch ptr null, !dbg [[DBG183]]
-// CHECK5-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP4]], 0, !dbg [[DBG183]]
-// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP5]]) #[[ATTR11]], !dbg [[DBG183]]
-// CHECK5-NEXT: unreachable, !dbg [[DBG183]]
+// CHECK5-NEXT: catch ptr null, !dbg [[DBG185]]
+// CHECK5-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP4]], 0, !dbg [[DBG185]]
+// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP5]]) #[[ATTR11]], !dbg [[DBG185]]
+// CHECK5-NEXT: unreachable, !dbg [[DBG185]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_codegen.cpp
-// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG185:![0-9]+]] {
+// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG187:![0-9]+]] {
// CHECK5-NEXT: entry:
-// CHECK5-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG186:![0-9]+]]
-// CHECK5-NEXT: call void @__cxx_global_var_init.4(), !dbg [[DBG186]]
-// CHECK5-NEXT: call void @.__omp_threadprivate_init_.(), !dbg [[DBG186]]
-// CHECK5-NEXT: call void @.__omp_threadprivate_init_..3(), !dbg [[DBG186]]
+// CHECK5-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG188:![0-9]+]]
+// CHECK5-NEXT: call void @__cxx_global_var_init.4(), !dbg [[DBG188]]
+// CHECK5-NEXT: call void @.__omp_threadprivate_init_.(), !dbg [[DBG188]]
+// CHECK5-NEXT: call void @.__omp_threadprivate_init_..3(), !dbg [[DBG188]]
// CHECK5-NEXT: ret void
//
//
diff --git a/clang/test/OpenMP/target_parallel_debug_codegen.cpp b/clang/test/OpenMP/target_parallel_debug_codegen.cpp
index 78793222ed7a1..ebf60329a44ec 100644
--- a/clang/test/OpenMP/target_parallel_debug_codegen.cpp
+++ b/clang/test/OpenMP/target_parallel_debug_codegen.cpp
@@ -195,60 +195,60 @@ int main() {
// CHECK1-NEXT: store ptr [[TMP6]], ptr [[_TMP2]], align 8, !dbg [[DBG87]]
// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG87]], !nonnull [[META37]]
// CHECK1-NEXT: #dbg_declare(ptr [[B3]], [[META88:![0-9]+]], !DIExpression(), [[META77]])
-// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B3]], ptr align 4 [[TMP4]], i64 400, i1 false), !dbg [[DBG87]]
-// CHECK1-NEXT: #dbg_declare(ptr [[F]], [[META89:![0-9]+]], !DIExpression(), [[META92:![0-9]+]])
-// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG93:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG93]]
-// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX4]], i64 0, i64 1, !dbg [[DBG93]]
-// CHECK1-NEXT: store ptr [[ARRAYIDX5]], ptr [[F]], align 8, !dbg [[META92]]
-// CHECK1-NEXT: #dbg_declare(ptr [[G]], [[META94:![0-9]+]], !DIExpression(), [[META95:![0-9]+]])
-// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[META95]]
-// CHECK1-NEXT: #dbg_declare(ptr [[H]], [[META96:![0-9]+]], !DIExpression(), [[META97:![0-9]+]])
-// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], i64 0, i64 1, !dbg [[DBG98:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], i64 0, i64 1, !dbg [[DBG98]]
-// CHECK1-NEXT: store ptr [[ARRAYIDX7]], ptr [[H]], align 8, !dbg [[META97]]
-// CHECK1-NEXT: #dbg_declare(ptr [[D]], [[META99:![0-9]+]], !DIExpression(), [[META100:![0-9]+]])
-// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[META100]]
-// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG101:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], i64 0, i64 0, !dbg [[DBG102:![0-9]+]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG103:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i64, !dbg [[DBG102]]
-// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], i64 0, i64 [[IDXPROM]], !dbg [[DBG102]]
-// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX9]], align 4, !dbg [[DBG104:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG105:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX10]], i64 0, i64 0, !dbg [[DBG105]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG106:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP9]] to i64, !dbg [[DBG105]]
-// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM12]], !dbg [[DBG105]]
-// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX13]], align 4, !dbg [[DBG107:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG108:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX14]], i64 0, i64 0, !dbg [[DBG108]]
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG109:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP10]] to i64, !dbg [[DBG108]]
-// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX15]], i64 0, i64 [[IDXPROM16]], !dbg [[DBG108]]
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX17]], align 4, !dbg [[DBG108]]
-// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], i64 0, i64 0, !dbg [[DBG110:![0-9]+]]
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG111:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP12]] to i64, !dbg [[DBG110]]
-// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG110]]
-// CHECK1-NEXT: store i32 [[TMP11]], ptr [[ARRAYIDX20]], align 4, !dbg [[DBG112:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], i64 0, i64 0, !dbg [[DBG113:![0-9]+]]
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG114:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG113]]
-// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG113]]
-// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX23]], align 4, !dbg [[DBG113]]
-// CHECK1-NEXT: [[TMP15:%.*]] = load i8, ptr [[TMP7]], align 1, !dbg [[DBG115:![0-9]+]]
-// CHECK1-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP15]], 0, !dbg [[DBG115]]
-// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[LOADEDV]] to i32, !dbg [[DBG115]]
-// CHECK1-NEXT: [[OR:%.*]] = or i32 [[CONV]], [[TMP14]], !dbg [[DBG115]]
-// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[OR]], 0, !dbg [[DBG115]]
-// CHECK1-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG115]]
-// CHECK1-NEXT: store i8 [[STOREDV]], ptr [[TMP7]], align 1, !dbg [[DBG115]]
-// CHECK1-NEXT: ret void, !dbg [[DBG116:![0-9]+]]
+// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B3]], ptr align 4 [[TMP4]], i64 400, i1 false), !dbg [[DBG89:![0-9]+]]
+// CHECK1-NEXT: #dbg_declare(ptr [[F]], [[META92:![0-9]+]], !DIExpression(), [[META95:![0-9]+]])
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG96:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG96]]
+// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX4]], i64 0, i64 1, !dbg [[DBG96]]
+// CHECK1-NEXT: store ptr [[ARRAYIDX5]], ptr [[F]], align 8, !dbg [[META95]]
+// CHECK1-NEXT: #dbg_declare(ptr [[G]], [[META97:![0-9]+]], !DIExpression(), [[META98:![0-9]+]])
+// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[META98]]
+// CHECK1-NEXT: #dbg_declare(ptr [[H]], [[META99:![0-9]+]], !DIExpression(), [[META100:![0-9]+]])
+// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], i64 0, i64 1, !dbg [[DBG101:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], i64 0, i64 1, !dbg [[DBG101]]
+// CHECK1-NEXT: store ptr [[ARRAYIDX7]], ptr [[H]], align 8, !dbg [[META100]]
+// CHECK1-NEXT: #dbg_declare(ptr [[D]], [[META102:![0-9]+]], !DIExpression(), [[META103:![0-9]+]])
+// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[META103]]
+// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG104:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], i64 0, i64 0, !dbg [[DBG105:![0-9]+]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG106:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i64, !dbg [[DBG105]]
+// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], i64 0, i64 [[IDXPROM]], !dbg [[DBG105]]
+// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX9]], align 4, !dbg [[DBG107:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG108:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX10]], i64 0, i64 0, !dbg [[DBG108]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG109:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP9]] to i64, !dbg [[DBG108]]
+// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM12]], !dbg [[DBG108]]
+// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX13]], align 4, !dbg [[DBG110:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG111:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX14]], i64 0, i64 0, !dbg [[DBG111]]
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG112:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP10]] to i64, !dbg [[DBG111]]
+// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX15]], i64 0, i64 [[IDXPROM16]], !dbg [[DBG111]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX17]], align 4, !dbg [[DBG111]]
+// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], i64 0, i64 0, !dbg [[DBG113:![0-9]+]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG114:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP12]] to i64, !dbg [[DBG113]]
+// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG113]]
+// CHECK1-NEXT: store i32 [[TMP11]], ptr [[ARRAYIDX20]], align 4, !dbg [[DBG115:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], i64 0, i64 0, !dbg [[DBG116:![0-9]+]]
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG117:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG116]]
+// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG116]]
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX23]], align 4, !dbg [[DBG116]]
+// CHECK1-NEXT: [[TMP15:%.*]] = load i8, ptr [[TMP7]], align 1, !dbg [[DBG118:![0-9]+]]
+// CHECK1-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP15]], 0, !dbg [[DBG118]]
+// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[LOADEDV]] to i32, !dbg [[DBG118]]
+// CHECK1-NEXT: [[OR:%.*]] = or i32 [[CONV]], [[TMP14]], !dbg [[DBG118]]
+// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[OR]], 0, !dbg [[DBG118]]
+// CHECK1-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG118]]
+// CHECK1-NEXT: store i8 [[STOREDV]], ptr [[TMP7]], align 1, !dbg [[DBG118]]
+// CHECK1-NEXT: ret void, !dbg [[DBG119:![0-9]+]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_debug___omp_outlined
-// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG117:![0-9]+]] {
+// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG120:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -257,34 +257,34 @@ int main() {
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META120:![0-9]+]], !DIExpression(), [[META121:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META123:![0-9]+]], !DIExpression(), [[META124:![0-9]+]])
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META122:![0-9]+]], !DIExpression(), [[META121]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META125:![0-9]+]], !DIExpression(), [[META124]])
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META123:![0-9]+]], !DIExpression(), [[META121]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META126:![0-9]+]], !DIExpression(), [[META124]])
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META124:![0-9]+]], !DIExpression(), [[META121]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META127:![0-9]+]], !DIExpression(), [[META124]])
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META125:![0-9]+]], !DIExpression(), [[META121]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META128:![0-9]+]], !DIExpression(), [[META124]])
// CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META126:![0-9]+]], !DIExpression(), [[META121]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG127:![0-9]+]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG127]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG127]], !nonnull [[META37]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG127]]
-// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG127]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG127]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG127]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG127]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG127]]
-// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG127]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG127]]
-// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr [[TMP7]], ptr addrspace(1) [[TMP10]]) #[[ATTR3]], !dbg [[DBG127]]
-// CHECK1-NEXT: ret void, !dbg [[DBG127]]
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META129:![0-9]+]], !DIExpression(), [[META124]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG130:![0-9]+]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG130]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG130]], !nonnull [[META37]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG130]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG130]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG130]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG130]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG130]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG130]]
+// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG130]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG130]]
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr [[TMP7]], ptr addrspace(1) [[TMP10]]) #[[ATTR3]], !dbg [[DBG130]]
+// CHECK1-NEXT: ret void, !dbg [[DBG130]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug__
-// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] !dbg [[DBG128:![0-9]+]] {
+// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] !dbg [[DBG131:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr addrspace(1), align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
@@ -297,53 +297,53 @@ int main() {
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8
// CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META133:![0-9]+]], !DIExpression(), [[META134:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META136:![0-9]+]], !DIExpression(), [[META137:![0-9]+]])
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META135:![0-9]+]], !DIExpression(), [[META136:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META138:![0-9]+]], !DIExpression(), [[META139:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META137:![0-9]+]], !DIExpression(), [[META138:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META140:![0-9]+]], !DIExpression(), [[META141:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META139:![0-9]+]], !DIExpression(), [[META140:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META142:![0-9]+]], !DIExpression(), [[META143:![0-9]+]])
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META141:![0-9]+]], !DIExpression(), [[META142:![0-9]+]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG143:![0-9]+]]
-// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG143]]
-// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG143]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG143]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG143]]
-// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG143]]
-// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG143]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG143]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG143]]
-// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG143]]
-// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG143]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG143]], !nonnull [[META37]]
-// CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_kernel_environment, ptr [[DYN_PTR]]), !dbg [[DBG143]]
-// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP9]], -1, !dbg [[DBG143]]
-// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG143]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META144:![0-9]+]], !DIExpression(), [[META145:![0-9]+]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG146:![0-9]+]]
+// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG146]]
+// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG146]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG146]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG146]]
+// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG146]]
+// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG146]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG146]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG146]]
+// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG146]]
+// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG146]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG146]], !nonnull [[META37]]
+// CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_kernel_environment, ptr [[DYN_PTR]]), !dbg [[DBG146]]
+// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP9]], -1, !dbg [[DBG146]]
+// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG146]]
// CHECK1: user_code.entry:
-// CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7:[0-9]+]]), !dbg [[DBG144:![0-9]+]]
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG146:![0-9]+]]
-// CHECK1-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4, !dbg [[DBG146]]
-// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG146]]
-// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG146]]
-// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP13]], align 8, !dbg [[DBG146]]
-// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG146]]
-// CHECK1-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP12]] to ptr, !dbg [[DBG146]]
-// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8, !dbg [[DBG146]]
-// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG146]]
-// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 8, !dbg [[DBG146]]
-// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG146]]
-// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP17]], align 8, !dbg [[DBG146]]
-// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB7]], i32 [[TMP10]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0), !dbg [[DBG146]]
-// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG147:![0-9]+]]
-// CHECK1-NEXT: ret void, !dbg [[DBG148:![0-9]+]]
+// CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7:[0-9]+]]), !dbg [[DBG147:![0-9]+]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG149:![0-9]+]]
+// CHECK1-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4, !dbg [[DBG149]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG149]]
+// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG149]]
+// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP13]], align 8, !dbg [[DBG149]]
+// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG149]]
+// CHECK1-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP12]] to ptr, !dbg [[DBG149]]
+// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8, !dbg [[DBG149]]
+// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG149]]
+// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 8, !dbg [[DBG149]]
+// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG149]]
+// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP17]], align 8, !dbg [[DBG149]]
+// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB7]], i32 [[TMP10]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0), !dbg [[DBG149]]
+// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG150:![0-9]+]]
+// CHECK1-NEXT: ret void, !dbg [[DBG151:![0-9]+]]
// CHECK1: worker.exit:
-// CHECK1-NEXT: ret void, !dbg [[DBG143]]
+// CHECK1-NEXT: ret void, !dbg [[DBG146]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37
-// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] !dbg [[DBG149:![0-9]+]] {
+// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] !dbg [[DBG152:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
@@ -351,32 +351,32 @@ int main() {
// CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META150:![0-9]+]], !DIExpression(), [[META151:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META153:![0-9]+]], !DIExpression(), [[META154:![0-9]+]])
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META152:![0-9]+]], !DIExpression(), [[META151]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META155:![0-9]+]], !DIExpression(), [[META154]])
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META153:![0-9]+]], !DIExpression(), [[META151]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META156:![0-9]+]], !DIExpression(), [[META154]])
// CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META154:![0-9]+]], !DIExpression(), [[META151]])
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META157:![0-9]+]], !DIExpression(), [[META154]])
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META155:![0-9]+]], !DIExpression(), [[META151]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG156:![0-9]+]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG156]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG156]], !nonnull [[META37]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG156]]
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG156]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG156]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG156]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8, !dbg [[DBG156]]
-// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP3]] to ptr addrspace(1), !dbg [[DBG156]]
-// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG156]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG156]]
-// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug__(ptr addrspace(1) [[TMP8]], i32 [[TMP4]], ptr addrspace(1) [[TMP9]], ptr addrspace(1) [[TMP10]], ptr [[TMP7]]) #[[ATTR3]], !dbg [[DBG156]]
-// CHECK1-NEXT: ret void, !dbg [[DBG156]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META158:![0-9]+]], !DIExpression(), [[META154]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG159:![0-9]+]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG159]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG159]], !nonnull [[META37]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG159]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG159]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG159]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG159]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8, !dbg [[DBG159]]
+// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP3]] to ptr addrspace(1), !dbg [[DBG159]]
+// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG159]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG159]]
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug__(ptr addrspace(1) [[TMP8]], i32 [[TMP4]], ptr addrspace(1) [[TMP9]], ptr addrspace(1) [[TMP10]], ptr [[TMP7]]) #[[ATTR3]], !dbg [[DBG159]]
+// CHECK1-NEXT: ret void, !dbg [[DBG159]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug___omp_outlined_debug__
-// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG157:![0-9]+]] {
+// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG160:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -392,74 +392,74 @@ int main() {
// CHECK1-NEXT: [[H:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[D:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META160:![0-9]+]], !DIExpression(), [[META161:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META163:![0-9]+]], !DIExpression(), [[META164:![0-9]+]])
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META162:![0-9]+]], !DIExpression(), [[META161]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META165:![0-9]+]], !DIExpression(), [[META164]])
// CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META163:![0-9]+]], !DIExpression(), [[META164:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META166:![0-9]+]], !DIExpression(), [[META167:![0-9]+]])
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META165:![0-9]+]], !DIExpression(), [[META166:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META168:![0-9]+]], !DIExpression(), [[META169:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META167:![0-9]+]], !DIExpression(), [[META168:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META170:![0-9]+]], !DIExpression(), [[META171:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META169:![0-9]+]], !DIExpression(), [[META170:![0-9]+]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG171:![0-9]+]]
-// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG171]]
-// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG171]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG171]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG171]]
-// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG171]]
-// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG171]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG171]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG171]]
-// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG171]]
-// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG171]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG171]], !nonnull [[META37]]
-// CHECK1-NEXT: #dbg_declare(ptr [[F]], [[META172:![0-9]+]], !DIExpression(), [[META174:![0-9]+]])
-// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG175:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG175]]
-// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX3]], i64 0, i64 1, !dbg [[DBG175]]
-// CHECK1-NEXT: store ptr [[ARRAYIDX4]], ptr [[F]], align 8, !dbg [[META174]]
-// CHECK1-NEXT: #dbg_declare(ptr [[G]], [[META176:![0-9]+]], !DIExpression(), [[META177:![0-9]+]])
-// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[META177]]
-// CHECK1-NEXT: #dbg_declare(ptr [[H]], [[META178:![0-9]+]], !DIExpression(), [[META179:![0-9]+]])
-// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 1, !dbg [[DBG180:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX5]], i64 0, i64 1, !dbg [[DBG180]]
-// CHECK1-NEXT: store ptr [[ARRAYIDX6]], ptr [[H]], align 8, !dbg [[META179]]
-// CHECK1-NEXT: #dbg_declare(ptr [[D]], [[META181:![0-9]+]], !DIExpression(), [[META182:![0-9]+]])
-// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[META182]]
-// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG183:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG184:![0-9]+]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG185:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64, !dbg [[DBG184]]
-// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 [[IDXPROM]], !dbg [[DBG184]]
-// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX8]], align 4, !dbg [[DBG186:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG187:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX9]], i64 0, i64 0, !dbg [[DBG187]]
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG188:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP10]] to i64, !dbg [[DBG187]]
-// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX10]], i64 0, i64 [[IDXPROM11]], !dbg [[DBG187]]
-// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG189:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG190:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG190]]
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG191:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP11]] to i64, !dbg [[DBG190]]
-// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG190]]
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG190]]
-// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG192:![0-9]+]]
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG193:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM18:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG192]]
-// CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX17]], i64 0, i64 [[IDXPROM18]], !dbg [[DBG192]]
-// CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX19]], align 4, !dbg [[DBG194:![0-9]+]]
-// CHECK1-NEXT: [[TMP14:%.*]] = load i8, ptr [[TMP8]], align 1, !dbg [[DBG195:![0-9]+]]
-// CHECK1-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP14]], 0, !dbg [[DBG195]]
-// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[LOADEDV]] to i32, !dbg [[DBG195]]
-// CHECK1-NEXT: store i32 [[CONV]], ptr [[D]], align 4, !dbg [[DBG196:![0-9]+]]
-// CHECK1-NEXT: ret void, !dbg [[DBG197:![0-9]+]]
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META172:![0-9]+]], !DIExpression(), [[META173:![0-9]+]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG174:![0-9]+]]
+// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG174]]
+// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG174]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG174]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG174]]
+// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG174]]
+// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG174]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG174]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG174]]
+// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG174]]
+// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG174]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG174]], !nonnull [[META37]]
+// CHECK1-NEXT: #dbg_declare(ptr [[F]], [[META175:![0-9]+]], !DIExpression(), [[META177:![0-9]+]])
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG178:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG178]]
+// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX3]], i64 0, i64 1, !dbg [[DBG178]]
+// CHECK1-NEXT: store ptr [[ARRAYIDX4]], ptr [[F]], align 8, !dbg [[META177]]
+// CHECK1-NEXT: #dbg_declare(ptr [[G]], [[META179:![0-9]+]], !DIExpression(), [[META180:![0-9]+]])
+// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[META180]]
+// CHECK1-NEXT: #dbg_declare(ptr [[H]], [[META181:![0-9]+]], !DIExpression(), [[META182:![0-9]+]])
+// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 1, !dbg [[DBG183:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX5]], i64 0, i64 1, !dbg [[DBG183]]
+// CHECK1-NEXT: store ptr [[ARRAYIDX6]], ptr [[H]], align 8, !dbg [[META182]]
+// CHECK1-NEXT: #dbg_declare(ptr [[D]], [[META184:![0-9]+]], !DIExpression(), [[META185:![0-9]+]])
+// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[META185]]
+// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG186:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG187:![0-9]+]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG188:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64, !dbg [[DBG187]]
+// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 [[IDXPROM]], !dbg [[DBG187]]
+// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX8]], align 4, !dbg [[DBG189:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG190:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX9]], i64 0, i64 0, !dbg [[DBG190]]
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG191:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP10]] to i64, !dbg [[DBG190]]
+// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX10]], i64 0, i64 [[IDXPROM11]], !dbg [[DBG190]]
+// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG192:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG193:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG193]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG194:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP11]] to i64, !dbg [[DBG193]]
+// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG193]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG193]]
+// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG195:![0-9]+]]
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG196:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM18:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG195]]
+// CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX17]], i64 0, i64 [[IDXPROM18]], !dbg [[DBG195]]
+// CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX19]], align 4, !dbg [[DBG197:![0-9]+]]
+// CHECK1-NEXT: [[TMP14:%.*]] = load i8, ptr [[TMP8]], align 1, !dbg [[DBG198:![0-9]+]]
+// CHECK1-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP14]], 0, !dbg [[DBG198]]
+// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[LOADEDV]] to i32, !dbg [[DBG198]]
+// CHECK1-NEXT: store i32 [[CONV]], ptr [[D]], align 4, !dbg [[DBG199:![0-9]+]]
+// CHECK1-NEXT: ret void, !dbg [[DBG200:![0-9]+]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug___omp_outlined
-// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG198:![0-9]+]] {
+// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG201:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -468,35 +468,35 @@ int main() {
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META199:![0-9]+]], !DIExpression(), [[META200:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META202:![0-9]+]], !DIExpression(), [[META203:![0-9]+]])
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META201:![0-9]+]], !DIExpression(), [[META200]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META204:![0-9]+]], !DIExpression(), [[META203]])
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META202:![0-9]+]], !DIExpression(), [[META200]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META205:![0-9]+]], !DIExpression(), [[META203]])
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META203:![0-9]+]], !DIExpression(), [[META200]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META206:![0-9]+]], !DIExpression(), [[META203]])
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META204:![0-9]+]], !DIExpression(), [[META200]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META207:![0-9]+]], !DIExpression(), [[META203]])
// CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META205:![0-9]+]], !DIExpression(), [[META200]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG206:![0-9]+]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG206]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG206]], !nonnull [[META37]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG206]]
-// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG206]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG206]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG206]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG206]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG206]]
-// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG206]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG206]]
-// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG206]]
-// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]]) #[[ATTR3]], !dbg [[DBG206]]
-// CHECK1-NEXT: ret void, !dbg [[DBG206]]
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META208:![0-9]+]], !DIExpression(), [[META203]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG209:![0-9]+]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG209]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG209]], !nonnull [[META37]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG209]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG209]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG209]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG209]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG209]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG209]]
+// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG209]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG209]]
+// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG209]]
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]]) #[[ATTR3]], !dbg [[DBG209]]
+// CHECK1-NEXT: ret void, !dbg [[DBG209]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug__
-// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] !dbg [[DBG207:![0-9]+]] {
+// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] !dbg [[DBG210:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr addrspace(1), align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr addrspace(1), align 8
@@ -509,53 +509,53 @@ int main() {
// CHECK1-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8
// CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META212:![0-9]+]], !DIExpression(), [[META213:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META215:![0-9]+]], !DIExpression(), [[META216:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META214:![0-9]+]], !DIExpression(), [[META215:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META217:![0-9]+]], !DIExpression(), [[META218:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META216:![0-9]+]], !DIExpression(), [[META217:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META219:![0-9]+]], !DIExpression(), [[META220:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META218:![0-9]+]], !DIExpression(), [[META219:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META221:![0-9]+]], !DIExpression(), [[META222:![0-9]+]])
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META220:![0-9]+]], !DIExpression(), [[META221:![0-9]+]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG222:![0-9]+]]
-// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG222]]
-// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG222]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG222]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG222]]
-// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG222]]
-// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG222]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG222]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG222]]
-// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG222]]
-// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG222]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG222]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG222]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG222]]
-// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG222]]
-// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG222]], !nonnull [[META37]]
-// CHECK1-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_kernel_environment, ptr [[DYN_PTR]]), !dbg [[DBG222]]
-// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP12]], -1, !dbg [[DBG222]]
-// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG222]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META223:![0-9]+]], !DIExpression(), [[META224:![0-9]+]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG225:![0-9]+]]
+// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG225]]
+// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG225]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG225]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG225]]
+// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG225]]
+// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG225]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG225]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG225]]
+// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG225]]
+// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG225]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG225]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG225]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG225]]
+// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG225]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG225]], !nonnull [[META37]]
+// CHECK1-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_kernel_environment, ptr [[DYN_PTR]]), !dbg [[DBG225]]
+// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP12]], -1, !dbg [[DBG225]]
+// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG225]]
// CHECK1: user_code.entry:
-// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB11:[0-9]+]]), !dbg [[DBG223:![0-9]+]]
-// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG225:![0-9]+]]
-// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP14]], align 8, !dbg [[DBG225]]
-// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG225]]
-// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP15]], align 8, !dbg [[DBG225]]
-// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG225]]
-// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP16]], align 8, !dbg [[DBG225]]
-// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG225]]
-// CHECK1-NEXT: store ptr [[TMP11]], ptr [[TMP17]], align 8, !dbg [[DBG225]]
-// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB11]], i32 [[TMP13]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0), !dbg [[DBG225]]
-// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG226:![0-9]+]]
-// CHECK1-NEXT: ret void, !dbg [[DBG227:![0-9]+]]
+// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB11:[0-9]+]]), !dbg [[DBG226:![0-9]+]]
+// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG228:![0-9]+]]
+// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP14]], align 8, !dbg [[DBG228]]
+// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG228]]
+// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP15]], align 8, !dbg [[DBG228]]
+// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG228]]
+// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP16]], align 8, !dbg [[DBG228]]
+// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG228]]
+// CHECK1-NEXT: store ptr [[TMP11]], ptr [[TMP17]], align 8, !dbg [[DBG228]]
+// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB11]], i32 [[TMP13]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0), !dbg [[DBG228]]
+// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG229:![0-9]+]]
+// CHECK1-NEXT: ret void, !dbg [[DBG230:![0-9]+]]
// CHECK1: worker.exit:
-// CHECK1-NEXT: ret void, !dbg [[DBG222]]
+// CHECK1-NEXT: ret void, !dbg [[DBG225]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51
-// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] !dbg [[DBG228:![0-9]+]] {
+// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] !dbg [[DBG231:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
@@ -563,34 +563,34 @@ int main() {
// CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META231:![0-9]+]], !DIExpression(), [[META232:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META234:![0-9]+]], !DIExpression(), [[META235:![0-9]+]])
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META233:![0-9]+]], !DIExpression(), [[META232]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META236:![0-9]+]], !DIExpression(), [[META235]])
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META234:![0-9]+]], !DIExpression(), [[META232]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META237:![0-9]+]], !DIExpression(), [[META235]])
// CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META235:![0-9]+]], !DIExpression(), [[META232]])
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META238:![0-9]+]], !DIExpression(), [[META235]])
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META236:![0-9]+]], !DIExpression(), [[META232]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG237:![0-9]+]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG237]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG237]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG237]], !nonnull [[META37]]
-// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG237]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG237]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG237]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG237]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8, !dbg [[DBG237]]
-// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP4]] to ptr addrspace(1), !dbg [[DBG237]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG237]]
-// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG237]]
-// CHECK1-NEXT: [[TMP12:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG237]]
-// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug__(ptr addrspace(1) [[TMP9]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]], ptr addrspace(1) [[TMP12]], ptr [[TMP8]]) #[[ATTR3]], !dbg [[DBG237]]
-// CHECK1-NEXT: ret void, !dbg [[DBG237]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META239:![0-9]+]], !DIExpression(), [[META235]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG240:![0-9]+]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG240]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG240]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG240]], !nonnull [[META37]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG240]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG240]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG240]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG240]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8, !dbg [[DBG240]]
+// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP4]] to ptr addrspace(1), !dbg [[DBG240]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG240]]
+// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG240]]
+// CHECK1-NEXT: [[TMP12:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG240]]
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug__(ptr addrspace(1) [[TMP9]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]], ptr addrspace(1) [[TMP12]], ptr [[TMP8]]) #[[ATTR3]], !dbg [[DBG240]]
+// CHECK1-NEXT: ret void, !dbg [[DBG240]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug___omp_outlined_debug__
-// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG238:![0-9]+]] {
+// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG241:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -607,82 +607,82 @@ int main() {
// CHECK1-NEXT: [[H:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[D:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META241:![0-9]+]], !DIExpression(), [[META242:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META244:![0-9]+]], !DIExpression(), [[META245:![0-9]+]])
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META243:![0-9]+]], !DIExpression(), [[META242]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META246:![0-9]+]], !DIExpression(), [[META245]])
// CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META244:![0-9]+]], !DIExpression(), [[META245:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META247:![0-9]+]], !DIExpression(), [[META248:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META246:![0-9]+]], !DIExpression(), [[META247:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META249:![0-9]+]], !DIExpression(), [[META250:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META248:![0-9]+]], !DIExpression(), [[META249:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META251:![0-9]+]], !DIExpression(), [[META252:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META250:![0-9]+]], !DIExpression(), [[META251:![0-9]+]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG252:![0-9]+]]
-// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG252]]
-// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG252]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG252]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG252]]
-// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG252]]
-// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG252]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG252]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG252]]
-// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG252]]
-// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG252]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG252]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG252]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG252]]
-// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG252]]
-// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG252]], !nonnull [[META37]]
-// CHECK1-NEXT: #dbg_declare(ptr [[F]], [[META253:![0-9]+]], !DIExpression(), [[META255:![0-9]+]])
-// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG256:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG256]]
-// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX4]], i64 0, i64 1, !dbg [[DBG256]]
-// CHECK1-NEXT: store ptr [[ARRAYIDX5]], ptr [[F]], align 8, !dbg [[META255]]
-// CHECK1-NEXT: #dbg_declare(ptr [[G]], [[META257:![0-9]+]], !DIExpression(), [[META258:![0-9]+]])
-// CHECK1-NEXT: store ptr [[TMP5]], ptr [[G]], align 8, !dbg [[META258]]
-// CHECK1-NEXT: #dbg_declare(ptr [[H]], [[META259:![0-9]+]], !DIExpression(), [[META260:![0-9]+]])
-// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 1, !dbg [[DBG261:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], i64 0, i64 1, !dbg [[DBG261]]
-// CHECK1-NEXT: store ptr [[ARRAYIDX7]], ptr [[H]], align 8, !dbg [[META260]]
-// CHECK1-NEXT: #dbg_declare(ptr [[D]], [[META262:![0-9]+]], !DIExpression(), [[META263:![0-9]+]])
-// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[META263]]
-// CHECK1-NEXT: store i32 5, ptr [[TMP5]], align 4, !dbg [[DBG264:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG265:![0-9]+]]
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG266:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64, !dbg [[DBG265]]
-// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], i64 0, i64 [[IDXPROM]], !dbg [[DBG265]]
-// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX9]], align 4, !dbg [[DBG267:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG268:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX10]], i64 0, i64 0, !dbg [[DBG268]]
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG269:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG268]]
-// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM12]], !dbg [[DBG268]]
-// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX13]], align 4, !dbg [[DBG270:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG271:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX14]], i64 0, i64 0, !dbg [[DBG271]]
-// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG272:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP14]] to i64, !dbg [[DBG271]]
-// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX15]], i64 0, i64 [[IDXPROM16]], !dbg [[DBG271]]
-// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX17]], align 4, !dbg [[DBG271]]
-// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG273:![0-9]+]]
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG274:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG273]]
-// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG273]]
-// CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX20]], align 4, !dbg [[DBG275:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG276:![0-9]+]]
-// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG277:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP17]] to i64, !dbg [[DBG276]]
-// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG276]]
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX23]], align 4, !dbg [[DBG276]]
-// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP18]], 0, !dbg [[DBG276]]
-// CHECK1-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG278:![0-9]+]]
-// CHECK1-NEXT: store i8 [[STOREDV]], ptr [[TMP11]], align 1, !dbg [[DBG278]]
-// CHECK1-NEXT: ret void, !dbg [[DBG279:![0-9]+]]
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META253:![0-9]+]], !DIExpression(), [[META254:![0-9]+]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG255:![0-9]+]]
+// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG255]]
+// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG255]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG255]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG255]]
+// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG255]]
+// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG255]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG255]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG255]]
+// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG255]]
+// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG255]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG255]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG255]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG255]]
+// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG255]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG255]], !nonnull [[META37]]
+// CHECK1-NEXT: #dbg_declare(ptr [[F]], [[META256:![0-9]+]], !DIExpression(), [[META258:![0-9]+]])
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG259:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG259]]
+// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX4]], i64 0, i64 1, !dbg [[DBG259]]
+// CHECK1-NEXT: store ptr [[ARRAYIDX5]], ptr [[F]], align 8, !dbg [[META258]]
+// CHECK1-NEXT: #dbg_declare(ptr [[G]], [[META260:![0-9]+]], !DIExpression(), [[META261:![0-9]+]])
+// CHECK1-NEXT: store ptr [[TMP5]], ptr [[G]], align 8, !dbg [[META261]]
+// CHECK1-NEXT: #dbg_declare(ptr [[H]], [[META262:![0-9]+]], !DIExpression(), [[META263:![0-9]+]])
+// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 1, !dbg [[DBG264:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], i64 0, i64 1, !dbg [[DBG264]]
+// CHECK1-NEXT: store ptr [[ARRAYIDX7]], ptr [[H]], align 8, !dbg [[META263]]
+// CHECK1-NEXT: #dbg_declare(ptr [[D]], [[META265:![0-9]+]], !DIExpression(), [[META266:![0-9]+]])
+// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[META266]]
+// CHECK1-NEXT: store i32 5, ptr [[TMP5]], align 4, !dbg [[DBG267:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG268:![0-9]+]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG269:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64, !dbg [[DBG268]]
+// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], i64 0, i64 [[IDXPROM]], !dbg [[DBG268]]
+// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX9]], align 4, !dbg [[DBG270:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG271:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX10]], i64 0, i64 0, !dbg [[DBG271]]
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG272:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG271]]
+// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM12]], !dbg [[DBG271]]
+// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX13]], align 4, !dbg [[DBG273:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG274:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX14]], i64 0, i64 0, !dbg [[DBG274]]
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG275:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP14]] to i64, !dbg [[DBG274]]
+// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX15]], i64 0, i64 [[IDXPROM16]], !dbg [[DBG274]]
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX17]], align 4, !dbg [[DBG274]]
+// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG276:![0-9]+]]
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG277:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG276]]
+// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG276]]
+// CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX20]], align 4, !dbg [[DBG278:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG279:![0-9]+]]
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG280:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP17]] to i64, !dbg [[DBG279]]
+// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX23]], align 4, !dbg [[DBG279]]
+// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP18]], 0, !dbg [[DBG279]]
+// CHECK1-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG281:![0-9]+]]
+// CHECK1-NEXT: store i8 [[STOREDV]], ptr [[TMP11]], align 1, !dbg [[DBG281]]
+// CHECK1-NEXT: ret void, !dbg [[DBG282:![0-9]+]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug___omp_outlined
-// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG280:![0-9]+]] {
+// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG283:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -691,31 +691,31 @@ int main() {
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META283:![0-9]+]], !DIExpression(), [[META284:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META286:![0-9]+]], !DIExpression(), [[META287:![0-9]+]])
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META285:![0-9]+]], !DIExpression(), [[META284]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META288:![0-9]+]], !DIExpression(), [[META287]])
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META286:![0-9]+]], !DIExpression(), [[META284]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META289:![0-9]+]], !DIExpression(), [[META287]])
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META287:![0-9]+]], !DIExpression(), [[META284]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META290:![0-9]+]], !DIExpression(), [[META287]])
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META288:![0-9]+]], !DIExpression(), [[META284]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META291:![0-9]+]], !DIExpression(), [[META287]])
// CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META289:![0-9]+]], !DIExpression(), [[META284]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG290:![0-9]+]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG290]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG290]], !nonnull [[META37]], !align [[META49]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG290]], !nonnull [[META37]]
-// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG290]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG290]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG290]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG290]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG290]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG290]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG290]]
-// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG290]]
-// CHECK1-NEXT: [[TMP12:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG290]]
-// CHECK1-NEXT: [[TMP13:%.*]] = addrspacecast ptr [[TMP9]] to ptr addrspace(1), !dbg [[DBG290]]
-// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug___omp_outlined_debug__(ptr [[TMP4]], ptr [[TMP5]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]], ptr addrspace(1) [[TMP12]], ptr addrspace(1) [[TMP13]]) #[[ATTR3]], !dbg [[DBG290]]
-// CHECK1-NEXT: ret void, !dbg [[DBG290]]
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META292:![0-9]+]], !DIExpression(), [[META287]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG293:![0-9]+]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG293]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG293]], !nonnull [[META37]], !align [[META49]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG293]], !nonnull [[META37]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG293]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG293]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG293]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG293]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG293]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG293]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG293]]
+// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG293]]
+// CHECK1-NEXT: [[TMP12:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG293]]
+// CHECK1-NEXT: [[TMP13:%.*]] = addrspacecast ptr [[TMP9]] to ptr addrspace(1), !dbg [[DBG293]]
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug___omp_outlined_debug__(ptr [[TMP4]], ptr [[TMP5]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]], ptr addrspace(1) [[TMP12]], ptr addrspace(1) [[TMP13]]) #[[ATTR3]], !dbg [[DBG293]]
+// CHECK1-NEXT: ret void, !dbg [[DBG293]]
//
diff --git a/clang/test/OpenMP/target_parallel_for_debug_codegen.cpp b/clang/test/OpenMP/target_parallel_for_debug_codegen.cpp
index dafb37bec13e4..4a5b278e8ccab 100644
--- a/clang/test/OpenMP/target_parallel_for_debug_codegen.cpp
+++ b/clang/test/OpenMP/target_parallel_for_debug_codegen.cpp
@@ -213,11 +213,11 @@ int main() {
// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_IS_LAST]], [[META89:![0-9]+]], !DIExpression(), [[META73]])
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG86]]
// CHECK1-NEXT: #dbg_declare(ptr [[B4]], [[META90:![0-9]+]], !DIExpression(), [[META73]])
-// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B4]], ptr align 4 [[TMP4]], i64 400, i1 false), !dbg [[DBG83]]
-// CHECK1-NEXT: #dbg_declare(ptr [[I]], [[META91:![0-9]+]], !DIExpression(), [[META73]])
+// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B4]], ptr align 4 [[TMP4]], i64 400, i1 false), !dbg [[DBG91:![0-9]+]]
+// CHECK1-NEXT: #dbg_declare(ptr [[I]], [[META94:![0-9]+]], !DIExpression(), [[META73]])
// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG83]]
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4, !dbg [[DBG83]]
-// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG92:![0-9]+]]
+// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG95:![0-9]+]]
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG83]]
// CHECK1: omp.dispatch.cond:
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG86]]
@@ -246,67 +246,67 @@ int main() {
// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG83]]
// CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG86]]
-// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1, !dbg [[DBG93:![0-9]+]]
-// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG93]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG93]]
-// CHECK1-NEXT: #dbg_declare(ptr [[F]], [[META94:![0-9]+]], !DIExpression(), [[META97:![0-9]+]])
-// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG98:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG98]]
-// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 1, !dbg [[DBG98]]
-// CHECK1-NEXT: store ptr [[ARRAYIDX8]], ptr [[F]], align 8, !dbg [[META97]]
-// CHECK1-NEXT: #dbg_declare(ptr [[G]], [[META99:![0-9]+]], !DIExpression(), [[META100:![0-9]+]])
-// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[META100]]
-// CHECK1-NEXT: #dbg_declare(ptr [[H]], [[META101:![0-9]+]], !DIExpression(), [[META102:![0-9]+]])
-// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 1, !dbg [[DBG103:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX9]], i64 0, i64 1, !dbg [[DBG103]]
-// CHECK1-NEXT: store ptr [[ARRAYIDX10]], ptr [[H]], align 8, !dbg [[META102]]
-// CHECK1-NEXT: #dbg_declare(ptr [[D]], [[META104:![0-9]+]], !DIExpression(), [[META105:![0-9]+]])
-// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[META105]]
-// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG106:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG107:![0-9]+]]
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG108:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64, !dbg [[DBG107]]
-// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM]], !dbg [[DBG107]]
-// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG109:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG110:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG110]]
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG111:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG110]]
-// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG110]]
-// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG112:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG113:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX17]], i64 0, i64 0, !dbg [[DBG113]]
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG114:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG113]]
-// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG113]]
-// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4, !dbg [[DBG113]]
-// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG115:![0-9]+]]
-// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG116:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG115]]
-// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG115]]
-// CHECK1-NEXT: store i32 [[TMP21]], ptr [[ARRAYIDX23]], align 4, !dbg [[DBG117:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG118:![0-9]+]]
-// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG119:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG118]]
-// CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX24]], i64 0, i64 [[IDXPROM25]], !dbg [[DBG118]]
-// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[ARRAYIDX26]], align 4, !dbg [[DBG118]]
-// CHECK1-NEXT: [[TMP25:%.*]] = load i8, ptr [[TMP7]], align 1, !dbg [[DBG120:![0-9]+]]
-// CHECK1-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP25]], 0, !dbg [[DBG120]]
-// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[LOADEDV]] to i32, !dbg [[DBG120]]
-// CHECK1-NEXT: [[OR:%.*]] = or i32 [[CONV]], [[TMP24]], !dbg [[DBG120]]
-// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[OR]], 0, !dbg [[DBG120]]
-// CHECK1-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG120]]
-// CHECK1-NEXT: store i8 [[STOREDV]], ptr [[TMP7]], align 1, !dbg [[DBG120]]
-// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG121:![0-9]+]]
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1, !dbg [[DBG96:![0-9]+]]
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG96]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG96]]
+// CHECK1-NEXT: #dbg_declare(ptr [[F]], [[META97:![0-9]+]], !DIExpression(), [[META100:![0-9]+]])
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG101:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG101]]
+// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 1, !dbg [[DBG101]]
+// CHECK1-NEXT: store ptr [[ARRAYIDX8]], ptr [[F]], align 8, !dbg [[META100]]
+// CHECK1-NEXT: #dbg_declare(ptr [[G]], [[META102:![0-9]+]], !DIExpression(), [[META103:![0-9]+]])
+// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[META103]]
+// CHECK1-NEXT: #dbg_declare(ptr [[H]], [[META104:![0-9]+]], !DIExpression(), [[META105:![0-9]+]])
+// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 1, !dbg [[DBG106:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX9]], i64 0, i64 1, !dbg [[DBG106]]
+// CHECK1-NEXT: store ptr [[ARRAYIDX10]], ptr [[H]], align 8, !dbg [[META105]]
+// CHECK1-NEXT: #dbg_declare(ptr [[D]], [[META107:![0-9]+]], !DIExpression(), [[META108:![0-9]+]])
+// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[META108]]
+// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG109:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG110:![0-9]+]]
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG111:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64, !dbg [[DBG110]]
+// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM]], !dbg [[DBG110]]
+// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG112:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG113:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG113]]
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG114:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG113]]
+// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG113]]
+// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG115:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG116:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX17]], i64 0, i64 0, !dbg [[DBG116]]
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG117:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG116]]
+// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG116]]
+// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4, !dbg [[DBG116]]
+// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG118:![0-9]+]]
+// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG119:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG118]]
+// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG118]]
+// CHECK1-NEXT: store i32 [[TMP21]], ptr [[ARRAYIDX23]], align 4, !dbg [[DBG120:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG121:![0-9]+]]
+// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG122:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG121]]
+// CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX24]], i64 0, i64 [[IDXPROM25]], !dbg [[DBG121]]
+// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[ARRAYIDX26]], align 4, !dbg [[DBG121]]
+// CHECK1-NEXT: [[TMP25:%.*]] = load i8, ptr [[TMP7]], align 1, !dbg [[DBG123:![0-9]+]]
+// CHECK1-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP25]], 0, !dbg [[DBG123]]
+// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[LOADEDV]] to i32, !dbg [[DBG123]]
+// CHECK1-NEXT: [[OR:%.*]] = or i32 [[CONV]], [[TMP24]], !dbg [[DBG123]]
+// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[OR]], 0, !dbg [[DBG123]]
+// CHECK1-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG123]]
+// CHECK1-NEXT: store i8 [[STOREDV]], ptr [[TMP7]], align 1, !dbg [[DBG123]]
+// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG124:![0-9]+]]
// CHECK1: omp.body.continue:
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG92]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG95]]
// CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG86]]
// CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP26]], 1, !dbg [[DBG83]]
// CHECK1-NEXT: store i32 [[ADD27]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG83]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG92]], !llvm.loop [[LOOP122:![0-9]+]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG95]], !llvm.loop [[LOOP125:![0-9]+]]
// CHECK1: omp.inner.for.end:
-// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG92]]
+// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG95]]
// CHECK1: omp.dispatch.inc:
// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG86]]
// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG86]]
@@ -316,14 +316,14 @@ int main() {
// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG86]]
// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP29]], [[TMP30]], !dbg [[DBG83]]
// CHECK1-NEXT: store i32 [[ADD29]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG83]]
-// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG92]], !llvm.loop [[LOOP124:![0-9]+]]
+// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG95]], !llvm.loop [[LOOP127:![0-9]+]]
// CHECK1: omp.dispatch.end:
-// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB5:[0-9]+]], i32 [[TMP9]]), !dbg [[DBG123:![0-9]+]]
-// CHECK1-NEXT: ret void, !dbg [[DBG125:![0-9]+]]
+// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB5:[0-9]+]], i32 [[TMP9]]), !dbg [[DBG126:![0-9]+]]
+// CHECK1-NEXT: ret void, !dbg [[DBG128:![0-9]+]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug___omp_outlined
-// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG126:![0-9]+]] {
+// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG129:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -332,34 +332,34 @@ int main() {
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META129:![0-9]+]], !DIExpression(), [[META130:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META132:![0-9]+]], !DIExpression(), [[META133:![0-9]+]])
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META131:![0-9]+]], !DIExpression(), [[META130]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META134:![0-9]+]], !DIExpression(), [[META133]])
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META132:![0-9]+]], !DIExpression(), [[META130]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META135:![0-9]+]], !DIExpression(), [[META133]])
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META133:![0-9]+]], !DIExpression(), [[META130]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META136:![0-9]+]], !DIExpression(), [[META133]])
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META134:![0-9]+]], !DIExpression(), [[META130]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META137:![0-9]+]], !DIExpression(), [[META133]])
// CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META135:![0-9]+]], !DIExpression(), [[META130]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG136:![0-9]+]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG136]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG136]], !nonnull [[META29]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG136]]
-// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG136]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG136]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG136]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG136]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG136]]
-// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG136]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG136]]
-// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr [[TMP7]], ptr addrspace(1) [[TMP10]]) #[[ATTR3]], !dbg [[DBG136]]
-// CHECK1-NEXT: ret void, !dbg [[DBG136]]
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META138:![0-9]+]], !DIExpression(), [[META133]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG139:![0-9]+]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG139]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG139]], !nonnull [[META29]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG139]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG139]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG139]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG139]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG139]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG139]]
+// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG139]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG139]]
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr [[TMP7]], ptr addrspace(1) [[TMP10]]) #[[ATTR3]], !dbg [[DBG139]]
+// CHECK1-NEXT: ret void, !dbg [[DBG139]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug__
-// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] !dbg [[DBG137:![0-9]+]] {
+// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] !dbg [[DBG140:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr addrspace(1), align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
@@ -372,53 +372,53 @@ int main() {
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8
// CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META142:![0-9]+]], !DIExpression(), [[META143:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META145:![0-9]+]], !DIExpression(), [[META146:![0-9]+]])
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META144:![0-9]+]], !DIExpression(), [[META145:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META147:![0-9]+]], !DIExpression(), [[META148:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META146:![0-9]+]], !DIExpression(), [[META147:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META149:![0-9]+]], !DIExpression(), [[META150:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META148:![0-9]+]], !DIExpression(), [[META149:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META151:![0-9]+]], !DIExpression(), [[META152:![0-9]+]])
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META150:![0-9]+]], !DIExpression(), [[META151:![0-9]+]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG152:![0-9]+]]
-// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG152]]
-// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG152]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG152]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG152]]
-// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG152]]
-// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG152]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG152]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG152]]
-// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG152]]
-// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG152]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG152]], !nonnull [[META29]]
-// CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_kernel_environment, ptr [[DYN_PTR]]), !dbg [[DBG152]]
-// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP9]], -1, !dbg [[DBG152]]
-// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG152]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META153:![0-9]+]], !DIExpression(), [[META154:![0-9]+]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG155:![0-9]+]]
+// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG155]]
+// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG155]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG155]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG155]]
+// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG155]]
+// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG155]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG155]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG155]]
+// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG155]]
+// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG155]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG155]], !nonnull [[META29]]
+// CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_kernel_environment, ptr [[DYN_PTR]]), !dbg [[DBG155]]
+// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP9]], -1, !dbg [[DBG155]]
+// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG155]]
// CHECK1: user_code.entry:
-// CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB13:[0-9]+]]), !dbg [[DBG153:![0-9]+]]
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG155:![0-9]+]]
-// CHECK1-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4, !dbg [[DBG155]]
-// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG155]]
-// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG155]]
-// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP13]], align 8, !dbg [[DBG155]]
-// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG155]]
-// CHECK1-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP12]] to ptr, !dbg [[DBG155]]
-// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8, !dbg [[DBG155]]
-// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG155]]
-// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 8, !dbg [[DBG155]]
-// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG155]]
-// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP17]], align 8, !dbg [[DBG155]]
-// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB13]], i32 [[TMP10]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0), !dbg [[DBG155]]
-// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG156:![0-9]+]]
-// CHECK1-NEXT: ret void, !dbg [[DBG157:![0-9]+]]
+// CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB13:[0-9]+]]), !dbg [[DBG156:![0-9]+]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG158:![0-9]+]]
+// CHECK1-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4, !dbg [[DBG158]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG158]]
+// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG158]]
+// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP13]], align 8, !dbg [[DBG158]]
+// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG158]]
+// CHECK1-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP12]] to ptr, !dbg [[DBG158]]
+// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8, !dbg [[DBG158]]
+// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG158]]
+// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 8, !dbg [[DBG158]]
+// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG158]]
+// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP17]], align 8, !dbg [[DBG158]]
+// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB13]], i32 [[TMP10]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0), !dbg [[DBG158]]
+// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG159:![0-9]+]]
+// CHECK1-NEXT: ret void, !dbg [[DBG160:![0-9]+]]
// CHECK1: worker.exit:
-// CHECK1-NEXT: ret void, !dbg [[DBG152]]
+// CHECK1-NEXT: ret void, !dbg [[DBG155]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27
-// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] !dbg [[DBG158:![0-9]+]] {
+// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] !dbg [[DBG161:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
@@ -426,32 +426,32 @@ int main() {
// CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META161:![0-9]+]], !DIExpression(), [[META162:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META164:![0-9]+]], !DIExpression(), [[META165:![0-9]+]])
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META163:![0-9]+]], !DIExpression(), [[META162]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META166:![0-9]+]], !DIExpression(), [[META165]])
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META164:![0-9]+]], !DIExpression(), [[META162]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META167:![0-9]+]], !DIExpression(), [[META165]])
// CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META165:![0-9]+]], !DIExpression(), [[META162]])
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META168:![0-9]+]], !DIExpression(), [[META165]])
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META166:![0-9]+]], !DIExpression(), [[META162]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG167:![0-9]+]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG167]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG167]], !nonnull [[META29]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG167]]
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG167]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG167]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG167]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8, !dbg [[DBG167]]
-// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP3]] to ptr addrspace(1), !dbg [[DBG167]]
-// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG167]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG167]]
-// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug__(ptr addrspace(1) [[TMP8]], i32 [[TMP4]], ptr addrspace(1) [[TMP9]], ptr addrspace(1) [[TMP10]], ptr [[TMP7]]) #[[ATTR3]], !dbg [[DBG167]]
-// CHECK1-NEXT: ret void, !dbg [[DBG167]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META169:![0-9]+]], !DIExpression(), [[META165]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG170:![0-9]+]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG170]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG170]], !nonnull [[META29]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG170]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG170]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG170]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG170]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8, !dbg [[DBG170]]
+// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP3]] to ptr addrspace(1), !dbg [[DBG170]]
+// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG170]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG170]]
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug__(ptr addrspace(1) [[TMP8]], i32 [[TMP4]], ptr addrspace(1) [[TMP9]], ptr addrspace(1) [[TMP10]], ptr [[TMP7]]) #[[ATTR3]], !dbg [[DBG170]]
+// CHECK1-NEXT: ret void, !dbg [[DBG170]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined_debug__
-// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG168:![0-9]+]] {
+// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG171:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -474,140 +474,140 @@ int main() {
// CHECK1-NEXT: [[H:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[D:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META171:![0-9]+]], !DIExpression(), [[META172:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META174:![0-9]+]], !DIExpression(), [[META175:![0-9]+]])
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META173:![0-9]+]], !DIExpression(), [[META172]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META176:![0-9]+]], !DIExpression(), [[META175]])
// CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META174:![0-9]+]], !DIExpression(), [[META175:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META177:![0-9]+]], !DIExpression(), [[META178:![0-9]+]])
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META176:![0-9]+]], !DIExpression(), [[META177:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META179:![0-9]+]], !DIExpression(), [[META180:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META178:![0-9]+]], !DIExpression(), [[META179:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META181:![0-9]+]], !DIExpression(), [[META182:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META180:![0-9]+]], !DIExpression(), [[META181:![0-9]+]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG182:![0-9]+]]
-// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG182]]
-// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG182]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG182]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG182]]
-// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG182]]
-// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG182]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG182]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG182]]
-// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG182]]
-// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG182]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG182]], !nonnull [[META29]]
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_IV]], [[META183:![0-9]+]], !DIExpression(), [[META172]])
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_LB]], [[META184:![0-9]+]], !DIExpression(), [[META172]])
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG185:![0-9]+]]
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_UB]], [[META186:![0-9]+]], !DIExpression(), [[META172]])
-// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_STRIDE]], [[META187:![0-9]+]], !DIExpression(), [[META172]])
-// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_IS_LAST]], [[META188:![0-9]+]], !DIExpression(), [[META172]])
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: #dbg_declare(ptr [[I]], [[META189:![0-9]+]], !DIExpression(), [[META172]])
-// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG182]]
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4, !dbg [[DBG182]]
-// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB10:[0-9]+]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG190:![0-9]+]]
-// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG182]]
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META183:![0-9]+]], !DIExpression(), [[META184:![0-9]+]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG185:![0-9]+]]
+// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG185]]
+// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG185]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG185]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG185]]
+// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG185]]
+// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG185]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG185]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG185]]
+// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG185]]
+// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG185]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG185]], !nonnull [[META29]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_IV]], [[META186:![0-9]+]], !DIExpression(), [[META175]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_LB]], [[META187:![0-9]+]], !DIExpression(), [[META175]])
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG188:![0-9]+]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_UB]], [[META189:![0-9]+]], !DIExpression(), [[META175]])
+// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_STRIDE]], [[META190:![0-9]+]], !DIExpression(), [[META175]])
+// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_IS_LAST]], [[META191:![0-9]+]], !DIExpression(), [[META175]])
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: #dbg_declare(ptr [[I]], [[META192:![0-9]+]], !DIExpression(), [[META175]])
+// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG185]]
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4, !dbg [[DBG185]]
+// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB10:[0-9]+]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG193:![0-9]+]]
+// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG185]]
// CHECK1: omp.dispatch.cond:
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9, !dbg [[DBG185]]
-// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG185]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9, !dbg [[DBG188]]
+// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG188]]
// CHECK1: cond.true:
-// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG185]]
+// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG188]]
// CHECK1: cond.false:
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: br label [[COND_END]], !dbg [[DBG185]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: br label [[COND_END]], !dbg [[DBG188]]
// CHECK1: cond.end:
-// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ], !dbg [[DBG185]]
-// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]], !dbg [[DBG182]]
-// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG182]]
+// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ], !dbg [[DBG188]]
+// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]], !dbg [[DBG185]]
+// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG185]]
// CHECK1: omp.dispatch.body:
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG182]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG185]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]], !dbg [[DBG182]]
-// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG182]]
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]], !dbg [[DBG185]]
+// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG185]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1, !dbg [[DBG191:![0-9]+]]
-// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG191]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG191]]
-// CHECK1-NEXT: #dbg_declare(ptr [[F]], [[META192:![0-9]+]], !DIExpression(), [[META194:![0-9]+]])
-// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG195:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG195]]
-// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], i64 0, i64 1, !dbg [[DBG195]]
-// CHECK1-NEXT: store ptr [[ARRAYIDX7]], ptr [[F]], align 8, !dbg [[META194]]
-// CHECK1-NEXT: #dbg_declare(ptr [[G]], [[META196:![0-9]+]], !DIExpression(), [[META197:![0-9]+]])
-// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[META197]]
-// CHECK1-NEXT: #dbg_declare(ptr [[H]], [[META198:![0-9]+]], !DIExpression(), [[META199:![0-9]+]])
-// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 1, !dbg [[DBG200:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], i64 0, i64 1, !dbg [[DBG200]]
-// CHECK1-NEXT: store ptr [[ARRAYIDX9]], ptr [[H]], align 8, !dbg [[META199]]
-// CHECK1-NEXT: #dbg_declare(ptr [[D]], [[META201:![0-9]+]], !DIExpression(), [[META202:![0-9]+]])
-// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[META202]]
-// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG203:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG204:![0-9]+]]
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG205:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG204]]
-// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX10]], i64 0, i64 [[IDXPROM]], !dbg [[DBG204]]
-// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX11]], align 4, !dbg [[DBG206:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG207:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX12]], i64 0, i64 0, !dbg [[DBG207]]
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG208:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG207]]
-// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX13]], i64 0, i64 [[IDXPROM14]], !dbg [[DBG207]]
-// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX15]], align 4, !dbg [[DBG209:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG210:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX16]], i64 0, i64 0, !dbg [[DBG210]]
-// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG211:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM18:%.*]] = sext i32 [[TMP21]] to i64, !dbg [[DBG210]]
-// CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX17]], i64 0, i64 [[IDXPROM18]], !dbg [[DBG210]]
-// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[ARRAYIDX19]], align 4, !dbg [[DBG210]]
-// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG212:![0-9]+]]
-// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG213:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM21:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG212]]
-// CHECK1-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX20]], i64 0, i64 [[IDXPROM21]], !dbg [[DBG212]]
-// CHECK1-NEXT: store i32 [[TMP22]], ptr [[ARRAYIDX22]], align 4, !dbg [[DBG214:![0-9]+]]
-// CHECK1-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP8]], align 1, !dbg [[DBG215:![0-9]+]]
-// CHECK1-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP24]], 0, !dbg [[DBG215]]
-// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[LOADEDV]] to i32, !dbg [[DBG215]]
-// CHECK1-NEXT: store i32 [[CONV]], ptr [[D]], align 4, !dbg [[DBG216:![0-9]+]]
-// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG217:![0-9]+]]
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1, !dbg [[DBG194:![0-9]+]]
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG194]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG194]]
+// CHECK1-NEXT: #dbg_declare(ptr [[F]], [[META195:![0-9]+]], !DIExpression(), [[META197:![0-9]+]])
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG198:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG198]]
+// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], i64 0, i64 1, !dbg [[DBG198]]
+// CHECK1-NEXT: store ptr [[ARRAYIDX7]], ptr [[F]], align 8, !dbg [[META197]]
+// CHECK1-NEXT: #dbg_declare(ptr [[G]], [[META199:![0-9]+]], !DIExpression(), [[META200:![0-9]+]])
+// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[META200]]
+// CHECK1-NEXT: #dbg_declare(ptr [[H]], [[META201:![0-9]+]], !DIExpression(), [[META202:![0-9]+]])
+// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 1, !dbg [[DBG203:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], i64 0, i64 1, !dbg [[DBG203]]
+// CHECK1-NEXT: store ptr [[ARRAYIDX9]], ptr [[H]], align 8, !dbg [[META202]]
+// CHECK1-NEXT: #dbg_declare(ptr [[D]], [[META204:![0-9]+]], !DIExpression(), [[META205:![0-9]+]])
+// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[META205]]
+// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG206:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG207:![0-9]+]]
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG208:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG207]]
+// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX10]], i64 0, i64 [[IDXPROM]], !dbg [[DBG207]]
+// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX11]], align 4, !dbg [[DBG209:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG210:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX12]], i64 0, i64 0, !dbg [[DBG210]]
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG211:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG210]]
+// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX13]], i64 0, i64 [[IDXPROM14]], !dbg [[DBG210]]
+// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX15]], align 4, !dbg [[DBG212:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG213:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX16]], i64 0, i64 0, !dbg [[DBG213]]
+// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG214:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM18:%.*]] = sext i32 [[TMP21]] to i64, !dbg [[DBG213]]
+// CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX17]], i64 0, i64 [[IDXPROM18]], !dbg [[DBG213]]
+// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[ARRAYIDX19]], align 4, !dbg [[DBG213]]
+// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG215:![0-9]+]]
+// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG216:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM21:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG215]]
+// CHECK1-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX20]], i64 0, i64 [[IDXPROM21]], !dbg [[DBG215]]
+// CHECK1-NEXT: store i32 [[TMP22]], ptr [[ARRAYIDX22]], align 4, !dbg [[DBG217:![0-9]+]]
+// CHECK1-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP8]], align 1, !dbg [[DBG218:![0-9]+]]
+// CHECK1-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP24]], 0, !dbg [[DBG218]]
+// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[LOADEDV]] to i32, !dbg [[DBG218]]
+// CHECK1-NEXT: store i32 [[CONV]], ptr [[D]], align 4, !dbg [[DBG219:![0-9]+]]
+// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG220:![0-9]+]]
// CHECK1: omp.body.continue:
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG190]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG193]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP25]], 1, !dbg [[DBG182]]
-// CHECK1-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG182]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG190]], !llvm.loop [[LOOP218:![0-9]+]]
+// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP25]], 1, !dbg [[DBG185]]
+// CHECK1-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG185]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG193]], !llvm.loop [[LOOP221:![0-9]+]]
// CHECK1: omp.inner.for.end:
-// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG190]]
+// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG193]]
// CHECK1: omp.dispatch.inc:
-// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP26]], [[TMP27]], !dbg [[DBG182]]
-// CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG182]]
-// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]], !dbg [[DBG182]]
-// CHECK1-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG182]]
-// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG190]], !llvm.loop [[LOOP220:![0-9]+]]
+// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP26]], [[TMP27]], !dbg [[DBG185]]
+// CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG185]]
+// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]], !dbg [[DBG185]]
+// CHECK1-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG185]]
+// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG193]], !llvm.loop [[LOOP223:![0-9]+]]
// CHECK1: omp.dispatch.end:
-// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB12:[0-9]+]], i32 [[TMP10]]), !dbg [[DBG219:![0-9]+]]
-// CHECK1-NEXT: ret void, !dbg [[DBG221:![0-9]+]]
+// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB12:[0-9]+]], i32 [[TMP10]]), !dbg [[DBG222:![0-9]+]]
+// CHECK1-NEXT: ret void, !dbg [[DBG224:![0-9]+]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined
-// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG222:![0-9]+]] {
+// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG225:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -616,35 +616,35 @@ int main() {
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META223:![0-9]+]], !DIExpression(), [[META224:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META226:![0-9]+]], !DIExpression(), [[META227:![0-9]+]])
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META225:![0-9]+]], !DIExpression(), [[META224]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META228:![0-9]+]], !DIExpression(), [[META227]])
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META226:![0-9]+]], !DIExpression(), [[META224]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META229:![0-9]+]], !DIExpression(), [[META227]])
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META227:![0-9]+]], !DIExpression(), [[META224]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META230:![0-9]+]], !DIExpression(), [[META227]])
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META228:![0-9]+]], !DIExpression(), [[META224]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META231:![0-9]+]], !DIExpression(), [[META227]])
// CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META229:![0-9]+]], !DIExpression(), [[META224]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG230:![0-9]+]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG230]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG230]], !nonnull [[META29]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG230]]
-// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG230]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG230]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG230]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG230]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG230]]
-// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG230]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG230]]
-// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG230]]
-// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]]) #[[ATTR3]], !dbg [[DBG230]]
-// CHECK1-NEXT: ret void, !dbg [[DBG230]]
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META232:![0-9]+]], !DIExpression(), [[META227]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG233:![0-9]+]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG233]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG233]], !nonnull [[META29]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG233]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG233]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG233]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG233]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG233]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG233]]
+// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG233]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG233]]
+// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG233]]
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]]) #[[ATTR3]], !dbg [[DBG233]]
+// CHECK1-NEXT: ret void, !dbg [[DBG233]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug__
-// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] !dbg [[DBG231:![0-9]+]] {
+// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] !dbg [[DBG234:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr addrspace(1), align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr addrspace(1), align 8
@@ -657,53 +657,53 @@ int main() {
// CHECK1-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8
// CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META236:![0-9]+]], !DIExpression(), [[META237:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META239:![0-9]+]], !DIExpression(), [[META240:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META238:![0-9]+]], !DIExpression(), [[META239:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META241:![0-9]+]], !DIExpression(), [[META242:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META240:![0-9]+]], !DIExpression(), [[META241:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META243:![0-9]+]], !DIExpression(), [[META244:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META242:![0-9]+]], !DIExpression(), [[META243:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META245:![0-9]+]], !DIExpression(), [[META246:![0-9]+]])
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META244:![0-9]+]], !DIExpression(), [[META245:![0-9]+]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG246:![0-9]+]]
-// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG246]]
-// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG246]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG246]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG246]]
-// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG246]]
-// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG246]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG246]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG246]]
-// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG246]]
-// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG246]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG246]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG246]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG246]]
-// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG246]]
-// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG246]], !nonnull [[META29]]
-// CHECK1-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_kernel_environment, ptr [[DYN_PTR]]), !dbg [[DBG246]]
-// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP12]], -1, !dbg [[DBG246]]
-// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG246]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META247:![0-9]+]], !DIExpression(), [[META248:![0-9]+]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG249:![0-9]+]]
+// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG249]]
+// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG249]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG249]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG249]]
+// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG249]]
+// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG249]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG249]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG249]]
+// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG249]]
+// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG249]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG249]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG249]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG249]]
+// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG249]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG249]], !nonnull [[META29]]
+// CHECK1-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_kernel_environment, ptr [[DYN_PTR]]), !dbg [[DBG249]]
+// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP12]], -1, !dbg [[DBG249]]
+// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG249]]
// CHECK1: user_code.entry:
-// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB20:[0-9]+]]), !dbg [[DBG247:![0-9]+]]
-// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG249:![0-9]+]]
-// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP14]], align 8, !dbg [[DBG249]]
-// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG249]]
-// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP15]], align 8, !dbg [[DBG249]]
-// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG249]]
-// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP16]], align 8, !dbg [[DBG249]]
-// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG249]]
-// CHECK1-NEXT: store ptr [[TMP11]], ptr [[TMP17]], align 8, !dbg [[DBG249]]
-// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB20]], i32 [[TMP13]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0), !dbg [[DBG249]]
-// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG250:![0-9]+]]
-// CHECK1-NEXT: ret void, !dbg [[DBG251:![0-9]+]]
+// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB20:[0-9]+]]), !dbg [[DBG250:![0-9]+]]
+// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG252:![0-9]+]]
+// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP14]], align 8, !dbg [[DBG252]]
+// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG252]]
+// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP15]], align 8, !dbg [[DBG252]]
+// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG252]]
+// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP16]], align 8, !dbg [[DBG252]]
+// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG252]]
+// CHECK1-NEXT: store ptr [[TMP11]], ptr [[TMP17]], align 8, !dbg [[DBG252]]
+// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB20]], i32 [[TMP13]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0), !dbg [[DBG252]]
+// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG253:![0-9]+]]
+// CHECK1-NEXT: ret void, !dbg [[DBG254:![0-9]+]]
// CHECK1: worker.exit:
-// CHECK1-NEXT: ret void, !dbg [[DBG246]]
+// CHECK1-NEXT: ret void, !dbg [[DBG249]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41
-// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] !dbg [[DBG252:![0-9]+]] {
+// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] !dbg [[DBG255:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
@@ -711,34 +711,34 @@ int main() {
// CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META255:![0-9]+]], !DIExpression(), [[META256:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META258:![0-9]+]], !DIExpression(), [[META259:![0-9]+]])
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META257:![0-9]+]], !DIExpression(), [[META256]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META260:![0-9]+]], !DIExpression(), [[META259]])
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META258:![0-9]+]], !DIExpression(), [[META256]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META261:![0-9]+]], !DIExpression(), [[META259]])
// CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META259:![0-9]+]], !DIExpression(), [[META256]])
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META262:![0-9]+]], !DIExpression(), [[META259]])
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META260:![0-9]+]], !DIExpression(), [[META256]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG261:![0-9]+]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG261]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG261]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG261]], !nonnull [[META29]]
-// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG261]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG261]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG261]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG261]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8, !dbg [[DBG261]]
-// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP4]] to ptr addrspace(1), !dbg [[DBG261]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG261]]
-// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG261]]
-// CHECK1-NEXT: [[TMP12:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG261]]
-// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug__(ptr addrspace(1) [[TMP9]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]], ptr addrspace(1) [[TMP12]], ptr [[TMP8]]) #[[ATTR3]], !dbg [[DBG261]]
-// CHECK1-NEXT: ret void, !dbg [[DBG261]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META263:![0-9]+]], !DIExpression(), [[META259]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG264:![0-9]+]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG264]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG264]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG264]], !nonnull [[META29]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG264]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG264]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG264]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG264]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8, !dbg [[DBG264]]
+// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP4]] to ptr addrspace(1), !dbg [[DBG264]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG264]]
+// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG264]]
+// CHECK1-NEXT: [[TMP12:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG264]]
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug__(ptr addrspace(1) [[TMP9]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]], ptr addrspace(1) [[TMP12]], ptr [[TMP8]]) #[[ATTR3]], !dbg [[DBG264]]
+// CHECK1-NEXT: ret void, !dbg [[DBG264]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined_debug__
-// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG262:![0-9]+]] {
+// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG265:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -762,148 +762,148 @@ int main() {
// CHECK1-NEXT: [[H:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[D:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META265:![0-9]+]], !DIExpression(), [[META266:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META268:![0-9]+]], !DIExpression(), [[META269:![0-9]+]])
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META267:![0-9]+]], !DIExpression(), [[META266]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META270:![0-9]+]], !DIExpression(), [[META269]])
// CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META268:![0-9]+]], !DIExpression(), [[META269:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META271:![0-9]+]], !DIExpression(), [[META272:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META270:![0-9]+]], !DIExpression(), [[META271:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META273:![0-9]+]], !DIExpression(), [[META274:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META272:![0-9]+]], !DIExpression(), [[META273:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META275:![0-9]+]], !DIExpression(), [[META276:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META274:![0-9]+]], !DIExpression(), [[META275:![0-9]+]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG276:![0-9]+]]
-// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG276]]
-// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG276]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG276]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG276]]
-// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG276]]
-// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG276]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG276]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG276]]
-// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG276]]
-// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG276]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG276]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG276]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG276]]
-// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG276]]
-// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG276]], !nonnull [[META29]]
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_IV]], [[META277:![0-9]+]], !DIExpression(), [[META266]])
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_LB]], [[META278:![0-9]+]], !DIExpression(), [[META266]])
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG279:![0-9]+]]
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_UB]], [[META280:![0-9]+]], !DIExpression(), [[META266]])
-// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_STRIDE]], [[META281:![0-9]+]], !DIExpression(), [[META266]])
-// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_IS_LAST]], [[META282:![0-9]+]], !DIExpression(), [[META266]])
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: #dbg_declare(ptr [[I]], [[META283:![0-9]+]], !DIExpression(), [[META266]])
-// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG276]]
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG276]]
-// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB17:[0-9]+]], i32 [[TMP13]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG284:![0-9]+]]
-// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG276]]
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META277:![0-9]+]], !DIExpression(), [[META278:![0-9]+]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG279:![0-9]+]]
+// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG279]]
+// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG279]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG279]]
+// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG279]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG279]]
+// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG279]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG279]]
+// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG279]], !nonnull [[META29]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_IV]], [[META280:![0-9]+]], !DIExpression(), [[META269]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_LB]], [[META281:![0-9]+]], !DIExpression(), [[META269]])
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG282:![0-9]+]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_UB]], [[META283:![0-9]+]], !DIExpression(), [[META269]])
+// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_STRIDE]], [[META284:![0-9]+]], !DIExpression(), [[META269]])
+// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_IS_LAST]], [[META285:![0-9]+]], !DIExpression(), [[META269]])
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: #dbg_declare(ptr [[I]], [[META286:![0-9]+]], !DIExpression(), [[META269]])
+// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG279]]
+// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB17:[0-9]+]], i32 [[TMP13]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG287:![0-9]+]]
+// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG279]]
// CHECK1: omp.dispatch.cond:
-// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP14]], 9, !dbg [[DBG279]]
-// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP14]], 9, !dbg [[DBG282]]
+// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG282]]
// CHECK1: cond.true:
-// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG279]]
+// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG282]]
// CHECK1: cond.false:
-// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: br label [[COND_END]], !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: br label [[COND_END]], !dbg [[DBG282]]
// CHECK1: cond.end:
-// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ], !dbg [[DBG279]]
-// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]], !dbg [[DBG276]]
-// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG276]]
+// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ], !dbg [[DBG282]]
+// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]], !dbg [[DBG279]]
+// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG279]]
// CHECK1: omp.dispatch.body:
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG276]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG279]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]], !dbg [[DBG276]]
-// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG276]]
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]], !dbg [[DBG279]]
+// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG279]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1, !dbg [[DBG285:![0-9]+]]
-// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG285]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG285]]
-// CHECK1-NEXT: #dbg_declare(ptr [[F]], [[META286:![0-9]+]], !DIExpression(), [[META288:![0-9]+]])
-// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG289:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG289]]
-// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 1, !dbg [[DBG289]]
-// CHECK1-NEXT: store ptr [[ARRAYIDX8]], ptr [[F]], align 8, !dbg [[META288]]
-// CHECK1-NEXT: #dbg_declare(ptr [[G]], [[META290:![0-9]+]], !DIExpression(), [[META291:![0-9]+]])
-// CHECK1-NEXT: store ptr [[TMP5]], ptr [[G]], align 8, !dbg [[META291]]
-// CHECK1-NEXT: #dbg_declare(ptr [[H]], [[META292:![0-9]+]], !DIExpression(), [[META293:![0-9]+]])
-// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 1, !dbg [[DBG294:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX9]], i64 0, i64 1, !dbg [[DBG294]]
-// CHECK1-NEXT: store ptr [[ARRAYIDX10]], ptr [[H]], align 8, !dbg [[META293]]
-// CHECK1-NEXT: #dbg_declare(ptr [[D]], [[META295:![0-9]+]], !DIExpression(), [[META296:![0-9]+]])
-// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[META296]]
-// CHECK1-NEXT: store i32 5, ptr [[TMP5]], align 4, !dbg [[DBG297:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG298:![0-9]+]]
-// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG299:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG298]]
-// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM]], !dbg [[DBG298]]
-// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG300:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG301:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG301]]
-// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG302:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG301]]
-// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG301]]
-// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG303:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG304:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX17]], i64 0, i64 0, !dbg [[DBG304]]
-// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG305:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP24]] to i64, !dbg [[DBG304]]
-// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG304]]
-// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4, !dbg [[DBG304]]
-// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG306:![0-9]+]]
-// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG307:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP26]] to i64, !dbg [[DBG306]]
-// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG306]]
-// CHECK1-NEXT: store i32 [[TMP25]], ptr [[ARRAYIDX23]], align 4, !dbg [[DBG308:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX24:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG309:![0-9]+]]
-// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG310:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP27]] to i64, !dbg [[DBG309]]
-// CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX24]], i64 0, i64 [[IDXPROM25]], !dbg [[DBG309]]
-// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARRAYIDX26]], align 4, !dbg [[DBG309]]
-// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP28]], 0, !dbg [[DBG309]]
-// CHECK1-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG311:![0-9]+]]
-// CHECK1-NEXT: store i8 [[STOREDV]], ptr [[TMP11]], align 1, !dbg [[DBG311]]
-// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG312:![0-9]+]]
+// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1, !dbg [[DBG288:![0-9]+]]
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG288]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG288]]
+// CHECK1-NEXT: #dbg_declare(ptr [[F]], [[META289:![0-9]+]], !DIExpression(), [[META291:![0-9]+]])
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG292:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG292]]
+// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 1, !dbg [[DBG292]]
+// CHECK1-NEXT: store ptr [[ARRAYIDX8]], ptr [[F]], align 8, !dbg [[META291]]
+// CHECK1-NEXT: #dbg_declare(ptr [[G]], [[META293:![0-9]+]], !DIExpression(), [[META294:![0-9]+]])
+// CHECK1-NEXT: store ptr [[TMP5]], ptr [[G]], align 8, !dbg [[META294]]
+// CHECK1-NEXT: #dbg_declare(ptr [[H]], [[META295:![0-9]+]], !DIExpression(), [[META296:![0-9]+]])
+// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 1, !dbg [[DBG297:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX9]], i64 0, i64 1, !dbg [[DBG297]]
+// CHECK1-NEXT: store ptr [[ARRAYIDX10]], ptr [[H]], align 8, !dbg [[META296]]
+// CHECK1-NEXT: #dbg_declare(ptr [[D]], [[META298:![0-9]+]], !DIExpression(), [[META299:![0-9]+]])
+// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[META299]]
+// CHECK1-NEXT: store i32 5, ptr [[TMP5]], align 4, !dbg [[DBG300:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG301:![0-9]+]]
+// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG302:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG301]]
+// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM]], !dbg [[DBG301]]
+// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG303:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG304:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG304]]
+// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG305:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG304]]
+// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG304]]
+// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG306:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG307:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX17]], i64 0, i64 0, !dbg [[DBG307]]
+// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG308:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP24]] to i64, !dbg [[DBG307]]
+// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG307]]
+// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4, !dbg [[DBG307]]
+// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG309:![0-9]+]]
+// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG310:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP26]] to i64, !dbg [[DBG309]]
+// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG309]]
+// CHECK1-NEXT: store i32 [[TMP25]], ptr [[ARRAYIDX23]], align 4, !dbg [[DBG311:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX24:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG312:![0-9]+]]
+// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG313:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP27]] to i64, !dbg [[DBG312]]
+// CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX24]], i64 0, i64 [[IDXPROM25]], !dbg [[DBG312]]
+// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARRAYIDX26]], align 4, !dbg [[DBG312]]
+// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP28]], 0, !dbg [[DBG312]]
+// CHECK1-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG314:![0-9]+]]
+// CHECK1-NEXT: store i8 [[STOREDV]], ptr [[TMP11]], align 1, !dbg [[DBG314]]
+// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG315:![0-9]+]]
// CHECK1: omp.body.continue:
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG284]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG287]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP29]], 1, !dbg [[DBG276]]
-// CHECK1-NEXT: store i32 [[ADD27]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG276]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG284]], !llvm.loop [[LOOP313:![0-9]+]]
+// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP29]], 1, !dbg [[DBG279]]
+// CHECK1-NEXT: store i32 [[ADD27]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG279]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG287]], !llvm.loop [[LOOP316:![0-9]+]]
// CHECK1: omp.inner.for.end:
-// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG284]]
+// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG287]]
// CHECK1: omp.dispatch.inc:
-// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]], !dbg [[DBG276]]
-// CHECK1-NEXT: store i32 [[ADD28]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG276]]
-// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP32]], [[TMP33]], !dbg [[DBG276]]
-// CHECK1-NEXT: store i32 [[ADD29]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG276]]
-// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG284]], !llvm.loop [[LOOP315:![0-9]+]]
+// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]], !dbg [[DBG279]]
+// CHECK1-NEXT: store i32 [[ADD28]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP32]], [[TMP33]], !dbg [[DBG279]]
+// CHECK1-NEXT: store i32 [[ADD29]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG279]]
+// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG287]], !llvm.loop [[LOOP318:![0-9]+]]
// CHECK1: omp.dispatch.end:
-// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB19:[0-9]+]], i32 [[TMP13]]), !dbg [[DBG314:![0-9]+]]
-// CHECK1-NEXT: ret void, !dbg [[DBG316:![0-9]+]]
+// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB19:[0-9]+]], i32 [[TMP13]]), !dbg [[DBG317:![0-9]+]]
+// CHECK1-NEXT: ret void, !dbg [[DBG319:![0-9]+]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined
-// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG317:![0-9]+]] {
+// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG320:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -912,31 +912,31 @@ int main() {
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META320:![0-9]+]], !DIExpression(), [[META321:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META323:![0-9]+]], !DIExpression(), [[META324:![0-9]+]])
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META322:![0-9]+]], !DIExpression(), [[META321]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META325:![0-9]+]], !DIExpression(), [[META324]])
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META323:![0-9]+]], !DIExpression(), [[META321]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META326:![0-9]+]], !DIExpression(), [[META324]])
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META324:![0-9]+]], !DIExpression(), [[META321]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META327:![0-9]+]], !DIExpression(), [[META324]])
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META325:![0-9]+]], !DIExpression(), [[META321]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META328:![0-9]+]], !DIExpression(), [[META324]])
// CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META326:![0-9]+]], !DIExpression(), [[META321]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG327:![0-9]+]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG327]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG327]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG327]], !nonnull [[META29]]
-// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG327]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG327]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG327]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG327]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG327]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG327]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG327]]
-// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG327]]
-// CHECK1-NEXT: [[TMP12:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG327]]
-// CHECK1-NEXT: [[TMP13:%.*]] = addrspacecast ptr [[TMP9]] to ptr addrspace(1), !dbg [[DBG327]]
-// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined_debug__(ptr [[TMP4]], ptr [[TMP5]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]], ptr addrspace(1) [[TMP12]], ptr addrspace(1) [[TMP13]]) #[[ATTR3]], !dbg [[DBG327]]
-// CHECK1-NEXT: ret void, !dbg [[DBG327]]
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META329:![0-9]+]], !DIExpression(), [[META324]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG330:![0-9]+]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG330]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG330]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG330]], !nonnull [[META29]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG330]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG330]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG330]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG330]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG330]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG330]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG330]]
+// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG330]]
+// CHECK1-NEXT: [[TMP12:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG330]]
+// CHECK1-NEXT: [[TMP13:%.*]] = addrspacecast ptr [[TMP9]] to ptr addrspace(1), !dbg [[DBG330]]
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined_debug__(ptr [[TMP4]], ptr [[TMP5]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]], ptr addrspace(1) [[TMP12]], ptr addrspace(1) [[TMP13]]) #[[ATTR3]], !dbg [[DBG330]]
+// CHECK1-NEXT: ret void, !dbg [[DBG330]]
//
diff --git a/clang/test/OpenMP/target_parallel_generic_loop_codegen-3.cpp b/clang/test/OpenMP/target_parallel_generic_loop_codegen-3.cpp
index cf5bd7df38a5b..39156f95c2e55 100644
--- a/clang/test/OpenMP/target_parallel_generic_loop_codegen-3.cpp
+++ b/clang/test/OpenMP/target_parallel_generic_loop_codegen-3.cpp
@@ -213,11 +213,11 @@ int main() {
// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_IS_LAST]], [[META89:![0-9]+]], !DIExpression(), [[META73]])
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG86]]
// CHECK1-NEXT: #dbg_declare(ptr [[B4]], [[META90:![0-9]+]], !DIExpression(), [[META73]])
-// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B4]], ptr align 4 [[TMP4]], i64 400, i1 false), !dbg [[DBG83]]
-// CHECK1-NEXT: #dbg_declare(ptr [[I]], [[META91:![0-9]+]], !DIExpression(), [[META73]])
+// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B4]], ptr align 4 [[TMP4]], i64 400, i1 false), !dbg [[DBG91:![0-9]+]]
+// CHECK1-NEXT: #dbg_declare(ptr [[I]], [[META94:![0-9]+]], !DIExpression(), [[META73]])
// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG83]]
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4, !dbg [[DBG83]]
-// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG92:![0-9]+]]
+// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG95:![0-9]+]]
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG83]]
// CHECK1: omp.dispatch.cond:
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG86]]
@@ -246,67 +246,67 @@ int main() {
// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG83]]
// CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG86]]
-// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1, !dbg [[DBG93:![0-9]+]]
-// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG93]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG93]]
-// CHECK1-NEXT: #dbg_declare(ptr [[F]], [[META94:![0-9]+]], !DIExpression(), [[META97:![0-9]+]])
-// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG98:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG98]]
-// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 1, !dbg [[DBG98]]
-// CHECK1-NEXT: store ptr [[ARRAYIDX8]], ptr [[F]], align 8, !dbg [[META97]]
-// CHECK1-NEXT: #dbg_declare(ptr [[G]], [[META99:![0-9]+]], !DIExpression(), [[META100:![0-9]+]])
-// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[META100]]
-// CHECK1-NEXT: #dbg_declare(ptr [[H]], [[META101:![0-9]+]], !DIExpression(), [[META102:![0-9]+]])
-// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 1, !dbg [[DBG103:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX9]], i64 0, i64 1, !dbg [[DBG103]]
-// CHECK1-NEXT: store ptr [[ARRAYIDX10]], ptr [[H]], align 8, !dbg [[META102]]
-// CHECK1-NEXT: #dbg_declare(ptr [[D]], [[META104:![0-9]+]], !DIExpression(), [[META105:![0-9]+]])
-// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[META105]]
-// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG106:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG107:![0-9]+]]
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG108:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64, !dbg [[DBG107]]
-// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM]], !dbg [[DBG107]]
-// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG109:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG110:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG110]]
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG111:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG110]]
-// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG110]]
-// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG112:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG113:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX17]], i64 0, i64 0, !dbg [[DBG113]]
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG114:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG113]]
-// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG113]]
-// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4, !dbg [[DBG113]]
-// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG115:![0-9]+]]
-// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG116:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG115]]
-// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG115]]
-// CHECK1-NEXT: store i32 [[TMP21]], ptr [[ARRAYIDX23]], align 4, !dbg [[DBG117:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG118:![0-9]+]]
-// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG119:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG118]]
-// CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX24]], i64 0, i64 [[IDXPROM25]], !dbg [[DBG118]]
-// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[ARRAYIDX26]], align 4, !dbg [[DBG118]]
-// CHECK1-NEXT: [[TMP25:%.*]] = load i8, ptr [[TMP7]], align 1, !dbg [[DBG120:![0-9]+]]
-// CHECK1-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP25]], 0, !dbg [[DBG120]]
-// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[LOADEDV]] to i32, !dbg [[DBG120]]
-// CHECK1-NEXT: [[OR:%.*]] = or i32 [[CONV]], [[TMP24]], !dbg [[DBG120]]
-// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[OR]], 0, !dbg [[DBG120]]
-// CHECK1-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG120]]
-// CHECK1-NEXT: store i8 [[STOREDV]], ptr [[TMP7]], align 1, !dbg [[DBG120]]
-// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG121:![0-9]+]]
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1, !dbg [[DBG96:![0-9]+]]
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG96]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG96]]
+// CHECK1-NEXT: #dbg_declare(ptr [[F]], [[META97:![0-9]+]], !DIExpression(), [[META100:![0-9]+]])
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG101:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG101]]
+// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 1, !dbg [[DBG101]]
+// CHECK1-NEXT: store ptr [[ARRAYIDX8]], ptr [[F]], align 8, !dbg [[META100]]
+// CHECK1-NEXT: #dbg_declare(ptr [[G]], [[META102:![0-9]+]], !DIExpression(), [[META103:![0-9]+]])
+// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[META103]]
+// CHECK1-NEXT: #dbg_declare(ptr [[H]], [[META104:![0-9]+]], !DIExpression(), [[META105:![0-9]+]])
+// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 1, !dbg [[DBG106:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX9]], i64 0, i64 1, !dbg [[DBG106]]
+// CHECK1-NEXT: store ptr [[ARRAYIDX10]], ptr [[H]], align 8, !dbg [[META105]]
+// CHECK1-NEXT: #dbg_declare(ptr [[D]], [[META107:![0-9]+]], !DIExpression(), [[META108:![0-9]+]])
+// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[META108]]
+// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG109:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG110:![0-9]+]]
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG111:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64, !dbg [[DBG110]]
+// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM]], !dbg [[DBG110]]
+// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG112:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG113:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG113]]
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG114:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG113]]
+// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG113]]
+// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG115:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG116:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX17]], i64 0, i64 0, !dbg [[DBG116]]
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG117:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG116]]
+// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG116]]
+// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4, !dbg [[DBG116]]
+// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG118:![0-9]+]]
+// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG119:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG118]]
+// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG118]]
+// CHECK1-NEXT: store i32 [[TMP21]], ptr [[ARRAYIDX23]], align 4, !dbg [[DBG120:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG121:![0-9]+]]
+// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG122:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG121]]
+// CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX24]], i64 0, i64 [[IDXPROM25]], !dbg [[DBG121]]
+// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[ARRAYIDX26]], align 4, !dbg [[DBG121]]
+// CHECK1-NEXT: [[TMP25:%.*]] = load i8, ptr [[TMP7]], align 1, !dbg [[DBG123:![0-9]+]]
+// CHECK1-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP25]], 0, !dbg [[DBG123]]
+// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[LOADEDV]] to i32, !dbg [[DBG123]]
+// CHECK1-NEXT: [[OR:%.*]] = or i32 [[CONV]], [[TMP24]], !dbg [[DBG123]]
+// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[OR]], 0, !dbg [[DBG123]]
+// CHECK1-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG123]]
+// CHECK1-NEXT: store i8 [[STOREDV]], ptr [[TMP7]], align 1, !dbg [[DBG123]]
+// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG124:![0-9]+]]
// CHECK1: omp.body.continue:
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG92]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG95]]
// CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG86]]
// CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP26]], 1, !dbg [[DBG83]]
// CHECK1-NEXT: store i32 [[ADD27]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG83]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG92]], !llvm.loop [[LOOP122:![0-9]+]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG95]], !llvm.loop [[LOOP125:![0-9]+]]
// CHECK1: omp.inner.for.end:
-// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG92]]
+// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG95]]
// CHECK1: omp.dispatch.inc:
// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG86]]
// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG86]]
@@ -316,14 +316,14 @@ int main() {
// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG86]]
// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP29]], [[TMP30]], !dbg [[DBG83]]
// CHECK1-NEXT: store i32 [[ADD29]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG83]]
-// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG92]], !llvm.loop [[LOOP124:![0-9]+]]
+// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG95]], !llvm.loop [[LOOP127:![0-9]+]]
// CHECK1: omp.dispatch.end:
-// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB5:[0-9]+]], i32 [[TMP9]]), !dbg [[DBG123:![0-9]+]]
-// CHECK1-NEXT: ret void, !dbg [[DBG125:![0-9]+]]
+// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB5:[0-9]+]], i32 [[TMP9]]), !dbg [[DBG126:![0-9]+]]
+// CHECK1-NEXT: ret void, !dbg [[DBG128:![0-9]+]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug___omp_outlined
-// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG126:![0-9]+]] {
+// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG129:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -332,34 +332,34 @@ int main() {
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META129:![0-9]+]], !DIExpression(), [[META130:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META132:![0-9]+]], !DIExpression(), [[META133:![0-9]+]])
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META131:![0-9]+]], !DIExpression(), [[META130]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META134:![0-9]+]], !DIExpression(), [[META133]])
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META132:![0-9]+]], !DIExpression(), [[META130]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META135:![0-9]+]], !DIExpression(), [[META133]])
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META133:![0-9]+]], !DIExpression(), [[META130]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META136:![0-9]+]], !DIExpression(), [[META133]])
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META134:![0-9]+]], !DIExpression(), [[META130]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META137:![0-9]+]], !DIExpression(), [[META133]])
// CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META135:![0-9]+]], !DIExpression(), [[META130]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG136:![0-9]+]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG136]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG136]], !nonnull [[META29]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG136]]
-// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG136]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG136]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG136]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG136]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG136]]
-// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG136]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG136]]
-// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr [[TMP7]], ptr addrspace(1) [[TMP10]]) #[[ATTR3]], !dbg [[DBG136]]
-// CHECK1-NEXT: ret void, !dbg [[DBG136]]
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META138:![0-9]+]], !DIExpression(), [[META133]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG139:![0-9]+]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG139]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG139]], !nonnull [[META29]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG139]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG139]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG139]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG139]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG139]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG139]]
+// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG139]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG139]]
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr [[TMP7]], ptr addrspace(1) [[TMP10]]) #[[ATTR3]], !dbg [[DBG139]]
+// CHECK1-NEXT: ret void, !dbg [[DBG139]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug__
-// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] !dbg [[DBG137:![0-9]+]] {
+// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] !dbg [[DBG140:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr addrspace(1), align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
@@ -372,53 +372,53 @@ int main() {
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8
// CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META142:![0-9]+]], !DIExpression(), [[META143:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META145:![0-9]+]], !DIExpression(), [[META146:![0-9]+]])
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META144:![0-9]+]], !DIExpression(), [[META145:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META147:![0-9]+]], !DIExpression(), [[META148:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META146:![0-9]+]], !DIExpression(), [[META147:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META149:![0-9]+]], !DIExpression(), [[META150:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META148:![0-9]+]], !DIExpression(), [[META149:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META151:![0-9]+]], !DIExpression(), [[META152:![0-9]+]])
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META150:![0-9]+]], !DIExpression(), [[META151:![0-9]+]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG152:![0-9]+]]
-// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG152]]
-// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG152]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG152]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG152]]
-// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG152]]
-// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG152]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG152]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG152]]
-// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG152]]
-// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG152]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG152]], !nonnull [[META29]]
-// CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_kernel_environment, ptr [[DYN_PTR]]), !dbg [[DBG152]]
-// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP9]], -1, !dbg [[DBG152]]
-// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG152]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META153:![0-9]+]], !DIExpression(), [[META154:![0-9]+]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG155:![0-9]+]]
+// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG155]]
+// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG155]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG155]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG155]]
+// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG155]]
+// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG155]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG155]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG155]]
+// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG155]]
+// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG155]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG155]], !nonnull [[META29]]
+// CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_kernel_environment, ptr [[DYN_PTR]]), !dbg [[DBG155]]
+// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP9]], -1, !dbg [[DBG155]]
+// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG155]]
// CHECK1: user_code.entry:
-// CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB13:[0-9]+]]), !dbg [[DBG153:![0-9]+]]
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG155:![0-9]+]]
-// CHECK1-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4, !dbg [[DBG155]]
-// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG155]]
-// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG155]]
-// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP13]], align 8, !dbg [[DBG155]]
-// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG155]]
-// CHECK1-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP12]] to ptr, !dbg [[DBG155]]
-// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8, !dbg [[DBG155]]
-// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG155]]
-// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 8, !dbg [[DBG155]]
-// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG155]]
-// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP17]], align 8, !dbg [[DBG155]]
-// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB13]], i32 [[TMP10]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0), !dbg [[DBG155]]
-// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG156:![0-9]+]]
-// CHECK1-NEXT: ret void, !dbg [[DBG157:![0-9]+]]
+// CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB13:[0-9]+]]), !dbg [[DBG156:![0-9]+]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG158:![0-9]+]]
+// CHECK1-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4, !dbg [[DBG158]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG158]]
+// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG158]]
+// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP13]], align 8, !dbg [[DBG158]]
+// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG158]]
+// CHECK1-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP12]] to ptr, !dbg [[DBG158]]
+// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8, !dbg [[DBG158]]
+// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG158]]
+// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 8, !dbg [[DBG158]]
+// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG158]]
+// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP17]], align 8, !dbg [[DBG158]]
+// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB13]], i32 [[TMP10]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0), !dbg [[DBG158]]
+// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG159:![0-9]+]]
+// CHECK1-NEXT: ret void, !dbg [[DBG160:![0-9]+]]
// CHECK1: worker.exit:
-// CHECK1-NEXT: ret void, !dbg [[DBG152]]
+// CHECK1-NEXT: ret void, !dbg [[DBG155]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27
-// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] !dbg [[DBG158:![0-9]+]] {
+// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] !dbg [[DBG161:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
@@ -426,32 +426,32 @@ int main() {
// CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META161:![0-9]+]], !DIExpression(), [[META162:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META164:![0-9]+]], !DIExpression(), [[META165:![0-9]+]])
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META163:![0-9]+]], !DIExpression(), [[META162]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META166:![0-9]+]], !DIExpression(), [[META165]])
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META164:![0-9]+]], !DIExpression(), [[META162]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META167:![0-9]+]], !DIExpression(), [[META165]])
// CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META165:![0-9]+]], !DIExpression(), [[META162]])
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META168:![0-9]+]], !DIExpression(), [[META165]])
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META166:![0-9]+]], !DIExpression(), [[META162]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG167:![0-9]+]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG167]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG167]], !nonnull [[META29]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG167]]
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG167]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG167]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG167]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8, !dbg [[DBG167]]
-// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP3]] to ptr addrspace(1), !dbg [[DBG167]]
-// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG167]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG167]]
-// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug__(ptr addrspace(1) [[TMP8]], i32 [[TMP4]], ptr addrspace(1) [[TMP9]], ptr addrspace(1) [[TMP10]], ptr [[TMP7]]) #[[ATTR3]], !dbg [[DBG167]]
-// CHECK1-NEXT: ret void, !dbg [[DBG167]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META169:![0-9]+]], !DIExpression(), [[META165]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG170:![0-9]+]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG170]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG170]], !nonnull [[META29]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG170]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG170]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG170]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG170]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8, !dbg [[DBG170]]
+// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP3]] to ptr addrspace(1), !dbg [[DBG170]]
+// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG170]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG170]]
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug__(ptr addrspace(1) [[TMP8]], i32 [[TMP4]], ptr addrspace(1) [[TMP9]], ptr addrspace(1) [[TMP10]], ptr [[TMP7]]) #[[ATTR3]], !dbg [[DBG170]]
+// CHECK1-NEXT: ret void, !dbg [[DBG170]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined_debug__
-// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG168:![0-9]+]] {
+// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG171:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -474,140 +474,140 @@ int main() {
// CHECK1-NEXT: [[H:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[D:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META171:![0-9]+]], !DIExpression(), [[META172:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META174:![0-9]+]], !DIExpression(), [[META175:![0-9]+]])
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META173:![0-9]+]], !DIExpression(), [[META172]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META176:![0-9]+]], !DIExpression(), [[META175]])
// CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META174:![0-9]+]], !DIExpression(), [[META175:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META177:![0-9]+]], !DIExpression(), [[META178:![0-9]+]])
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META176:![0-9]+]], !DIExpression(), [[META177:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META179:![0-9]+]], !DIExpression(), [[META180:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META178:![0-9]+]], !DIExpression(), [[META179:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META181:![0-9]+]], !DIExpression(), [[META182:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META180:![0-9]+]], !DIExpression(), [[META181:![0-9]+]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG182:![0-9]+]]
-// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG182]]
-// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG182]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG182]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG182]]
-// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG182]]
-// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG182]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG182]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG182]]
-// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG182]]
-// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG182]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG182]], !nonnull [[META29]]
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_IV]], [[META183:![0-9]+]], !DIExpression(), [[META172]])
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_LB]], [[META184:![0-9]+]], !DIExpression(), [[META172]])
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG185:![0-9]+]]
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_UB]], [[META186:![0-9]+]], !DIExpression(), [[META172]])
-// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_STRIDE]], [[META187:![0-9]+]], !DIExpression(), [[META172]])
-// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_IS_LAST]], [[META188:![0-9]+]], !DIExpression(), [[META172]])
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: #dbg_declare(ptr [[I]], [[META189:![0-9]+]], !DIExpression(), [[META172]])
-// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG182]]
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4, !dbg [[DBG182]]
-// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB10:[0-9]+]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG190:![0-9]+]]
-// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG182]]
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META183:![0-9]+]], !DIExpression(), [[META184:![0-9]+]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG185:![0-9]+]]
+// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG185]]
+// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG185]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG185]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG185]]
+// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG185]]
+// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG185]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG185]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG185]]
+// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG185]]
+// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG185]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG185]], !nonnull [[META29]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_IV]], [[META186:![0-9]+]], !DIExpression(), [[META175]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_LB]], [[META187:![0-9]+]], !DIExpression(), [[META175]])
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG188:![0-9]+]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_UB]], [[META189:![0-9]+]], !DIExpression(), [[META175]])
+// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_STRIDE]], [[META190:![0-9]+]], !DIExpression(), [[META175]])
+// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_IS_LAST]], [[META191:![0-9]+]], !DIExpression(), [[META175]])
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: #dbg_declare(ptr [[I]], [[META192:![0-9]+]], !DIExpression(), [[META175]])
+// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG185]]
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4, !dbg [[DBG185]]
+// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB10:[0-9]+]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG193:![0-9]+]]
+// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG185]]
// CHECK1: omp.dispatch.cond:
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9, !dbg [[DBG185]]
-// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG185]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9, !dbg [[DBG188]]
+// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG188]]
// CHECK1: cond.true:
-// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG185]]
+// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG188]]
// CHECK1: cond.false:
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: br label [[COND_END]], !dbg [[DBG185]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: br label [[COND_END]], !dbg [[DBG188]]
// CHECK1: cond.end:
-// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ], !dbg [[DBG185]]
-// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]], !dbg [[DBG182]]
-// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG182]]
+// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ], !dbg [[DBG188]]
+// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]], !dbg [[DBG185]]
+// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG185]]
// CHECK1: omp.dispatch.body:
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG182]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG185]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]], !dbg [[DBG182]]
-// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG182]]
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]], !dbg [[DBG185]]
+// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG185]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1, !dbg [[DBG191:![0-9]+]]
-// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG191]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG191]]
-// CHECK1-NEXT: #dbg_declare(ptr [[F]], [[META192:![0-9]+]], !DIExpression(), [[META194:![0-9]+]])
-// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG195:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG195]]
-// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], i64 0, i64 1, !dbg [[DBG195]]
-// CHECK1-NEXT: store ptr [[ARRAYIDX7]], ptr [[F]], align 8, !dbg [[META194]]
-// CHECK1-NEXT: #dbg_declare(ptr [[G]], [[META196:![0-9]+]], !DIExpression(), [[META197:![0-9]+]])
-// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[META197]]
-// CHECK1-NEXT: #dbg_declare(ptr [[H]], [[META198:![0-9]+]], !DIExpression(), [[META199:![0-9]+]])
-// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 1, !dbg [[DBG200:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], i64 0, i64 1, !dbg [[DBG200]]
-// CHECK1-NEXT: store ptr [[ARRAYIDX9]], ptr [[H]], align 8, !dbg [[META199]]
-// CHECK1-NEXT: #dbg_declare(ptr [[D]], [[META201:![0-9]+]], !DIExpression(), [[META202:![0-9]+]])
-// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[META202]]
-// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG203:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG204:![0-9]+]]
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG205:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG204]]
-// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX10]], i64 0, i64 [[IDXPROM]], !dbg [[DBG204]]
-// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX11]], align 4, !dbg [[DBG206:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG207:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX12]], i64 0, i64 0, !dbg [[DBG207]]
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG208:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG207]]
-// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX13]], i64 0, i64 [[IDXPROM14]], !dbg [[DBG207]]
-// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX15]], align 4, !dbg [[DBG209:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG210:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX16]], i64 0, i64 0, !dbg [[DBG210]]
-// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG211:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM18:%.*]] = sext i32 [[TMP21]] to i64, !dbg [[DBG210]]
-// CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX17]], i64 0, i64 [[IDXPROM18]], !dbg [[DBG210]]
-// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[ARRAYIDX19]], align 4, !dbg [[DBG210]]
-// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG212:![0-9]+]]
-// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG213:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM21:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG212]]
-// CHECK1-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX20]], i64 0, i64 [[IDXPROM21]], !dbg [[DBG212]]
-// CHECK1-NEXT: store i32 [[TMP22]], ptr [[ARRAYIDX22]], align 4, !dbg [[DBG214:![0-9]+]]
-// CHECK1-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP8]], align 1, !dbg [[DBG215:![0-9]+]]
-// CHECK1-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP24]], 0, !dbg [[DBG215]]
-// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[LOADEDV]] to i32, !dbg [[DBG215]]
-// CHECK1-NEXT: store i32 [[CONV]], ptr [[D]], align 4, !dbg [[DBG216:![0-9]+]]
-// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG217:![0-9]+]]
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1, !dbg [[DBG194:![0-9]+]]
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG194]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG194]]
+// CHECK1-NEXT: #dbg_declare(ptr [[F]], [[META195:![0-9]+]], !DIExpression(), [[META197:![0-9]+]])
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG198:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG198]]
+// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], i64 0, i64 1, !dbg [[DBG198]]
+// CHECK1-NEXT: store ptr [[ARRAYIDX7]], ptr [[F]], align 8, !dbg [[META197]]
+// CHECK1-NEXT: #dbg_declare(ptr [[G]], [[META199:![0-9]+]], !DIExpression(), [[META200:![0-9]+]])
+// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[META200]]
+// CHECK1-NEXT: #dbg_declare(ptr [[H]], [[META201:![0-9]+]], !DIExpression(), [[META202:![0-9]+]])
+// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 1, !dbg [[DBG203:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], i64 0, i64 1, !dbg [[DBG203]]
+// CHECK1-NEXT: store ptr [[ARRAYIDX9]], ptr [[H]], align 8, !dbg [[META202]]
+// CHECK1-NEXT: #dbg_declare(ptr [[D]], [[META204:![0-9]+]], !DIExpression(), [[META205:![0-9]+]])
+// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[META205]]
+// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG206:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG207:![0-9]+]]
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG208:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG207]]
+// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX10]], i64 0, i64 [[IDXPROM]], !dbg [[DBG207]]
+// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX11]], align 4, !dbg [[DBG209:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG210:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX12]], i64 0, i64 0, !dbg [[DBG210]]
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG211:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG210]]
+// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX13]], i64 0, i64 [[IDXPROM14]], !dbg [[DBG210]]
+// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX15]], align 4, !dbg [[DBG212:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG213:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX16]], i64 0, i64 0, !dbg [[DBG213]]
+// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG214:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM18:%.*]] = sext i32 [[TMP21]] to i64, !dbg [[DBG213]]
+// CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX17]], i64 0, i64 [[IDXPROM18]], !dbg [[DBG213]]
+// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[ARRAYIDX19]], align 4, !dbg [[DBG213]]
+// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG215:![0-9]+]]
+// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG216:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM21:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG215]]
+// CHECK1-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX20]], i64 0, i64 [[IDXPROM21]], !dbg [[DBG215]]
+// CHECK1-NEXT: store i32 [[TMP22]], ptr [[ARRAYIDX22]], align 4, !dbg [[DBG217:![0-9]+]]
+// CHECK1-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP8]], align 1, !dbg [[DBG218:![0-9]+]]
+// CHECK1-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP24]], 0, !dbg [[DBG218]]
+// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[LOADEDV]] to i32, !dbg [[DBG218]]
+// CHECK1-NEXT: store i32 [[CONV]], ptr [[D]], align 4, !dbg [[DBG219:![0-9]+]]
+// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG220:![0-9]+]]
// CHECK1: omp.body.continue:
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG190]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG193]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP25]], 1, !dbg [[DBG182]]
-// CHECK1-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG182]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG190]], !llvm.loop [[LOOP218:![0-9]+]]
+// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP25]], 1, !dbg [[DBG185]]
+// CHECK1-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG185]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG193]], !llvm.loop [[LOOP221:![0-9]+]]
// CHECK1: omp.inner.for.end:
-// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG190]]
+// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG193]]
// CHECK1: omp.dispatch.inc:
-// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP26]], [[TMP27]], !dbg [[DBG182]]
-// CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG182]]
-// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG185]]
-// CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]], !dbg [[DBG182]]
-// CHECK1-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG182]]
-// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG190]], !llvm.loop [[LOOP220:![0-9]+]]
+// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP26]], [[TMP27]], !dbg [[DBG185]]
+// CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG185]]
+// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG188]]
+// CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]], !dbg [[DBG185]]
+// CHECK1-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG185]]
+// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG193]], !llvm.loop [[LOOP223:![0-9]+]]
// CHECK1: omp.dispatch.end:
-// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB12:[0-9]+]], i32 [[TMP10]]), !dbg [[DBG219:![0-9]+]]
-// CHECK1-NEXT: ret void, !dbg [[DBG221:![0-9]+]]
+// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB12:[0-9]+]], i32 [[TMP10]]), !dbg [[DBG222:![0-9]+]]
+// CHECK1-NEXT: ret void, !dbg [[DBG224:![0-9]+]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined
-// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG222:![0-9]+]] {
+// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG225:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -616,35 +616,35 @@ int main() {
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META223:![0-9]+]], !DIExpression(), [[META224:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META226:![0-9]+]], !DIExpression(), [[META227:![0-9]+]])
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META225:![0-9]+]], !DIExpression(), [[META224]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META228:![0-9]+]], !DIExpression(), [[META227]])
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META226:![0-9]+]], !DIExpression(), [[META224]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META229:![0-9]+]], !DIExpression(), [[META227]])
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META227:![0-9]+]], !DIExpression(), [[META224]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META230:![0-9]+]], !DIExpression(), [[META227]])
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META228:![0-9]+]], !DIExpression(), [[META224]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META231:![0-9]+]], !DIExpression(), [[META227]])
// CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META229:![0-9]+]], !DIExpression(), [[META224]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG230:![0-9]+]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG230]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG230]], !nonnull [[META29]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG230]]
-// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG230]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG230]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG230]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG230]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG230]]
-// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG230]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG230]]
-// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG230]]
-// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]]) #[[ATTR3]], !dbg [[DBG230]]
-// CHECK1-NEXT: ret void, !dbg [[DBG230]]
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META232:![0-9]+]], !DIExpression(), [[META227]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG233:![0-9]+]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG233]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG233]], !nonnull [[META29]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG233]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG233]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG233]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG233]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG233]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG233]]
+// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG233]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG233]]
+// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG233]]
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]]) #[[ATTR3]], !dbg [[DBG233]]
+// CHECK1-NEXT: ret void, !dbg [[DBG233]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug__
-// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] !dbg [[DBG231:![0-9]+]] {
+// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] !dbg [[DBG234:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr addrspace(1), align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr addrspace(1), align 8
@@ -657,53 +657,53 @@ int main() {
// CHECK1-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8
// CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META236:![0-9]+]], !DIExpression(), [[META237:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META239:![0-9]+]], !DIExpression(), [[META240:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META238:![0-9]+]], !DIExpression(), [[META239:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META241:![0-9]+]], !DIExpression(), [[META242:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META240:![0-9]+]], !DIExpression(), [[META241:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META243:![0-9]+]], !DIExpression(), [[META244:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META242:![0-9]+]], !DIExpression(), [[META243:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META245:![0-9]+]], !DIExpression(), [[META246:![0-9]+]])
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META244:![0-9]+]], !DIExpression(), [[META245:![0-9]+]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG246:![0-9]+]]
-// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG246]]
-// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG246]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG246]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG246]]
-// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG246]]
-// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG246]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG246]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG246]]
-// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG246]]
-// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG246]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG246]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG246]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG246]]
-// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG246]]
-// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG246]], !nonnull [[META29]]
-// CHECK1-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_kernel_environment, ptr [[DYN_PTR]]), !dbg [[DBG246]]
-// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP12]], -1, !dbg [[DBG246]]
-// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG246]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META247:![0-9]+]], !DIExpression(), [[META248:![0-9]+]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG249:![0-9]+]]
+// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG249]]
+// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG249]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG249]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG249]]
+// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG249]]
+// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG249]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG249]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG249]]
+// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG249]]
+// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG249]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG249]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG249]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG249]]
+// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG249]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG249]], !nonnull [[META29]]
+// CHECK1-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_kernel_environment, ptr [[DYN_PTR]]), !dbg [[DBG249]]
+// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP12]], -1, !dbg [[DBG249]]
+// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG249]]
// CHECK1: user_code.entry:
-// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB20:[0-9]+]]), !dbg [[DBG247:![0-9]+]]
-// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG249:![0-9]+]]
-// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP14]], align 8, !dbg [[DBG249]]
-// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG249]]
-// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP15]], align 8, !dbg [[DBG249]]
-// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG249]]
-// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP16]], align 8, !dbg [[DBG249]]
-// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG249]]
-// CHECK1-NEXT: store ptr [[TMP11]], ptr [[TMP17]], align 8, !dbg [[DBG249]]
-// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB20]], i32 [[TMP13]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0), !dbg [[DBG249]]
-// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG250:![0-9]+]]
-// CHECK1-NEXT: ret void, !dbg [[DBG251:![0-9]+]]
+// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB20:[0-9]+]]), !dbg [[DBG250:![0-9]+]]
+// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG252:![0-9]+]]
+// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP14]], align 8, !dbg [[DBG252]]
+// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG252]]
+// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP15]], align 8, !dbg [[DBG252]]
+// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG252]]
+// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP16]], align 8, !dbg [[DBG252]]
+// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG252]]
+// CHECK1-NEXT: store ptr [[TMP11]], ptr [[TMP17]], align 8, !dbg [[DBG252]]
+// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB20]], i32 [[TMP13]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0), !dbg [[DBG252]]
+// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG253:![0-9]+]]
+// CHECK1-NEXT: ret void, !dbg [[DBG254:![0-9]+]]
// CHECK1: worker.exit:
-// CHECK1-NEXT: ret void, !dbg [[DBG246]]
+// CHECK1-NEXT: ret void, !dbg [[DBG249]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41
-// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] !dbg [[DBG252:![0-9]+]] {
+// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] !dbg [[DBG255:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
@@ -711,34 +711,34 @@ int main() {
// CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META255:![0-9]+]], !DIExpression(), [[META256:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META258:![0-9]+]], !DIExpression(), [[META259:![0-9]+]])
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META257:![0-9]+]], !DIExpression(), [[META256]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META260:![0-9]+]], !DIExpression(), [[META259]])
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META258:![0-9]+]], !DIExpression(), [[META256]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META261:![0-9]+]], !DIExpression(), [[META259]])
// CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META259:![0-9]+]], !DIExpression(), [[META256]])
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META262:![0-9]+]], !DIExpression(), [[META259]])
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META260:![0-9]+]], !DIExpression(), [[META256]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG261:![0-9]+]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG261]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG261]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG261]], !nonnull [[META29]]
-// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG261]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG261]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG261]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG261]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8, !dbg [[DBG261]]
-// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP4]] to ptr addrspace(1), !dbg [[DBG261]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG261]]
-// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG261]]
-// CHECK1-NEXT: [[TMP12:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG261]]
-// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug__(ptr addrspace(1) [[TMP9]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]], ptr addrspace(1) [[TMP12]], ptr [[TMP8]]) #[[ATTR3]], !dbg [[DBG261]]
-// CHECK1-NEXT: ret void, !dbg [[DBG261]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DYN_PTR_ADDR]], [[META263:![0-9]+]], !DIExpression(), [[META259]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG264:![0-9]+]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG264]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG264]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG264]], !nonnull [[META29]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG264]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG264]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG264]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG264]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8, !dbg [[DBG264]]
+// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP4]] to ptr addrspace(1), !dbg [[DBG264]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG264]]
+// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG264]]
+// CHECK1-NEXT: [[TMP12:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG264]]
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug__(ptr addrspace(1) [[TMP9]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]], ptr addrspace(1) [[TMP12]], ptr [[TMP8]]) #[[ATTR3]], !dbg [[DBG264]]
+// CHECK1-NEXT: ret void, !dbg [[DBG264]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined_debug__
-// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG262:![0-9]+]] {
+// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG265:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -762,148 +762,148 @@ int main() {
// CHECK1-NEXT: [[H:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[D:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META265:![0-9]+]], !DIExpression(), [[META266:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META268:![0-9]+]], !DIExpression(), [[META269:![0-9]+]])
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META267:![0-9]+]], !DIExpression(), [[META266]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META270:![0-9]+]], !DIExpression(), [[META269]])
// CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META268:![0-9]+]], !DIExpression(), [[META269:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META271:![0-9]+]], !DIExpression(), [[META272:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META270:![0-9]+]], !DIExpression(), [[META271:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META273:![0-9]+]], !DIExpression(), [[META274:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META272:![0-9]+]], !DIExpression(), [[META273:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META275:![0-9]+]], !DIExpression(), [[META276:![0-9]+]])
// CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META274:![0-9]+]], !DIExpression(), [[META275:![0-9]+]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG276:![0-9]+]]
-// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG276]]
-// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG276]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG276]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG276]]
-// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG276]]
-// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG276]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG276]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG276]]
-// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG276]]
-// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG276]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG276]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG276]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG276]]
-// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG276]]
-// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG276]], !nonnull [[META29]]
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_IV]], [[META277:![0-9]+]], !DIExpression(), [[META266]])
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_LB]], [[META278:![0-9]+]], !DIExpression(), [[META266]])
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG279:![0-9]+]]
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_UB]], [[META280:![0-9]+]], !DIExpression(), [[META266]])
-// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_STRIDE]], [[META281:![0-9]+]], !DIExpression(), [[META266]])
-// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_IS_LAST]], [[META282:![0-9]+]], !DIExpression(), [[META266]])
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: #dbg_declare(ptr [[I]], [[META283:![0-9]+]], !DIExpression(), [[META266]])
-// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG276]]
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG276]]
-// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB17:[0-9]+]], i32 [[TMP13]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG284:![0-9]+]]
-// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG276]]
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META277:![0-9]+]], !DIExpression(), [[META278:![0-9]+]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG279:![0-9]+]]
+// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG279]]
+// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG279]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG279]]
+// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG279]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG279]]
+// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG279]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG279]]
+// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG279]], !nonnull [[META29]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_IV]], [[META280:![0-9]+]], !DIExpression(), [[META269]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_LB]], [[META281:![0-9]+]], !DIExpression(), [[META269]])
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG282:![0-9]+]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_UB]], [[META283:![0-9]+]], !DIExpression(), [[META269]])
+// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_STRIDE]], [[META284:![0-9]+]], !DIExpression(), [[META269]])
+// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTOMP_IS_LAST]], [[META285:![0-9]+]], !DIExpression(), [[META269]])
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: #dbg_declare(ptr [[I]], [[META286:![0-9]+]], !DIExpression(), [[META269]])
+// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG279]]
+// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB17:[0-9]+]], i32 [[TMP13]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG287:![0-9]+]]
+// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG279]]
// CHECK1: omp.dispatch.cond:
-// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP14]], 9, !dbg [[DBG279]]
-// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP14]], 9, !dbg [[DBG282]]
+// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG282]]
// CHECK1: cond.true:
-// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG279]]
+// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG282]]
// CHECK1: cond.false:
-// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: br label [[COND_END]], !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: br label [[COND_END]], !dbg [[DBG282]]
// CHECK1: cond.end:
-// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ], !dbg [[DBG279]]
-// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]], !dbg [[DBG276]]
-// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG276]]
+// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ], !dbg [[DBG282]]
+// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]], !dbg [[DBG279]]
+// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG279]]
// CHECK1: omp.dispatch.body:
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG276]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG279]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]], !dbg [[DBG276]]
-// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG276]]
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]], !dbg [[DBG279]]
+// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG279]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1, !dbg [[DBG285:![0-9]+]]
-// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG285]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG285]]
-// CHECK1-NEXT: #dbg_declare(ptr [[F]], [[META286:![0-9]+]], !DIExpression(), [[META288:![0-9]+]])
-// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG289:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG289]]
-// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 1, !dbg [[DBG289]]
-// CHECK1-NEXT: store ptr [[ARRAYIDX8]], ptr [[F]], align 8, !dbg [[META288]]
-// CHECK1-NEXT: #dbg_declare(ptr [[G]], [[META290:![0-9]+]], !DIExpression(), [[META291:![0-9]+]])
-// CHECK1-NEXT: store ptr [[TMP5]], ptr [[G]], align 8, !dbg [[META291]]
-// CHECK1-NEXT: #dbg_declare(ptr [[H]], [[META292:![0-9]+]], !DIExpression(), [[META293:![0-9]+]])
-// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 1, !dbg [[DBG294:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX9]], i64 0, i64 1, !dbg [[DBG294]]
-// CHECK1-NEXT: store ptr [[ARRAYIDX10]], ptr [[H]], align 8, !dbg [[META293]]
-// CHECK1-NEXT: #dbg_declare(ptr [[D]], [[META295:![0-9]+]], !DIExpression(), [[META296:![0-9]+]])
-// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[META296]]
-// CHECK1-NEXT: store i32 5, ptr [[TMP5]], align 4, !dbg [[DBG297:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG298:![0-9]+]]
-// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG299:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG298]]
-// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM]], !dbg [[DBG298]]
-// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG300:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG301:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG301]]
-// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG302:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG301]]
-// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG301]]
-// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG303:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG304:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX17]], i64 0, i64 0, !dbg [[DBG304]]
-// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG305:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP24]] to i64, !dbg [[DBG304]]
-// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG304]]
-// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4, !dbg [[DBG304]]
-// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG306:![0-9]+]]
-// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG307:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP26]] to i64, !dbg [[DBG306]]
-// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG306]]
-// CHECK1-NEXT: store i32 [[TMP25]], ptr [[ARRAYIDX23]], align 4, !dbg [[DBG308:![0-9]+]]
-// CHECK1-NEXT: [[ARRAYIDX24:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG309:![0-9]+]]
-// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG310:![0-9]+]]
-// CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP27]] to i64, !dbg [[DBG309]]
-// CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX24]], i64 0, i64 [[IDXPROM25]], !dbg [[DBG309]]
-// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARRAYIDX26]], align 4, !dbg [[DBG309]]
-// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP28]], 0, !dbg [[DBG309]]
-// CHECK1-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG311:![0-9]+]]
-// CHECK1-NEXT: store i8 [[STOREDV]], ptr [[TMP11]], align 1, !dbg [[DBG311]]
-// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG312:![0-9]+]]
+// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1, !dbg [[DBG288:![0-9]+]]
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG288]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG288]]
+// CHECK1-NEXT: #dbg_declare(ptr [[F]], [[META289:![0-9]+]], !DIExpression(), [[META291:![0-9]+]])
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG292:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG292]]
+// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 1, !dbg [[DBG292]]
+// CHECK1-NEXT: store ptr [[ARRAYIDX8]], ptr [[F]], align 8, !dbg [[META291]]
+// CHECK1-NEXT: #dbg_declare(ptr [[G]], [[META293:![0-9]+]], !DIExpression(), [[META294:![0-9]+]])
+// CHECK1-NEXT: store ptr [[TMP5]], ptr [[G]], align 8, !dbg [[META294]]
+// CHECK1-NEXT: #dbg_declare(ptr [[H]], [[META295:![0-9]+]], !DIExpression(), [[META296:![0-9]+]])
+// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 1, !dbg [[DBG297:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX9]], i64 0, i64 1, !dbg [[DBG297]]
+// CHECK1-NEXT: store ptr [[ARRAYIDX10]], ptr [[H]], align 8, !dbg [[META296]]
+// CHECK1-NEXT: #dbg_declare(ptr [[D]], [[META298:![0-9]+]], !DIExpression(), [[META299:![0-9]+]])
+// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[META299]]
+// CHECK1-NEXT: store i32 5, ptr [[TMP5]], align 4, !dbg [[DBG300:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG301:![0-9]+]]
+// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG302:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG301]]
+// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM]], !dbg [[DBG301]]
+// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG303:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG304:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG304]]
+// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG305:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG304]]
+// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG304]]
+// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG306:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG307:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr [10 x [10 x i32]], ptr [[ARRAYIDX17]], i64 0, i64 0, !dbg [[DBG307]]
+// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG308:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP24]] to i64, !dbg [[DBG307]]
+// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG307]]
+// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4, !dbg [[DBG307]]
+// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG309:![0-9]+]]
+// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG310:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP26]] to i64, !dbg [[DBG309]]
+// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG309]]
+// CHECK1-NEXT: store i32 [[TMP25]], ptr [[ARRAYIDX23]], align 4, !dbg [[DBG311:![0-9]+]]
+// CHECK1-NEXT: [[ARRAYIDX24:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG312:![0-9]+]]
+// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG313:![0-9]+]]
+// CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP27]] to i64, !dbg [[DBG312]]
+// CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX24]], i64 0, i64 [[IDXPROM25]], !dbg [[DBG312]]
+// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARRAYIDX26]], align 4, !dbg [[DBG312]]
+// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP28]], 0, !dbg [[DBG312]]
+// CHECK1-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG314:![0-9]+]]
+// CHECK1-NEXT: store i8 [[STOREDV]], ptr [[TMP11]], align 1, !dbg [[DBG314]]
+// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG315:![0-9]+]]
// CHECK1: omp.body.continue:
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG284]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG287]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP29]], 1, !dbg [[DBG276]]
-// CHECK1-NEXT: store i32 [[ADD27]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG276]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG284]], !llvm.loop [[LOOP313:![0-9]+]]
+// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP29]], 1, !dbg [[DBG279]]
+// CHECK1-NEXT: store i32 [[ADD27]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG279]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG287]], !llvm.loop [[LOOP316:![0-9]+]]
// CHECK1: omp.inner.for.end:
-// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG284]]
+// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG287]]
// CHECK1: omp.dispatch.inc:
-// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]], !dbg [[DBG276]]
-// CHECK1-NEXT: store i32 [[ADD28]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG276]]
-// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG279]]
-// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP32]], [[TMP33]], !dbg [[DBG276]]
-// CHECK1-NEXT: store i32 [[ADD29]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG276]]
-// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG284]], !llvm.loop [[LOOP315:![0-9]+]]
+// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]], !dbg [[DBG279]]
+// CHECK1-NEXT: store i32 [[ADD28]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG279]]
+// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG282]]
+// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP32]], [[TMP33]], !dbg [[DBG279]]
+// CHECK1-NEXT: store i32 [[ADD29]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG279]]
+// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG287]], !llvm.loop [[LOOP318:![0-9]+]]
// CHECK1: omp.dispatch.end:
-// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB19:[0-9]+]], i32 [[TMP13]]), !dbg [[DBG314:![0-9]+]]
-// CHECK1-NEXT: ret void, !dbg [[DBG316:![0-9]+]]
+// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB19:[0-9]+]], i32 [[TMP13]]), !dbg [[DBG317:![0-9]+]]
+// CHECK1-NEXT: ret void, !dbg [[DBG319:![0-9]+]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined
-// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG317:![0-9]+]] {
+// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG320:![0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -912,31 +912,31 @@ int main() {
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META320:![0-9]+]], !DIExpression(), [[META321:![0-9]+]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META323:![0-9]+]], !DIExpression(), [[META324:![0-9]+]])
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META322:![0-9]+]], !DIExpression(), [[META321]])
+// CHECK1-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META325:![0-9]+]], !DIExpression(), [[META324]])
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META323:![0-9]+]], !DIExpression(), [[META321]])
+// CHECK1-NEXT: #dbg_declare(ptr [[C_ADDR]], [[META326:![0-9]+]], !DIExpression(), [[META324]])
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META324:![0-9]+]], !DIExpression(), [[META321]])
+// CHECK1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META327:![0-9]+]], !DIExpression(), [[META324]])
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META325:![0-9]+]], !DIExpression(), [[META321]])
+// CHECK1-NEXT: #dbg_declare(ptr [[B_ADDR]], [[META328:![0-9]+]], !DIExpression(), [[META324]])
// CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8
-// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META326:![0-9]+]], !DIExpression(), [[META321]])
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG327:![0-9]+]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG327]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG327]], !nonnull [[META29]], !align [[META43]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG327]], !nonnull [[META29]]
-// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG327]]
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG327]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG327]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG327]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG327]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG327]]
-// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG327]]
-// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG327]]
-// CHECK1-NEXT: [[TMP12:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG327]]
-// CHECK1-NEXT: [[TMP13:%.*]] = addrspacecast ptr [[TMP9]] to ptr addrspace(1), !dbg [[DBG327]]
-// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined_debug__(ptr [[TMP4]], ptr [[TMP5]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]], ptr addrspace(1) [[TMP12]], ptr addrspace(1) [[TMP13]]) #[[ATTR3]], !dbg [[DBG327]]
-// CHECK1-NEXT: ret void, !dbg [[DBG327]]
+// CHECK1-NEXT: #dbg_declare(ptr [[BB_ADDR]], [[META329:![0-9]+]], !DIExpression(), [[META324]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG330:![0-9]+]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG330]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG330]], !nonnull [[META29]], !align [[META43]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG330]], !nonnull [[META29]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG330]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG330]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG330]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG330]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG330]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG330]]
+// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG330]]
+// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG330]]
+// CHECK1-NEXT: [[TMP12:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG330]]
+// CHECK1-NEXT: [[TMP13:%.*]] = addrspacecast ptr [[TMP9]] to ptr addrspace(1), !dbg [[DBG330]]
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined_debug__(ptr [[TMP4]], ptr [[TMP5]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]], ptr addrspace(1) [[TMP12]], ptr addrspace(1) [[TMP13]]) #[[ATTR3]], !dbg [[DBG330]]
+// CHECK1-NEXT: ret void, !dbg [[DBG330]]
//
>From 261e37ca3021b447825af958cf9bbbbcc791e993 Mon Sep 17 00:00:00 2001
From: mxms <mxms at google.com>
Date: Mon, 5 Oct 2026 16:29:38 -0400
Subject: [PATCH 2/2] Add synthetic inlined debug info for llvm.memset and
llvm.memcpy emitted by Clang CodeGen.
When list-initializers or aggregate initializations (such as `char
array[24] = { 0 }`) are lowered to `llvm.memset` or `llvm.memcpy`,
compiler optimizations can inline these memory operations into sequences
stores. Without debug information attributing the generated machine
instructions to an inlined `memset` or `memcpy` frame, sampling
profilers attribute execution samples directly to the enclosing function
at the variable declaration line, obscuring implicit initialization.
`CGBuilderTy::CreateMemSet` and `CGBuilderTy::CreateMemCpy` now rewrite
the debug location of the emitted intrinsic call so it appears inlined
from a synthetic artificial `memset`/`memcpy` subprogram at the
builder's current location.
When the intrinsic is expanded into stores, DWARF contains
`DW_TAG_inlined_subroutine` records, so profilers and debuggers
attribute those stores to an inlined `memset` or `memcpy` frame at the
source location.
The location is set after the instruction is created rather than in
`CGBuilderInserter::InsertHelper`, because `IRBuilder` applies the
current debug location after the inserter runs.
The OpenMP debug-info tests were regenerated with
`update_cc_test_checks.py`.
---
clang/lib/CodeGen/CGBuilder.h | 12 +-
clang/lib/CodeGen/CGDebugInfo.cpp | 52 ++++-----
clang/lib/CodeGen/CGDebugInfo.h | 7 +-
clang/lib/CodeGen/CodeGenFunction.cpp | 154 ++++++++++++++------------
4 files changed, 114 insertions(+), 111 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuilder.h b/clang/lib/CodeGen/CGBuilder.h
index bef44fa8ee789..645496209cad2 100644
--- a/clang/lib/CodeGen/CGBuilder.h
+++ b/clang/lib/CodeGen/CGBuilder.h
@@ -407,8 +407,8 @@ class CGBuilderTy : public CGBuilderBaseTy {
llvm::Value *DestPtr = emitRawPointerFromAddress(Dest);
llvm::Value *SrcPtr = emitRawPointerFromAddress(Src);
llvm::CallInst *CI =
- CreateMemCpy(DestPtr, Dest.getAlignment().getAsAlign(), SrcPtr,
- Src.getAlignment().getAsAlign(), Size, IsVolatile);
+ CreateMemCpy(DestPtr, Dest.getAlignment().getAsAlign(), SrcPtr,
+ Src.getAlignment().getAsAlign(), Size, IsVolatile);
attachSyntheticInlineDebugLoc(CI, "memcpy");
return CI;
}
@@ -417,8 +417,8 @@ class CGBuilderTy : public CGBuilderBaseTy {
llvm::Value *DestPtr = emitRawPointerFromAddress(Dest);
llvm::Value *SrcPtr = emitRawPointerFromAddress(Src);
llvm::CallInst *CI =
- CreateMemCpy(DestPtr, Dest.getAlignment().getAsAlign(), SrcPtr,
- Src.getAlignment().getAsAlign(), Size, IsVolatile);
+ CreateMemCpy(DestPtr, Dest.getAlignment().getAsAlign(), SrcPtr,
+ Src.getAlignment().getAsAlign(), Size, IsVolatile);
attachSyntheticInlineDebugLoc(CI, "memcpy");
return CI;
}
@@ -444,8 +444,8 @@ class CGBuilderTy : public CGBuilderBaseTy {
llvm::CallInst *CreateMemSet(Address Dest, llvm::Value *Value,
llvm::Value *Size, bool IsVolatile = false) {
llvm::CallInst *CI =
- CreateMemSet(emitRawPointerFromAddress(Dest), Value, Size,
- Dest.getAlignment().getAsAlign(), IsVolatile);
+ CreateMemSet(emitRawPointerFromAddress(Dest), Value, Size,
+ Dest.getAlignment().getAsAlign(), IsVolatile);
attachSyntheticInlineDebugLoc(CI, "memset");
return CI;
}
diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp b/clang/lib/CodeGen/CGDebugInfo.cpp
index 88908dbae2a61..d9b05d32b8786 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -623,7 +623,7 @@ llvm::DIFile *CGDebugInfo::getOrCreateFile(SourceLocation Loc) {
SmallString<64> Checksum;
if (!CSInfo) {
std::optional<llvm::DIFile::ChecksumKind> CSKind =
- computeChecksum(FID, Checksum);
+ computeChecksum(FID, Checksum);
if (CSKind)
CSInfo.emplace(*CSKind, Checksum);
}
@@ -971,8 +971,8 @@ llvm::DIType *CGDebugInfo::CreateType(const BuiltinType *BT) {
return getOrCreateStructPtrType("opencl_queue_t", OCLQueueDITy);
case BuiltinType::OCLReserveID:
return getOrCreateStructPtrType("opencl_reserve_id_t", OCLReserveIDDITy);
-#define EXT_OPAQUE_TYPE(ExtType, Id, Ext) \
- case BuiltinType::Id: \
+#define EXT_OPAQUE_TYPE(ExtType, Id, Ext) \
+ case BuiltinType::Id: \
return getOrCreateStructPtrType("opencl_" #ExtType, Id##Ty);
#include "clang/Basic/OpenCLExtensionTypes.def"
#define HLSL_INTANGIBLE_TYPE(Name, Id, SingletonId) \
@@ -1043,10 +1043,9 @@ llvm::DIType *CGDebugInfo::CreateType(const BuiltinType *BT) {
return DBuilder.createVectorType(/*Size*/ 0, Align, ElemTy,
SubscriptArray, BitStride);
}
- // It doesn't make sense to generate debug info for PowerPC MMA vector types.
- // So we return a safe type here to avoid generating an error.
-#define PPC_VECTOR_TYPE(Name, Id, size) \
- case BuiltinType::Id:
+ // It doesn't make sense to generate debug info for PowerPC MMA vector
+ // types. So we return a safe type here to avoid generating an error.
+#define PPC_VECTOR_TYPE(Name, Id, size) case BuiltinType::Id:
#include "clang/Basic/PPCTypes.def"
return CreateType(cast<const BuiltinType>(CGM.getContext().IntTy));
@@ -1091,7 +1090,8 @@ llvm::DIType *CGDebugInfo::CreateType(const BuiltinType *BT) {
Expr.push_back(llvm::dwarf::DW_OP_mul);
// NFIELDS multiplier
if (NFIELDS > 1)
- Expr.append({llvm::dwarf::DW_OP_constu, NFIELDS, llvm::dwarf::DW_OP_mul});
+ Expr.append(
+ {llvm::dwarf::DW_OP_constu, NFIELDS, llvm::dwarf::DW_OP_mul});
// Element max index = count - 1
Expr.append({llvm::dwarf::DW_OP_constu, 1, llvm::dwarf::DW_OP_minus});
@@ -1628,8 +1628,8 @@ llvm::DIType *CGDebugInfo::CreateType(const BlockPointerType *Ty,
auto *DescTy = DBuilder.createPointerType(EltTy, Size);
- FieldOffset = collectDefaultElementTypesForBlockPointer(Ty, Unit, DescTy,
- 0, EltTys);
+ FieldOffset =
+ collectDefaultElementTypesForBlockPointer(Ty, Unit, DescTy, 0, EltTys);
Elements = DBuilder.getOrCreateArray(EltTys);
@@ -1637,8 +1637,8 @@ llvm::DIType *CGDebugInfo::CreateType(const BlockPointerType *Ty,
// DW_AT_APPLE_BLOCK attribute and are an implementation detail only
// the debugger needs to know about. To allow type uniquing, emit
// them without a name or a location.
- EltTy = DBuilder.createStructType(Unit, "", nullptr, 0, FieldOffset, 0,
- Flags, nullptr, Elements);
+ EltTy = DBuilder.createStructType(Unit, "", nullptr, 0, FieldOffset, 0, Flags,
+ nullptr, Elements);
return DBuilder.createPointerType(EltTy, Size);
}
@@ -2348,8 +2348,8 @@ CGDebugInfo::getOrCreateInstanceMethodType(QualType ThisPtr,
// CreateQualifiedType(const FunctionPrototype*, DIFile *Unit)
// On a 'real' member function type, these qualifiers are carried on the type
// of the first parameter, not as separate DW_TAG_const_type (etc) decorator
- // tags around them. (But, in the raw function types with qualifiers, they have
- // to use wrapper types.)
+ // tags around them. (But, in the raw function types with qualifiers, they
+ // have to use wrapper types.)
// Add "this" pointer.
const auto *OriginalFunc = cast<llvm::DISubroutineType>(
@@ -3670,9 +3670,8 @@ llvm::DIModule *CGDebugInfo::getOrCreateModuleRef(ASTSourceDescriptor Mod,
if (!Sysroot.empty() && IncludePath.starts_with(Sysroot))
IncludePath = "";
}
- llvm::DIModule *DIMod =
- DBuilder.createModule(Parent, Mod.getModuleName(), ConfigMacros,
- RemapPath(IncludePath));
+ llvm::DIModule *DIMod = DBuilder.createModule(
+ Parent, Mod.getModuleName(), ConfigMacros, RemapPath(IncludePath));
ModuleCache[M].reset(DIMod);
return DIMod;
}
@@ -4190,7 +4189,7 @@ CGDebugInfo::CreateSyntheticInlineAt(llvm::DebugLoc ParentLocation,
llvm::DIFile *SynthFile) {
if (!ParentLocation)
return nullptr;
- if (!SynthFile)
+ if (!SynthFile)
SynthFile = ParentLocation->getFile();
if (!SynthFile && TheCU)
SynthFile = TheCU->getFile();
@@ -4563,7 +4562,7 @@ llvm::DICompositeType *CGDebugInfo::CreateLimitedType(const RecordType *Ty) {
// Record exports it symbols to the containing structure.
if (CXXRD->isAnonymousStructOrUnion())
- Flags |= llvm::DINode::FlagExportSymbols;
+ Flags |= llvm::DINode::FlagExportSymbols;
Flags |= getAccessFlag(CXXRD->getAccess(),
dyn_cast<CXXRecordDecl>(CXXRD->getDeclContext()));
@@ -5174,9 +5173,8 @@ void CGDebugInfo::EmitFunctionDecl(GlobalDecl GD, SourceLocation Loc,
if (!D)
return;
- llvm::TimeTraceScope TimeScope("DebugFunction", [&]() {
- return GetName(D, true);
- });
+ llvm::TimeTraceScope TimeScope("DebugFunction",
+ [&]() { return GetName(D, true); });
llvm::DINode::DIFlags Flags = llvm::DINode::FlagZero;
llvm::DIFile *Unit = getOrCreateFile(Loc);
@@ -6360,9 +6358,8 @@ void CGDebugInfo::EmitGlobalVariable(llvm::GlobalVariable *Var,
if (D->hasAttr<NoDebugAttr>())
return;
- llvm::TimeTraceScope TimeScope("DebugGlobalVariable", [&]() {
- return GetName(D, true);
- });
+ llvm::TimeTraceScope TimeScope("DebugGlobalVariable",
+ [&]() { return GetName(D, true); });
// If we already created a DIGlobalVariable for this declaration, just attach
// it to the llvm::GlobalVariable.
@@ -6424,9 +6421,8 @@ void CGDebugInfo::EmitGlobalVariable(const ValueDecl *VD, const APValue &Init) {
assert(CGM.getCodeGenOpts().hasReducedDebugInfo());
if (VD->hasAttr<NoDebugAttr>())
return;
- llvm::TimeTraceScope TimeScope("DebugConstGlobalVariable", [&]() {
- return GetName(VD, true);
- });
+ llvm::TimeTraceScope TimeScope("DebugConstGlobalVariable",
+ [&]() { return GetName(VD, true); });
auto Align = getDeclAlignIfRequired(VD, CGM.getContext());
// Create the descriptor for the variable.
diff --git a/clang/lib/CodeGen/CGDebugInfo.h b/clang/lib/CodeGen/CGDebugInfo.h
index 59569ce96be90..940e09ae755fb 100644
--- a/clang/lib/CodeGen/CGDebugInfo.h
+++ b/clang/lib/CodeGen/CGDebugInfo.h
@@ -86,8 +86,7 @@ class CGDebugInfo {
llvm::DIType *OCLQueueDITy = nullptr;
llvm::DIType *OCLNDRangeDITy = nullptr;
llvm::DIType *OCLReserveIDDITy = nullptr;
-#define EXT_OPAQUE_TYPE(ExtType, Id, Ext) \
- llvm::DIType *Id##Ty = nullptr;
+#define EXT_OPAQUE_TYPE(ExtType, Id, Ext) llvm::DIType *Id##Ty = nullptr;
#include "clang/Basic/OpenCLExtensionTypes.def"
#define WASM_TYPE(Name, Id, SingletonId) llvm::DIType *SingletonId = nullptr;
#include "clang/Basic/WebAssemblyReferenceTypes.def"
@@ -525,8 +524,8 @@ class CGDebugInfo {
/// Emit debug info for a function declaration.
/// \p Fn is set only when a declaration for a debug call site gets created.
- void EmitFunctionDecl(GlobalDecl GD, SourceLocation Loc,
- QualType FnType, llvm::Function *Fn = nullptr);
+ void EmitFunctionDecl(GlobalDecl GD, SourceLocation Loc, QualType FnType,
+ llvm::Function *Fn = nullptr);
/// Emit debug info for an extern function being called.
/// This is needed for call site debug info.
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index 130b5a9717710..a2ecab083db68 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -106,9 +106,12 @@ llvm::fp::ExceptionBehavior
clang::ToConstrainedExceptMD(LangOptions::FPExceptionModeKind Kind) {
switch (Kind) {
- case LangOptions::FPE_Ignore: return llvm::fp::ebIgnore;
- case LangOptions::FPE_MayTrap: return llvm::fp::ebMayTrap;
- case LangOptions::FPE_Strict: return llvm::fp::ebStrict;
+ case LangOptions::FPE_Ignore:
+ return llvm::fp::ebIgnore;
+ case LangOptions::FPE_MayTrap:
+ return llvm::fp::ebMayTrap;
+ case LangOptions::FPE_Strict:
+ return llvm::fp::ebStrict;
default:
llvm_unreachable("Unsupported FP Exception Behavior");
}
@@ -166,8 +169,7 @@ void CodeGenFunction::CGFPOptionsRAII::ConstructorHelper(FPOptions FPFeatures) {
"FPConstrained should be enabled on entire function");
auto mergeFnAttrValue = [&](StringRef Name, bool Value) {
- auto OldValue =
- CGF.CurFn->getFnAttribute(Name).getValueAsBool();
+ auto OldValue = CGF.CurFn->getFnAttribute(Name).getValueAsBool();
auto NewValue = OldValue & Value;
if (OldValue != NewValue)
CGF.CurFn->addFnAttr(Name, llvm::toStringRef(NewValue));
@@ -205,8 +207,8 @@ CodeGenFunction::MakeNaturalAlignAddrLValue(llvm::Value *V, QualType T,
IsKnownNonNull);
}
-LValue
-CodeGenFunction::MakeNaturalAlignPointeeAddrLValue(llvm::Value *V, QualType T) {
+LValue CodeGenFunction::MakeNaturalAlignPointeeAddrLValue(llvm::Value *V,
+ QualType T) {
return ::makeNaturalAlignAddrLValue(V, T, /*ForPointeeType*/ true,
/*MightBeSigned*/ true, *this);
}
@@ -342,7 +344,8 @@ llvm::DebugLoc CodeGenFunction::EmitReturnBlock() {
}
static void EmitIfUsed(CodeGenFunction &CGF, llvm::BasicBlock *BB) {
- if (!BB) return;
+ if (!BB)
+ return;
if (!BB->use_empty()) {
CGF.CurFn->insert(CGF.CurFn->end(), BB);
return;
@@ -364,9 +367,9 @@ void CodeGenFunction::FinishFunction(SourceLocation EndLoc) {
"mismatched push/pop in convergence stack!");
}
- bool OnlySimpleReturnStmts = NumSimpleReturnExprs > 0
- && NumSimpleReturnExprs == NumReturnExprs
- && ReturnBlock.getBlock()->use_empty();
+ bool OnlySimpleReturnStmts = NumSimpleReturnExprs > 0 &&
+ NumSimpleReturnExprs == NumReturnExprs &&
+ ReturnBlock.getBlock()->use_empty();
// Usually the return expression is evaluated before the cleanup
// code. If the function contains only a simple return statement,
// such as a constant, the location before the cleanup code becomes
@@ -434,8 +437,7 @@ void CodeGenFunction::FinishFunction(SourceLocation EndLoc) {
RetKeyInstructionsAtomGroup);
EmitEndEHSpec(CurCodeDecl);
- assert(EHStack.empty() &&
- "did not remove all scopes from cleanup stack!");
+ assert(EHStack.empty() && "did not remove all scopes from cleanup stack!");
// If someone did an indirect goto, emit the indirect goto block at the end of
// the function.
@@ -645,7 +647,8 @@ void CodeGenFunction::EmitKernelMetadata(const FunctionDecl *FD,
llvm::ConstantAsMetadata::get(Builder.getInt32(Eval(A->getXDim()))),
llvm::ConstantAsMetadata::get(Builder.getInt32(Eval(A->getYDim()))),
llvm::ConstantAsMetadata::get(Builder.getInt32(Eval(A->getZDim())))};
- Fn->setMetadata("work_group_size_hint", llvm::MDNode::get(Context, AttrMDArgs));
+ Fn->setMetadata("work_group_size_hint",
+ llvm::MDNode::get(Context, AttrMDArgs));
}
if (const ReqdWorkGroupSizeAttr *A = FD->getAttr<ReqdWorkGroupSizeAttr>()) {
@@ -656,7 +659,8 @@ void CodeGenFunction::EmitKernelMetadata(const FunctionDecl *FD,
llvm::ConstantAsMetadata::get(Builder.getInt32(Eval(A->getXDim()))),
llvm::ConstantAsMetadata::get(Builder.getInt32(Eval(A->getYDim()))),
llvm::ConstantAsMetadata::get(Builder.getInt32(Eval(A->getZDim())))};
- Fn->setMetadata("reqd_work_group_size", llvm::MDNode::get(Context, AttrMDArgs));
+ Fn->setMetadata("reqd_work_group_size",
+ llvm::MDNode::get(Context, AttrMDArgs));
}
if (const OpenCLIntelReqdSubGroupSizeAttr *A =
@@ -669,7 +673,7 @@ void CodeGenFunction::EmitKernelMetadata(const FunctionDecl *FD,
}
/// Determine whether the function F ends with a return stmt.
-static bool endsWithReturn(const Decl* F) {
+static bool endsWithReturn(const Decl *F) {
const Stmt *Body = nullptr;
if (auto *FD = dyn_cast_or_null<FunctionDecl>(F))
Body = FD->getBody();
@@ -859,7 +863,8 @@ void CodeGenFunction::StartFunction(GlobalDecl GD, QualType RetTy,
const IdentifierInfo *II = OMD->getSelector().getIdentifierInfoForSlot(0);
if (OMD->getMethodFamily() == OMF_dealloc ||
OMD->getMethodFamily() == OMF_initialize ||
- (OMD->getSelector().isUnarySelector() && II->isStr(".cxx_destruct"))) {
+ (OMD->getSelector().isUnarySelector() &&
+ II->isStr(".cxx_destruct"))) {
markAsIgnoreThreadCheckingAtRuntime(Fn);
}
}
@@ -1202,14 +1207,14 @@ void CodeGenFunction::StartFunction(GlobalDecl GD, QualType RetTy,
if (CGM.getCodeGenOpts().MNopMCount) {
if (!CGM.getCodeGenOpts().CallFEntry)
CGM.getDiags().Report(diag::err_opt_not_valid_without_opt)
- << "-mnop-mcount" << "-mfentry";
+ << "-mnop-mcount" << "-mfentry";
Fn->addFnAttr("mnop-mcount");
}
if (CGM.getCodeGenOpts().RecordMCount) {
if (!CGM.getCodeGenOpts().CallFEntry)
CGM.getDiags().Report(diag::err_opt_not_valid_without_opt)
- << "-mrecord-mcount" << "-mfentry";
+ << "-mrecord-mcount" << "-mfentry";
Fn->addFnAttr("mrecord-mcount");
}
}
@@ -1219,7 +1224,7 @@ void CodeGenFunction::StartFunction(GlobalDecl GD, QualType RetTy,
if (getContext().getTargetInfo().getTriple().getArch() !=
llvm::Triple::systemz)
CGM.getDiags().Report(diag::err_opt_not_valid_on_target)
- << "-mpacked-stack";
+ << "-mpacked-stack";
Fn->addFnAttr("packed-stack");
}
@@ -1259,8 +1264,8 @@ void CodeGenFunction::StartFunction(GlobalDecl GD, QualType RetTy,
unsigned Idx = CurFnInfo->getReturnInfo().getInAllocaFieldIndex();
llvm::Function::arg_iterator EI = CurFn->arg_end();
--EI;
- llvm::Value *Addr = Builder.CreateStructGEP(
- CurFnInfo->getArgStruct(), &*EI, Idx);
+ llvm::Value *Addr =
+ Builder.CreateStructGEP(CurFnInfo->getArgStruct(), &*EI, Idx);
llvm::Type *Ty =
cast<llvm::GetElementPtrInst>(Addr)->getResultElementType();
ReturnValuePointer = Address(Addr, Ty, getPointerAlign());
@@ -1273,8 +1278,7 @@ void CodeGenFunction::StartFunction(GlobalDecl GD, QualType RetTy,
// Tell the epilog emitter to autorelease the result. We do this
// now so that various specialized functions can suppress it
// during their IR-generation.
- if (getLangOpts().ObjCAutoRefCount &&
- !CurFnInfo->isReturnsRetained() &&
+ if (getLangOpts().ObjCAutoRefCount && !CurFnInfo->isReturnsRetained() &&
RetTy->isObjCRetainableType())
AutoreleaseResult = true;
}
@@ -1313,7 +1317,8 @@ void CodeGenFunction::StartFunction(GlobalDecl GD, QualType RetTy,
// Get the lvalue for the field (which is a copy of the enclosing object
// or contains the address of the enclosing object).
- LValue ThisFieldLValue = EmitLValueForLambdaField(LambdaThisCaptureField);
+ LValue ThisFieldLValue =
+ EmitLValueForLambdaField(LambdaThisCaptureField);
if (!LambdaThisCaptureField->getType()->isPointerType()) {
// If the enclosing object was captured by value, just use its
// address. Sign this pointer.
@@ -1321,14 +1326,15 @@ void CodeGenFunction::StartFunction(GlobalDecl GD, QualType RetTy,
} else {
// Load the lvalue pointed to by the field, since '*this' was captured
// by reference.
- CXXThisValue =
- EmitLoadOfLValue(ThisFieldLValue, SourceLocation()).getScalarVal();
+ CXXThisValue = EmitLoadOfLValue(ThisFieldLValue, SourceLocation())
+ .getScalarVal();
}
}
for (auto *FD : MD->getParent()->fields()) {
if (FD->hasCapturedVLAType()) {
- auto *ExprArg = EmitLoadOfLValue(EmitLValueForLambdaField(FD),
- SourceLocation()).getScalarVal();
+ auto *ExprArg =
+ EmitLoadOfLValue(EmitLValueForLambdaField(FD), SourceLocation())
+ .getScalarVal();
auto VAT = FD->getCapturedVLAType();
VLASizeMap[VAT->getSizeExpr()] = ExprArg;
}
@@ -1426,7 +1432,8 @@ void CodeGenFunction::EmitBlockWithFallThrough(llvm::BasicBlock *BB,
static void TryMarkNoThrow(llvm::Function *F) {
// LLVM treats 'nounwind' on a function as part of the type, so we
// can't do this on functions that can be overwritten.
- if (F->isInterposable()) return;
+ if (F->isInterposable())
+ return;
for (llvm::BasicBlock &BB : *F)
for (llvm::Instruction &I : BB)
@@ -1597,8 +1604,7 @@ void CodeGenFunction::GenerateCode(GlobalDecl GD, llvm::Function *Fn,
EmitDestructorBody(Args);
else if (isa<CXXConstructorDecl>(FD))
EmitConstructorBody(Args);
- else if (getLangOpts().CUDA &&
- !getLangOpts().CUDAIsDevice &&
+ else if (getLangOpts().CUDA && !getLangOpts().CUDAIsDevice &&
FD->hasAttr<CUDAGlobalAttr>())
CGM.getCUDARuntime().emitDeviceStub(*this, Args);
else if (isa<CXXMethodDecl>(FD) &&
@@ -1702,7 +1708,8 @@ void CodeGenFunction::GenerateCode(GlobalDecl GD, llvm::Function *Fn,
/// that we can just remove the code.
bool CodeGenFunction::ContainsLabel(const Stmt *S, bool IgnoreCaseStmts) {
// Null statement, not a label!
- if (!S) return false;
+ if (!S)
+ return false;
// If this is a label, we have to emit the code, consider something like:
// if (0) { ... foo: bar(); } goto foo;
@@ -1734,7 +1741,8 @@ bool CodeGenFunction::ContainsLabel(const Stmt *S, bool IgnoreCaseStmts) {
/// inside of it, this is fine.
bool CodeGenFunction::containsBreak(const Stmt *S) {
// Null statement, not a label!
- if (!S) return false;
+ if (!S)
+ return false;
// If this is a switch or loop that defines its own break scope, then we can
// include it and anything inside of it.
@@ -1754,7 +1762,8 @@ bool CodeGenFunction::containsBreak(const Stmt *S) {
}
bool CodeGenFunction::mightAddDeclToScope(const Stmt *S) {
- if (!S) return false;
+ if (!S)
+ return false;
// Some statement kinds add a scope and thus never add a decl to the current
// scope. Note, this list is longer than the list of statements that might
@@ -1807,11 +1816,11 @@ bool CodeGenFunction::ConstantFoldsToSimpleInteger(const Expr *Cond,
// to bool.
Expr::EvalResult Result;
if (!Cond->EvaluateAsInt(Result, getContext()))
- return false; // Not foldable, not integer or not fully evaluatable.
+ return false; // Not foldable, not integer or not fully evaluatable.
llvm::APSInt Int = Result.Val.getInt();
if (!AllowLabels && CodeGenFunction::ContainsLabel(Cond))
- return false; // Contains a label.
+ return false; // Contains a label.
PGO->markStmtMaybeUsed(Cond);
ResultInt = std::move(Int);
@@ -2129,7 +2138,7 @@ void CodeGenFunction::EmitBranchOnBoolExpr(
// br(c ? throw x : y, t, f) -> br(c, br(throw x, t, f), br(y, t, f)
// Fold this to:
// br(c, throw x, br(y, t, f))
- EmitCXXThrowExpr(Throw, /*KeepInsertionPoint*/false);
+ EmitCXXThrowExpr(Throw, /*KeepInsertionPoint*/ false);
return;
}
@@ -2249,8 +2258,8 @@ static void emitNonZeroVLAInit(CodeGenFunction &CGF, QualType baseType,
CGBuilderTy &Builder = CGF.Builder;
CharUnits baseSize = CGF.getContext().getTypeSizeInChars(baseType);
- llvm::Value *baseSizeInChars
- = llvm::ConstantInt::get(CGF.IntPtrTy, baseSize.getQuantity());
+ llvm::Value *baseSizeInChars =
+ llvm::ConstantInt::get(CGF.IntPtrTy, baseSize.getQuantity());
Address begin = dest.withElementType(CGF.Int8Ty);
llvm::Value *end = Builder.CreateInBoundsGEP(begin.getElementType(),
@@ -2268,8 +2277,7 @@ static void emitNonZeroVLAInit(CodeGenFunction &CGF, QualType baseType,
llvm::PHINode *cur = Builder.CreatePHI(begin.getType(), 2, "vla.cur");
cur->addIncoming(begin.emitRawPointer(CGF), originBB);
- CharUnits curAlign =
- dest.getAlignment().alignmentOfArrayElement(baseSize);
+ CharUnits curAlign = dest.getAlignment().alignmentOfArrayElement(baseSize);
// memcpy the individual element bit-pattern.
Builder.CreateMemCpy(Address(cur, CGF.Int8Ty, curAlign), src, baseSizeInChars,
@@ -2277,7 +2285,7 @@ static void emitNonZeroVLAInit(CodeGenFunction &CGF, QualType baseType,
// Go to the next element.
llvm::Value *next =
- Builder.CreateInBoundsGEP(CGF.Int8Ty, cur, baseSizeInChars, "vla.next");
+ Builder.CreateInBoundsGEP(CGF.Int8Ty, cur, baseSizeInChars, "vla.next");
// Leave if that's the end of the VLA.
llvm::Value *done = Builder.CreateICmpEQ(next, end, "vla-init.isdone");
@@ -2317,8 +2325,7 @@ Address CodeGenFunction::EmitAddressOfPFPField(Address RecordPtr,
VoidPtrTy, PtrPtr.getAlignment());
}
-void
-CodeGenFunction::EmitNullInitialization(Address DestPtr, QualType Ty) {
+void CodeGenFunction::EmitNullInitialization(Address DestPtr, QualType Ty) {
// Ignore empty classes in C++.
if (getLangOpts().CPlusPlus)
if (const auto *RD = Ty->getAsCXXRecordDecl(); RD && RD->isEmpty())
@@ -2336,9 +2343,8 @@ CodeGenFunction::EmitNullInitialization(Address DestPtr, QualType Ty) {
// Don't bother emitting a zero-byte memset.
if (size.isZero()) {
// But note that getTypeInfo returns 0 for a VLA.
- if (const VariableArrayType *vlaType =
- dyn_cast_or_null<VariableArrayType>(
- getContext().getAsArrayType(Ty))) {
+ if (const VariableArrayType *vlaType = dyn_cast_or_null<VariableArrayType>(
+ getContext().getAsArrayType(Ty))) {
auto VlaSize = getVLASize(vlaType);
SizeVal = VlaSize.NumElts;
CharUnits eltSize = getContext().getTypeSizeInChars(VlaSize.Type);
@@ -2359,20 +2365,21 @@ CodeGenFunction::EmitNullInitialization(Address DestPtr, QualType Ty) {
// like -1, which happens to be the pattern used by member-pointers.
if (!CGM.getTypes().isZeroInitializable(Ty)) {
// For a VLA, emit a single element, then splat that over the VLA.
- if (vla) Ty = getContext().getBaseElementType(vla);
+ if (vla)
+ Ty = getContext().getBaseElementType(vla);
llvm::Constant *NullConstant = CGM.EmitNullConstant(Ty);
- llvm::GlobalVariable *NullVariable =
- new llvm::GlobalVariable(CGM.getModule(), NullConstant->getType(),
- /*isConstant=*/true,
- llvm::GlobalVariable::PrivateLinkage,
- NullConstant, Twine());
+ llvm::GlobalVariable *NullVariable = new llvm::GlobalVariable(
+ CGM.getModule(), NullConstant->getType(),
+ /*isConstant=*/true, llvm::GlobalVariable::PrivateLinkage, NullConstant,
+ Twine());
CharUnits NullAlign = DestPtr.getAlignment();
NullVariable->setAlignment(NullAlign.getAsAlign());
Address SrcPtr(NullVariable, Builder.getInt8Ty(), NullAlign);
- if (vla) return emitNonZeroVLAInit(*this, Ty, DestPtr, SrcPtr, SizeVal);
+ if (vla)
+ return emitNonZeroVLAInit(*this, Ty, DestPtr, SrcPtr, SizeVal);
// Get and call the appropriate llvm.memcpy overload.
Builder.CreateMemCpy(DestPtr, SrcPtr, SizeVal, false);
@@ -2406,13 +2413,14 @@ llvm::BlockAddress *CodeGenFunction::GetAddrOfLabel(const LabelDecl *L) {
llvm::BasicBlock *CodeGenFunction::GetIndirectGotoBlock() {
// If we already made the indirect branch for indirect goto, return its block.
- if (IndirectBranch) return IndirectBranch->getParent();
+ if (IndirectBranch)
+ return IndirectBranch->getParent();
CGBuilderTy TmpBuilder(CGM, createBasicBlock("indirectgoto"));
// Create the PHI node that indirect gotos will add entries to.
- llvm::Value *DestVal = TmpBuilder.CreatePHI(Int8PtrTy, 0,
- "indirect.goto.dest");
+ llvm::Value *DestVal =
+ TmpBuilder.CreatePHI(Int8PtrTy, 0, "indirect.goto.dest");
// Create the indirect branch instruction.
IndirectBranch = TmpBuilder.CreateIndirectBr(DestVal);
@@ -2452,7 +2460,7 @@ llvm::Value *CodeGenFunction::emitArrayLength(const ArrayType *origArrayType,
// We have some number of constant-length arrays, so addr should
// have LLVM type [M x [N x [...]]]*. Build a GEP that walks
// down to the first element of addr.
- SmallVector<llvm::Value*, 8> gepIndices;
+ SmallVector<llvm::Value *, 8> gepIndices;
// GEP down to the array type.
llvm::ConstantInt *zero = Builder.getInt32(0);
@@ -2462,7 +2470,7 @@ llvm::Value *CodeGenFunction::emitArrayLength(const ArrayType *origArrayType,
QualType eltType;
llvm::ArrayType *llvmArrayType =
- dyn_cast<llvm::ArrayType>(addr.getElementType());
+ dyn_cast<llvm::ArrayType>(addr.getElementType());
while (llvmArrayType) {
assert(isa<ConstantArrayType>(arrayType));
assert(cast<ConstantArrayType>(arrayType)->getZExtSize() ==
@@ -2472,8 +2480,7 @@ llvm::Value *CodeGenFunction::emitArrayLength(const ArrayType *origArrayType,
countFromCLAs *= llvmArrayType->getNumElements();
eltType = arrayType->getElementType();
- llvmArrayType =
- dyn_cast<llvm::ArrayType>(llvmArrayType->getElementType());
+ llvmArrayType = dyn_cast<llvm::ArrayType>(llvmArrayType->getElementType());
arrayType = getContext().getAsArrayType(arrayType->getElementType());
assert((!llvmArrayType || arrayType) &&
"LLVM and Clang types are out-of-synch");
@@ -2501,8 +2508,7 @@ llvm::Value *CodeGenFunction::emitArrayLength(const ArrayType *origArrayType,
baseType = eltType;
- llvm::Value *numElements
- = llvm::ConstantInt::get(SizeTy, countFromCLAs);
+ llvm::Value *numElements = llvm::ConstantInt::get(SizeTy, countFromCLAs);
// If we had any VLA dimensions, factor them in.
if (numVLAElements)
@@ -2538,11 +2544,10 @@ CodeGenFunction::getVLASize(const VariableArrayType *type) {
}
} while ((type = getContext().getAsVariableArrayType(elementType)));
- return { numElements, elementType };
+ return {numElements, elementType};
}
-CodeGenFunction::VlaSizePair
-CodeGenFunction::getVLAElements1D(QualType type) {
+CodeGenFunction::VlaSizePair CodeGenFunction::getVLAElements1D(QualType type) {
const VariableArrayType *vla = getContext().getAsVariableArrayType(type);
assert(vla && "type was not a variable array type!");
return getVLAElements1D(vla);
@@ -2553,7 +2558,7 @@ CodeGenFunction::getVLAElements1D(const VariableArrayType *Vla) {
llvm::Value *VlaSize = VLASizeMap[Vla->getSizeExpr()];
assert(VlaSize && "no size for VLA!");
assert(VlaSize->getType() == SizeTy);
- return { VlaSize, Vla->getElementType() };
+ return {VlaSize, Vla->getElementType()};
}
void CodeGenFunction::EmitVariablyModifiedType(QualType type) {
@@ -2717,7 +2722,7 @@ void CodeGenFunction::EmitVariablyModifiedType(QualType type) {
} while (type->isVariablyModifiedType());
}
-Address CodeGenFunction::EmitVAListRef(const Expr* E) {
+Address CodeGenFunction::EmitVAListRef(const Expr *E) {
if (getContext().getBuiltinVaListType()->isArrayType())
return EmitPointerWithAlignment(E);
return EmitLValue(E).getAddress();
@@ -2745,9 +2750,11 @@ CodeGenFunction::protectFromPeepholes(RValue rvalue) {
// is trunc(zext) folding, but if we add more, we can easily
// extend this protection.
- if (!rvalue.isScalar()) return PeepholeProtection();
+ if (!rvalue.isScalar())
+ return PeepholeProtection();
llvm::Value *value = rvalue.getScalarVal();
- if (!isa<llvm::ZExtInst>(value)) return PeepholeProtection();
+ if (!isa<llvm::ZExtInst>(value))
+ return PeepholeProtection();
// Just make an extra bitcast.
assert(HaveInsertPoint());
@@ -2760,7 +2767,8 @@ CodeGenFunction::protectFromPeepholes(RValue rvalue) {
}
void CodeGenFunction::unprotectFromPeepholes(PeepholeProtection protection) {
- if (!protection.Inst) return;
+ if (!protection.Inst)
+ return;
// In theory, we could try to duplicate the peepholes now, but whatever.
protection.Inst->eraseFromParent();
@@ -2867,7 +2875,7 @@ Address CodeGenFunction::EmitFieldAnnotations(const FieldDecl *D,
return Address(V, Addr.getElementType(), Addr.getAlignment());
}
-CodeGenFunction::CGCapturedStmtInfo::~CGCapturedStmtInfo() { }
+CodeGenFunction::CGCapturedStmtInfo::~CGCapturedStmtInfo() {}
CodeGenFunction::SanitizerScope::SanitizerScope(CodeGenFunction *CGF)
: CGF(CGF) {
More information about the cfe-commits
mailing list