[clang] [llvm] [RISCV] Add Tenstorrent Ascalon XG (PR #229030)

[Min-Yih Hsu via cfe-commits]

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@@ -0,0 +1,116 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64-unknown-unknown -mcpu=tt-ascalon-xg --iterations=1 < %s | FileCheck %s
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mshockwave wrote:

please use `-instruction-tables=full` for new scheduling model tests.

https://github.com/llvm/llvm-project/pull/229030