[clang] [CIR] Upstream missing support for floating point unary operator (PR #193215)
Haocong Lu via cfe-commits
cfe-commits at lists.llvm.org
Thu Oct 1 04:07:06 PDT 2026
https://github.com/Luhaocong updated https://github.com/llvm/llvm-project/pull/193215
>From e279d95e8a953f72ef5a6d55f90fefc495b15a9a Mon Sep 17 00:00:00 2001
From: Haocong Lu <haocong.lu at witintech.com>
Date: Sat, 5 Sep 2026 13:25:08 +0800
Subject: [PATCH 1/6] [CIR] Upstream missing support for floating point unary
operator
- Add Support for `__bf16/Float16/bfloat16/float128` scalar
pre/post increment and decrement.
- Add support for float vector increment and decrement.
- Add test case for `__bf16/Float16/bfloat16/double/long double/float128`
unary operator with target `x86_64`.
- Add test case for interger/float vector increment and decrement
with target `powerpc64le + altivec`.
---
clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp | 72 +-
.../CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp | 5 +-
clang/lib/CodeGen/CGExprScalar.cpp | 15 +-
.../CIR/CodeGen/unary-inc-dec-unsupport.cpp | 11 +
.../test/CIR/CodeGen/unary-inc-dec-vector.cpp | 153 ++++
clang/test/CIR/CodeGen/unary.cpp | 695 +++++++++++++++++-
6 files changed, 889 insertions(+), 62 deletions(-)
create mode 100644 clang/test/CIR/CodeGen/unary-inc-dec-unsupport.cpp
create mode 100644 clang/test/CIR/CodeGen/unary-inc-dec-vector.cpp
diff --git a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
index 80e8b36dfda6bfe..359034c5a9bb958 100644
--- a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
@@ -767,7 +767,7 @@ class ScalarExprEmitter : public StmtVisitor<ScalarExprEmitter, mlir::Value> {
value = emitIncDecConsiderOverflowBehavior(e, value);
} else {
// NOTE(CIR): clang calls CreateAdd but folds this to a unary op
- value = emitIncOrDec(e, input, /*nsw=*/false);
+ value = emitIntIncOrDec(e, input, /*nsw=*/false);
}
} else if (const PointerType *ptr = type->getAs<PointerType>()) {
QualType type = ptr->getPointeeType();
@@ -789,32 +789,14 @@ class ScalarExprEmitter : public StmtVisitor<ScalarExprEmitter, mlir::Value> {
}
} else if (type->isVectorType()) {
if (type->hasIntegerRepresentation()) {
- value = emitIncOrDec(e, input, /*nsw=*/false);
+ value = emitIntIncOrDec(e, input, /*nsw=*/false);
} else {
- cgf.cgm.errorNYI(e->getSourceRange(), "Unary inc/dec vector of float");
- return {};
+ CIRGenFunction::CIRGenFPOptionsRAII FPOptsRAII(cgf, e);
+ value = emitFloatIncOrDec(e, input);
}
} else if (type->isRealFloatingType()) {
CIRGenFunction::CIRGenFPOptionsRAII FPOptsRAII(cgf, e);
-
- if (type->isHalfType() &&
- !cgf.getContext().getLangOpts().NativeHalfType) {
- cgf.cgm.errorNYI(e->getSourceRange(), "Unary inc/dec half");
- return {};
- }
-
- if (mlir::isa<cir::SingleType, cir::DoubleType, cir::LongDoubleType>(
- value.getType())) {
- mlir::Location loc = cgf.getLoc(e->getExprLoc());
- auto fpType = mlir::cast<cir::FPTypeInterface>(value.getType());
- mlir::Value amount = builder.getConstFP(
- loc, value.getType(), llvm::APFloat(fpType.getFloatSemantics(), 1));
- value = e->isIncrementOp() ? builder.createFAdd(loc, value, amount)
- : builder.createFSub(loc, value, amount);
- } else {
- cgf.cgm.errorNYI(e->getSourceRange(), "Unary inc/dec other fp type");
- return {};
- }
+ value = emitFloatIncOrDec(e, input);
} else if (type->isFixedPointType()) {
value = emitFixedPointIncDec(e, value, type);
} else {
@@ -840,13 +822,13 @@ class ScalarExprEmitter : public StmtVisitor<ScalarExprEmitter, mlir::Value> {
mlir::Value inVal) {
switch (cgf.getLangOpts().getSignedOverflowBehavior()) {
case LangOptions::SOB_Defined:
- return emitIncOrDec(e, inVal, /*nsw=*/false);
+ return emitIntIncOrDec(e, inVal, /*nsw=*/false);
case LangOptions::SOB_Undefined:
assert(!cir::MissingFeatures::sanitizers());
- return emitIncOrDec(e, inVal, /*nsw=*/true);
+ return emitIntIncOrDec(e, inVal, /*nsw=*/true);
case LangOptions::SOB_Trapping:
if (!e->canOverflow())
- return emitIncOrDec(e, inVal, /*nsw=*/true);
+ return emitIntIncOrDec(e, inVal, /*nsw=*/true);
cgf.cgm.errorNYI(e->getSourceRange(), "inc/def overflow SOB_Trapping");
return {};
}
@@ -912,14 +894,48 @@ class ScalarExprEmitter : public StmtVisitor<ScalarExprEmitter, mlir::Value> {
return builder.createOrFold<cir::MinusOp>(loc, operand, nsw);
}
- mlir::Value emitIncOrDec(const UnaryOperator *e, mlir::Value input,
- bool nsw = false) {
+ mlir::Value emitIntIncOrDec(const UnaryOperator *e, mlir::Value input,
+ bool nsw = false) {
mlir::Location loc = cgf.getLoc(e->getSourceRange().getBegin());
return e->isIncrementOp()
? builder.createOrFold<cir::IncOp>(loc, input, nsw)
: builder.createOrFold<cir::DecOp>(loc, input, nsw);
}
+ mlir::Value emitFloatIncOrDec(const UnaryOperator *e, mlir::Value input) {
+ assert(cir::isFPOrVectorOfFPType(input.getType()) &&
+ "Expect floating-point operand");
+ mlir::Location loc = cgf.getLoc(e->getSourceRange().getBegin());
+
+ if (auto vecType = mlir::dyn_cast<cir::VectorType>(input.getType())) {
+ mlir::Type fpScalarType = vecType.getElementType();
+ auto fpInterface = mlir::cast<cir::FPTypeInterface>(fpScalarType);
+ mlir::Value amount = builder.getConstFP(
+ loc, fpScalarType, llvm::APFloat(fpInterface.getFloatSemantics(), 1));
+ amount = cir::VecSplatOp::create(builder, loc, vecType, amount);
+ return e->isIncrementOp() ? builder.createFAdd(loc, input, amount)
+ : builder.createFSub(loc, input, amount);
+ } else {
+ QualType type = e->getSubExpr()->getType();
+ // Another special case: half FP increment should be done via float.
+ if (type->isHalfType() && !cgf.getContext().getLangOpts().NativeHalfType)
+ input = builder.createFloatingCast(input, builder.getSingleTy());
+
+ auto fpInterface = mlir::cast<cir::FPTypeInterface>(input.getType());
+ mlir::Value amount =
+ builder.getConstFP(loc, input.getType(),
+ llvm::APFloat(fpInterface.getFloatSemantics(), 1));
+ mlir::Value output = e->isIncrementOp()
+ ? builder.createFAdd(loc, input, amount)
+ : builder.createFSub(loc, input, amount);
+
+ if (type->isHalfType() && !cgf.getContext().getLangOpts().NativeHalfType)
+ output = builder.createFloatingCast(output, builder.getFp16Ty());
+
+ return output;
+ }
+ }
+
mlir::Value VisitUnaryNot(const UnaryOperator *e) {
ignoreResultAssign = false;
mlir::Value op = Visit(e->getSubExpr());
diff --git a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
index 0d715e6023d044b..78a5def5c39148b 100644
--- a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+++ b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
@@ -3313,8 +3313,9 @@ lowerIncDecOp(CIROp op, typename CIROp::Adaptor adaptor,
auto maybeNSW = nswFlag(op.getNoSignedWrap());
mlir::LLVM::ConstantOp one;
if (mlir::isa<cir::VectorType>(op.getType())) {
- mlir::DenseIntElementsAttr oneVec = mlir::DenseIntElementsAttr::get(
- mlir::cast<mlir::ShapedType>(llvmType), 1);
+ mlir::ShapedType shapedTy = mlir::cast<mlir::ShapedType>(llvmType);
+ mlir::APInt oneAP(shapedTy.getElementTypeBitWidth(), 1);
+ auto oneVec = mlir::DenseElementsAttr::get(shapedTy, {oneAP});
one = mlir::LLVM::ConstantOp::create(rewriter, loc, llvmType, oneVec);
} else {
one = mlir::LLVM::ConstantOp::create(rewriter, loc, llvmType, 1);
diff --git a/clang/lib/CodeGen/CGExprScalar.cpp b/clang/lib/CodeGen/CGExprScalar.cpp
index a024562b82f201f..24c6b6c0c1ecedd 100644
--- a/clang/lib/CodeGen/CGExprScalar.cpp
+++ b/clang/lib/CodeGen/CGExprScalar.cpp
@@ -3554,12 +3554,9 @@ ScalarExprEmitter::EmitScalarPrePostIncDec(const UnaryOperator *E, LValue LV,
llvm::Value *amt;
CodeGenFunction::CGFPOptionsRAII FPOptsRAII(CGF, E);
- if (type->isHalfType() && !CGF.getContext().getLangOpts().NativeHalfType) {
- // Another special case: half FP increment should be done via float. If
- // the input isn't already half, it may be i16.
- Value *bitcast = Builder.CreateBitCast(input, CGF.CGM.HalfTy);
- value = Builder.CreateFPExt(bitcast, CGF.CGM.FloatTy, "incdec.conv");
- }
+ // Another special case: half FP increment should be done via float.
+ if (type->isHalfType() && !CGF.getContext().getLangOpts().NativeHalfType)
+ value = Builder.CreateFPExt(value, CGF.CGM.FloatTy, "incdec.conv");
if (value->getType()->isFloatTy())
amt = llvm::ConstantFP::get(VMContext,
@@ -3590,12 +3587,10 @@ ScalarExprEmitter::EmitScalarPrePostIncDec(const UnaryOperator *E, LValue LV,
}
value = Builder.CreateFAdd(value, amt, isInc ? "inc" : "dec");
- if (type->isHalfType() && !CGF.getContext().getLangOpts().NativeHalfType) {
+ if (type->isHalfType() && !CGF.getContext().getLangOpts().NativeHalfType)
value = Builder.CreateFPTrunc(value, CGF.CGM.HalfTy, "incdec.conv");
- value = Builder.CreateBitCast(value, input->getType());
- }
- // Fixed-point types.
+ // Fixed-point types.
} else if (type->isFixedPointType()) {
// Fixed-point types are tricky. In some cases, it isn't possible to
// represent a 1 or a -1 in the type at all. Piggyback off of
diff --git a/clang/test/CIR/CodeGen/unary-inc-dec-unsupport.cpp b/clang/test/CIR/CodeGen/unary-inc-dec-unsupport.cpp
new file mode 100644
index 000000000000000..58cf166eee2b981
--- /dev/null
+++ b/clang/test/CIR/CodeGen/unary-inc-dec-unsupport.cpp
@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -triple powerpc64le -fclangir -emit-cir -verify %s -o -
+
+// PPC fp128 (__ibm128) unary inc/dec is not yet supported, drop the errorNYI
+// and turn this into a regular test.
+
+__ibm128 g; // expected-error@*:* {{ClangIR code gen Not Yet Implemented: processing of built-in type: '__ibm128'}}
+
+void test_pre_inc() { ++g; }
+void test_pre_dec() { --g; }
+void test_post_inc() { g++; }
+void test_post_dec() { g--; }
diff --git a/clang/test/CIR/CodeGen/unary-inc-dec-vector.cpp b/clang/test/CIR/CodeGen/unary-inc-dec-vector.cpp
new file mode 100644
index 000000000000000..5b5bf72af369d42
--- /dev/null
+++ b/clang/test/CIR/CodeGen/unary-inc-dec-vector.cpp
@@ -0,0 +1,153 @@
+// RUN: %clang_cc1 -triple powerpc64le -target-feature +altivec -Wno-unused-value -fclangir -emit-cir %s -o %t.cir
+// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR
+// RUN: %clang_cc1 -triple powerpc64le -target-feature +altivec -Wno-unused-value -fclangir -emit-llvm %s -o %t-cir.ll
+// RUN: FileCheck --input-file=%t-cir.ll %s -check-prefix=LLVM
+// RUN: %clang_cc1 -triple powerpc64le -target-feature +altivec -Wno-unused-value -emit-llvm %s -o %t.ll
+// RUN: FileCheck --input-file=%t.ll %s -check-prefix=OGCG
+
+// Unary inc/dec on vector types, covering the CIRGenExprScalar.cpp vector
+// branch:
+// * integer vectors go through emitIntIncOrDec -> cir.inc/cir.dec
+// * float vectors go through emitFloatIncOrDec -> cir.fadd/cir.fsub
+
+typedef int vi4 __attribute__((vector_size(16)));
+typedef unsigned uvi4 __attribute__((vector_size(16)));
+typedef short vsh8 __attribute__((vector_size(16)));
+typedef float vf4 __attribute__((vector_size(16)));
+typedef double vd2 __attribute__((vector_size(16)));
+
+void vecIntIncDec(vi4 a) {
+ ++a;
+ --a;
+ a++;
+ a--;
+}
+// CIR-LABEL: @_Z12vecIntIncDecDv4_i
+// CIR: cir.inc %{{.+}} : !cir.vector<4 x !s32i>
+// CIR: cir.dec %{{.+}} : !cir.vector<4 x !s32i>
+// CIR: cir.inc %{{.+}} : !cir.vector<4 x !s32i>
+// CIR: cir.dec %{{.+}} : !cir.vector<4 x !s32i>
+
+// LLVM-LABEL: @_Z12vecIntIncDecDv4_i
+// LLVM: add <4 x i32> %{{.+}}, splat (i32 1)
+// LLVM: sub <4 x i32> %{{.+}}, splat (i32 1)
+// LLVM: add <4 x i32> %{{.+}}, splat (i32 1)
+// LLVM: sub <4 x i32> %{{.+}}, splat (i32 1)
+
+// OGCG-LABEL: @_Z12vecIntIncDecDv4_i
+// OGCG: add <4 x i32> %{{.+}}, splat (i32 1)
+// OGCG: add <4 x i32> %{{.+}}, splat (i32 -1)
+// OGCG: add <4 x i32> %{{.+}}, splat (i32 1)
+// OGCG: add <4 x i32> %{{.+}}, splat (i32 -1)
+
+void vecUIntIncDec(uvi4 b) {
+ ++b;
+ --b;
+ b++;
+ b--;
+}
+// CIR-LABEL: @_Z13vecUIntIncDecDv4_j
+// CIR: cir.inc %{{.+}} : !cir.vector<4 x !u32i>
+// CIR: cir.dec %{{.+}} : !cir.vector<4 x !u32i>
+// CIR: cir.inc %{{.+}} : !cir.vector<4 x !u32i>
+// CIR: cir.dec %{{.+}} : !cir.vector<4 x !u32i>
+
+// LLVM-LABEL: @_Z13vecUIntIncDecDv4_j
+// LLVM: add <4 x i32> %{{.+}}, splat (i32 1)
+// LLVM: sub <4 x i32> %{{.+}}, splat (i32 1)
+// LLVM: add <4 x i32> %{{.+}}, splat (i32 1)
+// LLVM: sub <4 x i32> %{{.+}}, splat (i32 1)
+
+// OGCG-LABEL: @_Z13vecUIntIncDecDv4_j
+// OGCG: add <4 x i32> %{{.+}}, splat (i32 1)
+// OGCG: add <4 x i32> %{{.+}}, splat (i32 -1)
+// OGCG: add <4 x i32> %{{.+}}, splat (i32 1)
+// OGCG: add <4 x i32> %{{.+}}, splat (i32 -1)
+
+void vecShortIncDec(vsh8 c) {
+ ++c;
+ --c;
+ c++;
+ c--;
+}
+// CIR-LABEL: @_Z14vecShortIncDecDv8_s
+// CIR: cir.inc %{{.+}} : !cir.vector<8 x !s16i>
+// CIR: cir.dec %{{.+}} : !cir.vector<8 x !s16i>
+// CIR: cir.inc %{{.+}} : !cir.vector<8 x !s16i>
+// CIR: cir.dec %{{.+}} : !cir.vector<8 x !s16i>
+
+// LLVM-LABEL: @_Z14vecShortIncDecDv8_s
+// LLVM: add <8 x i16> %{{.+}}, splat (i16 1)
+// LLVM: sub <8 x i16> %{{.+}}, splat (i16 1)
+// LLVM: add <8 x i16> %{{.+}}, splat (i16 1)
+// LLVM: sub <8 x i16> %{{.+}}, splat (i16 1)
+
+// OGCG-LABEL: @_Z14vecShortIncDecDv8_s
+// OGCG: add <8 x i16> %{{.+}}, splat (i16 1)
+// OGCG: add <8 x i16> %{{.+}}, splat (i16 -1)
+// OGCG: add <8 x i16> %{{.+}}, splat (i16 1)
+// OGCG: add <8 x i16> %{{.+}}, splat (i16 -1)
+
+void vecFloatIncDec(vf4 a) {
+ ++a;
+ --a;
+ a++;
+ a--;
+}
+// CIR-LABEL: @_Z14vecFloatIncDecDv4_f
+// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
+// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.float, !cir.vector<4 x !cir.float>
+// CIR: cir.fadd %{{.+}}, %[[ONEVEC]] : !cir.vector<4 x !cir.float>
+// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
+// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.float, !cir.vector<4 x !cir.float>
+// CIR: cir.fsub %{{.+}}, %[[ONEVEC]] : !cir.vector<4 x !cir.float>
+// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
+// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.float, !cir.vector<4 x !cir.float>
+// CIR: cir.fadd %{{.+}}, %[[ONEVEC]] : !cir.vector<4 x !cir.float>
+// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
+// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.float, !cir.vector<4 x !cir.float>
+// CIR: cir.fsub %{{.+}}, %[[ONEVEC]] : !cir.vector<4 x !cir.float>
+
+// LLVM-LABEL: @_Z14vecFloatIncDecDv4_f
+// LLVM: fadd <4 x float> %{{.+}}, splat (float 1.000000e+00)
+// LLVM: fsub <4 x float> %{{.+}}, splat (float 1.000000e+00)
+// LLVM: fadd <4 x float> %{{.+}}, splat (float 1.000000e+00)
+// LLVM: fsub <4 x float> %{{.+}}, splat (float 1.000000e+00)
+
+// OGCG-LABEL: @_Z14vecFloatIncDecDv4_f
+// OGCG: fadd <4 x float> %{{.+}}, splat (float 1.000000e+00)
+// OGCG: fadd <4 x float> %{{.+}}, splat (float -1.000000e+00)
+// OGCG: fadd <4 x float> %{{.+}}, splat (float 1.000000e+00)
+// OGCG: fadd <4 x float> %{{.+}}, splat (float -1.000000e+00)
+
+void vecDoubleIncDec(vd2 b) {
+ ++b;
+ --b;
+ b++;
+ b--;
+}
+// CIR-LABEL: @_Z15vecDoubleIncDecDv2_d
+// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
+// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.double, !cir.vector<2 x !cir.double>
+// CIR: cir.fadd %{{.+}}, %[[ONEVEC]] : !cir.vector<2 x !cir.double>
+// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
+// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.double, !cir.vector<2 x !cir.double>
+// CIR: cir.fsub %{{.+}}, %[[ONEVEC]] : !cir.vector<2 x !cir.double>
+// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
+// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.double, !cir.vector<2 x !cir.double>
+// CIR: cir.fadd %{{.+}}, %[[ONEVEC]] : !cir.vector<2 x !cir.double>
+// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
+// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.double, !cir.vector<2 x !cir.double>
+// CIR: cir.fsub %{{.+}}, %[[ONEVEC]] : !cir.vector<2 x !cir.double>
+
+// LLVM-LABEL: @_Z15vecDoubleIncDecDv2_d
+// LLVM: fadd <2 x double> %{{.+}}, splat (double 1.000000e+00)
+// LLVM: fsub <2 x double> %{{.+}}, splat (double 1.000000e+00)
+// LLVM: fadd <2 x double> %{{.+}}, splat (double 1.000000e+00)
+// LLVM: fsub <2 x double> %{{.+}}, splat (double 1.000000e+00)
+
+// OGCG-LABEL: @_Z15vecDoubleIncDecDv2_d
+// OGCG: fadd <2 x double> %{{.+}}, splat (double 1.000000e+00)
+// OGCG: fadd <2 x double> %{{.+}}, splat (double -1.000000e+00)
+// OGCG: fadd <2 x double> %{{.+}}, splat (double 1.000000e+00)
+// OGCG: fadd <2 x double> %{{.+}}, splat (double -1.000000e+00)
diff --git a/clang/test/CIR/CodeGen/unary.cpp b/clang/test/CIR/CodeGen/unary.cpp
index 03b068a68d06607..84a07691ce85be4 100644
--- a/clang/test/CIR/CodeGen/unary.cpp
+++ b/clang/test/CIR/CodeGen/unary.cpp
@@ -222,6 +222,24 @@ int inc2() {
// OGCG: store i32 %[[A_LOAD]], ptr %[[B]], align 4
// OGCG: %[[B_TO_OUTPUT:.*]] = load i32, ptr %[[B]], align 4
+void chars(char c) {
+// CHECK: cir.func{{.*}} @_Z5charsc
+
+ int c1 = +c;
+ // CHECK: %[[PROMO:.*]] = cir.cast integral %{{.+}} : !s8i -> !s32i
+ int c2 = -c;
+ // CHECK: %[[PROMO:.*]] = cir.cast integral %{{.+}} : !s8i -> !s32i
+ // CHECK: cir.minus nsw %[[PROMO]] : !s32i
+
+ // Chars can go through some integer promotion codegen paths even when not promoted.
+ // These should not have nsw attributes because the intermediate promotion makes the
+ // overflow defined behavior.
+ ++c; // CHECK: cir.inc %{{.+}} : !s8i
+ --c; // CHECK: cir.dec %{{.+}} : !s8i
+ c++; // CHECK: cir.inc %{{.+}} : !s8i
+ c--; // CHECK: cir.dec %{{.+}} : !s8i
+}
+
float fpPlus() {
float a = 1.0f;
return +a;
@@ -409,65 +427,698 @@ float fpPostInc2() {
// OGCG: store float %[[A_LOAD]], ptr %[[B]], align 4
// OGCG: %[[B_TO_OUTPUT:.*]] = load float, ptr %[[B]], align 4
-void chars(char c) {
-// CHECK: cir.func{{.*}} @_Z5charsc
+// double unary operations
+double doubleUPlus(double f) {
+ return +f;
+}
- int c1 = +c;
- // CHECK: %[[PROMO:.*]] = cir.cast integral %{{.+}} : !s8i -> !s32i
- int c2 = -c;
- // CHECK: %[[PROMO:.*]] = cir.cast integral %{{.+}} : !s8i -> !s32i
- // CHECK: cir.minus nsw %[[PROMO]] : !s32i
+// CHECK: cir.func{{.*}} @_Z11doubleUPlusd({{.*}}) -> (!cir.double{{.*}})
+// CHECK: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
+// CHECK: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
- // Chars can go through some integer promotion codegen paths even when not promoted.
- // These should not have nsw attributes because the intermediate promotion makes the
- // overflow defined behavior.
- ++c; // CHECK: cir.inc %{{.+}} : !s8i
- --c; // CHECK: cir.dec %{{.+}} : !s8i
- c++; // CHECK: cir.inc %{{.+}} : !s8i
- c--; // CHECK: cir.dec %{{.+}} : !s8i
+// LLVM: define{{.*}} double @_Z11doubleUPlusd({{.*}})
+// LLVM: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
+
+// OGCG: define{{.*}} double @_Z11doubleUPlusd({{.*}})
+// OGCG: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
+
+double doubleUMinus(double f) {
+ return -f;
+}
+
+// CHECK: cir.func{{.*}} @_Z12doubleUMinusd({{.*}}) -> (!cir.double{{.*}})
+// CHECK: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
+// CHECK: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
+// CHECK: %[[DBL_NEGATED:.*]] = cir.fneg %[[DBL_LOAD]]
+
+// LLVM: define{{.*}} double @_Z12doubleUMinusd({{.*}})
+// LLVM: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
+// LLVM: %[[DBL_NEGATED:.*]] = fneg double %[[DBL_LOAD]]
+
+// OGCG: define{{.*}} double @_Z12doubleUMinusd({{.*}})
+// OGCG: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
+// OGCG: %[[DBL_NEGATED:.*]] = fneg double %[[DBL_LOAD]]
+
+double doubleUPreInc(double f) {
+ return ++f;
+}
+
+// CHECK: cir.func{{.*}} @_Z13doubleUPreIncd({{.*}}) -> (!cir.double{{.*}})
+// CHECK: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
+// CHECK: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
+// CHECK: %[[DBL_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
+// CHECK: %[[DBL_INC:.*]] = cir.fadd %[[DBL_LOAD]], %[[DBL_ONE]]
+
+// LLVM: define{{.*}} double @_Z13doubleUPreIncd({{.*}})
+// LLVM: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
+// LLVM: %[[DBL_INC:.*]] = fadd double %[[DBL_LOAD]], 1.000000e+00
+
+// OGCG: define{{.*}} double @_Z13doubleUPreIncd({{.*}})
+// OGCG: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
+// OGCG: %[[DBL_INC:.*]] = fadd double %[[DBL_LOAD]], 1.000000e+00
+
+double doubleUPreDec(double f) {
+ return --f;
+}
+
+// CHECK: cir.func{{.*}} @_Z13doubleUPreDecd({{.*}}) -> (!cir.double{{.*}})
+// CHECK: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
+// CHECK: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
+// CHECK: %[[DBL_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
+// CHECK: %[[DBL_DEC:.*]] = cir.fsub %[[DBL_LOAD]], %[[DBL_ONE]]
+
+// LLVM: define{{.*}} double @_Z13doubleUPreDecd({{.*}})
+// LLVM: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
+// LLVM: %[[DBL_DEC:.*]] = fsub double %[[DBL_LOAD]], 1.000000e+00
+
+// OGCG: define{{.*}} double @_Z13doubleUPreDecd({{.*}})
+// OGCG: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
+// OGCG: %[[DBL_DEC:.*]] = fadd double %[[DBL_LOAD]], -1.000000e+00
+
+double doubleUPostInc(double f) {
+ return f++;
+}
+
+// CHECK: cir.func{{.*}} @_Z14doubleUPostIncd({{.*}}) -> (!cir.double{{.*}})
+// CHECK: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
+// CHECK: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
+// CHECK: %[[DBL_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
+// CHECK: %[[DBL_INC:.*]] = cir.fadd %[[DBL_LOAD]], %[[DBL_ONE]]
+
+// LLVM: define{{.*}} double @_Z14doubleUPostIncd({{.*}})
+// LLVM: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
+// LLVM: %[[DBL_INC:.*]] = fadd double %[[DBL_LOAD]], 1.000000e+00
+
+// OGCG: define{{.*}} double @_Z14doubleUPostIncd({{.*}})
+// OGCG: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
+// OGCG: %[[DBL_INC:.*]] = fadd double %[[DBL_LOAD]], 1.000000e+00
+
+double doubleUPostDec(double f) {
+ return f--;
+}
+
+// CHECK: cir.func{{.*}} @_Z14doubleUPostDecd({{.*}}) -> (!cir.double{{.*}})
+// CHECK: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
+// CHECK: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
+// CHECK: %[[DBL_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
+// CHECK: %[[DBL_DEC:.*]] = cir.fsub %[[DBL_LOAD]], %[[DBL_ONE]]
+
+// LLVM: define{{.*}} double @_Z14doubleUPostDecd({{.*}})
+// LLVM: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
+// LLVM: %[[DBL_DEC:.*]] = fsub double %[[DBL_LOAD]], 1.000000e+00
+
+// OGCG: define{{.*}} double @_Z14doubleUPostDecd({{.*}})
+// OGCG: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
+// OGCG: %[[DBL_DEC:.*]] = fadd double %[[DBL_LOAD]], -1.000000e+00
+
+// long double unary operations
+long double ldUPlus(long double f) {
+ return +f;
+}
+
+// CHECK: cir.func{{.*}} @_Z7ldUPluse({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
+// CHECK: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
+// CHECK: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
+
+// LLVM: define{{.*}} x86_fp80 @_Z7ldUPluse({{.*}})
+// LLVM: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
+
+// OGCG: define{{.*}} x86_fp80 @_Z7ldUPluse({{.*}})
+// OGCG: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
+
+long double ldUMinus(long double f) {
+ return -f;
+}
+
+// CHECK: cir.func{{.*}} @_Z8ldUMinuse({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
+// CHECK: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
+// CHECK: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
+// CHECK: %[[LD_NEGATED:.*]] = cir.fneg %[[LD_LOAD]]
+
+// LLVM: define{{.*}} x86_fp80 @_Z8ldUMinuse({{.*}})
+// LLVM: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
+// LLVM: %[[LD_NEGATED:.*]] = fneg x86_fp80 %[[LD_LOAD]]
+
+// OGCG: define{{.*}} x86_fp80 @_Z8ldUMinuse({{.*}})
+// OGCG: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
+// OGCG: %[[LD_NEGATED:.*]] = fneg x86_fp80 %[[LD_LOAD]]
+
+long double ldUPreInc(long double f) {
+ return ++f;
+}
+
+// CHECK: cir.func{{.*}} @_Z9ldUPreInce({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
+// CHECK: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
+// CHECK: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
+// CHECK: %[[LD_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.long_double<!cir.f80>
+// CHECK: %[[LD_INC:.*]] = cir.fadd %[[LD_LOAD]], %[[LD_ONE]]
+
+// LLVM: define{{.*}} x86_fp80 @_Z9ldUPreInce({{.*}})
+// LLVM: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
+// LLVM: %[[LD_INC:.*]] = fadd x86_fp80 %[[LD_LOAD]], 1.000000e+00
+
+// OGCG: define{{.*}} x86_fp80 @_Z9ldUPreInce({{.*}})
+// OGCG: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
+// OGCG: %[[LD_INC:.*]] = fadd x86_fp80 %[[LD_LOAD]], 1.000000e+00
+
+long double ldUPreDec(long double f) {
+ return --f;
+}
+
+// CHECK: cir.func{{.*}} @_Z9ldUPreDece({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
+// CHECK: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
+// CHECK: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
+// CHECK: %[[LD_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.long_double<!cir.f80>
+// CHECK: %[[LD_DEC:.*]] = cir.fsub %[[LD_LOAD]], %[[LD_ONE]]
+
+// LLVM: define{{.*}} x86_fp80 @_Z9ldUPreDece({{.*}})
+// LLVM: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
+// LLVM: %[[LD_DEC:.*]] = fsub x86_fp80 %[[LD_LOAD]], 1.000000e+00
+
+// OGCG: define{{.*}} x86_fp80 @_Z9ldUPreDece({{.*}})
+// OGCG: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
+// OGCG: %[[LD_DEC:.*]] = fadd x86_fp80 %[[LD_LOAD]], -1.000000e+00
+
+long double ldUPostInc(long double f) {
+ return f++;
+}
+
+// CHECK: cir.func{{.*}} @_Z10ldUPostInce({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
+// CHECK: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
+// CHECK: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
+// CHECK: %[[LD_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.long_double<!cir.f80>
+// CHECK: %[[LD_INC:.*]] = cir.fadd %[[LD_LOAD]], %[[LD_ONE]]
+
+// LLVM: define{{.*}} x86_fp80 @_Z10ldUPostInce({{.*}})
+// LLVM: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
+// LLVM: %[[LD_INC:.*]] = fadd x86_fp80 %[[LD_LOAD]], 1.000000e+00
+
+// OGCG: define{{.*}} x86_fp80 @_Z10ldUPostInce({{.*}})
+// OGCG: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
+// OGCG: %[[LD_INC:.*]] = fadd x86_fp80 %[[LD_LOAD]], 1.000000e+00
+
+long double ldUPostDec(long double f) {
+ return f--;
+}
+
+// CHECK: cir.func{{.*}} @_Z10ldUPostDece({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
+// CHECK: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
+// CHECK: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
+// CHECK: %[[LD_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.long_double<!cir.f80>
+// CHECK: %[[LD_DEC:.*]] = cir.fsub %[[LD_LOAD]], %[[LD_ONE]]
+
+// LLVM: define{{.*}} x86_fp80 @_Z10ldUPostDece({{.*}})
+// LLVM: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
+// LLVM: %[[LD_DEC:.*]] = fsub x86_fp80 %[[LD_LOAD]], 1.000000e+00
+
+// OGCG: define{{.*}} x86_fp80 @_Z10ldUPostDece({{.*}})
+// OGCG: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
+// OGCG: %[[LD_DEC:.*]] = fadd x86_fp80 %[[LD_LOAD]], -1.000000e+00
+
+// __float128 unary operations
+__float128 f128UPlus(__float128 f) {
+ return +f;
+}
+
+// CHECK: cir.func{{.*}} @_Z9f128UPlusg({{.*}}) -> (!cir.f128{{.*}})
+// CHECK: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
+// CHECK: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
+
+// LLVM: define{{.*}} fp128 @_Z9f128UPlusg({{.*}})
+// LLVM: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
+
+// OGCG: define{{.*}} fp128 @_Z9f128UPlusg({{.*}})
+// OGCG: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
+
+__float128 f128UMinus(__float128 f) {
+ return -f;
+}
+
+// CHECK: cir.func{{.*}} @_Z10f128UMinusg({{.*}}) -> (!cir.f128{{.*}})
+// CHECK: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
+// CHECK: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
+// CHECK: %[[F128_NEG:.*]] = cir.fneg %[[F128_LOAD]]
+
+// LLVM: define{{.*}} fp128 @_Z10f128UMinusg({{.*}})
+// LLVM: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
+// LLVM: %[[F128_NEG:.*]] = fneg fp128 %[[F128_LOAD]]
+
+// OGCG: define{{.*}} fp128 @_Z10f128UMinusg({{.*}})
+// OGCG: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
+// OGCG: %[[F128_NEG:.*]] = fneg fp128 %[[F128_LOAD]]
+
+__float128 f128UPreInc(__float128 f) {
+ return ++f;
+}
+
+// CHECK: cir.func{{.*}} @_Z11f128UPreIncg({{.*}}) -> (!cir.f128{{.*}})
+// CHECK: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
+// CHECK: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
+// CHECK: %[[F128_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f128
+// CHECK: %[[F128_INC:.*]] = cir.fadd %[[F128_LOAD]], %[[F128_ONE]]
+
+// LLVM: define{{.*}} fp128 @_Z11f128UPreIncg({{.*}})
+// LLVM: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
+// LLVM: %[[F128_INC:.*]] = fadd fp128 %[[F128_LOAD]], 1.000000e+00
+
+// OGCG: define{{.*}} fp128 @_Z11f128UPreIncg({{.*}})
+// OGCG: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
+// OGCG: %[[F128_INC:.*]] = fadd fp128 %[[F128_LOAD]], 1.000000e+00
+
+__float128 f128UPreDec(__float128 f) {
+ return --f;
+}
+
+// CHECK: cir.func{{.*}} @_Z11f128UPreDecg({{.*}}) -> (!cir.f128{{.*}})
+// CHECK: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
+// CHECK: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
+// CHECK: %[[F128_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f128
+// CHECK: %[[F128_DEC:.*]] = cir.fsub %[[F128_LOAD]], %[[F128_ONE]]
+
+// LLVM: define{{.*}} fp128 @_Z11f128UPreDecg({{.*}})
+// LLVM: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
+// LLVM: %[[F128_DEC:.*]] = fsub fp128 %[[F128_LOAD]], 1.000000e+00
+
+// OGCG: define{{.*}} fp128 @_Z11f128UPreDecg({{.*}})
+// OGCG: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
+// OGCG: %[[F128_DEC:.*]] = fadd fp128 %[[F128_LOAD]], -1.000000e+00
+
+__float128 f128UPostInc(__float128 f) {
+ return f++;
+}
+
+// CHECK: cir.func{{.*}} @_Z12f128UPostIncg({{.*}}) -> (!cir.f128{{.*}})
+// CHECK: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
+// CHECK: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
+// CHECK: %[[F128_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f128
+// CHECK: %[[F128_INC:.*]] = cir.fadd %[[F128_LOAD]], %[[F128_ONE]]
+
+// LLVM: define{{.*}} fp128 @_Z12f128UPostIncg({{.*}})
+// LLVM: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
+// LLVM: %[[F128_INC:.*]] = fadd fp128 %[[F128_LOAD]], 1.000000e+00
+
+// OGCG: define{{.*}} fp128 @_Z12f128UPostIncg({{.*}})
+// OGCG: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
+// OGCG: %[[F128_INC:.*]] = fadd fp128 %[[F128_LOAD]], 1.000000e+00
+
+__float128 f128UPostDec(__float128 f) {
+ return f--;
}
-_Float16 fp16UPlus(_Float16 f) {
+// CHECK: cir.func{{.*}} @_Z12f128UPostDecg({{.*}}) -> (!cir.f128{{.*}})
+// CHECK: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
+// CHECK: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
+// CHECK: %[[F128_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f128
+// CHECK: %[[F128_DEC:.*]] = cir.fsub %[[F128_LOAD]], %[[F128_ONE]]
+
+// LLVM: define{{.*}} fp128 @_Z12f128UPostDecg({{.*}})
+// LLVM: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
+// LLVM: %[[F128_DEC:.*]] = fsub fp128 %[[F128_LOAD]], 1.000000e+00
+
+// OGCG: define{{.*}} fp128 @_Z12f128UPostDecg({{.*}})
+// OGCG: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
+// OGCG: %[[F128_DEC:.*]] = fadd fp128 %[[F128_LOAD]], -1.000000e+00
+
+// Float16 unary operations
+_Float16 Float16UPlus(_Float16 f) {
return +f;
}
-// CHECK: cir.func{{.*}} @_Z9fp16UPlusDF16_({{.*}}) -> (!cir.f16{{.*}})
+// CHECK: cir.func{{.*}} @_Z12Float16UPlusDF16_({{.*}}) -> (!cir.f16{{.*}})
// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[F:.*]]
// CHECK: %[[PROMOTED:.*]] = cir.cast floating %[[INPUT]] : !cir.f16 -> !cir.float
// CHECK: %[[UNPROMOTED:.*]] = cir.cast floating %[[PROMOTED]] : !cir.float -> !cir.f16
-// LLVM: define{{.*}} half @_Z9fp16UPlusDF16_({{.*}})
+// LLVM: define{{.*}} half @_Z12Float16UPlusDF16_({{.*}})
// LLVM: %[[F_LOAD:.*]] = load half, ptr %{{.*}}, align 2
// LLVM: %[[PROMOTED:.*]] = fpext half %[[F_LOAD]] to float
// LLVM: %[[UNPROMOTED:.*]] = fptrunc float %[[PROMOTED]] to half
-// OGCG: define{{.*}} half @_Z9fp16UPlusDF16_({{.*}})
+// OGCG: define{{.*}} half @_Z12Float16UPlusDF16_({{.*}})
// OGCG: %[[F_LOAD:.*]] = load half, ptr %{{.*}}, align 2
// OGCG: %[[PROMOTED:.*]] = fpext half %[[F_LOAD]] to float
// OGCG: %[[UNPROMOTED:.*]] = fptrunc float %[[PROMOTED]] to half
-_Float16 fp16UMinus(_Float16 f) {
+_Float16 Float16UMinus(_Float16 f) {
return -f;
}
-// CHECK: cir.func{{.*}} @_Z10fp16UMinusDF16_({{.*}}) -> (!cir.f16{{.*}})
+// CHECK: cir.func{{.*}} @_Z13Float16UMinusDF16_({{.*}}) -> (!cir.f16{{.*}})
// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[F:.*]]
// CHECK: %[[PROMOTED:.*]] = cir.cast floating %[[INPUT]] : !cir.f16 -> !cir.float
// CHECK: %[[RESULT:.*]] = cir.fneg %[[PROMOTED]]
// CHECK: %[[UNPROMOTED:.*]] = cir.cast floating %[[RESULT]] : !cir.float -> !cir.f16
-// LLVM: define{{.*}} half @_Z10fp16UMinusDF16_({{.*}})
+// LLVM: define{{.*}} half @_Z13Float16UMinusDF16_({{.*}})
// LLVM: %[[F_LOAD:.*]] = load half, ptr %{{.*}}, align 2
// LLVM: %[[PROMOTED:.*]] = fpext half %[[F_LOAD]] to float
// LLVM: %[[RESULT:.*]] = fneg float %[[PROMOTED]]
// LLVM: %[[UNPROMOTED:.*]] = fptrunc float %[[RESULT]] to half
-// OGCG: define{{.*}} half @_Z10fp16UMinusDF16_({{.*}})
+// OGCG: define{{.*}} half @_Z13Float16UMinusDF16_({{.*}})
// OGCG: %[[F_LOAD:.*]] = load half, ptr %{{.*}}, align 2
// OGCG: %[[PROMOTED:.*]] = fpext half %[[F_LOAD]] to float
// OGCG: %[[RESULT:.*]] = fneg float %[[PROMOTED]]
// OGCG: %[[UNPROMOTED:.*]] = fptrunc float %[[RESULT]] to half
+_Float16 Float16UPreInc(_Float16 f) {
+ return ++f;
+}
+
+// CHECK: cir.func{{.*}} @_Z14Float16UPreIncDF16_({{.*}}) -> (!cir.f16{{.*}})
+// CHECK: %[[PREINC_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f16>
+// CHECK: %[[PREINC_INPUT:.*]] = cir.load{{.*}} %[[PREINC_F]]
+// CHECK: %[[PREINC_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f16
+// CHECK: %[[PREINC_RESULT:.*]] = cir.fadd %[[PREINC_INPUT]], %[[PREINC_ONE]] : !cir.f16
+
+// LLVM: define{{.*}} half @_Z14Float16UPreIncDF16_({{.*}})
+// LLVM: %[[PREINC_F_ADDR:.*]] = alloca half, align 2
+// LLVM: %[[PREINC_INPUT:.*]] = load half, ptr %[[PREINC_F_ADDR]], align 2
+// LLVM: %[[PREINC_RESULT:.*]] = fadd half %[[PREINC_INPUT]], 1.000000e+00
+
+// OGCG: define{{.*}} half @_Z14Float16UPreIncDF16_({{.*}})
+// OGCG: %[[PREINC_F_ADDR:.*]] = alloca half, align 2
+// OGCG: %[[PREINC_INPUT:.*]] = load half, ptr %[[PREINC_F_ADDR]], align 2
+// OGCG: %[[PREINC_RESULT:.*]] = fadd half %[[PREINC_INPUT]], 1.000000e+00
+
+_Float16 Float16UPreDec(_Float16 f) {
+ return --f;
+}
+
+// CHECK: cir.func{{.*}} @_Z14Float16UPreDecDF16_({{.*}}) -> (!cir.f16{{.*}})
+// CHECK: %[[PREDEC_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f16>
+// CHECK: %[[PREDEC_INPUT:.*]] = cir.load{{.*}} %[[PREDEC_F]]
+// CHECK: %[[PREDEC_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f16
+// CHECK: %[[PREDEC_RESULT:.*]] = cir.fsub %[[PREDEC_INPUT]], %[[PREDEC_ONE]] : !cir.f16
+
+// LLVM: define{{.*}} half @_Z14Float16UPreDecDF16_({{.*}})
+// LLVM: %[[PREDEC_F_ADDR:.*]] = alloca half, align 2
+// LLVM: %[[PREDEC_INPUT:.*]] = load half, ptr %[[PREDEC_F_ADDR]], align 2
+// LLVM: %[[PREDEC_RESULT:.*]] = fsub half %[[PREDEC_INPUT]], 1.000000e+00
+
+// OGCG: define{{.*}} half @_Z14Float16UPreDecDF16_({{.*}})
+// OGCG: %[[PREDEC_F_ADDR:.*]] = alloca half, align 2
+// OGCG: %[[PREDEC_INPUT:.*]] = load half, ptr %[[PREDEC_F_ADDR]], align 2
+// OGCG: %[[PREDEC_RESULT:.*]] = fadd half %[[PREDEC_INPUT]], -1.000000e+00
+
+_Float16 Float16UPostInc(_Float16 f) {
+ return f++;
+}
+
+// CHECK: cir.func{{.*}} @_Z15Float16UPostIncDF16_({{.*}}) -> (!cir.f16{{.*}})
+// CHECK: %[[POSTINC_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f16>
+// CHECK: %[[POSTINC_INPUT:.*]] = cir.load{{.*}} %[[POSTINC_F]]
+// CHECK: %[[POSTINC_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f16
+// CHECK: %[[POSTINC_RESULT:.*]] = cir.fadd %[[POSTINC_INPUT]], %[[POSTINC_ONE]] : !cir.f16
+
+// LLVM: define{{.*}} half @_Z15Float16UPostIncDF16_({{.*}})
+// LLVM: %[[POSTINC_F_ADDR:.*]] = alloca half, align 2
+// LLVM: %[[POSTINC_INPUT:.*]] = load half, ptr %[[POSTINC_F_ADDR]], align 2
+// LLVM: %[[POSTINC_RESULT:.*]] = fadd half %[[POSTINC_INPUT]], 1.000000e+00
+
+// OGCG: define{{.*}} half @_Z15Float16UPostIncDF16_({{.*}})
+// OGCG: %[[POSTINC_F_ADDR:.*]] = alloca half, align 2
+// OGCG: %[[POSTINC_INPUT:.*]] = load half, ptr %[[POSTINC_F_ADDR]], align 2
+// OGCG: %[[POSTINC_RESULT:.*]] = fadd half %[[POSTINC_INPUT]], 1.000000e+00
+
+_Float16 Float16UPostDec(_Float16 f) {
+ return f--;
+}
+
+// CHECK: cir.func{{.*}} @_Z15Float16UPostDecDF16_({{.*}}) -> (!cir.f16{{.*}})
+// CHECK: %[[POSTDEC_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f16>
+// CHECK: %[[POSTDEC_INPUT:.*]] = cir.load{{.*}} %[[POSTDEC_F]]
+// CHECK: %[[POSTDEC_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f16
+// CHECK: %[[POSTDEC_RESULT:.*]] = cir.fsub %[[POSTDEC_INPUT]], %[[POSTDEC_ONE]] : !cir.f16
+
+// LLVM: define{{.*}} half @_Z15Float16UPostDecDF16_({{.*}})
+// LLVM: %[[POSTDEC_F_ADDR:.*]] = alloca half, align 2
+// LLVM: %[[POSTDEC_INPUT:.*]] = load half, ptr %[[POSTDEC_F_ADDR]], align 2
+// LLVM: %[[POSTDEC_RESULT:.*]] = fsub half %[[POSTDEC_INPUT]], 1.000000e+00
+
+// OGCG: define{{.*}} half @_Z15Float16UPostDecDF16_({{.*}})
+// OGCG: %[[POSTDEC_F_ADDR:.*]] = alloca half, align 2
+// OGCG: %[[POSTDEC_INPUT:.*]] = load half, ptr %[[POSTDEC_F_ADDR]], align 2
+// OGCG: %[[POSTDEC_RESULT:.*]] = fadd half %[[POSTDEC_INPUT]], -1.000000e+00
+
+// __fp16 unary operations
+void fp16PtrUPlus(__fp16 *f) {
+ *f = +(*f);
+}
+
+// CHECK: cir.func{{.*}} @_Z12fp16PtrUPlusPDh({{.*}})
+// CHECK: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
+// CHECK: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
+// CHECK: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
+// CHECK: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
+// CHECK: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_PROMOTED]] : !cir.float -> !cir.f16
+
+// LLVM: define{{.*}} void @_Z12fp16PtrUPlusPDh({{.*}})
+// LLVM: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
+// LLVM: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
+// LLVM: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_PROMOTED]] to half
+
+// OGCG: define{{.*}} void @_Z12fp16PtrUPlusPDh({{.*}})
+// OGCG: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
+// OGCG: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
+// OGCG: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_PROMOTED]] to half
+
+void fp16PtrUMinus(__fp16 *f) {
+ *f = -(*f);
+}
+
+// CHECK: cir.func{{.*}} @_Z13fp16PtrUMinusPDh({{.*}})
+// CHECK: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
+// CHECK: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
+// CHECK: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
+// CHECK: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
+// CHECK: %[[FPTR_NEGATED:.*]] = cir.fneg %[[FPTR_PROMOTED]]
+// CHECK: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_NEGATED]] : !cir.float -> !cir.f16
+
+// LLVM: define{{.*}} void @_Z13fp16PtrUMinusPDh({{.*}})
+// LLVM: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
+// LLVM: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
+// LLVM: %[[FPTR_NEGATED:.*]] = fneg float %[[FPTR_PROMOTED]]
+// LLVM: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_NEGATED]] to half
+
+// OGCG: define{{.*}} void @_Z13fp16PtrUMinusPDh({{.*}})
+// OGCG: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
+// OGCG: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
+// OGCG: %[[FPTR_NEGATED:.*]] = fneg float %[[FPTR_PROMOTED]]
+// OGCG: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_NEGATED]] to half
+
+void fp16PtrUPreInc(__fp16 *f) {
+ ++(*f);
+}
+
+// CHECK: cir.func{{.*}} @_Z14fp16PtrUPreIncPDh({{.*}})
+// CHECK: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
+// CHECK: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
+// CHECK: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
+// CHECK: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
+// CHECK: %[[FPTR_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
+// CHECK: %[[FPTR_INC:.*]] = cir.fadd %[[FPTR_PROMOTED]], %[[FPTR_ONE]] : !cir.float
+// CHECK: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_INC]] : !cir.float -> !cir.f16
+
+// LLVM: define{{.*}} void @_Z14fp16PtrUPreIncPDh({{.*}})
+// LLVM: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
+// LLVM: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
+// LLVM: %[[FPTR_INC:.*]] = fadd float %[[FPTR_PROMOTED]], 1.000000e+00
+// LLVM: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_INC]] to half
+
+// OGCG: define{{.*}} void @_Z14fp16PtrUPreIncPDh({{.*}})
+// OGCG: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
+// OGCG: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
+// OGCG: %[[FPTR_INC:.*]] = fadd float %[[FPTR_PROMOTED]], 1.000000e+00
+// OGCG: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_INC]] to half
+
+void fp16PtrUPreDec(__fp16 *f) {
+ --(*f);
+}
+
+// CHECK: cir.func{{.*}} @_Z14fp16PtrUPreDecPDh({{.*}})
+// CHECK: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
+// CHECK: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
+// CHECK: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
+// CHECK: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
+// CHECK: %[[FPTR_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
+// CHECK: %[[FPTR_DEC:.*]] = cir.fsub %[[FPTR_PROMOTED]], %[[FPTR_ONE]] : !cir.float
+// CHECK: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_DEC]] : !cir.float -> !cir.f16
+
+// LLVM: define{{.*}} void @_Z14fp16PtrUPreDecPDh({{.*}})
+// LLVM: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
+// LLVM: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
+// LLVM: %[[FPTR_DEC:.*]] = fsub float %[[FPTR_PROMOTED]], 1.000000e+00
+// LLVM: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_DEC]] to half
+
+// OGCG: define{{.*}} void @_Z14fp16PtrUPreDecPDh({{.*}})
+// OGCG: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
+// OGCG: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
+// OGCG: %[[FPTR_DEC:.*]] = fadd float %[[FPTR_PROMOTED]], -1.000000e+00
+// OGCG: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_DEC]] to half
+
+void fp16PtrUPostInc(__fp16 *f) {
+ (*f)++;
+}
+
+// CHECK: cir.func{{.*}} @_Z15fp16PtrUPostIncPDh({{.*}})
+// CHECK: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
+// CHECK: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
+// CHECK: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
+// CHECK: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
+// CHECK: %[[FPTR_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
+// CHECK: %[[FPTR_INC:.*]] = cir.fadd %[[FPTR_PROMOTED]], %[[FPTR_ONE]] : !cir.float
+// CHECK: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_DEC]] : !cir.float -> !cir.f16
+
+// LLVM: define{{.*}} void @_Z15fp16PtrUPostIncPDh({{.*}})
+// LLVM: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
+// LLVM: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
+// LLVM: %[[FPTR_INC:.*]] = fadd float %[[FPTR_PROMOTED]], 1.000000e+00
+// LLVM: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_INC]] to half
+
+// OGCG: define{{.*}} void @_Z15fp16PtrUPostIncPDh({{.*}})
+// OGCG: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
+// OGCG: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
+// OGCG: %[[FPTR_INC:.*]] = fadd float %[[FPTR_PROMOTED]], 1.000000e+00
+// OGCG: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_INC]] to half
+
+void fp16PtrUPostDec(__fp16 *f) {
+ (*f)--;
+}
+
+// CHECK: cir.func{{.*}} @_Z15fp16PtrUPostDecPDh({{.*}})
+// CHECK: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
+// CHECK: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
+// CHECK: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
+// CHECK: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
+// CHECK: %[[FPTR_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
+// CHECK: %[[FPTR_DEC:.*]] = cir.fsub %[[FPTR_PROMOTED]], %[[FPTR_ONE]] : !cir.float
+// CHECK: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_DEC]] : !cir.float -> !cir.f16
+
+// LLVM: define{{.*}} void @_Z15fp16PtrUPostDecPDh({{.*}})
+// LLVM: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
+// LLVM: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
+// LLVM: %[[FPTR_DEC:.*]] = fsub float %[[FPTR_PROMOTED]], 1.000000e+00
+// LLVM: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_DEC]] to half
+
+// OGCG: define{{.*}} void @_Z15fp16PtrUPostDecPDh({{.*}})
+// OGCG: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
+// OGCG: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
+// OGCG: %[[FPTR_DEC:.*]] = fadd float %[[FPTR_PROMOTED]], -1.000000e+00
+// OGCG: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_DEC]] to half
+
+// __bf16 unary operations
+__bf16 bf16UPlus(__bf16 f) {
+ return +f;
+}
+
+// CHECK: cir.func{{.*}} @_Z9bf16UPlusDF16b({{.*}}) -> (!cir.bf16{{.*}})
+// CHECK: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
+// CHECK: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
+// CHECK: %[[BF16_PROMOTED:.*]] = cir.cast floating %[[BF16_LOAD]] : !cir.bf16 -> !cir.float
+// CHECK: %[[BF16_UNPROMOTED:.*]] = cir.cast floating %[[BF16_PROMOTED]] : !cir.float -> !cir.bf16
+
+// LLVM: define{{.*}} bfloat @_Z9bf16UPlusDF16b({{.*}})
+// LLVM: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
+// LLVM: %[[BF16_PROMOTED:.*]] = fpext bfloat %[[BF16_LOAD]] to float
+// LLVM: %[[BF16_UNPROMOTED:.*]] = fptrunc float %[[BF16_PROMOTED]] to bfloat
+
+// OGCG: define{{.*}} bfloat @_Z9bf16UPlusDF16b({{.*}})
+// OGCG: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
+// OGCG: %[[BF16_PROMOTED:.*]] = fpext bfloat %[[BF16_LOAD]] to float
+// OGCG: %[[BF16_UNPROMOTED:.*]] = fptrunc float %[[BF16_PROMOTED]] to bfloat
+
+__bf16 bf16UMinus(__bf16 f) {
+ return -f;
+}
+
+// CHECK: cir.func{{.*}} @_Z10bf16UMinusDF16b({{.*}}) -> (!cir.bf16{{.*}})
+// CHECK: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
+// CHECK: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
+// CHECK: %[[BF16_PROMOTED:.*]] = cir.cast floating %[[BF16_LOAD]] : !cir.bf16 -> !cir.float
+// CHECK: %[[BF16_NEGATED:.*]] = cir.fneg %[[BF16_PROMOTED]]
+// CHECK: %[[BF16_UNPROMOTED:.*]] = cir.cast floating %[[BF16_NEGATED]] : !cir.float -> !cir.bf16
+
+// LLVM: define{{.*}} bfloat @_Z10bf16UMinusDF16b({{.*}})
+// LLVM: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
+// LLVM: %[[BF16_PROMOTED:.*]] = fpext bfloat %[[BF16_LOAD]] to float
+// LLVM: %[[BF16_NEGATED:.*]] = fneg float %[[BF16_PROMOTED]]
+// LLVM: %[[BF16_UNPROMOTED:.*]] = fptrunc float %[[BF16_NEGATED]] to bfloat
+
+// OGCG: define{{.*}} bfloat @_Z10bf16UMinusDF16b({{.*}})
+// OGCG: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
+// OGCG: %[[BF16_PROMOTED:.*]] = fpext bfloat %[[BF16_LOAD]] to float
+// OGCG: %[[BF16_NEGATED:.*]] = fneg float %[[BF16_PROMOTED]]
+// OGCG: %[[BF16_UNPROMOTED:.*]] = fptrunc float %[[BF16_NEGATED]] to bfloat
+
+__bf16 bf16UPreInc(__bf16 f) {
+ return ++f;
+}
+
+// CHECK: cir.func{{.*}} @_Z11bf16UPreIncDF16b({{.*}}) -> (!cir.bf16{{.*}})
+// CHECK: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
+// CHECK: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
+// CHECK: %[[BF16_INC:.*]] = cir.fadd %[[BF16_LOAD]], %{{.*}} : !cir.bf16
+
+// LLVM: define{{.*}} bfloat @_Z11bf16UPreIncDF16b({{.*}})
+// LLVM: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
+// LLVM: %[[BF16_INC:.*]] = fadd bfloat %[[BF16_LOAD]], 1.000000e+00
+
+// OGCG: define{{.*}} bfloat @_Z11bf16UPreIncDF16b({{.*}})
+// OGCG: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
+// OGCG: %[[BF16_INC:.*]] = fadd bfloat %[[BF16_LOAD]], 1.000000e+00
+
+__bf16 bf16UPreDec(__bf16 f) {
+ return --f;
+}
+
+// CHECK: cir.func{{.*}} @_Z11bf16UPreDecDF16b({{.*}}) -> (!cir.bf16{{.*}})
+// CHECK: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
+// CHECK: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
+// CHECK: %[[BF16_DEC:.*]] = cir.fsub %[[BF16_LOAD]], %{{.*}} : !cir.bf16
+
+// LLVM: define{{.*}} bfloat @_Z11bf16UPreDecDF16b({{.*}})
+// LLVM: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
+// LLVM: %[[BF16_DEC:.*]] = fsub bfloat %[[BF16_LOAD]], 1.000000e+00
+
+// OGCG: define{{.*}} bfloat @_Z11bf16UPreDecDF16b({{.*}})
+// OGCG: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
+// OGCG: %[[BF16_DEC:.*]] = fadd bfloat %[[BF16_LOAD]], -1.000000e+00
+
+__bf16 bf16UPostInc(__bf16 f) {
+ return f++;
+}
+
+// CHECK: cir.func{{.*}} @_Z12bf16UPostIncDF16b({{.*}}) -> (!cir.bf16{{.*}})
+// CHECK: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
+// CHECK: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
+// CHECK: %[[BF16_INC:.*]] = cir.fadd %[[BF16_LOAD]], %{{.*}} : !cir.bf16
+
+// LLVM: define{{.*}} bfloat @_Z12bf16UPostIncDF16b({{.*}})
+// LLVM: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
+// LLVM: %[[BF16_INC:.*]] = fadd bfloat %[[BF16_LOAD]], 1.000000e+00
+
+// OGCG: define{{.*}} bfloat @_Z12bf16UPostIncDF16b({{.*}})
+// OGCG: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
+// OGCG: %[[BF16_INC:.*]] = fadd bfloat %[[BF16_LOAD]], 1.000000e+00
+
+__bf16 bf16UPostDec(__bf16 f) {
+ return f--;
+}
+
+// CHECK: cir.func{{.*}} @_Z12bf16UPostDecDF16b({{.*}}) -> (!cir.bf16{{.*}})
+// CHECK: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
+// CHECK: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
+// CHECK: %[[BF16_DEC:.*]] = cir.fsub %[[BF16_LOAD]], %{{.*}} : !cir.bf16
+
+// LLVM: define{{.*}} bfloat @_Z12bf16UPostDecDF16b({{.*}})
+// LLVM: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
+// LLVM: %[[BF16_DEC:.*]] = fsub bfloat %[[BF16_LOAD]], 1.000000e+00
+
+// OGCG: define{{.*}} bfloat @_Z12bf16UPostDecDF16b({{.*}})
+// OGCG: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
+// OGCG: %[[BF16_DEC:.*]] = fadd bfloat %[[BF16_LOAD]], -1.000000e+00
+
void test_logical_not() {
int a = 5;
a = !a;
>From 6ea065ed22c47f72169415df342de7bcbee5bb71 Mon Sep 17 00:00:00 2001
From: Haocong Lu <haocong.lu at witintech.com>
Date: Wed, 9 Sep 2026 15:05:14 +0800
Subject: [PATCH 2/6] address comments
---
clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp | 20 +-
.../test/CIR/CodeGen/long-double-inc-dec.cpp | 12 +-
.../CIR/CodeGen/unary-inc-dec-unsupport.cpp | 11 -
.../test/CIR/CodeGen/unary-inc-dec-vector.cpp | 153 ----
clang/test/CIR/CodeGen/unary.cpp | 867 +++++++++++-------
5 files changed, 532 insertions(+), 531 deletions(-)
delete mode 100644 clang/test/CIR/CodeGen/unary-inc-dec-unsupport.cpp
delete mode 100644 clang/test/CIR/CodeGen/unary-inc-dec-vector.cpp
diff --git a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
index 359034c5a9bb958..5308475f490f6d8 100644
--- a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
@@ -910,11 +910,11 @@ class ScalarExprEmitter : public StmtVisitor<ScalarExprEmitter, mlir::Value> {
if (auto vecType = mlir::dyn_cast<cir::VectorType>(input.getType())) {
mlir::Type fpScalarType = vecType.getElementType();
auto fpInterface = mlir::cast<cir::FPTypeInterface>(fpScalarType);
- mlir::Value amount = builder.getConstFP(
- loc, fpScalarType, llvm::APFloat(fpInterface.getFloatSemantics(), 1));
- amount = cir::VecSplatOp::create(builder, loc, vecType, amount);
- return e->isIncrementOp() ? builder.createFAdd(loc, input, amount)
- : builder.createFSub(loc, input, amount);
+ auto amount = llvm::APFloat::getOne(fpInterface.getFloatSemantics(),
+ /*Negative=*/e->isDecrementOp());
+ mlir::Value amtValue = builder.getConstFP(loc, fpScalarType, amount);
+ amtValue = cir::VecSplatOp::create(builder, loc, vecType, amtValue);
+ return builder.createFAdd(loc, input, amtValue);
} else {
QualType type = e->getSubExpr()->getType();
// Another special case: half FP increment should be done via float.
@@ -922,12 +922,10 @@ class ScalarExprEmitter : public StmtVisitor<ScalarExprEmitter, mlir::Value> {
input = builder.createFloatingCast(input, builder.getSingleTy());
auto fpInterface = mlir::cast<cir::FPTypeInterface>(input.getType());
- mlir::Value amount =
- builder.getConstFP(loc, input.getType(),
- llvm::APFloat(fpInterface.getFloatSemantics(), 1));
- mlir::Value output = e->isIncrementOp()
- ? builder.createFAdd(loc, input, amount)
- : builder.createFSub(loc, input, amount);
+ auto amount = llvm::APFloat::getOne(fpInterface.getFloatSemantics(),
+ /*Negative=*/e->isDecrementOp());
+ mlir::Value amtValue = builder.getConstFP(loc, input.getType(), amount);
+ mlir::Value output = builder.createFAdd(loc, input, amtValue);
if (type->isHalfType() && !cgf.getContext().getLangOpts().NativeHalfType)
output = builder.createFloatingCast(output, builder.getFp16Ty());
diff --git a/clang/test/CIR/CodeGen/long-double-inc-dec.cpp b/clang/test/CIR/CodeGen/long-double-inc-dec.cpp
index daf71e5af5a4629..a5fa4ff40a7b206 100644
--- a/clang/test/CIR/CodeGen/long-double-inc-dec.cpp
+++ b/clang/test/CIR/CodeGen/long-double-inc-dec.cpp
@@ -85,15 +85,15 @@ extern "C" long double do_pre_dec(long double d) {
return --d;
// CIR: %[[ARG_LOAD:.*]] = cir.load {{.*}}%[[ARG_ALLOCA]] : !cir.ptr<!cir.long_double<![[LDTY]]>>, !cir.long_double<![[LDTY]]>
- // CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.long_double<![[LDTY]]>
- // CIR: %[[ARG_DEC:.*]] = cir.fsub %[[ARG_LOAD]], %[[ONE]]
+ // CIR: %[[NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.long_double<![[LDTY]]>
+ // CIR: %[[ARG_DEC:.*]] = cir.fadd %[[ARG_LOAD]], %[[NEGONE]]
// CIR: cir.store{{.*}} %[[ARG_DEC]], %[[ARG_ALLOCA]] : !cir.long_double<![[LDTY]]>, !cir.ptr<!cir.long_double<![[LDTY]]>>
// CIR: cir.store %[[ARG_DEC]], %[[RET_ALLOCA]] : !cir.long_double<![[LDTY]]>, !cir.ptr<!cir.long_double<![[LDTY]]>>
// CIR: %[[LOAD_RET:.*]] = cir.load %[[RET_ALLOCA]]
// CIR: cir.return %[[LOAD_RET]] : !cir.long_double<![[LDTY]]>
//
// LLVM: %[[ARG_LOAD:.*]] = load [[LDTY]], ptr %[[ARG_ALLOCA]]
- // LLVMCIR: %[[ARG_DEC:.*]] = fsub [[LDTY]] %[[ARG_LOAD]], 1.000000e+00
+ // LLVMCIR: %[[ARG_DEC:.*]] = fadd [[LDTY]] %[[ARG_LOAD]], -1.000000e+00
// OGCG: %[[ARG_DEC:.*]] = fadd [[LDTY]] %[[ARG_LOAD]], -1.000000e+00
// LLVM: store [[LDTY]] %[[ARG_DEC]], ptr %[[ARG_ALLOCA]]
// LLVMCIR: store [[LDTY]] %[[ARG_DEC]], ptr %[[RET_ALLOCA]]
@@ -112,15 +112,15 @@ extern "C" long double do_post_dec(long double d) {
return d--;
// CIR: %[[ARG_LOAD:.*]] = cir.load {{.*}}%[[ARG_ALLOCA]] : !cir.ptr<!cir.long_double<![[LDTY]]>>, !cir.long_double<![[LDTY]]>
- // CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.long_double<![[LDTY]]>
- // CIR: %[[ARG_DEC:.*]] = cir.fsub %[[ARG_LOAD]], %[[ONE]]
+ // CIR: %[[NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.long_double<![[LDTY]]>
+ // CIR: %[[ARG_DEC:.*]] = cir.fadd %[[ARG_LOAD]], %[[NEGONE]]
// CIR: cir.store{{.*}} %[[ARG_DEC]], %[[ARG_ALLOCA]] : !cir.long_double<![[LDTY]]>, !cir.ptr<!cir.long_double<![[LDTY]]>>
// CIR: cir.store %[[ARG_LOAD]], %[[RET_ALLOCA]] : !cir.long_double<![[LDTY]]>, !cir.ptr<!cir.long_double<![[LDTY]]>>
// CIR: %[[LOAD_RET:.*]] = cir.load %[[RET_ALLOCA]]
// CIR: cir.return %[[LOAD_RET]] : !cir.long_double<![[LDTY]]>
//
// LLVM: %[[ARG_LOAD:.*]] = load [[LDTY]], ptr %[[ARG_ALLOCA]]
- // LLVMCIR: %[[ARG_DEC:.*]] = fsub [[LDTY]] %[[ARG_LOAD]], 1.000000e+00
+ // LLVMCIR: %[[ARG_DEC:.*]] = fadd [[LDTY]] %[[ARG_LOAD]], -1.000000e+00
// OGCG: %[[ARG_DEC:.*]] = fadd [[LDTY]] %[[ARG_LOAD]], -1.000000e+00
// LLVM: store [[LDTY]] %[[ARG_DEC]], ptr %[[ARG_ALLOCA]]
// LLVMCIR: store [[LDTY]] %[[ARG_LOAD]], ptr %[[RET_ALLOCA]]
diff --git a/clang/test/CIR/CodeGen/unary-inc-dec-unsupport.cpp b/clang/test/CIR/CodeGen/unary-inc-dec-unsupport.cpp
deleted file mode 100644
index 58cf166eee2b981..000000000000000
--- a/clang/test/CIR/CodeGen/unary-inc-dec-unsupport.cpp
+++ /dev/null
@@ -1,11 +0,0 @@
-// RUN: %clang_cc1 -triple powerpc64le -fclangir -emit-cir -verify %s -o -
-
-// PPC fp128 (__ibm128) unary inc/dec is not yet supported, drop the errorNYI
-// and turn this into a regular test.
-
-__ibm128 g; // expected-error@*:* {{ClangIR code gen Not Yet Implemented: processing of built-in type: '__ibm128'}}
-
-void test_pre_inc() { ++g; }
-void test_pre_dec() { --g; }
-void test_post_inc() { g++; }
-void test_post_dec() { g--; }
diff --git a/clang/test/CIR/CodeGen/unary-inc-dec-vector.cpp b/clang/test/CIR/CodeGen/unary-inc-dec-vector.cpp
deleted file mode 100644
index 5b5bf72af369d42..000000000000000
--- a/clang/test/CIR/CodeGen/unary-inc-dec-vector.cpp
+++ /dev/null
@@ -1,153 +0,0 @@
-// RUN: %clang_cc1 -triple powerpc64le -target-feature +altivec -Wno-unused-value -fclangir -emit-cir %s -o %t.cir
-// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR
-// RUN: %clang_cc1 -triple powerpc64le -target-feature +altivec -Wno-unused-value -fclangir -emit-llvm %s -o %t-cir.ll
-// RUN: FileCheck --input-file=%t-cir.ll %s -check-prefix=LLVM
-// RUN: %clang_cc1 -triple powerpc64le -target-feature +altivec -Wno-unused-value -emit-llvm %s -o %t.ll
-// RUN: FileCheck --input-file=%t.ll %s -check-prefix=OGCG
-
-// Unary inc/dec on vector types, covering the CIRGenExprScalar.cpp vector
-// branch:
-// * integer vectors go through emitIntIncOrDec -> cir.inc/cir.dec
-// * float vectors go through emitFloatIncOrDec -> cir.fadd/cir.fsub
-
-typedef int vi4 __attribute__((vector_size(16)));
-typedef unsigned uvi4 __attribute__((vector_size(16)));
-typedef short vsh8 __attribute__((vector_size(16)));
-typedef float vf4 __attribute__((vector_size(16)));
-typedef double vd2 __attribute__((vector_size(16)));
-
-void vecIntIncDec(vi4 a) {
- ++a;
- --a;
- a++;
- a--;
-}
-// CIR-LABEL: @_Z12vecIntIncDecDv4_i
-// CIR: cir.inc %{{.+}} : !cir.vector<4 x !s32i>
-// CIR: cir.dec %{{.+}} : !cir.vector<4 x !s32i>
-// CIR: cir.inc %{{.+}} : !cir.vector<4 x !s32i>
-// CIR: cir.dec %{{.+}} : !cir.vector<4 x !s32i>
-
-// LLVM-LABEL: @_Z12vecIntIncDecDv4_i
-// LLVM: add <4 x i32> %{{.+}}, splat (i32 1)
-// LLVM: sub <4 x i32> %{{.+}}, splat (i32 1)
-// LLVM: add <4 x i32> %{{.+}}, splat (i32 1)
-// LLVM: sub <4 x i32> %{{.+}}, splat (i32 1)
-
-// OGCG-LABEL: @_Z12vecIntIncDecDv4_i
-// OGCG: add <4 x i32> %{{.+}}, splat (i32 1)
-// OGCG: add <4 x i32> %{{.+}}, splat (i32 -1)
-// OGCG: add <4 x i32> %{{.+}}, splat (i32 1)
-// OGCG: add <4 x i32> %{{.+}}, splat (i32 -1)
-
-void vecUIntIncDec(uvi4 b) {
- ++b;
- --b;
- b++;
- b--;
-}
-// CIR-LABEL: @_Z13vecUIntIncDecDv4_j
-// CIR: cir.inc %{{.+}} : !cir.vector<4 x !u32i>
-// CIR: cir.dec %{{.+}} : !cir.vector<4 x !u32i>
-// CIR: cir.inc %{{.+}} : !cir.vector<4 x !u32i>
-// CIR: cir.dec %{{.+}} : !cir.vector<4 x !u32i>
-
-// LLVM-LABEL: @_Z13vecUIntIncDecDv4_j
-// LLVM: add <4 x i32> %{{.+}}, splat (i32 1)
-// LLVM: sub <4 x i32> %{{.+}}, splat (i32 1)
-// LLVM: add <4 x i32> %{{.+}}, splat (i32 1)
-// LLVM: sub <4 x i32> %{{.+}}, splat (i32 1)
-
-// OGCG-LABEL: @_Z13vecUIntIncDecDv4_j
-// OGCG: add <4 x i32> %{{.+}}, splat (i32 1)
-// OGCG: add <4 x i32> %{{.+}}, splat (i32 -1)
-// OGCG: add <4 x i32> %{{.+}}, splat (i32 1)
-// OGCG: add <4 x i32> %{{.+}}, splat (i32 -1)
-
-void vecShortIncDec(vsh8 c) {
- ++c;
- --c;
- c++;
- c--;
-}
-// CIR-LABEL: @_Z14vecShortIncDecDv8_s
-// CIR: cir.inc %{{.+}} : !cir.vector<8 x !s16i>
-// CIR: cir.dec %{{.+}} : !cir.vector<8 x !s16i>
-// CIR: cir.inc %{{.+}} : !cir.vector<8 x !s16i>
-// CIR: cir.dec %{{.+}} : !cir.vector<8 x !s16i>
-
-// LLVM-LABEL: @_Z14vecShortIncDecDv8_s
-// LLVM: add <8 x i16> %{{.+}}, splat (i16 1)
-// LLVM: sub <8 x i16> %{{.+}}, splat (i16 1)
-// LLVM: add <8 x i16> %{{.+}}, splat (i16 1)
-// LLVM: sub <8 x i16> %{{.+}}, splat (i16 1)
-
-// OGCG-LABEL: @_Z14vecShortIncDecDv8_s
-// OGCG: add <8 x i16> %{{.+}}, splat (i16 1)
-// OGCG: add <8 x i16> %{{.+}}, splat (i16 -1)
-// OGCG: add <8 x i16> %{{.+}}, splat (i16 1)
-// OGCG: add <8 x i16> %{{.+}}, splat (i16 -1)
-
-void vecFloatIncDec(vf4 a) {
- ++a;
- --a;
- a++;
- a--;
-}
-// CIR-LABEL: @_Z14vecFloatIncDecDv4_f
-// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
-// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.float, !cir.vector<4 x !cir.float>
-// CIR: cir.fadd %{{.+}}, %[[ONEVEC]] : !cir.vector<4 x !cir.float>
-// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
-// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.float, !cir.vector<4 x !cir.float>
-// CIR: cir.fsub %{{.+}}, %[[ONEVEC]] : !cir.vector<4 x !cir.float>
-// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
-// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.float, !cir.vector<4 x !cir.float>
-// CIR: cir.fadd %{{.+}}, %[[ONEVEC]] : !cir.vector<4 x !cir.float>
-// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
-// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.float, !cir.vector<4 x !cir.float>
-// CIR: cir.fsub %{{.+}}, %[[ONEVEC]] : !cir.vector<4 x !cir.float>
-
-// LLVM-LABEL: @_Z14vecFloatIncDecDv4_f
-// LLVM: fadd <4 x float> %{{.+}}, splat (float 1.000000e+00)
-// LLVM: fsub <4 x float> %{{.+}}, splat (float 1.000000e+00)
-// LLVM: fadd <4 x float> %{{.+}}, splat (float 1.000000e+00)
-// LLVM: fsub <4 x float> %{{.+}}, splat (float 1.000000e+00)
-
-// OGCG-LABEL: @_Z14vecFloatIncDecDv4_f
-// OGCG: fadd <4 x float> %{{.+}}, splat (float 1.000000e+00)
-// OGCG: fadd <4 x float> %{{.+}}, splat (float -1.000000e+00)
-// OGCG: fadd <4 x float> %{{.+}}, splat (float 1.000000e+00)
-// OGCG: fadd <4 x float> %{{.+}}, splat (float -1.000000e+00)
-
-void vecDoubleIncDec(vd2 b) {
- ++b;
- --b;
- b++;
- b--;
-}
-// CIR-LABEL: @_Z15vecDoubleIncDecDv2_d
-// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
-// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.double, !cir.vector<2 x !cir.double>
-// CIR: cir.fadd %{{.+}}, %[[ONEVEC]] : !cir.vector<2 x !cir.double>
-// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
-// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.double, !cir.vector<2 x !cir.double>
-// CIR: cir.fsub %{{.+}}, %[[ONEVEC]] : !cir.vector<2 x !cir.double>
-// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
-// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.double, !cir.vector<2 x !cir.double>
-// CIR: cir.fadd %{{.+}}, %[[ONEVEC]] : !cir.vector<2 x !cir.double>
-// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
-// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.double, !cir.vector<2 x !cir.double>
-// CIR: cir.fsub %{{.+}}, %[[ONEVEC]] : !cir.vector<2 x !cir.double>
-
-// LLVM-LABEL: @_Z15vecDoubleIncDecDv2_d
-// LLVM: fadd <2 x double> %{{.+}}, splat (double 1.000000e+00)
-// LLVM: fsub <2 x double> %{{.+}}, splat (double 1.000000e+00)
-// LLVM: fadd <2 x double> %{{.+}}, splat (double 1.000000e+00)
-// LLVM: fsub <2 x double> %{{.+}}, splat (double 1.000000e+00)
-
-// OGCG-LABEL: @_Z15vecDoubleIncDecDv2_d
-// OGCG: fadd <2 x double> %{{.+}}, splat (double 1.000000e+00)
-// OGCG: fadd <2 x double> %{{.+}}, splat (double -1.000000e+00)
-// OGCG: fadd <2 x double> %{{.+}}, splat (double 1.000000e+00)
-// OGCG: fadd <2 x double> %{{.+}}, splat (double -1.000000e+00)
diff --git a/clang/test/CIR/CodeGen/unary.cpp b/clang/test/CIR/CodeGen/unary.cpp
index 84a07691ce85be4..06569d63bf48416 100644
--- a/clang/test/CIR/CodeGen/unary.cpp
+++ b/clang/test/CIR/CodeGen/unary.cpp
@@ -1,8 +1,8 @@
-// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -Wno-unused-value -emit-cir %s -o %t.cir
-// RUN: FileCheck --input-file=%t.cir %s
-// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -Wno-unused-value -emit-llvm %s -o %t-cir.ll
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fzvector -fclangir -Wno-unused-value -emit-cir %s -o %t.cir
+// RUN: FileCheck --input-file=%t.cir %s --check-prefix=CIR
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fzvector -fclangir -Wno-unused-value -emit-llvm %s -o %t-cir.ll
// RUN: FileCheck --input-file=%t-cir.ll %s --check-prefix=LLVM
-// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -Wno-unused-value -emit-llvm %s -o %t.ll
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fzvector -Wno-unused-value -emit-llvm %s -o %t.ll
// RUN: FileCheck --input-file=%t.ll %s --check-prefix=OGCG
unsigned up0() {
@@ -10,9 +10,9 @@ unsigned up0() {
return +a;
}
-// CHECK: cir.func{{.*}} @_Z3up0v() -> (!u32i{{.*}})
-// CHECK: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!u32i>
-// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
+// CIR: cir.func{{.*}} @_Z3up0v() -> (!u32i{{.*}})
+// CIR: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!u32i>
+// CIR: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
// LLVM: define{{.*}} i32 @_Z3up0v()
// LLVM: %[[RV:.*]] = alloca i32, align 4
@@ -30,10 +30,10 @@ unsigned um0() {
return -a;
}
-// CHECK: cir.func{{.*}} @_Z3um0v() -> (!u32i{{.*}})
-// CHECK: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!u32i>
-// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
-// CHECK: %[[OUTPUT:.*]] = cir.minus %[[INPUT]]
+// CIR: cir.func{{.*}} @_Z3um0v() -> (!u32i{{.*}})
+// CIR: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!u32i>
+// CIR: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
+// CIR: %[[OUTPUT:.*]] = cir.minus %[[INPUT]]
// LLVM: define{{.*}} i32 @_Z3um0v()
// LLVM: %[[RV:.*]] = alloca i32, align 4
@@ -53,10 +53,10 @@ unsigned un0() {
return ~a; // a ^ -1 , not
}
-// CHECK: cir.func{{.*}} @_Z3un0v() -> (!u32i{{.*}})
-// CHECK: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!u32i>
-// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
-// CHECK: %[[OUTPUT:.*]] = cir.not %[[INPUT]]
+// CIR: cir.func{{.*}} @_Z3un0v() -> (!u32i{{.*}})
+// CIR: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!u32i>
+// CIR: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
+// CIR: %[[OUTPUT:.*]] = cir.not %[[INPUT]]
// LLVM: define{{.*}} i32 @_Z3un0v()
// LLVM: %[[RV:.*]] = alloca i32, align 4
@@ -77,14 +77,14 @@ int inc0() {
return a;
}
-// CHECK: cir.func{{.*}} @_Z4inc0v() -> (!s32i{{.*}})
-// CHECK: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!s32i>
-// CHECK: %[[ATMP:.*]] = cir.const #cir.int<1> : !s32i
-// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !s32i
-// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
-// CHECK: %[[INCREMENTED:.*]] = cir.inc nsw %[[INPUT]]
-// CHECK: cir.store{{.*}} %[[INCREMENTED]], %[[A]]
-// CHECK: %[[A_TO_OUTPUT:.*]] = cir.load{{.*}} %[[A]]
+// CIR: cir.func{{.*}} @_Z4inc0v() -> (!s32i{{.*}})
+// CIR: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!s32i>
+// CIR: %[[ATMP:.*]] = cir.const #cir.int<1> : !s32i
+// CIR: cir.store{{.*}} %[[ATMP]], %[[A]] : !s32i
+// CIR: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
+// CIR: %[[INCREMENTED:.*]] = cir.inc nsw %[[INPUT]]
+// CIR: cir.store{{.*}} %[[INCREMENTED]], %[[A]]
+// CIR: %[[A_TO_OUTPUT:.*]] = cir.load{{.*}} %[[A]]
// LLVM: define{{.*}} i32 @_Z4inc0v()
// LLVM: %[[RV:.*]] = alloca i32, align 4
@@ -105,14 +105,14 @@ int dec0() {
return a;
}
-// CHECK: cir.func{{.*}} @_Z4dec0v() -> (!s32i{{.*}})
-// CHECK: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!s32i>
-// CHECK: %[[ATMP:.*]] = cir.const #cir.int<1> : !s32i
-// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !s32i
-// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
-// CHECK: %[[DECREMENTED:.*]] = cir.dec nsw %[[INPUT]]
-// CHECK: cir.store{{.*}} %[[DECREMENTED]], %[[A]]
-// CHECK: %[[A_TO_OUTPUT:.*]] = cir.load{{.*}} %[[A]]
+// CIR: cir.func{{.*}} @_Z4dec0v() -> (!s32i{{.*}})
+// CIR: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!s32i>
+// CIR: %[[ATMP:.*]] = cir.const #cir.int<1> : !s32i
+// CIR: cir.store{{.*}} %[[ATMP]], %[[A]] : !s32i
+// CIR: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
+// CIR: %[[DECREMENTED:.*]] = cir.dec nsw %[[INPUT]]
+// CIR: cir.store{{.*}} %[[DECREMENTED]], %[[A]]
+// CIR: %[[A_TO_OUTPUT:.*]] = cir.load{{.*}} %[[A]]
// LLVM: define{{.*}} i32 @_Z4dec0v()
// LLVM: %[[RV:.*]] = alloca i32, align 4
@@ -133,14 +133,14 @@ int inc1() {
return a;
}
-// CHECK: cir.func{{.*}} @_Z4inc1v() -> (!s32i{{.*}})
-// CHECK: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!s32i>
-// CHECK: %[[ATMP:.*]] = cir.const #cir.int<1> : !s32i
-// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !s32i
-// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
-// CHECK: %[[INCREMENTED:.*]] = cir.inc nsw %[[INPUT]]
-// CHECK: cir.store{{.*}} %[[INCREMENTED]], %[[A]]
-// CHECK: %[[A_TO_OUTPUT:.*]] = cir.load{{.*}} %[[A]]
+// CIR: cir.func{{.*}} @_Z4inc1v() -> (!s32i{{.*}})
+// CIR: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!s32i>
+// CIR: %[[ATMP:.*]] = cir.const #cir.int<1> : !s32i
+// CIR: cir.store{{.*}} %[[ATMP]], %[[A]] : !s32i
+// CIR: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
+// CIR: %[[INCREMENTED:.*]] = cir.inc nsw %[[INPUT]]
+// CIR: cir.store{{.*}} %[[INCREMENTED]], %[[A]]
+// CIR: %[[A_TO_OUTPUT:.*]] = cir.load{{.*}} %[[A]]
// LLVM: define{{.*}} i32 @_Z4inc1v()
// LLVM: %[[RV:.*]] = alloca i32, align 4
@@ -161,14 +161,14 @@ int dec1() {
return a;
}
-// CHECK: cir.func{{.*}} @_Z4dec1v() -> (!s32i{{.*}})
-// CHECK: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!s32i>
-// CHECK: %[[ATMP:.*]] = cir.const #cir.int<1> : !s32i
-// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !s32i
-// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
-// CHECK: %[[DECREMENTED:.*]] = cir.dec nsw %[[INPUT]]
-// CHECK: cir.store{{.*}} %[[DECREMENTED]], %[[A]]
-// CHECK: %[[A_TO_OUTPUT:.*]] = cir.load{{.*}} %[[A]]
+// CIR: cir.func{{.*}} @_Z4dec1v() -> (!s32i{{.*}})
+// CIR: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!s32i>
+// CIR: %[[ATMP:.*]] = cir.const #cir.int<1> : !s32i
+// CIR: cir.store{{.*}} %[[ATMP]], %[[A]] : !s32i
+// CIR: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
+// CIR: %[[DECREMENTED:.*]] = cir.dec nsw %[[INPUT]]
+// CIR: cir.store{{.*}} %[[DECREMENTED]], %[[A]]
+// CIR: %[[A_TO_OUTPUT:.*]] = cir.load{{.*}} %[[A]]
// LLVM: define{{.*}} i32 @_Z4dec1v()
// LLVM: %[[RV:.*]] = alloca i32, align 4
@@ -190,16 +190,16 @@ int inc2() {
return b;
}
-// CHECK: cir.func{{.*}} @_Z4inc2v() -> (!s32i{{.*}})
-// CHECK: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!s32i>
-// CHECK: %[[B:.*]] = cir.alloca "b" {{.*}} init : !cir.ptr<!s32i>
-// CHECK: %[[ATMP:.*]] = cir.const #cir.int<1> : !s32i
-// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !s32i
-// CHECK: %[[ATOB:.*]] = cir.load{{.*}} %[[A]]
-// CHECK: %[[INCREMENTED:.*]] = cir.inc nsw %[[ATOB]]
-// CHECK: cir.store{{.*}} %[[INCREMENTED]], %[[A]]
-// CHECK: cir.store{{.*}} %[[ATOB]], %[[B]]
-// CHECK: %[[B_TO_OUTPUT:.*]] = cir.load{{.*}} %[[B]]
+// CIR: cir.func{{.*}} @_Z4inc2v() -> (!s32i{{.*}})
+// CIR: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!s32i>
+// CIR: %[[B:.*]] = cir.alloca "b" {{.*}} init : !cir.ptr<!s32i>
+// CIR: %[[ATMP:.*]] = cir.const #cir.int<1> : !s32i
+// CIR: cir.store{{.*}} %[[ATMP]], %[[A]] : !s32i
+// CIR: %[[ATOB:.*]] = cir.load{{.*}} %[[A]]
+// CIR: %[[INCREMENTED:.*]] = cir.inc nsw %[[ATOB]]
+// CIR: cir.store{{.*}} %[[INCREMENTED]], %[[A]]
+// CIR: cir.store{{.*}} %[[ATOB]], %[[B]]
+// CIR: %[[B_TO_OUTPUT:.*]] = cir.load{{.*}} %[[B]]
// LLVM: define{{.*}} i32 @_Z4inc2v()
// LLVM: %[[RV:.*]] = alloca i32, align 4
@@ -222,32 +222,52 @@ int inc2() {
// OGCG: store i32 %[[A_LOAD]], ptr %[[B]], align 4
// OGCG: %[[B_TO_OUTPUT:.*]] = load i32, ptr %[[B]], align 4
+// Chars can go through some integer promotion codegen paths even when not promoted.
+// These should not have nsw attributes because the intermediate promotion makes the
+// overflow defined behavior.
void chars(char c) {
-// CHECK: cir.func{{.*}} @_Z5charsc
-
int c1 = +c;
- // CHECK: %[[PROMO:.*]] = cir.cast integral %{{.+}} : !s8i -> !s32i
int c2 = -c;
- // CHECK: %[[PROMO:.*]] = cir.cast integral %{{.+}} : !s8i -> !s32i
- // CHECK: cir.minus nsw %[[PROMO]] : !s32i
-
- // Chars can go through some integer promotion codegen paths even when not promoted.
- // These should not have nsw attributes because the intermediate promotion makes the
- // overflow defined behavior.
- ++c; // CHECK: cir.inc %{{.+}} : !s8i
- --c; // CHECK: cir.dec %{{.+}} : !s8i
- c++; // CHECK: cir.inc %{{.+}} : !s8i
- c--; // CHECK: cir.dec %{{.+}} : !s8i
+ ++c;
+ --c;
+ c++;
+ c--;
}
+// CIR: cir.func{{.*}} @_Z5charsc
+// CIR: %[[PROMO1:.*]] = cir.cast integral %{{.+}} : !s8i -> !s32i
+// CIR: %[[PROMO2:.*]] = cir.cast integral %{{.+}} : !s8i -> !s32i
+// CIR: cir.minus nsw %[[PROMO2]] : !s32i
+// CIR: cir.inc %{{.+}} : !s8i
+// CIR: cir.dec %{{.+}} : !s8i
+// CIR: cir.inc %{{.+}} : !s8i
+// CIR: cir.dec %{{.+}} : !s8i
+
+// LLVM: define{{.*}} void @_Z5charsc
+// LLVM: %[[PROMO1:.*]] = sext i8 %{{.+}} to i32
+// LLVM: %[[PROMO2:.*]] = sext i8 %{{.+}} to i32
+// LLVM: %[[MINUS:.*]] = sub nsw i32 0, %[[PROMO2]]
+// LLVM: add i8 %{{.+}}, 1
+// LLVM: sub i8 %{{.+}}, 1
+// LLVM: add i8 %{{.+}}, 1
+// LLVM: sub i8 %{{.+}}, 1
+
+// OGCG: define{{.*}} void @_Z5charsc
+// OGCG: %[[PROMO1:.*]] = sext i8 %{{.+}} to i32
+// OGCG: %[[PROMO2:.*]] = sext i8 %{{.+}} to i32
+// OGCG: %[[MINUS:.*]] = sub nsw i32 0, %[[PROMO2]]
+// OGCG: add i8 %{{.+}}, 1
+// OGCG: add i8 %{{.+}}, -1
+// OGCG: add i8 %{{.+}}, 1
+// OGCG: add i8 %{{.+}}, -1
float fpPlus() {
float a = 1.0f;
return +a;
}
-// CHECK: cir.func{{.*}} @_Z6fpPlusv() -> (!cir.float{{.*}})
-// CHECK: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.float>
-// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
+// CIR: cir.func{{.*}} @_Z6fpPlusv() -> (!cir.float{{.*}})
+// CIR: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.float>
+// CIR: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
// LLVM: define{{.*}} float @_Z6fpPlusv()
// LLVM: %[[RV:.*]] = alloca float, align 4
@@ -265,10 +285,10 @@ float fpMinus() {
return -a;
}
-// CHECK: cir.func{{.*}} @_Z7fpMinusv() -> (!cir.float{{.*}})
-// CHECK: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.float>
-// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
-// CHECK: %[[OUTPUT:.*]] = cir.fneg %[[INPUT]]
+// CIR: cir.func{{.*}} @_Z7fpMinusv() -> (!cir.float{{.*}})
+// CIR: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.float>
+// CIR: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
+// CIR: %[[OUTPUT:.*]] = cir.fneg %[[INPUT]]
// LLVM: define{{.*}} float @_Z7fpMinusv()
// LLVM: %[[RV:.*]] = alloca float, align 4
@@ -288,13 +308,13 @@ float fpPreInc() {
return ++a;
}
-// CHECK: cir.func{{.*}} @_Z8fpPreIncv() -> (!cir.float{{.*}})
-// CHECK: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.float>
-// CHECK: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
-// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float
-// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
-// CHECK: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
-// CHECK: %[[INCREMENTED:.*]] = cir.fadd %[[INPUT]], %[[ONE]]
+// CIR: cir.func{{.*}} @_Z8fpPreIncv() -> (!cir.float{{.*}})
+// CIR: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.float>
+// CIR: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
+// CIR: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float
+// CIR: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
+// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
+// CIR: %[[INCREMENTED:.*]] = cir.fadd %[[INPUT]], %[[ONE]]
// LLVM: define{{.*}} float @_Z8fpPreIncv()
// LLVM: %[[RV:.*]] = alloca float, align 4
@@ -314,20 +334,20 @@ float fpPreDec() {
return --a;
}
-// CHECK: cir.func{{.*}} @_Z8fpPreDecv() -> (!cir.float{{.*}})
-// CHECK: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.float>
-// CHECK: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
-// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float
-// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
-// CHECK: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
-// CHECK: %[[DECREMENTED:.*]] = cir.fsub %[[INPUT]], %[[ONE]]
+// CIR: cir.func{{.*}} @_Z8fpPreDecv() -> (!cir.float{{.*}})
+// CIR: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.float>
+// CIR: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
+// CIR: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float
+// CIR: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
+// CIR: %[[NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.float
+// CIR: %[[DECREMENTED:.*]] = cir.fadd %[[INPUT]], %[[NEGONE]]
// LLVM: define{{.*}} float @_Z8fpPreDecv()
// LLVM: %[[RV:.*]] = alloca float, align 4
// LLVM: %[[A:.*]] = alloca float, align 4
// LLVM: store float 1.000000e+00, ptr %[[A]], align 4
// LLVM: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
-// LLVM: %[[RESULT:.*]] = fsub float %[[A_LOAD]], 1.000000e+00
+// LLVM: %[[RESULT:.*]] = fadd float %[[A_LOAD]], -1.000000e+00
// OGCG: define{{.*}} float @_Z8fpPreDecv()
// OGCG: %[[A:.*]] = alloca float, align 4
@@ -340,13 +360,13 @@ float fpPostInc() {
return a++;
}
-// CHECK: cir.func{{.*}} @_Z9fpPostIncv() -> (!cir.float{{.*}})
-// CHECK: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.float>
-// CHECK: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
-// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float
-// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
-// CHECK: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
-// CHECK: %[[INCREMENTED:.*]] = cir.fadd %[[INPUT]], %[[ONE]]
+// CIR: cir.func{{.*}} @_Z9fpPostIncv() -> (!cir.float{{.*}})
+// CIR: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.float>
+// CIR: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
+// CIR: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float
+// CIR: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
+// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
+// CIR: %[[INCREMENTED:.*]] = cir.fadd %[[INPUT]], %[[ONE]]
// LLVM: define{{.*}} float @_Z9fpPostIncv()
// LLVM: %[[RV:.*]] = alloca float, align 4
@@ -366,20 +386,20 @@ float fpPostDec() {
return a--;
}
-// CHECK: cir.func{{.*}} @_Z9fpPostDecv() -> (!cir.float{{.*}})
-// CHECK: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.float>
-// CHECK: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
-// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float
-// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
-// CHECK: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
-// CHECK: %[[DECREMENTED:.*]] = cir.fsub %[[INPUT]], %[[ONE]]
+// CIR: cir.func{{.*}} @_Z9fpPostDecv() -> (!cir.float{{.*}})
+// CIR: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.float>
+// CIR: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
+// CIR: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float
+// CIR: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
+// CIR: %[[NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.float
+// CIR: %[[DECREMENTED:.*]] = cir.fadd %[[INPUT]], %[[NEGONE]]
// LLVM: define{{.*}} float @_Z9fpPostDecv()
// LLVM: %[[RV:.*]] = alloca float, align 4
// LLVM: %[[A:.*]] = alloca float, align 4
// LLVM: store float 1.000000e+00, ptr %[[A]], align 4
// LLVM: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
-// LLVM: %[[RESULT:.*]] = fsub float %[[A_LOAD]], 1.000000e+00
+// LLVM: %[[RESULT:.*]] = fadd float %[[A_LOAD]], -1.000000e+00
// OGCG: define{{.*}} float @_Z9fpPostDecv()
// OGCG: %[[A:.*]] = alloca float, align 4
@@ -394,17 +414,17 @@ float fpPostInc2() {
return b;
}
-// CHECK: cir.func{{.*}} @_Z10fpPostInc2v() -> (!cir.float{{.*}})
-// CHECK: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.float>
-// CHECK: %[[B:.*]] = cir.alloca "b" {{.*}} init : !cir.ptr<!cir.float>
-// CHECK: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
-// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float
-// CHECK: %[[ATOB:.*]] = cir.load{{.*}} %[[A]]
-// CHECK: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
-// CHECK: %[[INCREMENTED:.*]] = cir.fadd %[[ATOB]], %[[ONE]]
-// CHECK: cir.store{{.*}} %[[INCREMENTED]], %[[A]]
-// CHECK: cir.store{{.*}} %[[ATOB]], %[[B]]
-// CHECK: %[[B_TO_OUTPUT:.*]] = cir.load{{.*}} %[[B]]
+// CIR: cir.func{{.*}} @_Z10fpPostInc2v() -> (!cir.float{{.*}})
+// CIR: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.float>
+// CIR: %[[B:.*]] = cir.alloca "b" {{.*}} init : !cir.ptr<!cir.float>
+// CIR: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
+// CIR: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float
+// CIR: %[[ATOB:.*]] = cir.load{{.*}} %[[A]]
+// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
+// CIR: %[[INCREMENTED:.*]] = cir.fadd %[[ATOB]], %[[ONE]]
+// CIR: cir.store{{.*}} %[[INCREMENTED]], %[[A]]
+// CIR: cir.store{{.*}} %[[ATOB]], %[[B]]
+// CIR: %[[B_TO_OUTPUT:.*]] = cir.load{{.*}} %[[B]]
// LLVM: define{{.*}} float @_Z10fpPostInc2v()
// LLVM: %[[RV:.*]] = alloca float, align 4
@@ -432,9 +452,9 @@ double doubleUPlus(double f) {
return +f;
}
-// CHECK: cir.func{{.*}} @_Z11doubleUPlusd({{.*}}) -> (!cir.double{{.*}})
-// CHECK: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
-// CHECK: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
+// CIR: cir.func{{.*}} @_Z11doubleUPlusd({{.*}}) -> (!cir.double{{.*}})
+// CIR: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
+// CIR: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
// LLVM: define{{.*}} double @_Z11doubleUPlusd({{.*}})
// LLVM: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
@@ -446,10 +466,10 @@ double doubleUMinus(double f) {
return -f;
}
-// CHECK: cir.func{{.*}} @_Z12doubleUMinusd({{.*}}) -> (!cir.double{{.*}})
-// CHECK: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
-// CHECK: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
-// CHECK: %[[DBL_NEGATED:.*]] = cir.fneg %[[DBL_LOAD]]
+// CIR: cir.func{{.*}} @_Z12doubleUMinusd({{.*}}) -> (!cir.double{{.*}})
+// CIR: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
+// CIR: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
+// CIR: %[[DBL_NEGATED:.*]] = cir.fneg %[[DBL_LOAD]]
// LLVM: define{{.*}} double @_Z12doubleUMinusd({{.*}})
// LLVM: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
@@ -463,11 +483,11 @@ double doubleUPreInc(double f) {
return ++f;
}
-// CHECK: cir.func{{.*}} @_Z13doubleUPreIncd({{.*}}) -> (!cir.double{{.*}})
-// CHECK: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
-// CHECK: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
-// CHECK: %[[DBL_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
-// CHECK: %[[DBL_INC:.*]] = cir.fadd %[[DBL_LOAD]], %[[DBL_ONE]]
+// CIR: cir.func{{.*}} @_Z13doubleUPreIncd({{.*}}) -> (!cir.double{{.*}})
+// CIR: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
+// CIR: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
+// CIR: %[[DBL_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
+// CIR: %[[DBL_INC:.*]] = cir.fadd %[[DBL_LOAD]], %[[DBL_ONE]]
// LLVM: define{{.*}} double @_Z13doubleUPreIncd({{.*}})
// LLVM: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
@@ -481,15 +501,15 @@ double doubleUPreDec(double f) {
return --f;
}
-// CHECK: cir.func{{.*}} @_Z13doubleUPreDecd({{.*}}) -> (!cir.double{{.*}})
-// CHECK: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
-// CHECK: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
-// CHECK: %[[DBL_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
-// CHECK: %[[DBL_DEC:.*]] = cir.fsub %[[DBL_LOAD]], %[[DBL_ONE]]
+// CIR: cir.func{{.*}} @_Z13doubleUPreDecd({{.*}}) -> (!cir.double{{.*}})
+// CIR: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
+// CIR: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
+// CIR: %[[DBL_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.double
+// CIR: %[[DBL_DEC:.*]] = cir.fadd %[[DBL_LOAD]], %[[DBL_NEGONE]]
// LLVM: define{{.*}} double @_Z13doubleUPreDecd({{.*}})
// LLVM: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
-// LLVM: %[[DBL_DEC:.*]] = fsub double %[[DBL_LOAD]], 1.000000e+00
+// LLVM: %[[DBL_DEC:.*]] = fadd double %[[DBL_LOAD]], -1.000000e+00
// OGCG: define{{.*}} double @_Z13doubleUPreDecd({{.*}})
// OGCG: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
@@ -499,11 +519,11 @@ double doubleUPostInc(double f) {
return f++;
}
-// CHECK: cir.func{{.*}} @_Z14doubleUPostIncd({{.*}}) -> (!cir.double{{.*}})
-// CHECK: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
-// CHECK: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
-// CHECK: %[[DBL_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
-// CHECK: %[[DBL_INC:.*]] = cir.fadd %[[DBL_LOAD]], %[[DBL_ONE]]
+// CIR: cir.func{{.*}} @_Z14doubleUPostIncd({{.*}}) -> (!cir.double{{.*}})
+// CIR: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
+// CIR: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
+// CIR: %[[DBL_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
+// CIR: %[[DBL_INC:.*]] = cir.fadd %[[DBL_LOAD]], %[[DBL_ONE]]
// LLVM: define{{.*}} double @_Z14doubleUPostIncd({{.*}})
// LLVM: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
@@ -517,15 +537,15 @@ double doubleUPostDec(double f) {
return f--;
}
-// CHECK: cir.func{{.*}} @_Z14doubleUPostDecd({{.*}}) -> (!cir.double{{.*}})
-// CHECK: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
-// CHECK: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
-// CHECK: %[[DBL_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
-// CHECK: %[[DBL_DEC:.*]] = cir.fsub %[[DBL_LOAD]], %[[DBL_ONE]]
+// CIR: cir.func{{.*}} @_Z14doubleUPostDecd({{.*}}) -> (!cir.double{{.*}})
+// CIR: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
+// CIR: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
+// CIR: %[[DBL_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.double
+// CIR: %[[DBL_DEC:.*]] = cir.fadd %[[DBL_LOAD]], %[[DBL_NEGONE]]
// LLVM: define{{.*}} double @_Z14doubleUPostDecd({{.*}})
// LLVM: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
-// LLVM: %[[DBL_DEC:.*]] = fsub double %[[DBL_LOAD]], 1.000000e+00
+// LLVM: %[[DBL_DEC:.*]] = fadd double %[[DBL_LOAD]], -1.000000e+00
// OGCG: define{{.*}} double @_Z14doubleUPostDecd({{.*}})
// OGCG: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
@@ -536,9 +556,9 @@ long double ldUPlus(long double f) {
return +f;
}
-// CHECK: cir.func{{.*}} @_Z7ldUPluse({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
-// CHECK: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
-// CHECK: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
+// CIR: cir.func{{.*}} @_Z7ldUPluse({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
+// CIR: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
+// CIR: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
// LLVM: define{{.*}} x86_fp80 @_Z7ldUPluse({{.*}})
// LLVM: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
@@ -550,10 +570,10 @@ long double ldUMinus(long double f) {
return -f;
}
-// CHECK: cir.func{{.*}} @_Z8ldUMinuse({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
-// CHECK: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
-// CHECK: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
-// CHECK: %[[LD_NEGATED:.*]] = cir.fneg %[[LD_LOAD]]
+// CIR: cir.func{{.*}} @_Z8ldUMinuse({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
+// CIR: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
+// CIR: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
+// CIR: %[[LD_NEGATED:.*]] = cir.fneg %[[LD_LOAD]]
// LLVM: define{{.*}} x86_fp80 @_Z8ldUMinuse({{.*}})
// LLVM: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
@@ -567,11 +587,11 @@ long double ldUPreInc(long double f) {
return ++f;
}
-// CHECK: cir.func{{.*}} @_Z9ldUPreInce({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
-// CHECK: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
-// CHECK: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
-// CHECK: %[[LD_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.long_double<!cir.f80>
-// CHECK: %[[LD_INC:.*]] = cir.fadd %[[LD_LOAD]], %[[LD_ONE]]
+// CIR: cir.func{{.*}} @_Z9ldUPreInce({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
+// CIR: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
+// CIR: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
+// CIR: %[[LD_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.long_double<!cir.f80>
+// CIR: %[[LD_INC:.*]] = cir.fadd %[[LD_LOAD]], %[[LD_ONE]]
// LLVM: define{{.*}} x86_fp80 @_Z9ldUPreInce({{.*}})
// LLVM: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
@@ -585,15 +605,15 @@ long double ldUPreDec(long double f) {
return --f;
}
-// CHECK: cir.func{{.*}} @_Z9ldUPreDece({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
-// CHECK: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
-// CHECK: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
-// CHECK: %[[LD_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.long_double<!cir.f80>
-// CHECK: %[[LD_DEC:.*]] = cir.fsub %[[LD_LOAD]], %[[LD_ONE]]
+// CIR: cir.func{{.*}} @_Z9ldUPreDece({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
+// CIR: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
+// CIR: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
+// CIR: %[[LD_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.long_double<!cir.f80>
+// CIR: %[[LD_DEC:.*]] = cir.fadd %[[LD_LOAD]], %[[LD_NEGONE]]
// LLVM: define{{.*}} x86_fp80 @_Z9ldUPreDece({{.*}})
// LLVM: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
-// LLVM: %[[LD_DEC:.*]] = fsub x86_fp80 %[[LD_LOAD]], 1.000000e+00
+// LLVM: %[[LD_DEC:.*]] = fadd x86_fp80 %[[LD_LOAD]], -1.000000e+00
// OGCG: define{{.*}} x86_fp80 @_Z9ldUPreDece({{.*}})
// OGCG: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
@@ -603,11 +623,11 @@ long double ldUPostInc(long double f) {
return f++;
}
-// CHECK: cir.func{{.*}} @_Z10ldUPostInce({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
-// CHECK: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
-// CHECK: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
-// CHECK: %[[LD_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.long_double<!cir.f80>
-// CHECK: %[[LD_INC:.*]] = cir.fadd %[[LD_LOAD]], %[[LD_ONE]]
+// CIR: cir.func{{.*}} @_Z10ldUPostInce({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
+// CIR: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
+// CIR: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
+// CIR: %[[LD_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.long_double<!cir.f80>
+// CIR: %[[LD_INC:.*]] = cir.fadd %[[LD_LOAD]], %[[LD_ONE]]
// LLVM: define{{.*}} x86_fp80 @_Z10ldUPostInce({{.*}})
// LLVM: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
@@ -621,15 +641,15 @@ long double ldUPostDec(long double f) {
return f--;
}
-// CHECK: cir.func{{.*}} @_Z10ldUPostDece({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
-// CHECK: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
-// CHECK: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
-// CHECK: %[[LD_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.long_double<!cir.f80>
-// CHECK: %[[LD_DEC:.*]] = cir.fsub %[[LD_LOAD]], %[[LD_ONE]]
+// CIR: cir.func{{.*}} @_Z10ldUPostDece({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
+// CIR: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
+// CIR: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
+// CIR: %[[LD_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.long_double<!cir.f80>
+// CIR: %[[LD_DEC:.*]] = cir.fadd %[[LD_LOAD]], %[[LD_NEGONE]]
// LLVM: define{{.*}} x86_fp80 @_Z10ldUPostDece({{.*}})
// LLVM: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
-// LLVM: %[[LD_DEC:.*]] = fsub x86_fp80 %[[LD_LOAD]], 1.000000e+00
+// LLVM: %[[LD_DEC:.*]] = fadd x86_fp80 %[[LD_LOAD]], -1.000000e+00
// OGCG: define{{.*}} x86_fp80 @_Z10ldUPostDece({{.*}})
// OGCG: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
@@ -640,9 +660,9 @@ __float128 f128UPlus(__float128 f) {
return +f;
}
-// CHECK: cir.func{{.*}} @_Z9f128UPlusg({{.*}}) -> (!cir.f128{{.*}})
-// CHECK: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
-// CHECK: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
+// CIR: cir.func{{.*}} @_Z9f128UPlusg({{.*}}) -> (!cir.f128{{.*}})
+// CIR: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
+// CIR: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
// LLVM: define{{.*}} fp128 @_Z9f128UPlusg({{.*}})
// LLVM: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
@@ -654,10 +674,10 @@ __float128 f128UMinus(__float128 f) {
return -f;
}
-// CHECK: cir.func{{.*}} @_Z10f128UMinusg({{.*}}) -> (!cir.f128{{.*}})
-// CHECK: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
-// CHECK: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
-// CHECK: %[[F128_NEG:.*]] = cir.fneg %[[F128_LOAD]]
+// CIR: cir.func{{.*}} @_Z10f128UMinusg({{.*}}) -> (!cir.f128{{.*}})
+// CIR: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
+// CIR: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
+// CIR: %[[F128_NEG:.*]] = cir.fneg %[[F128_LOAD]]
// LLVM: define{{.*}} fp128 @_Z10f128UMinusg({{.*}})
// LLVM: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
@@ -671,11 +691,11 @@ __float128 f128UPreInc(__float128 f) {
return ++f;
}
-// CHECK: cir.func{{.*}} @_Z11f128UPreIncg({{.*}}) -> (!cir.f128{{.*}})
-// CHECK: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
-// CHECK: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
-// CHECK: %[[F128_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f128
-// CHECK: %[[F128_INC:.*]] = cir.fadd %[[F128_LOAD]], %[[F128_ONE]]
+// CIR: cir.func{{.*}} @_Z11f128UPreIncg({{.*}}) -> (!cir.f128{{.*}})
+// CIR: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
+// CIR: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
+// CIR: %[[F128_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f128
+// CIR: %[[F128_INC:.*]] = cir.fadd %[[F128_LOAD]], %[[F128_ONE]]
// LLVM: define{{.*}} fp128 @_Z11f128UPreIncg({{.*}})
// LLVM: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
@@ -689,15 +709,15 @@ __float128 f128UPreDec(__float128 f) {
return --f;
}
-// CHECK: cir.func{{.*}} @_Z11f128UPreDecg({{.*}}) -> (!cir.f128{{.*}})
-// CHECK: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
-// CHECK: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
-// CHECK: %[[F128_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f128
-// CHECK: %[[F128_DEC:.*]] = cir.fsub %[[F128_LOAD]], %[[F128_ONE]]
+// CIR: cir.func{{.*}} @_Z11f128UPreDecg({{.*}}) -> (!cir.f128{{.*}})
+// CIR: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
+// CIR: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
+// CIR: %[[F128_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.f128
+// CIR: %[[F128_DEC:.*]] = cir.fadd %[[F128_LOAD]], %[[F128_NEGONE]]
// LLVM: define{{.*}} fp128 @_Z11f128UPreDecg({{.*}})
// LLVM: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
-// LLVM: %[[F128_DEC:.*]] = fsub fp128 %[[F128_LOAD]], 1.000000e+00
+// LLVM: %[[F128_DEC:.*]] = fadd fp128 %[[F128_LOAD]], -1.000000e+00
// OGCG: define{{.*}} fp128 @_Z11f128UPreDecg({{.*}})
// OGCG: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
@@ -707,11 +727,11 @@ __float128 f128UPostInc(__float128 f) {
return f++;
}
-// CHECK: cir.func{{.*}} @_Z12f128UPostIncg({{.*}}) -> (!cir.f128{{.*}})
-// CHECK: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
-// CHECK: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
-// CHECK: %[[F128_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f128
-// CHECK: %[[F128_INC:.*]] = cir.fadd %[[F128_LOAD]], %[[F128_ONE]]
+// CIR: cir.func{{.*}} @_Z12f128UPostIncg({{.*}}) -> (!cir.f128{{.*}})
+// CIR: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
+// CIR: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
+// CIR: %[[F128_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f128
+// CIR: %[[F128_INC:.*]] = cir.fadd %[[F128_LOAD]], %[[F128_ONE]]
// LLVM: define{{.*}} fp128 @_Z12f128UPostIncg({{.*}})
// LLVM: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
@@ -725,15 +745,15 @@ __float128 f128UPostDec(__float128 f) {
return f--;
}
-// CHECK: cir.func{{.*}} @_Z12f128UPostDecg({{.*}}) -> (!cir.f128{{.*}})
-// CHECK: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
-// CHECK: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
-// CHECK: %[[F128_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f128
-// CHECK: %[[F128_DEC:.*]] = cir.fsub %[[F128_LOAD]], %[[F128_ONE]]
+// CIR: cir.func{{.*}} @_Z12f128UPostDecg({{.*}}) -> (!cir.f128{{.*}})
+// CIR: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
+// CIR: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
+// CIR: %[[F128_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.f128
+// CIR: %[[F128_DEC:.*]] = cir.fadd %[[F128_LOAD]], %[[F128_NEGONE]]
// LLVM: define{{.*}} fp128 @_Z12f128UPostDecg({{.*}})
// LLVM: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
-// LLVM: %[[F128_DEC:.*]] = fsub fp128 %[[F128_LOAD]], 1.000000e+00
+// LLVM: %[[F128_DEC:.*]] = fadd fp128 %[[F128_LOAD]], -1.000000e+00
// OGCG: define{{.*}} fp128 @_Z12f128UPostDecg({{.*}})
// OGCG: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
@@ -744,10 +764,10 @@ _Float16 Float16UPlus(_Float16 f) {
return +f;
}
-// CHECK: cir.func{{.*}} @_Z12Float16UPlusDF16_({{.*}}) -> (!cir.f16{{.*}})
-// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[F:.*]]
-// CHECK: %[[PROMOTED:.*]] = cir.cast floating %[[INPUT]] : !cir.f16 -> !cir.float
-// CHECK: %[[UNPROMOTED:.*]] = cir.cast floating %[[PROMOTED]] : !cir.float -> !cir.f16
+// CIR: cir.func{{.*}} @_Z12Float16UPlusDF16_({{.*}}) -> (!cir.f16{{.*}})
+// CIR: %[[INPUT:.*]] = cir.load{{.*}} %[[F:.*]]
+// CIR: %[[PROMOTED:.*]] = cir.cast floating %[[INPUT]] : !cir.f16 -> !cir.float
+// CIR: %[[UNPROMOTED:.*]] = cir.cast floating %[[PROMOTED]] : !cir.float -> !cir.f16
// LLVM: define{{.*}} half @_Z12Float16UPlusDF16_({{.*}})
// LLVM: %[[F_LOAD:.*]] = load half, ptr %{{.*}}, align 2
@@ -763,11 +783,11 @@ _Float16 Float16UMinus(_Float16 f) {
return -f;
}
-// CHECK: cir.func{{.*}} @_Z13Float16UMinusDF16_({{.*}}) -> (!cir.f16{{.*}})
-// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[F:.*]]
-// CHECK: %[[PROMOTED:.*]] = cir.cast floating %[[INPUT]] : !cir.f16 -> !cir.float
-// CHECK: %[[RESULT:.*]] = cir.fneg %[[PROMOTED]]
-// CHECK: %[[UNPROMOTED:.*]] = cir.cast floating %[[RESULT]] : !cir.float -> !cir.f16
+// CIR: cir.func{{.*}} @_Z13Float16UMinusDF16_({{.*}}) -> (!cir.f16{{.*}})
+// CIR: %[[INPUT:.*]] = cir.load{{.*}} %[[F:.*]]
+// CIR: %[[PROMOTED:.*]] = cir.cast floating %[[INPUT]] : !cir.f16 -> !cir.float
+// CIR: %[[RESULT:.*]] = cir.fneg %[[PROMOTED]]
+// CIR: %[[UNPROMOTED:.*]] = cir.cast floating %[[RESULT]] : !cir.float -> !cir.f16
// LLVM: define{{.*}} half @_Z13Float16UMinusDF16_({{.*}})
// LLVM: %[[F_LOAD:.*]] = load half, ptr %{{.*}}, align 2
@@ -785,11 +805,11 @@ _Float16 Float16UPreInc(_Float16 f) {
return ++f;
}
-// CHECK: cir.func{{.*}} @_Z14Float16UPreIncDF16_({{.*}}) -> (!cir.f16{{.*}})
-// CHECK: %[[PREINC_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f16>
-// CHECK: %[[PREINC_INPUT:.*]] = cir.load{{.*}} %[[PREINC_F]]
-// CHECK: %[[PREINC_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f16
-// CHECK: %[[PREINC_RESULT:.*]] = cir.fadd %[[PREINC_INPUT]], %[[PREINC_ONE]] : !cir.f16
+// CIR: cir.func{{.*}} @_Z14Float16UPreIncDF16_({{.*}}) -> (!cir.f16{{.*}})
+// CIR: %[[PREINC_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f16>
+// CIR: %[[PREINC_INPUT:.*]] = cir.load{{.*}} %[[PREINC_F]]
+// CIR: %[[PREINC_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f16
+// CIR: %[[PREINC_RESULT:.*]] = cir.fadd %[[PREINC_INPUT]], %[[PREINC_ONE]] : !cir.f16
// LLVM: define{{.*}} half @_Z14Float16UPreIncDF16_({{.*}})
// LLVM: %[[PREINC_F_ADDR:.*]] = alloca half, align 2
@@ -805,16 +825,16 @@ _Float16 Float16UPreDec(_Float16 f) {
return --f;
}
-// CHECK: cir.func{{.*}} @_Z14Float16UPreDecDF16_({{.*}}) -> (!cir.f16{{.*}})
-// CHECK: %[[PREDEC_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f16>
-// CHECK: %[[PREDEC_INPUT:.*]] = cir.load{{.*}} %[[PREDEC_F]]
-// CHECK: %[[PREDEC_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f16
-// CHECK: %[[PREDEC_RESULT:.*]] = cir.fsub %[[PREDEC_INPUT]], %[[PREDEC_ONE]] : !cir.f16
+// CIR: cir.func{{.*}} @_Z14Float16UPreDecDF16_({{.*}}) -> (!cir.f16{{.*}})
+// CIR: %[[PREDEC_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f16>
+// CIR: %[[PREDEC_INPUT:.*]] = cir.load{{.*}} %[[PREDEC_F]]
+// CIR: %[[PREDEC_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.f16
+// CIR: %[[PREDEC_RESULT:.*]] = cir.fadd %[[PREDEC_INPUT]], %[[PREDEC_NEGONE]] : !cir.f16
// LLVM: define{{.*}} half @_Z14Float16UPreDecDF16_({{.*}})
// LLVM: %[[PREDEC_F_ADDR:.*]] = alloca half, align 2
// LLVM: %[[PREDEC_INPUT:.*]] = load half, ptr %[[PREDEC_F_ADDR]], align 2
-// LLVM: %[[PREDEC_RESULT:.*]] = fsub half %[[PREDEC_INPUT]], 1.000000e+00
+// LLVM: %[[PREDEC_RESULT:.*]] = fadd half %[[PREDEC_INPUT]], -1.000000e+00
// OGCG: define{{.*}} half @_Z14Float16UPreDecDF16_({{.*}})
// OGCG: %[[PREDEC_F_ADDR:.*]] = alloca half, align 2
@@ -825,11 +845,11 @@ _Float16 Float16UPostInc(_Float16 f) {
return f++;
}
-// CHECK: cir.func{{.*}} @_Z15Float16UPostIncDF16_({{.*}}) -> (!cir.f16{{.*}})
-// CHECK: %[[POSTINC_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f16>
-// CHECK: %[[POSTINC_INPUT:.*]] = cir.load{{.*}} %[[POSTINC_F]]
-// CHECK: %[[POSTINC_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f16
-// CHECK: %[[POSTINC_RESULT:.*]] = cir.fadd %[[POSTINC_INPUT]], %[[POSTINC_ONE]] : !cir.f16
+// CIR: cir.func{{.*}} @_Z15Float16UPostIncDF16_({{.*}}) -> (!cir.f16{{.*}})
+// CIR: %[[POSTINC_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f16>
+// CIR: %[[POSTINC_INPUT:.*]] = cir.load{{.*}} %[[POSTINC_F]]
+// CIR: %[[POSTINC_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f16
+// CIR: %[[POSTINC_RESULT:.*]] = cir.fadd %[[POSTINC_INPUT]], %[[POSTINC_ONE]] : !cir.f16
// LLVM: define{{.*}} half @_Z15Float16UPostIncDF16_({{.*}})
// LLVM: %[[POSTINC_F_ADDR:.*]] = alloca half, align 2
@@ -845,16 +865,16 @@ _Float16 Float16UPostDec(_Float16 f) {
return f--;
}
-// CHECK: cir.func{{.*}} @_Z15Float16UPostDecDF16_({{.*}}) -> (!cir.f16{{.*}})
-// CHECK: %[[POSTDEC_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f16>
-// CHECK: %[[POSTDEC_INPUT:.*]] = cir.load{{.*}} %[[POSTDEC_F]]
-// CHECK: %[[POSTDEC_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f16
-// CHECK: %[[POSTDEC_RESULT:.*]] = cir.fsub %[[POSTDEC_INPUT]], %[[POSTDEC_ONE]] : !cir.f16
+// CIR: cir.func{{.*}} @_Z15Float16UPostDecDF16_({{.*}}) -> (!cir.f16{{.*}})
+// CIR: %[[POSTDEC_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f16>
+// CIR: %[[POSTDEC_INPUT:.*]] = cir.load{{.*}} %[[POSTDEC_F]]
+// CIR: %[[POSTDEC_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.f16
+// CIR: %[[POSTDEC_RESULT:.*]] = cir.fadd %[[POSTDEC_INPUT]], %[[POSTDEC_NEGONE]] : !cir.f16
// LLVM: define{{.*}} half @_Z15Float16UPostDecDF16_({{.*}})
// LLVM: %[[POSTDEC_F_ADDR:.*]] = alloca half, align 2
// LLVM: %[[POSTDEC_INPUT:.*]] = load half, ptr %[[POSTDEC_F_ADDR]], align 2
-// LLVM: %[[POSTDEC_RESULT:.*]] = fsub half %[[POSTDEC_INPUT]], 1.000000e+00
+// LLVM: %[[POSTDEC_RESULT:.*]] = fadd half %[[POSTDEC_INPUT]], -1.000000e+00
// OGCG: define{{.*}} half @_Z15Float16UPostDecDF16_({{.*}})
// OGCG: %[[POSTDEC_F_ADDR:.*]] = alloca half, align 2
@@ -866,12 +886,12 @@ void fp16PtrUPlus(__fp16 *f) {
*f = +(*f);
}
-// CHECK: cir.func{{.*}} @_Z12fp16PtrUPlusPDh({{.*}})
-// CHECK: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
-// CHECK: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
-// CHECK: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
-// CHECK: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
-// CHECK: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_PROMOTED]] : !cir.float -> !cir.f16
+// CIR: cir.func{{.*}} @_Z12fp16PtrUPlusPDh({{.*}})
+// CIR: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
+// CIR: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
+// CIR: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
+// CIR: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
+// CIR: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_PROMOTED]] : !cir.float -> !cir.f16
// LLVM: define{{.*}} void @_Z12fp16PtrUPlusPDh({{.*}})
// LLVM: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
@@ -887,13 +907,13 @@ void fp16PtrUMinus(__fp16 *f) {
*f = -(*f);
}
-// CHECK: cir.func{{.*}} @_Z13fp16PtrUMinusPDh({{.*}})
-// CHECK: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
-// CHECK: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
-// CHECK: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
-// CHECK: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
-// CHECK: %[[FPTR_NEGATED:.*]] = cir.fneg %[[FPTR_PROMOTED]]
-// CHECK: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_NEGATED]] : !cir.float -> !cir.f16
+// CIR: cir.func{{.*}} @_Z13fp16PtrUMinusPDh({{.*}})
+// CIR: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
+// CIR: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
+// CIR: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
+// CIR: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
+// CIR: %[[FPTR_NEGATED:.*]] = cir.fneg %[[FPTR_PROMOTED]]
+// CIR: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_NEGATED]] : !cir.float -> !cir.f16
// LLVM: define{{.*}} void @_Z13fp16PtrUMinusPDh({{.*}})
// LLVM: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
@@ -911,14 +931,14 @@ void fp16PtrUPreInc(__fp16 *f) {
++(*f);
}
-// CHECK: cir.func{{.*}} @_Z14fp16PtrUPreIncPDh({{.*}})
-// CHECK: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
-// CHECK: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
-// CHECK: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
-// CHECK: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
-// CHECK: %[[FPTR_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
-// CHECK: %[[FPTR_INC:.*]] = cir.fadd %[[FPTR_PROMOTED]], %[[FPTR_ONE]] : !cir.float
-// CHECK: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_INC]] : !cir.float -> !cir.f16
+// CIR: cir.func{{.*}} @_Z14fp16PtrUPreIncPDh({{.*}})
+// CIR: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
+// CIR: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
+// CIR: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
+// CIR: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
+// CIR: %[[FPTR_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
+// CIR: %[[FPTR_INC:.*]] = cir.fadd %[[FPTR_PROMOTED]], %[[FPTR_ONE]] : !cir.float
+// CIR: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_INC]] : !cir.float -> !cir.f16
// LLVM: define{{.*}} void @_Z14fp16PtrUPreIncPDh({{.*}})
// LLVM: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
@@ -936,19 +956,19 @@ void fp16PtrUPreDec(__fp16 *f) {
--(*f);
}
-// CHECK: cir.func{{.*}} @_Z14fp16PtrUPreDecPDh({{.*}})
-// CHECK: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
-// CHECK: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
-// CHECK: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
-// CHECK: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
-// CHECK: %[[FPTR_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
-// CHECK: %[[FPTR_DEC:.*]] = cir.fsub %[[FPTR_PROMOTED]], %[[FPTR_ONE]] : !cir.float
-// CHECK: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_DEC]] : !cir.float -> !cir.f16
+// CIR: cir.func{{.*}} @_Z14fp16PtrUPreDecPDh({{.*}})
+// CIR: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
+// CIR: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
+// CIR: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
+// CIR: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
+// CIR: %[[FPTR_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.float
+// CIR: %[[FPTR_DEC:.*]] = cir.fadd %[[FPTR_PROMOTED]], %[[FPTR_NEGONE]] : !cir.float
+// CIR: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_DEC]] : !cir.float -> !cir.f16
// LLVM: define{{.*}} void @_Z14fp16PtrUPreDecPDh({{.*}})
// LLVM: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
// LLVM: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
-// LLVM: %[[FPTR_DEC:.*]] = fsub float %[[FPTR_PROMOTED]], 1.000000e+00
+// LLVM: %[[FPTR_DEC:.*]] = fadd float %[[FPTR_PROMOTED]], -1.000000e+00
// LLVM: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_DEC]] to half
// OGCG: define{{.*}} void @_Z14fp16PtrUPreDecPDh({{.*}})
@@ -961,14 +981,14 @@ void fp16PtrUPostInc(__fp16 *f) {
(*f)++;
}
-// CHECK: cir.func{{.*}} @_Z15fp16PtrUPostIncPDh({{.*}})
-// CHECK: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
-// CHECK: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
-// CHECK: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
-// CHECK: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
-// CHECK: %[[FPTR_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
-// CHECK: %[[FPTR_INC:.*]] = cir.fadd %[[FPTR_PROMOTED]], %[[FPTR_ONE]] : !cir.float
-// CHECK: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_DEC]] : !cir.float -> !cir.f16
+// CIR: cir.func{{.*}} @_Z15fp16PtrUPostIncPDh({{.*}})
+// CIR: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
+// CIR: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
+// CIR: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
+// CIR: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
+// CIR: %[[FPTR_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
+// CIR: %[[FPTR_INC:.*]] = cir.fadd %[[FPTR_PROMOTED]], %[[FPTR_ONE]] : !cir.float
+// CIR: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_DEC]] : !cir.float -> !cir.f16
// LLVM: define{{.*}} void @_Z15fp16PtrUPostIncPDh({{.*}})
// LLVM: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
@@ -986,19 +1006,19 @@ void fp16PtrUPostDec(__fp16 *f) {
(*f)--;
}
-// CHECK: cir.func{{.*}} @_Z15fp16PtrUPostDecPDh({{.*}})
-// CHECK: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
-// CHECK: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
-// CHECK: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
-// CHECK: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
-// CHECK: %[[FPTR_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
-// CHECK: %[[FPTR_DEC:.*]] = cir.fsub %[[FPTR_PROMOTED]], %[[FPTR_ONE]] : !cir.float
-// CHECK: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_DEC]] : !cir.float -> !cir.f16
+// CIR: cir.func{{.*}} @_Z15fp16PtrUPostDecPDh({{.*}})
+// CIR: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
+// CIR: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
+// CIR: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
+// CIR: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
+// CIR: %[[FPTR_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.float
+// CIR: %[[FPTR_DEC:.*]] = cir.fadd %[[FPTR_PROMOTED]], %[[FPTR_NEGONE]] : !cir.float
+// CIR: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_DEC]] : !cir.float -> !cir.f16
// LLVM: define{{.*}} void @_Z15fp16PtrUPostDecPDh({{.*}})
// LLVM: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
// LLVM: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
-// LLVM: %[[FPTR_DEC:.*]] = fsub float %[[FPTR_PROMOTED]], 1.000000e+00
+// LLVM: %[[FPTR_DEC:.*]] = fadd float %[[FPTR_PROMOTED]], -1.000000e+00
// LLVM: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_DEC]] to half
// OGCG: define{{.*}} void @_Z15fp16PtrUPostDecPDh({{.*}})
@@ -1012,11 +1032,11 @@ __bf16 bf16UPlus(__bf16 f) {
return +f;
}
-// CHECK: cir.func{{.*}} @_Z9bf16UPlusDF16b({{.*}}) -> (!cir.bf16{{.*}})
-// CHECK: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
-// CHECK: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
-// CHECK: %[[BF16_PROMOTED:.*]] = cir.cast floating %[[BF16_LOAD]] : !cir.bf16 -> !cir.float
-// CHECK: %[[BF16_UNPROMOTED:.*]] = cir.cast floating %[[BF16_PROMOTED]] : !cir.float -> !cir.bf16
+// CIR: cir.func{{.*}} @_Z9bf16UPlusDF16b({{.*}}) -> (!cir.bf16{{.*}})
+// CIR: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
+// CIR: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
+// CIR: %[[BF16_PROMOTED:.*]] = cir.cast floating %[[BF16_LOAD]] : !cir.bf16 -> !cir.float
+// CIR: %[[BF16_UNPROMOTED:.*]] = cir.cast floating %[[BF16_PROMOTED]] : !cir.float -> !cir.bf16
// LLVM: define{{.*}} bfloat @_Z9bf16UPlusDF16b({{.*}})
// LLVM: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
@@ -1032,12 +1052,12 @@ __bf16 bf16UMinus(__bf16 f) {
return -f;
}
-// CHECK: cir.func{{.*}} @_Z10bf16UMinusDF16b({{.*}}) -> (!cir.bf16{{.*}})
-// CHECK: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
-// CHECK: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
-// CHECK: %[[BF16_PROMOTED:.*]] = cir.cast floating %[[BF16_LOAD]] : !cir.bf16 -> !cir.float
-// CHECK: %[[BF16_NEGATED:.*]] = cir.fneg %[[BF16_PROMOTED]]
-// CHECK: %[[BF16_UNPROMOTED:.*]] = cir.cast floating %[[BF16_NEGATED]] : !cir.float -> !cir.bf16
+// CIR: cir.func{{.*}} @_Z10bf16UMinusDF16b({{.*}}) -> (!cir.bf16{{.*}})
+// CIR: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
+// CIR: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
+// CIR: %[[BF16_PROMOTED:.*]] = cir.cast floating %[[BF16_LOAD]] : !cir.bf16 -> !cir.float
+// CIR: %[[BF16_NEGATED:.*]] = cir.fneg %[[BF16_PROMOTED]]
+// CIR: %[[BF16_UNPROMOTED:.*]] = cir.cast floating %[[BF16_NEGATED]] : !cir.float -> !cir.bf16
// LLVM: define{{.*}} bfloat @_Z10bf16UMinusDF16b({{.*}})
// LLVM: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
@@ -1055,10 +1075,10 @@ __bf16 bf16UPreInc(__bf16 f) {
return ++f;
}
-// CHECK: cir.func{{.*}} @_Z11bf16UPreIncDF16b({{.*}}) -> (!cir.bf16{{.*}})
-// CHECK: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
-// CHECK: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
-// CHECK: %[[BF16_INC:.*]] = cir.fadd %[[BF16_LOAD]], %{{.*}} : !cir.bf16
+// CIR: cir.func{{.*}} @_Z11bf16UPreIncDF16b({{.*}}) -> (!cir.bf16{{.*}})
+// CIR: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
+// CIR: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
+// CIR: %[[BF16_INC:.*]] = cir.fadd %[[BF16_LOAD]], %{{.*}} : !cir.bf16
// LLVM: define{{.*}} bfloat @_Z11bf16UPreIncDF16b({{.*}})
// LLVM: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
@@ -1072,14 +1092,14 @@ __bf16 bf16UPreDec(__bf16 f) {
return --f;
}
-// CHECK: cir.func{{.*}} @_Z11bf16UPreDecDF16b({{.*}}) -> (!cir.bf16{{.*}})
-// CHECK: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
-// CHECK: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
-// CHECK: %[[BF16_DEC:.*]] = cir.fsub %[[BF16_LOAD]], %{{.*}} : !cir.bf16
+// CIR: cir.func{{.*}} @_Z11bf16UPreDecDF16b({{.*}}) -> (!cir.bf16{{.*}})
+// CIR: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
+// CIR: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
+// CIR: %[[BF16_DEC:.*]] = cir.fadd %[[BF16_LOAD]], %{{.*}} : !cir.bf16
// LLVM: define{{.*}} bfloat @_Z11bf16UPreDecDF16b({{.*}})
// LLVM: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
-// LLVM: %[[BF16_DEC:.*]] = fsub bfloat %[[BF16_LOAD]], 1.000000e+00
+// LLVM: %[[BF16_DEC:.*]] = fadd bfloat %[[BF16_LOAD]], -1.000000e+00
// OGCG: define{{.*}} bfloat @_Z11bf16UPreDecDF16b({{.*}})
// OGCG: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
@@ -1089,10 +1109,10 @@ __bf16 bf16UPostInc(__bf16 f) {
return f++;
}
-// CHECK: cir.func{{.*}} @_Z12bf16UPostIncDF16b({{.*}}) -> (!cir.bf16{{.*}})
-// CHECK: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
-// CHECK: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
-// CHECK: %[[BF16_INC:.*]] = cir.fadd %[[BF16_LOAD]], %{{.*}} : !cir.bf16
+// CIR: cir.func{{.*}} @_Z12bf16UPostIncDF16b({{.*}}) -> (!cir.bf16{{.*}})
+// CIR: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
+// CIR: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
+// CIR: %[[BF16_INC:.*]] = cir.fadd %[[BF16_LOAD]], %{{.*}} : !cir.bf16
// LLVM: define{{.*}} bfloat @_Z12bf16UPostIncDF16b({{.*}})
// LLVM: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
@@ -1106,14 +1126,14 @@ __bf16 bf16UPostDec(__bf16 f) {
return f--;
}
-// CHECK: cir.func{{.*}} @_Z12bf16UPostDecDF16b({{.*}}) -> (!cir.bf16{{.*}})
-// CHECK: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
-// CHECK: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
-// CHECK: %[[BF16_DEC:.*]] = cir.fsub %[[BF16_LOAD]], %{{.*}} : !cir.bf16
+// CIR: cir.func{{.*}} @_Z12bf16UPostDecDF16b({{.*}}) -> (!cir.bf16{{.*}})
+// CIR: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
+// CIR: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
+// CIR: %[[BF16_DEC:.*]] = cir.fadd %[[BF16_LOAD]], %{{.*}} : !cir.bf16
// LLVM: define{{.*}} bfloat @_Z12bf16UPostDecDF16b({{.*}})
// LLVM: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
-// LLVM: %[[BF16_DEC:.*]] = fsub bfloat %[[BF16_LOAD]], 1.000000e+00
+// LLVM: %[[BF16_DEC:.*]] = fadd bfloat %[[BF16_LOAD]], -1.000000e+00
// OGCG: define{{.*}} bfloat @_Z12bf16UPostDecDF16b({{.*}})
// OGCG: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
@@ -1132,28 +1152,28 @@ void test_logical_not() {
b = !d;
}
-// CHECK: cir.func{{.*}} @_Z16test_logical_notv()
-// CHECK: %[[A:.*]] = cir.load{{.*}} %[[A_ADDR:.*]] : !cir.ptr<!s32i>, !s32i
-// CHECK: %[[A_BOOL:.*]] = cir.cast int_to_bool %[[A]] : !s32i -> !cir.bool
-// CHECK: %[[A_NOT:.*]] = cir.not %[[A_BOOL]] : !cir.bool
-// CHECK: %[[A_CAST:.*]] = cir.cast bool_to_int %[[A_NOT]] : !cir.bool -> !s32i
-// CHECK: cir.store{{.*}} %[[A_CAST]], %[[A_ADDR]] : !s32i, !cir.ptr<!s32i>
-// CHECK: %[[B:.*]] = cir.load{{.*}} %[[B_ADDR:.*]] : !cir.ptr<!cir.bool>, !cir.bool
-// CHECK: %[[B_NOT:.*]] = cir.not %[[B]] : !cir.bool
-// CHECK: cir.store{{.*}} %[[B_NOT]], %[[B_ADDR]] : !cir.bool, !cir.ptr<!cir.bool>
-// CHECK: %[[C:.*]] = cir.load{{.*}} %[[C_ADDR:.*]] : !cir.ptr<!cir.float>, !cir.float
-// CHECK: %[[C_BOOL:.*]] = cir.cast float_to_bool %[[C]] : !cir.float -> !cir.bool
-// CHECK: %[[C_NOT:.*]] = cir.not %[[C_BOOL]] : !cir.bool
-// CHECK: %[[C_CAST:.*]] = cir.cast bool_to_float %[[C_NOT]] : !cir.bool -> !cir.float
-// CHECK: cir.store{{.*}} %[[C_CAST]], %[[C_ADDR]] : !cir.float, !cir.ptr<!cir.float>
-// CHECK: %[[P:.*]] = cir.load{{.*}} %[[P_ADDR:.*]] : !cir.ptr<!cir.ptr<!s32i>>, !cir.ptr<!s32i>
-// CHECK: %[[P_BOOL:.*]] = cir.cast ptr_to_bool %[[P]] : !cir.ptr<!s32i> -> !cir.bool
-// CHECK: %[[P_NOT:.*]] = cir.not %[[P_BOOL]] : !cir.bool
-// CHECK: cir.store{{.*}} %[[P_NOT]], %[[B_ADDR]] : !cir.bool, !cir.ptr<!cir.bool>
-// CHECK: %[[D:.*]] = cir.load{{.*}} %[[D_ADDR:.*]] : !cir.ptr<!cir.double>, !cir.double
-// CHECK: %[[D_BOOL:.*]] = cir.cast float_to_bool %[[D]] : !cir.double -> !cir.bool
-// CHECK: %[[D_NOT:.*]] = cir.not %[[D_BOOL]] : !cir.bool
-// CHECK: cir.store{{.*}} %[[D_NOT]], %[[B_ADDR]] : !cir.bool, !cir.ptr<!cir.bool>
+// CIR: cir.func{{.*}} @_Z16test_logical_notv()
+// CIR: %[[A:.*]] = cir.load{{.*}} %[[A_ADDR:.*]] : !cir.ptr<!s32i>, !s32i
+// CIR: %[[A_BOOL:.*]] = cir.cast int_to_bool %[[A]] : !s32i -> !cir.bool
+// CIR: %[[A_NOT:.*]] = cir.not %[[A_BOOL]] : !cir.bool
+// CIR: %[[A_CAST:.*]] = cir.cast bool_to_int %[[A_NOT]] : !cir.bool -> !s32i
+// CIR: cir.store{{.*}} %[[A_CAST]], %[[A_ADDR]] : !s32i, !cir.ptr<!s32i>
+// CIR: %[[B:.*]] = cir.load{{.*}} %[[B_ADDR:.*]] : !cir.ptr<!cir.bool>, !cir.bool
+// CIR: %[[B_NOT:.*]] = cir.not %[[B]] : !cir.bool
+// CIR: cir.store{{.*}} %[[B_NOT]], %[[B_ADDR]] : !cir.bool, !cir.ptr<!cir.bool>
+// CIR: %[[C:.*]] = cir.load{{.*}} %[[C_ADDR:.*]] : !cir.ptr<!cir.float>, !cir.float
+// CIR: %[[C_BOOL:.*]] = cir.cast float_to_bool %[[C]] : !cir.float -> !cir.bool
+// CIR: %[[C_NOT:.*]] = cir.not %[[C_BOOL]] : !cir.bool
+// CIR: %[[C_CAST:.*]] = cir.cast bool_to_float %[[C_NOT]] : !cir.bool -> !cir.float
+// CIR: cir.store{{.*}} %[[C_CAST]], %[[C_ADDR]] : !cir.float, !cir.ptr<!cir.float>
+// CIR: %[[P:.*]] = cir.load{{.*}} %[[P_ADDR:.*]] : !cir.ptr<!cir.ptr<!s32i>>, !cir.ptr<!s32i>
+// CIR: %[[P_BOOL:.*]] = cir.cast ptr_to_bool %[[P]] : !cir.ptr<!s32i> -> !cir.bool
+// CIR: %[[P_NOT:.*]] = cir.not %[[P_BOOL]] : !cir.bool
+// CIR: cir.store{{.*}} %[[P_NOT]], %[[B_ADDR]] : !cir.bool, !cir.ptr<!cir.bool>
+// CIR: %[[D:.*]] = cir.load{{.*}} %[[D_ADDR:.*]] : !cir.ptr<!cir.double>, !cir.double
+// CIR: %[[D_BOOL:.*]] = cir.cast float_to_bool %[[D]] : !cir.double -> !cir.bool
+// CIR: %[[D_NOT:.*]] = cir.not %[[D_BOOL]] : !cir.bool
+// CIR: cir.store{{.*}} %[[D_NOT]], %[[B_ADDR]] : !cir.bool, !cir.ptr<!cir.bool>
// LLVM: define{{.*}} void @_Z16test_logical_notv()
// LLVM: %[[A:.*]] = load i32, ptr %[[A_ADDR:.*]], align 4
@@ -1214,13 +1234,13 @@ void f16NestedUPlus() {
_Float16 b = +(+a);
}
-// CHECK: cir.func{{.*}} @_Z14f16NestedUPlusv()
-// CHECK: %[[A_ADDR:.*]] = cir.alloca "a" {{.*}} : !cir.ptr<!cir.f16>
-// CHECK: %[[B_ADDR:.*]] = cir.alloca "b" {{.*}} init : !cir.ptr<!cir.f16>
-// CHECK: %[[TMP_A:.*]] = cir.load{{.*}} %[[A_ADDR]] : !cir.ptr<!cir.f16>, !cir.f16
-// CHECK: %[[A_F32:.*]] = cir.cast floating %[[TMP_A]] : !cir.f16 -> !cir.float
-// CHECK: %[[RESULT:.*]] = cir.cast floating %[[A_F32]] : !cir.float -> !cir.f16
-// CHECK: cir.store{{.*}} %[[RESULT]], %[[B_ADDR]] : !cir.f16, !cir.ptr<!cir.f16>
+// CIR: cir.func{{.*}} @_Z14f16NestedUPlusv()
+// CIR: %[[A_ADDR:.*]] = cir.alloca "a" {{.*}} : !cir.ptr<!cir.f16>
+// CIR: %[[B_ADDR:.*]] = cir.alloca "b" {{.*}} init : !cir.ptr<!cir.f16>
+// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[A_ADDR]] : !cir.ptr<!cir.f16>, !cir.f16
+// CIR: %[[A_F32:.*]] = cir.cast floating %[[TMP_A]] : !cir.f16 -> !cir.float
+// CIR: %[[RESULT:.*]] = cir.cast floating %[[A_F32]] : !cir.float -> !cir.f16
+// CIR: cir.store{{.*}} %[[RESULT]], %[[B_ADDR]] : !cir.f16, !cir.ptr<!cir.f16>
// LLVM: define{{.*}} void @_Z14f16NestedUPlusv()
// LLVM: %[[A_ADDR:.*]] = alloca half, align 2
@@ -1243,15 +1263,15 @@ void f16NestedUMinus() {
_Float16 b = -(-a);
}
-// CHECK: cir.func{{.*}} @_Z15f16NestedUMinusv()
-// CHECK: %[[A_ADDR:.*]] = cir.alloca "a" {{.*}} : !cir.ptr<!cir.f16>
-// CHECK: %[[B_ADDR:.*]] = cir.alloca "b" {{.*}} init : !cir.ptr<!cir.f16>
-// CHECK: %[[TMP_A:.*]] = cir.load{{.*}} %[[A_ADDR]] : !cir.ptr<!cir.f16>, !cir.f16
-// CHECK: %[[A_F32:.*]] = cir.cast floating %[[TMP_A]] : !cir.f16 -> !cir.float
-// CHECK: %[[A_MINUS:.*]] = cir.fneg %[[A_F32]] : !cir.float
-// CHECK: %[[RESULT_F32:.*]] = cir.fneg %[[A_MINUS]] : !cir.float
-// CHECK: %[[RESULT:.*]] = cir.cast floating %[[RESULT_F32]] : !cir.float -> !cir.f16
-// CHECK: cir.store{{.*}} %[[RESULT]], %[[B_ADDR]] : !cir.f16, !cir.ptr<!cir.f16>
+// CIR: cir.func{{.*}} @_Z15f16NestedUMinusv()
+// CIR: %[[A_ADDR:.*]] = cir.alloca "a" {{.*}} : !cir.ptr<!cir.f16>
+// CIR: %[[B_ADDR:.*]] = cir.alloca "b" {{.*}} init : !cir.ptr<!cir.f16>
+// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[A_ADDR]] : !cir.ptr<!cir.f16>, !cir.f16
+// CIR: %[[A_F32:.*]] = cir.cast floating %[[TMP_A]] : !cir.f16 -> !cir.float
+// CIR: %[[A_MINUS:.*]] = cir.fneg %[[A_F32]] : !cir.float
+// CIR: %[[RESULT_F32:.*]] = cir.fneg %[[A_MINUS]] : !cir.float
+// CIR: %[[RESULT:.*]] = cir.cast floating %[[RESULT_F32]] : !cir.float -> !cir.f16
+// CIR: cir.store{{.*}} %[[RESULT]], %[[B_ADDR]] : !cir.f16, !cir.ptr<!cir.f16>
// LLVM: define{{.*}} void @_Z15f16NestedUMinusv()
// LLVM: %[[A_ADDR:.*]] = alloca half, align 2
@@ -1272,3 +1292,150 @@ void f16NestedUMinus() {
// OGCG: %[[RESULT_F32:.*]] = fneg float %[[A_MINUS]]
// OGCG: %[[RESULT:.*]] = fptrunc float %[[RESULT_F32]] to half
// OGCG: store half %[[RESULT]], ptr %[[B_ADDR]], align 2
+
+// Unary inc/dec on vector types, covering the CIRGenExprScalar.cpp vector
+// branch:
+// * integer vectors go through emitIntIncOrDec -> cir.inc/cir.dec
+// * float vectors go through emitFloatIncOrDec -> cir.fadd
+
+typedef int vi4 __attribute__((vector_size(16)));
+typedef unsigned uvi4 __attribute__((vector_size(16)));
+typedef short vsh8 __attribute__((vector_size(16)));
+typedef float vf4 __attribute__((vector_size(16)));
+typedef double vd2 __attribute__((vector_size(16)));
+
+void vecIntIncDec(vi4 a) {
+ ++a;
+ --a;
+ a++;
+ a--;
+}
+// CIR-LABEL: @_Z12vecIntIncDecDv4_i
+// CIR: cir.inc %{{.+}} : !cir.vector<4 x !s32i>
+// CIR: cir.dec %{{.+}} : !cir.vector<4 x !s32i>
+// CIR: cir.inc %{{.+}} : !cir.vector<4 x !s32i>
+// CIR: cir.dec %{{.+}} : !cir.vector<4 x !s32i>
+
+// LLVM-LABEL: @_Z12vecIntIncDecDv4_i
+// LLVM: add <4 x i32> %{{.+}}, splat (i32 1)
+// LLVM: sub <4 x i32> %{{.+}}, splat (i32 1)
+// LLVM: add <4 x i32> %{{.+}}, splat (i32 1)
+// LLVM: sub <4 x i32> %{{.+}}, splat (i32 1)
+
+// OGCG-LABEL: @_Z12vecIntIncDecDv4_i
+// OGCG: add <4 x i32> %{{.+}}, splat (i32 1)
+// OGCG: add <4 x i32> %{{.+}}, splat (i32 -1)
+// OGCG: add <4 x i32> %{{.+}}, splat (i32 1)
+// OGCG: add <4 x i32> %{{.+}}, splat (i32 -1)
+
+void vecUIntIncDec(uvi4 b) {
+ ++b;
+ --b;
+ b++;
+ b--;
+}
+// CIR-LABEL: @_Z13vecUIntIncDecDv4_j
+// CIR: cir.inc %{{.+}} : !cir.vector<4 x !u32i>
+// CIR: cir.dec %{{.+}} : !cir.vector<4 x !u32i>
+// CIR: cir.inc %{{.+}} : !cir.vector<4 x !u32i>
+// CIR: cir.dec %{{.+}} : !cir.vector<4 x !u32i>
+
+// LLVM-LABEL: @_Z13vecUIntIncDecDv4_j
+// LLVM: add <4 x i32> %{{.+}}, splat (i32 1)
+// LLVM: sub <4 x i32> %{{.+}}, splat (i32 1)
+// LLVM: add <4 x i32> %{{.+}}, splat (i32 1)
+// LLVM: sub <4 x i32> %{{.+}}, splat (i32 1)
+
+// OGCG-LABEL: @_Z13vecUIntIncDecDv4_j
+// OGCG: add <4 x i32> %{{.+}}, splat (i32 1)
+// OGCG: add <4 x i32> %{{.+}}, splat (i32 -1)
+// OGCG: add <4 x i32> %{{.+}}, splat (i32 1)
+// OGCG: add <4 x i32> %{{.+}}, splat (i32 -1)
+
+void vecShortIncDec(vsh8 c) {
+ ++c;
+ --c;
+ c++;
+ c--;
+}
+// CIR-LABEL: @_Z14vecShortIncDecDv8_s
+// CIR: cir.inc %{{.+}} : !cir.vector<8 x !s16i>
+// CIR: cir.dec %{{.+}} : !cir.vector<8 x !s16i>
+// CIR: cir.inc %{{.+}} : !cir.vector<8 x !s16i>
+// CIR: cir.dec %{{.+}} : !cir.vector<8 x !s16i>
+
+// LLVM-LABEL: @_Z14vecShortIncDecDv8_s
+// LLVM: add <8 x i16> %{{.+}}, splat (i16 1)
+// LLVM: sub <8 x i16> %{{.+}}, splat (i16 1)
+// LLVM: add <8 x i16> %{{.+}}, splat (i16 1)
+// LLVM: sub <8 x i16> %{{.+}}, splat (i16 1)
+
+// OGCG-LABEL: @_Z14vecShortIncDecDv8_s
+// OGCG: add <8 x i16> %{{.+}}, splat (i16 1)
+// OGCG: add <8 x i16> %{{.+}}, splat (i16 -1)
+// OGCG: add <8 x i16> %{{.+}}, splat (i16 1)
+// OGCG: add <8 x i16> %{{.+}}, splat (i16 -1)
+
+void vecFloatIncDec(vf4 a) {
+ ++a;
+ --a;
+ a++;
+ a--;
+}
+// CIR-LABEL: @_Z14vecFloatIncDecDv4_f
+// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
+// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.float, !cir.vector<4 x !cir.float>
+// CIR: cir.fadd %{{.+}}, %[[ONEVEC]] : !cir.vector<4 x !cir.float>
+// CIR: %[[NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.float
+// CIR: %[[NEGONEVEC:.*]] = cir.vec.splat %[[NEGONE]] : !cir.float, !cir.vector<4 x !cir.float>
+// CIR: cir.fadd %{{.+}}, %[[NEGONEVEC]] : !cir.vector<4 x !cir.float>
+// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
+// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.float, !cir.vector<4 x !cir.float>
+// CIR: cir.fadd %{{.+}}, %[[ONEVEC]] : !cir.vector<4 x !cir.float>
+// CIR: %[[NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.float
+// CIR: %[[NEGONEVEC:.*]] = cir.vec.splat %[[NEGONE]] : !cir.float, !cir.vector<4 x !cir.float>
+// CIR: cir.fadd %{{.+}}, %[[NEGONEVEC]] : !cir.vector<4 x !cir.float>
+
+// LLVM-LABEL: @_Z14vecFloatIncDecDv4_f
+// LLVM: fadd <4 x float> %{{.+}}, splat (float 1.000000e+00)
+// LLVM: fadd <4 x float> %{{.+}}, splat (float -1.000000e+00)
+// LLVM: fadd <4 x float> %{{.+}}, splat (float 1.000000e+00)
+// LLVM: fadd <4 x float> %{{.+}}, splat (float -1.000000e+00)
+
+// OGCG-LABEL: @_Z14vecFloatIncDecDv4_f
+// OGCG: fadd <4 x float> %{{.+}}, splat (float 1.000000e+00)
+// OGCG: fadd <4 x float> %{{.+}}, splat (float -1.000000e+00)
+// OGCG: fadd <4 x float> %{{.+}}, splat (float 1.000000e+00)
+// OGCG: fadd <4 x float> %{{.+}}, splat (float -1.000000e+00)
+
+void vecDoubleIncDec(vd2 b) {
+ ++b;
+ --b;
+ b++;
+ b--;
+}
+// CIR-LABEL: @_Z15vecDoubleIncDecDv2_d
+// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
+// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.double, !cir.vector<2 x !cir.double>
+// CIR: cir.fadd %{{.+}}, %[[ONEVEC]] : !cir.vector<2 x !cir.double>
+// CIR: %[[NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.double
+// CIR: %[[NEGONEVEC:.*]] = cir.vec.splat %[[NEGONE]] : !cir.double, !cir.vector<2 x !cir.double>
+// CIR: cir.fadd %{{.+}}, %[[NEGONEVEC]] : !cir.vector<2 x !cir.double>
+// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
+// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.double, !cir.vector<2 x !cir.double>
+// CIR: cir.fadd %{{.+}}, %[[ONEVEC]] : !cir.vector<2 x !cir.double>
+// CIR: %[[NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.double
+// CIR: %[[NEGONEVEC:.*]] = cir.vec.splat %[[NEGONE]] : !cir.double, !cir.vector<2 x !cir.double>
+// CIR: cir.fadd %{{.+}}, %[[NEGONEVEC]] : !cir.vector<2 x !cir.double>
+
+// LLVM-LABEL: @_Z15vecDoubleIncDecDv2_d
+// LLVM: fadd <2 x double> %{{.+}}, splat (double 1.000000e+00)
+// LLVM: fadd <2 x double> %{{.+}}, splat (double -1.000000e+00)
+// LLVM: fadd <2 x double> %{{.+}}, splat (double 1.000000e+00)
+// LLVM: fadd <2 x double> %{{.+}}, splat (double -1.000000e+00)
+
+// OGCG-LABEL: @_Z15vecDoubleIncDecDv2_d
+// OGCG: fadd <2 x double> %{{.+}}, splat (double 1.000000e+00)
+// OGCG: fadd <2 x double> %{{.+}}, splat (double -1.000000e+00)
+// OGCG: fadd <2 x double> %{{.+}}, splat (double 1.000000e+00)
+// OGCG: fadd <2 x double> %{{.+}}, splat (double -1.000000e+00)
>From ab1286832e79d04f854039ba864fa0d2b8e580b2 Mon Sep 17 00:00:00 2001
From: Haocong Lu <haocong.lu at witintech.com>
Date: Wed, 9 Sep 2026 15:26:39 +0800
Subject: [PATCH 3/6] [CIR] Fix failed case at CI
---
clang/test/CIR/CodeGenOpenACC/atomic-update.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/clang/test/CIR/CodeGenOpenACC/atomic-update.cpp b/clang/test/CIR/CodeGenOpenACC/atomic-update.cpp
index da511723489e99e..353db84000c0238 100644
--- a/clang/test/CIR/CodeGenOpenACC/atomic-update.cpp
+++ b/clang/test/CIR/CodeGenOpenACC/atomic-update.cpp
@@ -53,8 +53,8 @@ void use(int x, unsigned int y, float f, HasOps ops) {
// CHECK-NEXT: cir.store %[[RECIPE_ARG]], %[[TEMP_ALLOCA]] : !cir.float, !cir.ptr<!cir.float>
//
// CHECK-NEXT: %[[TEMP_LOAD:.*]] = cir.load{{.*}} %[[TEMP_ALLOCA]] : !cir.ptr<!cir.float>, !cir.float
- // CHECK-NEXT: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
- // CHECK-NEXT: %[[INC:.*]] = cir.fsub %[[TEMP_LOAD]], %[[ONE]] : !cir.float
+ // CHECK-NEXT: %[[NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.float
+ // CHECK-NEXT: %[[INC:.*]] = cir.fadd %[[TEMP_LOAD]], %[[NEGONE]] : !cir.float
// CHECK-NEXT: cir.store {{.*}}%[[INC]], %[[TEMP_ALLOCA]] : !cir.float, !cir.ptr<!cir.float>
//
// CHECK-NEXT: %[[TEMP_LOAD:.*]] = cir.load{{.*}} %[[TEMP_ALLOCA]] : !cir.ptr<!cir.float>, !cir.float
>From 249614d5f920415da95dfb4d77f08a6d18ea8a45 Mon Sep 17 00:00:00 2001
From: Haocong Lu <haocong.lu at witintech.com>
Date: Thu, 17 Sep 2026 23:27:30 +0800
Subject: [PATCH 4/6] [CIR] Enhance the distinction between post-inc/dec and
pre-inc/dec
---
.../test/CIR/CodeGen/long-double-inc-dec.cpp | 6 +-
clang/test/CIR/CodeGen/unary.cpp | 1330 ++++++++++++++---
2 files changed, 1135 insertions(+), 201 deletions(-)
diff --git a/clang/test/CIR/CodeGen/long-double-inc-dec.cpp b/clang/test/CIR/CodeGen/long-double-inc-dec.cpp
index a5fa4ff40a7b206..4321a63c0fbc982 100644
--- a/clang/test/CIR/CodeGen/long-double-inc-dec.cpp
+++ b/clang/test/CIR/CodeGen/long-double-inc-dec.cpp
@@ -38,8 +38,7 @@ extern "C" long double do_pre_inc(long double d) {
// CIR: cir.return %[[LOAD_RET]] : !cir.long_double<![[LDTY]]>
//
// LLVM: %[[ARG_LOAD:.*]] = load [[LDTY]], ptr %[[ARG_ALLOCA]]
- // LLVMCIR: %[[ARG_INC:.*]] = fadd [[LDTY]] %[[ARG_LOAD]], 1.000000e+00
- // OGCG: %[[ARG_INC:.*]] = fadd [[LDTY]] %[[ARG_LOAD]], 1.000000e+00
+ // LLVM: %[[ARG_INC:.*]] = fadd [[LDTY]] %[[ARG_LOAD]], 1.000000e+00
// LLVM: store [[LDTY]] %[[ARG_INC]], ptr %[[ARG_ALLOCA]]
// LLVMCIR: store [[LDTY]] %[[ARG_INC]], ptr %[[RET_ALLOCA]]
// LLVMCIR: %[[LOAD_RET:.*]] = load [[LDTY]], ptr %[[RET_ALLOCA]]
@@ -65,8 +64,7 @@ extern "C" long double do_post_inc(long double d) {
// CIR: cir.return %[[LOAD_RET]] : !cir.long_double<![[LDTY]]>
//
// LLVM: %[[ARG_LOAD:.*]] = load [[LDTY]], ptr %[[ARG_ALLOCA]]
- // LLVMCIR: %[[ARG_INC:.*]] = fadd [[LDTY]] %[[ARG_LOAD]], 1.000000e+00
- // OGCG: %[[ARG_INC:.*]] = fadd [[LDTY]] %[[ARG_LOAD]], 1.000000e+00
+ // LLVM: %[[ARG_INC:.*]] = fadd [[LDTY]] %[[ARG_LOAD]], 1.000000e+00
// LLVM: store [[LDTY]] %[[ARG_INC]], ptr %[[ARG_ALLOCA]]
// LLVMCIR: store [[LDTY]] %[[ARG_LOAD]], ptr %[[RET_ALLOCA]]
// LLVMCIR: %[[LOAD_RET:.*]] = load [[LDTY]], ptr %[[RET_ALLOCA]]
diff --git a/clang/test/CIR/CodeGen/unary.cpp b/clang/test/CIR/CodeGen/unary.cpp
index 06569d63bf48416..344b0374bd2fb1b 100644
--- a/clang/test/CIR/CodeGen/unary.cpp
+++ b/clang/test/CIR/CodeGen/unary.cpp
@@ -309,25 +309,35 @@ float fpPreInc() {
}
// CIR: cir.func{{.*}} @_Z8fpPreIncv() -> (!cir.float{{.*}})
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.float>
// CIR: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.float>
// CIR: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
// CIR: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float
// CIR: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
// CIR: %[[INCREMENTED:.*]] = cir.fadd %[[INPUT]], %[[ONE]]
+// CIR: cir.store{{.*}} %[[INCREMENTED]], %[[A]]
+// CIR: cir.store %[[INCREMENTED]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.float>, !cir.float
+// CIR: cir.return %[[RV_LOAD]] : !cir.float
// LLVM: define{{.*}} float @_Z8fpPreIncv()
// LLVM: %[[RV:.*]] = alloca float, align 4
// LLVM: %[[A:.*]] = alloca float, align 4
// LLVM: store float 1.000000e+00, ptr %[[A]], align 4
// LLVM: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
-// LLVM: %[[RESULT:.*]] = fadd float %[[A_LOAD]], 1.000000e+00
+// LLVM: %[[INCREMENTED:.*]] = fadd float %[[A_LOAD]], 1.000000e+00
+// LLVM: store float %[[INCREMENTED]], ptr %[[A]], align 4
+// LLVM: store float %[[INCREMENTED]], ptr %[[RV]], align 4
+// LLVM: %[[RV_LOAD:.*]] = load float, ptr %[[RV]], align 4
+// LLVM: ret float %[[RV_LOAD]]
// OGCG: define{{.*}} float @_Z8fpPreIncv()
// OGCG: %[[A:.*]] = alloca float, align 4
// OGCG: store float 1.000000e+00, ptr %[[A]], align 4
// OGCG: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
-// OGCG: %[[RESULT:.*]] = fadd float %[[A_LOAD]], 1.000000e+00
+// OGCG: %[[INCREMENTED:.*]] = fadd float %[[A_LOAD]], 1.000000e+00
+// OGCG: ret float %[[INCREMENTED]]
float fpPreDec() {
float a = 1.0f;
@@ -335,25 +345,35 @@ float fpPreDec() {
}
// CIR: cir.func{{.*}} @_Z8fpPreDecv() -> (!cir.float{{.*}})
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.float>
// CIR: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.float>
// CIR: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
// CIR: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float
// CIR: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
// CIR: %[[NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.float
// CIR: %[[DECREMENTED:.*]] = cir.fadd %[[INPUT]], %[[NEGONE]]
+// CIR: cir.store{{.*}} %[[DECREMENTED]], %[[A]]
+// CIR: cir.store %[[DECREMENTED]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.float>, !cir.float
+// CIR: cir.return %[[RV_LOAD]] : !cir.float
// LLVM: define{{.*}} float @_Z8fpPreDecv()
// LLVM: %[[RV:.*]] = alloca float, align 4
// LLVM: %[[A:.*]] = alloca float, align 4
// LLVM: store float 1.000000e+00, ptr %[[A]], align 4
// LLVM: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
-// LLVM: %[[RESULT:.*]] = fadd float %[[A_LOAD]], -1.000000e+00
+// LLVM: %[[DECREMENTED:.*]] = fadd float %[[A_LOAD]], -1.000000e+00
+// LLVM: store float %[[DECREMENTED]], ptr %[[A]], align 4
+// LLVM: store float %[[DECREMENTED]], ptr %[[RV]], align 4
+// LLVM: %[[RV_LOAD:.*]] = load float, ptr %[[RV]], align 4
+// LLVM: ret float %[[RV_LOAD]]
// OGCG: define{{.*}} float @_Z8fpPreDecv()
// OGCG: %[[A:.*]] = alloca float, align 4
// OGCG: store float 1.000000e+00, ptr %[[A]], align 4
// OGCG: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
-// OGCG: %[[RESULT:.*]] = fadd float %[[A_LOAD]], -1.000000e+00
+// OGCG: %[[DECREMENTED:.*]] = fadd float %[[A_LOAD]], -1.000000e+00
+// OGCG: ret float %[[DECREMENTED]]
float fpPostInc() {
float a = 1.0f;
@@ -361,25 +381,35 @@ float fpPostInc() {
}
// CIR: cir.func{{.*}} @_Z9fpPostIncv() -> (!cir.float{{.*}})
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.float>
// CIR: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.float>
// CIR: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
// CIR: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float
// CIR: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
// CIR: %[[INCREMENTED:.*]] = cir.fadd %[[INPUT]], %[[ONE]]
+// CIR: cir.store{{.*}} %[[INCREMENTED]], %[[A]]
+// CIR: cir.store %[[INPUT]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.float>, !cir.float
+// CIR: cir.return %[[RV_LOAD]] : !cir.float
// LLVM: define{{.*}} float @_Z9fpPostIncv()
// LLVM: %[[RV:.*]] = alloca float, align 4
// LLVM: %[[A:.*]] = alloca float, align 4
// LLVM: store float 1.000000e+00, ptr %[[A]], align 4
// LLVM: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
-// LLVM: %[[RESULT:.*]] = fadd float %[[A_LOAD]], 1.000000e+00
+// LLVM: %[[INCREMENTED:.*]] = fadd float %[[A_LOAD]], 1.000000e+00
+// LLVM: store float %[[INCREMENTED]], ptr %[[A]], align 4
+// LLVM: store float %[[A_LOAD]], ptr %[[RV]], align 4
+// LLVM: %[[RV_LOAD:.*]] = load float, ptr %[[RV]], align 4
+// LLVM: ret float %[[RV_LOAD]]
// OGCG: define{{.*}} float @_Z9fpPostIncv()
// OGCG: %[[A:.*]] = alloca float, align 4
// OGCG: store float 1.000000e+00, ptr %[[A]], align 4
// OGCG: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
-// OGCG: %[[RESULT:.*]] = fadd float %[[A_LOAD]], 1.000000e+00
+// OGCG: %[[INCREMENTED:.*]] = fadd float %[[A_LOAD]], 1.000000e+00
+// OGCG: ret float %[[A_LOAD]]
float fpPostDec() {
float a = 1.0f;
@@ -387,25 +417,35 @@ float fpPostDec() {
}
// CIR: cir.func{{.*}} @_Z9fpPostDecv() -> (!cir.float{{.*}})
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.float>
// CIR: %[[A:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.float>
// CIR: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
// CIR: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float
// CIR: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
// CIR: %[[NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.float
// CIR: %[[DECREMENTED:.*]] = cir.fadd %[[INPUT]], %[[NEGONE]]
+// CIR: cir.store{{.*}} %[[DECREMENTED]], %[[A]]
+// CIR: cir.store %[[INPUT]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.float>, !cir.float
+// CIR: cir.return %[[RV_LOAD]] : !cir.float
// LLVM: define{{.*}} float @_Z9fpPostDecv()
// LLVM: %[[RV:.*]] = alloca float, align 4
// LLVM: %[[A:.*]] = alloca float, align 4
// LLVM: store float 1.000000e+00, ptr %[[A]], align 4
// LLVM: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
-// LLVM: %[[RESULT:.*]] = fadd float %[[A_LOAD]], -1.000000e+00
+// LLVM: %[[DECREMENTED:.*]] = fadd float %[[A_LOAD]], -1.000000e+00
+// LLVM: store float %[[DECREMENTED]], ptr %[[A]], align 4
+// LLVM: store float %[[A_LOAD]], ptr %[[RV]], align 4
+// LLVM: %[[RV_LOAD:.*]] = load float, ptr %[[RV]], align 4
+// LLVM: ret float %[[RV_LOAD]]
// OGCG: define{{.*}} float @_Z9fpPostDecv()
// OGCG: %[[A:.*]] = alloca float, align 4
// OGCG: store float 1.000000e+00, ptr %[[A]], align 4
// OGCG: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
-// OGCG: %[[RESULT:.*]] = fadd float %[[A_LOAD]], -1.000000e+00
+// OGCG: %[[DECREMENTED:.*]] = fadd float %[[A_LOAD]], -1.000000e+00
+// OGCG: ret float %[[A_LOAD]]
// Ensure the increment is performed after the assignment to b.
float fpPostInc2() {
@@ -485,17 +525,33 @@ double doubleUPreInc(double f) {
// CIR: cir.func{{.*}} @_Z13doubleUPreIncd({{.*}}) -> (!cir.double{{.*}})
// CIR: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.double>
// CIR: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
// CIR: %[[DBL_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
// CIR: %[[DBL_INC:.*]] = cir.fadd %[[DBL_LOAD]], %[[DBL_ONE]]
+// CIR: cir.store{{.*}} %[[DBL_INC]], %[[DBL_F]]
+// CIR: cir.store %[[DBL_INC]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.double>, !cir.double
+// CIR: cir.return %[[RV_LOAD]] : !cir.double
// LLVM: define{{.*}} double @_Z13doubleUPreIncd({{.*}})
-// LLVM: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
+// LLVM: %[[DBL_F:.*]] = alloca double, align 8
+// LLVM: %[[RV:.*]] = alloca double, align 8
+// LLVM: store double %{{.*}}, ptr %[[DBL_F]], align 8
+// LLVM: %[[DBL_LOAD:.*]] = load double, ptr %[[DBL_F]], align 8
// LLVM: %[[DBL_INC:.*]] = fadd double %[[DBL_LOAD]], 1.000000e+00
+// LLVM: store double %[[DBL_INC]], ptr %[[DBL_F]], align 8
+// LLVM: store double %[[DBL_INC]], ptr %[[RV]], align 8
+// LLVM: %[[RV_LOAD:.*]] = load double, ptr %[[RV]], align 8
+// LLVM: ret double %[[RV_LOAD]]
// OGCG: define{{.*}} double @_Z13doubleUPreIncd({{.*}})
-// OGCG: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
+// OGCG: %[[DBL_F:.*]] = alloca double, align 8
+// OGCG: store double %{{.*}}, ptr %[[DBL_F]], align 8
+// OGCG: %[[DBL_LOAD:.*]] = load double, ptr %[[DBL_F]], align 8
// OGCG: %[[DBL_INC:.*]] = fadd double %[[DBL_LOAD]], 1.000000e+00
+// OGCG: store double %[[DBL_INC]], ptr %[[DBL_F]], align 8
+// OGCG: ret double %[[DBL_INC]]
double doubleUPreDec(double f) {
return --f;
@@ -503,17 +559,33 @@ double doubleUPreDec(double f) {
// CIR: cir.func{{.*}} @_Z13doubleUPreDecd({{.*}}) -> (!cir.double{{.*}})
// CIR: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.double>
// CIR: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
// CIR: %[[DBL_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.double
// CIR: %[[DBL_DEC:.*]] = cir.fadd %[[DBL_LOAD]], %[[DBL_NEGONE]]
+// CIR: cir.store{{.*}} %[[DBL_DEC]], %[[DBL_F]]
+// CIR: cir.store %[[DBL_DEC]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.double>, !cir.double
+// CIR: cir.return %[[RV_LOAD]] : !cir.double
// LLVM: define{{.*}} double @_Z13doubleUPreDecd({{.*}})
-// LLVM: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
+// LLVM: %[[DBL_F:.*]] = alloca double, align 8
+// LLVM: %[[RV:.*]] = alloca double, align 8
+// LLVM: store double %{{.*}}, ptr %[[DBL_F]], align 8
+// LLVM: %[[DBL_LOAD:.*]] = load double, ptr %[[DBL_F]], align 8
// LLVM: %[[DBL_DEC:.*]] = fadd double %[[DBL_LOAD]], -1.000000e+00
+// LLVM: store double %[[DBL_DEC]], ptr %[[DBL_F]], align 8
+// LLVM: store double %[[DBL_DEC]], ptr %[[RV]], align 8
+// LLVM: %[[RV_LOAD:.*]] = load double, ptr %[[RV]], align 8
+// LLVM: ret double %[[RV_LOAD]]
// OGCG: define{{.*}} double @_Z13doubleUPreDecd({{.*}})
-// OGCG: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
+// OGCG: %[[DBL_F:.*]] = alloca double, align 8
+// OGCG: store double %{{.*}}, ptr %[[DBL_F]], align 8
+// OGCG: %[[DBL_LOAD:.*]] = load double, ptr %[[DBL_F]], align 8
// OGCG: %[[DBL_DEC:.*]] = fadd double %[[DBL_LOAD]], -1.000000e+00
+// OGCG: store double %[[DBL_DEC]], ptr %[[DBL_F]], align 8
+// OGCG: ret double %[[DBL_DEC]]
double doubleUPostInc(double f) {
return f++;
@@ -521,17 +593,33 @@ double doubleUPostInc(double f) {
// CIR: cir.func{{.*}} @_Z14doubleUPostIncd({{.*}}) -> (!cir.double{{.*}})
// CIR: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.double>
// CIR: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
// CIR: %[[DBL_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
// CIR: %[[DBL_INC:.*]] = cir.fadd %[[DBL_LOAD]], %[[DBL_ONE]]
+// CIR: cir.store{{.*}} %[[DBL_INC]], %[[DBL_F]]
+// CIR: cir.store %[[DBL_LOAD]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.double>, !cir.double
+// CIR: cir.return %[[RV_LOAD]] : !cir.double
// LLVM: define{{.*}} double @_Z14doubleUPostIncd({{.*}})
-// LLVM: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
+// LLVM: %[[DBL_F:.*]] = alloca double, align 8
+// LLVM: %[[RV:.*]] = alloca double, align 8
+// LLVM: store double %{{.*}}, ptr %[[DBL_F]], align 8
+// LLVM: %[[DBL_LOAD:.*]] = load double, ptr %[[DBL_F]], align 8
// LLVM: %[[DBL_INC:.*]] = fadd double %[[DBL_LOAD]], 1.000000e+00
+// LLVM: store double %[[DBL_INC]], ptr %[[DBL_F]], align 8
+// LLVM: store double %[[DBL_LOAD]], ptr %[[RV]], align 8
+// LLVM: %[[RV_LOAD:.*]] = load double, ptr %[[RV]], align 8
+// LLVM: ret double %[[RV_LOAD]]
// OGCG: define{{.*}} double @_Z14doubleUPostIncd({{.*}})
-// OGCG: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
+// OGCG: %[[DBL_F:.*]] = alloca double, align 8
+// OGCG: store double %{{.*}}, ptr %[[DBL_F]], align 8
+// OGCG: %[[DBL_LOAD:.*]] = load double, ptr %[[DBL_F]], align 8
// OGCG: %[[DBL_INC:.*]] = fadd double %[[DBL_LOAD]], 1.000000e+00
+// OGCG: store double %[[DBL_INC]], ptr %[[DBL_F]], align 8
+// OGCG: ret double %[[DBL_LOAD]]
double doubleUPostDec(double f) {
return f--;
@@ -539,17 +627,33 @@ double doubleUPostDec(double f) {
// CIR: cir.func{{.*}} @_Z14doubleUPostDecd({{.*}}) -> (!cir.double{{.*}})
// CIR: %[[DBL_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.double>
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.double>
// CIR: %[[DBL_LOAD:.*]] = cir.load{{.*}} %[[DBL_F]]
// CIR: %[[DBL_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.double
// CIR: %[[DBL_DEC:.*]] = cir.fadd %[[DBL_LOAD]], %[[DBL_NEGONE]]
+// CIR: cir.store{{.*}} %[[DBL_DEC]], %[[DBL_F]]
+// CIR: cir.store %[[DBL_LOAD]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.double>, !cir.double
+// CIR: cir.return %[[RV_LOAD]] : !cir.double
// LLVM: define{{.*}} double @_Z14doubleUPostDecd({{.*}})
-// LLVM: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
+// LLVM: %[[DBL_F:.*]] = alloca double, align 8
+// LLVM: %[[RV:.*]] = alloca double, align 8
+// LLVM: store double %{{.*}}, ptr %[[DBL_F]], align 8
+// LLVM: %[[DBL_LOAD:.*]] = load double, ptr %[[DBL_F]], align 8
// LLVM: %[[DBL_DEC:.*]] = fadd double %[[DBL_LOAD]], -1.000000e+00
+// LLVM: store double %[[DBL_DEC]], ptr %[[DBL_F]], align 8
+// LLVM: store double %[[DBL_LOAD]], ptr %[[RV]], align 8
+// LLVM: %[[RV_LOAD:.*]] = load double, ptr %[[RV]], align 8
+// LLVM: ret double %[[RV_LOAD]]
// OGCG: define{{.*}} double @_Z14doubleUPostDecd({{.*}})
-// OGCG: %[[DBL_LOAD:.*]] = load double, ptr %{{.*}}, align 8
+// OGCG: %[[DBL_F:.*]] = alloca double, align 8
+// OGCG: store double %{{.*}}, ptr %[[DBL_F]], align 8
+// OGCG: %[[DBL_LOAD:.*]] = load double, ptr %[[DBL_F]], align 8
// OGCG: %[[DBL_DEC:.*]] = fadd double %[[DBL_LOAD]], -1.000000e+00
+// OGCG: store double %[[DBL_DEC]], ptr %[[DBL_F]], align 8
+// OGCG: ret double %[[DBL_LOAD]]
// long double unary operations
long double ldUPlus(long double f) {
@@ -589,17 +693,33 @@ long double ldUPreInc(long double f) {
// CIR: cir.func{{.*}} @_Z9ldUPreInce({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
// CIR: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.long_double<!cir.f80>>
// CIR: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
// CIR: %[[LD_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.long_double<!cir.f80>
// CIR: %[[LD_INC:.*]] = cir.fadd %[[LD_LOAD]], %[[LD_ONE]]
+// CIR: cir.store{{.*}} %[[LD_INC]], %[[LD_F]]
+// CIR: cir.store %[[LD_INC]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.long_double<!cir.f80>>, !cir.long_double<!cir.f80>
+// CIR: cir.return %[[RV_LOAD]] : !cir.long_double<!cir.f80>
// LLVM: define{{.*}} x86_fp80 @_Z9ldUPreInce({{.*}})
-// LLVM: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
+// LLVM: %[[LD_F:.*]] = alloca x86_fp80, align 16
+// LLVM: %[[RV:.*]] = alloca x86_fp80, align 16
+// LLVM: store x86_fp80 %{{.*}}, ptr %[[LD_F]], align 16
+// LLVM: %[[LD_LOAD:.*]] = load x86_fp80, ptr %[[LD_F]], align 16
// LLVM: %[[LD_INC:.*]] = fadd x86_fp80 %[[LD_LOAD]], 1.000000e+00
+// LLVM: store x86_fp80 %[[LD_INC]], ptr %[[LD_F]], align 16
+// LLVM: store x86_fp80 %[[LD_INC]], ptr %[[RV]], align 16
+// LLVM: %[[RV_LOAD:.*]] = load x86_fp80, ptr %[[RV]], align 16
+// LLVM: ret x86_fp80 %[[RV_LOAD]]
// OGCG: define{{.*}} x86_fp80 @_Z9ldUPreInce({{.*}})
-// OGCG: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
+// OGCG: %[[LD_F:.*]] = alloca x86_fp80, align 16
+// OGCG: store x86_fp80 %{{.*}}, ptr %[[LD_F]], align 16
+// OGCG: %[[LD_LOAD:.*]] = load x86_fp80, ptr %[[LD_F]], align 16
// OGCG: %[[LD_INC:.*]] = fadd x86_fp80 %[[LD_LOAD]], 1.000000e+00
+// OGCG: store x86_fp80 %[[LD_INC]], ptr %[[LD_F]], align 16
+// OGCG: ret x86_fp80 %[[LD_INC]]
long double ldUPreDec(long double f) {
return --f;
@@ -607,17 +727,33 @@ long double ldUPreDec(long double f) {
// CIR: cir.func{{.*}} @_Z9ldUPreDece({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
// CIR: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.long_double<!cir.f80>>
// CIR: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
// CIR: %[[LD_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.long_double<!cir.f80>
// CIR: %[[LD_DEC:.*]] = cir.fadd %[[LD_LOAD]], %[[LD_NEGONE]]
+// CIR: cir.store{{.*}} %[[LD_DEC]], %[[LD_F]]
+// CIR: cir.store %[[LD_DEC]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.long_double<!cir.f80>>, !cir.long_double<!cir.f80>
+// CIR: cir.return %[[RV_LOAD]] : !cir.long_double<!cir.f80>
// LLVM: define{{.*}} x86_fp80 @_Z9ldUPreDece({{.*}})
-// LLVM: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
+// LLVM: %[[LD_F:.*]] = alloca x86_fp80, align 16
+// LLVM: %[[RV:.*]] = alloca x86_fp80, align 16
+// LLVM: store x86_fp80 %{{.*}}, ptr %[[LD_F]], align 16
+// LLVM: %[[LD_LOAD:.*]] = load x86_fp80, ptr %[[LD_F]], align 16
// LLVM: %[[LD_DEC:.*]] = fadd x86_fp80 %[[LD_LOAD]], -1.000000e+00
+// LLVM: store x86_fp80 %[[LD_DEC]], ptr %[[LD_F]], align 16
+// LLVM: store x86_fp80 %[[LD_DEC]], ptr %[[RV]], align 16
+// LLVM: %[[RV_LOAD:.*]] = load x86_fp80, ptr %[[RV]], align 16
+// LLVM: ret x86_fp80 %[[RV_LOAD]]
// OGCG: define{{.*}} x86_fp80 @_Z9ldUPreDece({{.*}})
-// OGCG: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
+// OGCG: %[[LD_F:.*]] = alloca x86_fp80, align 16
+// OGCG: store x86_fp80 %{{.*}}, ptr %[[LD_F]], align 16
+// OGCG: %[[LD_LOAD:.*]] = load x86_fp80, ptr %[[LD_F]], align 16
// OGCG: %[[LD_DEC:.*]] = fadd x86_fp80 %[[LD_LOAD]], -1.000000e+00
+// OGCG: store x86_fp80 %[[LD_DEC]], ptr %[[LD_F]], align 16
+// OGCG: ret x86_fp80 %[[LD_DEC]]
long double ldUPostInc(long double f) {
return f++;
@@ -625,17 +761,33 @@ long double ldUPostInc(long double f) {
// CIR: cir.func{{.*}} @_Z10ldUPostInce({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
// CIR: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.long_double<!cir.f80>>
// CIR: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
// CIR: %[[LD_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.long_double<!cir.f80>
// CIR: %[[LD_INC:.*]] = cir.fadd %[[LD_LOAD]], %[[LD_ONE]]
+// CIR: cir.store{{.*}} %[[LD_INC]], %[[LD_F]]
+// CIR: cir.store %[[LD_LOAD]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.long_double<!cir.f80>>, !cir.long_double<!cir.f80>
+// CIR: cir.return %[[RV_LOAD]] : !cir.long_double<!cir.f80>
// LLVM: define{{.*}} x86_fp80 @_Z10ldUPostInce({{.*}})
-// LLVM: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
+// LLVM: %[[LD_F:.*]] = alloca x86_fp80, align 16
+// LLVM: %[[RV:.*]] = alloca x86_fp80, align 16
+// LLVM: store x86_fp80 %{{.*}}, ptr %[[LD_F]], align 16
+// LLVM: %[[LD_LOAD:.*]] = load x86_fp80, ptr %[[LD_F]], align 16
// LLVM: %[[LD_INC:.*]] = fadd x86_fp80 %[[LD_LOAD]], 1.000000e+00
+// LLVM: store x86_fp80 %[[LD_INC]], ptr %[[LD_F]], align 16
+// LLVM: store x86_fp80 %[[LD_LOAD]], ptr %[[RV]], align 16
+// LLVM: %[[RV_LOAD:.*]] = load x86_fp80, ptr %[[RV]], align 16
+// LLVM: ret x86_fp80 %[[RV_LOAD]]
// OGCG: define{{.*}} x86_fp80 @_Z10ldUPostInce({{.*}})
-// OGCG: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
+// OGCG: %[[LD_F:.*]] = alloca x86_fp80, align 16
+// OGCG: store x86_fp80 %{{.*}}, ptr %[[LD_F]], align 16
+// OGCG: %[[LD_LOAD:.*]] = load x86_fp80, ptr %[[LD_F]], align 16
// OGCG: %[[LD_INC:.*]] = fadd x86_fp80 %[[LD_LOAD]], 1.000000e+00
+// OGCG: store x86_fp80 %[[LD_INC]], ptr %[[LD_F]], align 16
+// OGCG: ret x86_fp80 %[[LD_LOAD]]
long double ldUPostDec(long double f) {
return f--;
@@ -643,17 +795,33 @@ long double ldUPostDec(long double f) {
// CIR: cir.func{{.*}} @_Z10ldUPostDece({{.*}}) -> (!cir.long_double<!cir.f80>{{.*}})
// CIR: %[[LD_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.long_double<!cir.f80>>
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.long_double<!cir.f80>>
// CIR: %[[LD_LOAD:.*]] = cir.load{{.*}} %[[LD_F]]
// CIR: %[[LD_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.long_double<!cir.f80>
// CIR: %[[LD_DEC:.*]] = cir.fadd %[[LD_LOAD]], %[[LD_NEGONE]]
+// CIR: cir.store{{.*}} %[[LD_DEC]], %[[LD_F]]
+// CIR: cir.store %[[LD_LOAD]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.long_double<!cir.f80>>, !cir.long_double<!cir.f80>
+// CIR: cir.return %[[RV_LOAD]] : !cir.long_double<!cir.f80>
// LLVM: define{{.*}} x86_fp80 @_Z10ldUPostDece({{.*}})
-// LLVM: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
+// LLVM: %[[LD_F:.*]] = alloca x86_fp80, align 16
+// LLVM: %[[RV:.*]] = alloca x86_fp80, align 16
+// LLVM: store x86_fp80 %{{.*}}, ptr %[[LD_F]], align 16
+// LLVM: %[[LD_LOAD:.*]] = load x86_fp80, ptr %[[LD_F]], align 16
// LLVM: %[[LD_DEC:.*]] = fadd x86_fp80 %[[LD_LOAD]], -1.000000e+00
+// LLVM: store x86_fp80 %[[LD_DEC]], ptr %[[LD_F]], align 16
+// LLVM: store x86_fp80 %[[LD_LOAD]], ptr %[[RV]], align 16
+// LLVM: %[[RV_LOAD:.*]] = load x86_fp80, ptr %[[RV]], align 16
+// LLVM: ret x86_fp80 %[[RV_LOAD]]
// OGCG: define{{.*}} x86_fp80 @_Z10ldUPostDece({{.*}})
-// OGCG: %[[LD_LOAD:.*]] = load x86_fp80, ptr %{{.*}}, align 16
+// OGCG: %[[LD_F:.*]] = alloca x86_fp80, align 16
+// OGCG: store x86_fp80 %{{.*}}, ptr %[[LD_F]], align 16
+// OGCG: %[[LD_LOAD:.*]] = load x86_fp80, ptr %[[LD_F]], align 16
// OGCG: %[[LD_DEC:.*]] = fadd x86_fp80 %[[LD_LOAD]], -1.000000e+00
+// OGCG: store x86_fp80 %[[LD_DEC]], ptr %[[LD_F]], align 16
+// OGCG: ret x86_fp80 %[[LD_LOAD]]
// __float128 unary operations
__float128 f128UPlus(__float128 f) {
@@ -693,17 +861,33 @@ __float128 f128UPreInc(__float128 f) {
// CIR: cir.func{{.*}} @_Z11f128UPreIncg({{.*}}) -> (!cir.f128{{.*}})
// CIR: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.f128>
// CIR: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
// CIR: %[[F128_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f128
// CIR: %[[F128_INC:.*]] = cir.fadd %[[F128_LOAD]], %[[F128_ONE]]
+// CIR: cir.store{{.*}} %[[F128_INC]], %[[F128_F]]
+// CIR: cir.store %[[F128_INC]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.f128>, !cir.f128
+// CIR: cir.return %[[RV_LOAD]] : !cir.f128
// LLVM: define{{.*}} fp128 @_Z11f128UPreIncg({{.*}})
-// LLVM: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
+// LLVM: %[[F128_F:.*]] = alloca fp128, align 16
+// LLVM: %[[RV:.*]] = alloca fp128, align 16
+// LLVM: store fp128 %{{.*}}, ptr %[[F128_F]], align 16
+// LLVM: %[[F128_LOAD:.*]] = load fp128, ptr %[[F128_F]], align 16
// LLVM: %[[F128_INC:.*]] = fadd fp128 %[[F128_LOAD]], 1.000000e+00
+// LLVM: store fp128 %[[F128_INC]], ptr %[[F128_F]], align 16
+// LLVM: store fp128 %[[F128_INC]], ptr %[[RV]], align 16
+// LLVM: %[[RV_LOAD:.*]] = load fp128, ptr %[[RV]], align 16
+// LLVM: ret fp128 %[[RV_LOAD]]
// OGCG: define{{.*}} fp128 @_Z11f128UPreIncg({{.*}})
-// OGCG: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
+// OGCG: %[[F128_F:.*]] = alloca fp128, align 16
+// OGCG: store fp128 %{{.*}}, ptr %[[F128_F]], align 16
+// OGCG: %[[F128_LOAD:.*]] = load fp128, ptr %[[F128_F]], align 16
// OGCG: %[[F128_INC:.*]] = fadd fp128 %[[F128_LOAD]], 1.000000e+00
+// OGCG: store fp128 %[[F128_INC]], ptr %[[F128_F]], align 16
+// OGCG: ret fp128 %[[F128_INC]]
__float128 f128UPreDec(__float128 f) {
return --f;
@@ -711,17 +895,33 @@ __float128 f128UPreDec(__float128 f) {
// CIR: cir.func{{.*}} @_Z11f128UPreDecg({{.*}}) -> (!cir.f128{{.*}})
// CIR: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.f128>
// CIR: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
// CIR: %[[F128_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.f128
// CIR: %[[F128_DEC:.*]] = cir.fadd %[[F128_LOAD]], %[[F128_NEGONE]]
+// CIR: cir.store{{.*}} %[[F128_DEC]], %[[F128_F]]
+// CIR: cir.store %[[F128_DEC]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.f128>, !cir.f128
+// CIR: cir.return %[[RV_LOAD]] : !cir.f128
// LLVM: define{{.*}} fp128 @_Z11f128UPreDecg({{.*}})
-// LLVM: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
+// LLVM: %[[F128_F:.*]] = alloca fp128, align 16
+// LLVM: %[[RV:.*]] = alloca fp128, align 16
+// LLVM: store fp128 %{{.*}}, ptr %[[F128_F]], align 16
+// LLVM: %[[F128_LOAD:.*]] = load fp128, ptr %[[F128_F]], align 16
// LLVM: %[[F128_DEC:.*]] = fadd fp128 %[[F128_LOAD]], -1.000000e+00
+// LLVM: store fp128 %[[F128_DEC]], ptr %[[F128_F]], align 16
+// LLVM: store fp128 %[[F128_DEC]], ptr %[[RV]], align 16
+// LLVM: %[[RV_LOAD:.*]] = load fp128, ptr %[[RV]], align 16
+// LLVM: ret fp128 %[[RV_LOAD]]
// OGCG: define{{.*}} fp128 @_Z11f128UPreDecg({{.*}})
-// OGCG: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
+// OGCG: %[[F128_F:.*]] = alloca fp128, align 16
+// OGCG: store fp128 %{{.*}}, ptr %[[F128_F]], align 16
+// OGCG: %[[F128_LOAD:.*]] = load fp128, ptr %[[F128_F]], align 16
// OGCG: %[[F128_DEC:.*]] = fadd fp128 %[[F128_LOAD]], -1.000000e+00
+// OGCG: store fp128 %[[F128_DEC]], ptr %[[F128_F]], align 16
+// OGCG: ret fp128 %[[F128_DEC]]
__float128 f128UPostInc(__float128 f) {
return f++;
@@ -729,17 +929,33 @@ __float128 f128UPostInc(__float128 f) {
// CIR: cir.func{{.*}} @_Z12f128UPostIncg({{.*}}) -> (!cir.f128{{.*}})
// CIR: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.f128>
// CIR: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
// CIR: %[[F128_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f128
// CIR: %[[F128_INC:.*]] = cir.fadd %[[F128_LOAD]], %[[F128_ONE]]
+// CIR: cir.store{{.*}} %[[F128_INC]], %[[F128_F]]
+// CIR: cir.store %[[F128_LOAD]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.f128>, !cir.f128
+// CIR: cir.return %[[RV_LOAD]] : !cir.f128
// LLVM: define{{.*}} fp128 @_Z12f128UPostIncg({{.*}})
-// LLVM: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
+// LLVM: %[[F128_F:.*]] = alloca fp128, align 16
+// LLVM: %[[RV:.*]] = alloca fp128, align 16
+// LLVM: store fp128 %{{.*}}, ptr %[[F128_F]], align 16
+// LLVM: %[[F128_LOAD:.*]] = load fp128, ptr %[[F128_F]], align 16
// LLVM: %[[F128_INC:.*]] = fadd fp128 %[[F128_LOAD]], 1.000000e+00
+// LLVM: store fp128 %[[F128_INC]], ptr %[[F128_F]], align 16
+// LLVM: store fp128 %[[F128_LOAD]], ptr %[[RV]], align 16
+// LLVM: %[[RV_LOAD:.*]] = load fp128, ptr %[[RV]], align 16
+// LLVM: ret fp128 %[[RV_LOAD]]
// OGCG: define{{.*}} fp128 @_Z12f128UPostIncg({{.*}})
-// OGCG: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
+// OGCG: %[[F128_F:.*]] = alloca fp128, align 16
+// OGCG: store fp128 %{{.*}}, ptr %[[F128_F]], align 16
+// OGCG: %[[F128_LOAD:.*]] = load fp128, ptr %[[F128_F]], align 16
// OGCG: %[[F128_INC:.*]] = fadd fp128 %[[F128_LOAD]], 1.000000e+00
+// OGCG: store fp128 %[[F128_INC]], ptr %[[F128_F]], align 16
+// OGCG: ret fp128 %[[F128_LOAD]]
__float128 f128UPostDec(__float128 f) {
return f--;
@@ -747,17 +963,33 @@ __float128 f128UPostDec(__float128 f) {
// CIR: cir.func{{.*}} @_Z12f128UPostDecg({{.*}}) -> (!cir.f128{{.*}})
// CIR: %[[F128_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f128>
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.f128>
// CIR: %[[F128_LOAD:.*]] = cir.load{{.*}} %[[F128_F]]
// CIR: %[[F128_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.f128
// CIR: %[[F128_DEC:.*]] = cir.fadd %[[F128_LOAD]], %[[F128_NEGONE]]
+// CIR: cir.store{{.*}} %[[F128_DEC]], %[[F128_F]]
+// CIR: cir.store %[[F128_LOAD]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.f128>, !cir.f128
+// CIR: cir.return %[[RV_LOAD]] : !cir.f128
// LLVM: define{{.*}} fp128 @_Z12f128UPostDecg({{.*}})
-// LLVM: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
+// LLVM: %[[F128_F:.*]] = alloca fp128, align 16
+// LLVM: %[[RV:.*]] = alloca fp128, align 16
+// LLVM: store fp128 %{{.*}}, ptr %[[F128_F]], align 16
+// LLVM: %[[F128_LOAD:.*]] = load fp128, ptr %[[F128_F]], align 16
// LLVM: %[[F128_DEC:.*]] = fadd fp128 %[[F128_LOAD]], -1.000000e+00
+// LLVM: store fp128 %[[F128_DEC]], ptr %[[F128_F]], align 16
+// LLVM: store fp128 %[[F128_LOAD]], ptr %[[RV]], align 16
+// LLVM: %[[RV_LOAD:.*]] = load fp128, ptr %[[RV]], align 16
+// LLVM: ret fp128 %[[RV_LOAD]]
// OGCG: define{{.*}} fp128 @_Z12f128UPostDecg({{.*}})
-// OGCG: %[[F128_LOAD:.*]] = load fp128, ptr %{{.*}}, align 16
+// OGCG: %[[F128_F:.*]] = alloca fp128, align 16
+// OGCG: store fp128 %{{.*}}, ptr %[[F128_F]], align 16
+// OGCG: %[[F128_LOAD:.*]] = load fp128, ptr %[[F128_F]], align 16
// OGCG: %[[F128_DEC:.*]] = fadd fp128 %[[F128_LOAD]], -1.000000e+00
+// OGCG: store fp128 %[[F128_DEC]], ptr %[[F128_F]], align 16
+// OGCG: ret fp128 %[[F128_LOAD]]
// Float16 unary operations
_Float16 Float16UPlus(_Float16 f) {
@@ -807,19 +1039,33 @@ _Float16 Float16UPreInc(_Float16 f) {
// CIR: cir.func{{.*}} @_Z14Float16UPreIncDF16_({{.*}}) -> (!cir.f16{{.*}})
// CIR: %[[PREINC_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f16>
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.f16>
// CIR: %[[PREINC_INPUT:.*]] = cir.load{{.*}} %[[PREINC_F]]
// CIR: %[[PREINC_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f16
// CIR: %[[PREINC_RESULT:.*]] = cir.fadd %[[PREINC_INPUT]], %[[PREINC_ONE]] : !cir.f16
+// CIR: cir.store{{.*}} %[[PREINC_RESULT]], %[[PREINC_F]]
+// CIR: cir.store %[[PREINC_RESULT]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.f16>, !cir.f16
+// CIR: cir.return %[[RV_LOAD]] : !cir.f16
// LLVM: define{{.*}} half @_Z14Float16UPreIncDF16_({{.*}})
// LLVM: %[[PREINC_F_ADDR:.*]] = alloca half, align 2
+// LLVM: %[[RV:.*]] = alloca half, align 2
+// LLVM: store half %{{.*}}, ptr %[[PREINC_F_ADDR]], align 2
// LLVM: %[[PREINC_INPUT:.*]] = load half, ptr %[[PREINC_F_ADDR]], align 2
// LLVM: %[[PREINC_RESULT:.*]] = fadd half %[[PREINC_INPUT]], 1.000000e+00
+// LLVM: store half %[[PREINC_RESULT]], ptr %[[PREINC_F_ADDR]], align 2
+// LLVM: store half %[[PREINC_RESULT]], ptr %[[RV]], align 2
+// LLVM: %[[RV_LOAD:.*]] = load half, ptr %[[RV]], align 2
+// LLVM: ret half %[[RV_LOAD]]
// OGCG: define{{.*}} half @_Z14Float16UPreIncDF16_({{.*}})
// OGCG: %[[PREINC_F_ADDR:.*]] = alloca half, align 2
+// OGCG: store half %{{.*}}, ptr %[[PREINC_F_ADDR]], align 2
// OGCG: %[[PREINC_INPUT:.*]] = load half, ptr %[[PREINC_F_ADDR]], align 2
// OGCG: %[[PREINC_RESULT:.*]] = fadd half %[[PREINC_INPUT]], 1.000000e+00
+// OGCG: store half %[[PREINC_RESULT]], ptr %[[PREINC_F_ADDR]], align 2
+// OGCG: ret half %[[PREINC_RESULT]]
_Float16 Float16UPreDec(_Float16 f) {
return --f;
@@ -827,19 +1073,33 @@ _Float16 Float16UPreDec(_Float16 f) {
// CIR: cir.func{{.*}} @_Z14Float16UPreDecDF16_({{.*}}) -> (!cir.f16{{.*}})
// CIR: %[[PREDEC_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f16>
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.f16>
// CIR: %[[PREDEC_INPUT:.*]] = cir.load{{.*}} %[[PREDEC_F]]
// CIR: %[[PREDEC_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.f16
// CIR: %[[PREDEC_RESULT:.*]] = cir.fadd %[[PREDEC_INPUT]], %[[PREDEC_NEGONE]] : !cir.f16
+// CIR: cir.store{{.*}} %[[PREDEC_RESULT]], %[[PREDEC_F]]
+// CIR: cir.store %[[PREDEC_RESULT]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.f16>, !cir.f16
+// CIR: cir.return %[[RV_LOAD]] : !cir.f16
// LLVM: define{{.*}} half @_Z14Float16UPreDecDF16_({{.*}})
// LLVM: %[[PREDEC_F_ADDR:.*]] = alloca half, align 2
+// LLVM: %[[RV:.*]] = alloca half, align 2
+// LLVM: store half %{{.*}}, ptr %[[PREDEC_F_ADDR]], align 2
// LLVM: %[[PREDEC_INPUT:.*]] = load half, ptr %[[PREDEC_F_ADDR]], align 2
// LLVM: %[[PREDEC_RESULT:.*]] = fadd half %[[PREDEC_INPUT]], -1.000000e+00
+// LLVM: store half %[[PREDEC_RESULT]], ptr %[[PREDEC_F_ADDR]], align 2
+// LLVM: store half %[[PREDEC_RESULT]], ptr %[[RV]], align 2
+// LLVM: %[[RV_LOAD:.*]] = load half, ptr %[[RV]], align 2
+// LLVM: ret half %[[RV_LOAD]]
// OGCG: define{{.*}} half @_Z14Float16UPreDecDF16_({{.*}})
// OGCG: %[[PREDEC_F_ADDR:.*]] = alloca half, align 2
+// OGCG: store half %{{.*}}, ptr %[[PREDEC_F_ADDR]], align 2
// OGCG: %[[PREDEC_INPUT:.*]] = load half, ptr %[[PREDEC_F_ADDR]], align 2
// OGCG: %[[PREDEC_RESULT:.*]] = fadd half %[[PREDEC_INPUT]], -1.000000e+00
+// OGCG: store half %[[PREDEC_RESULT]], ptr %[[PREDEC_F_ADDR]], align 2
+// OGCG: ret half %[[PREDEC_RESULT]]
_Float16 Float16UPostInc(_Float16 f) {
return f++;
@@ -847,19 +1107,33 @@ _Float16 Float16UPostInc(_Float16 f) {
// CIR: cir.func{{.*}} @_Z15Float16UPostIncDF16_({{.*}}) -> (!cir.f16{{.*}})
// CIR: %[[POSTINC_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f16>
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.f16>
// CIR: %[[POSTINC_INPUT:.*]] = cir.load{{.*}} %[[POSTINC_F]]
// CIR: %[[POSTINC_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.f16
// CIR: %[[POSTINC_RESULT:.*]] = cir.fadd %[[POSTINC_INPUT]], %[[POSTINC_ONE]] : !cir.f16
+// CIR: cir.store{{.*}} %[[POSTINC_RESULT]], %[[POSTINC_F]]
+// CIR: cir.store %[[POSTINC_INPUT]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.f16>, !cir.f16
+// CIR: cir.return %[[RV_LOAD]] : !cir.f16
// LLVM: define{{.*}} half @_Z15Float16UPostIncDF16_({{.*}})
// LLVM: %[[POSTINC_F_ADDR:.*]] = alloca half, align 2
+// LLVM: %[[RV:.*]] = alloca half, align 2
+// LLVM: store half %{{.*}}, ptr %[[POSTINC_F_ADDR]], align 2
// LLVM: %[[POSTINC_INPUT:.*]] = load half, ptr %[[POSTINC_F_ADDR]], align 2
// LLVM: %[[POSTINC_RESULT:.*]] = fadd half %[[POSTINC_INPUT]], 1.000000e+00
+// LLVM: store half %[[POSTINC_RESULT]], ptr %[[POSTINC_F_ADDR]], align 2
+// LLVM: store half %[[POSTINC_INPUT]], ptr %[[RV]], align 2
+// LLVM: %[[RV_LOAD:.*]] = load half, ptr %[[RV]], align 2
+// LLVM: ret half %[[RV_LOAD]]
// OGCG: define{{.*}} half @_Z15Float16UPostIncDF16_({{.*}})
// OGCG: %[[POSTINC_F_ADDR:.*]] = alloca half, align 2
+// OGCG: store half %{{.*}}, ptr %[[POSTINC_F_ADDR]], align 2
// OGCG: %[[POSTINC_INPUT:.*]] = load half, ptr %[[POSTINC_F_ADDR]], align 2
// OGCG: %[[POSTINC_RESULT:.*]] = fadd half %[[POSTINC_INPUT]], 1.000000e+00
+// OGCG: store half %[[POSTINC_RESULT]], ptr %[[POSTINC_F_ADDR]], align 2
+// OGCG: ret half %[[POSTINC_INPUT]]
_Float16 Float16UPostDec(_Float16 f) {
return f--;
@@ -867,19 +1141,33 @@ _Float16 Float16UPostDec(_Float16 f) {
// CIR: cir.func{{.*}} @_Z15Float16UPostDecDF16_({{.*}}) -> (!cir.f16{{.*}})
// CIR: %[[POSTDEC_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.f16>
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.f16>
// CIR: %[[POSTDEC_INPUT:.*]] = cir.load{{.*}} %[[POSTDEC_F]]
// CIR: %[[POSTDEC_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.f16
// CIR: %[[POSTDEC_RESULT:.*]] = cir.fadd %[[POSTDEC_INPUT]], %[[POSTDEC_NEGONE]] : !cir.f16
+// CIR: cir.store{{.*}} %[[POSTDEC_RESULT]], %[[POSTDEC_F]]
+// CIR: cir.store %[[POSTDEC_INPUT]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.f16>, !cir.f16
+// CIR: cir.return %[[RV_LOAD]] : !cir.f16
// LLVM: define{{.*}} half @_Z15Float16UPostDecDF16_({{.*}})
// LLVM: %[[POSTDEC_F_ADDR:.*]] = alloca half, align 2
+// LLVM: %[[RV:.*]] = alloca half, align 2
+// LLVM: store half %{{.*}}, ptr %[[POSTDEC_F_ADDR]], align 2
// LLVM: %[[POSTDEC_INPUT:.*]] = load half, ptr %[[POSTDEC_F_ADDR]], align 2
// LLVM: %[[POSTDEC_RESULT:.*]] = fadd half %[[POSTDEC_INPUT]], -1.000000e+00
+// LLVM: store half %[[POSTDEC_RESULT]], ptr %[[POSTDEC_F_ADDR]], align 2
+// LLVM: store half %[[POSTDEC_INPUT]], ptr %[[RV]], align 2
+// LLVM: %[[RV_LOAD:.*]] = load half, ptr %[[RV]], align 2
+// LLVM: ret half %[[RV_LOAD]]
// OGCG: define{{.*}} half @_Z15Float16UPostDecDF16_({{.*}})
// OGCG: %[[POSTDEC_F_ADDR:.*]] = alloca half, align 2
+// OGCG: store half %{{.*}}, ptr %[[POSTDEC_F_ADDR]], align 2
// OGCG: %[[POSTDEC_INPUT:.*]] = load half, ptr %[[POSTDEC_F_ADDR]], align 2
// OGCG: %[[POSTDEC_RESULT:.*]] = fadd half %[[POSTDEC_INPUT]], -1.000000e+00
+// OGCG: store half %[[POSTDEC_RESULT]], ptr %[[POSTDEC_F_ADDR]], align 2
+// OGCG: ret half %[[POSTDEC_INPUT]]
// __fp16 unary operations
void fp16PtrUPlus(__fp16 *f) {
@@ -927,105 +1215,185 @@ void fp16PtrUMinus(__fp16 *f) {
// OGCG: %[[FPTR_NEGATED:.*]] = fneg float %[[FPTR_PROMOTED]]
// OGCG: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_NEGATED]] to half
-void fp16PtrUPreInc(__fp16 *f) {
- ++(*f);
+void fp16PtrUPreInc(__fp16 *f, __fp16 *ret) {
+ *ret = ++(*f);
}
-// CIR: cir.func{{.*}} @_Z14fp16PtrUPreIncPDh({{.*}})
+// CIR: cir.func{{.*}} @_Z14fp16PtrUPreIncPDhS_({{.*}})
// CIR: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
+// CIR: %[[FPTR_RET:.*]] = cir.alloca "ret" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
// CIR: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
// CIR: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
// CIR: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
// CIR: %[[FPTR_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
// CIR: %[[FPTR_INC:.*]] = cir.fadd %[[FPTR_PROMOTED]], %[[FPTR_ONE]] : !cir.float
// CIR: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_INC]] : !cir.float -> !cir.f16
-
-// LLVM: define{{.*}} void @_Z14fp16PtrUPreIncPDh({{.*}})
-// LLVM: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
+// CIR: cir.store{{.*}} %[[FPTR_UNPROMOTED]], %[[FPTR_DEREF]]
+// CIR: %[[RET_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_RET]]
+// CIR: cir.store{{.*}} %[[FPTR_UNPROMOTED]], %[[RET_DEREF]]
+
+// LLVM: define{{.*}} void @_Z14fp16PtrUPreIncPDhS_({{.*}})
+// LLVM: %[[F_ADDR:.*]] = alloca ptr, align 8
+// LLVM: %[[RET_ADDR_PTR:.*]] = alloca ptr, align 8
+// LLVM: store ptr %{{.*}}, ptr %[[F_ADDR]], align 8
+// LLVM: store ptr %{{.*}}, ptr %[[RET_ADDR_PTR]], align 8
+// LLVM: %[[F_PTR:.*]] = load ptr, ptr %[[F_ADDR]], align 8
+// LLVM: %[[FPTR_LOAD:.*]] = load half, ptr %[[F_PTR]], align 2
// LLVM: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
// LLVM: %[[FPTR_INC:.*]] = fadd float %[[FPTR_PROMOTED]], 1.000000e+00
// LLVM: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_INC]] to half
-
-// OGCG: define{{.*}} void @_Z14fp16PtrUPreIncPDh({{.*}})
-// OGCG: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
+// LLVM: store half %[[FPTR_UNPROMOTED]], ptr %[[F_PTR]], align 2
+// LLVM: %[[RET_ADDR:.*]] = load ptr, ptr %[[RET_ADDR_PTR]], align 8
+// LLVM: store half %[[FPTR_UNPROMOTED]], ptr %[[RET_ADDR]], align 2
+
+// OGCG: define{{.*}} void @_Z14fp16PtrUPreIncPDhS_({{.*}})
+// OGCG: %[[F_ADDR:.*]] = alloca ptr, align 8
+// OGCG: %[[RET_ADDR_PTR:.*]] = alloca ptr, align 8
+// OGCG: store ptr %{{.*}}, ptr %[[F_ADDR]], align 8
+// OGCG: store ptr %{{.*}}, ptr %[[RET_ADDR_PTR]], align 8
+// OGCG: %[[F_PTR:.*]] = load ptr, ptr %[[F_ADDR]], align 8
+// OGCG: %[[FPTR_LOAD:.*]] = load half, ptr %[[F_PTR]], align 2
// OGCG: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
// OGCG: %[[FPTR_INC:.*]] = fadd float %[[FPTR_PROMOTED]], 1.000000e+00
// OGCG: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_INC]] to half
+// OGCG: store half %[[FPTR_UNPROMOTED]], ptr %[[F_PTR]], align 2
+// OGCG: %[[RET_ADDR:.*]] = load ptr, ptr %[[RET_ADDR_PTR]], align 8
+// OGCG: store half %[[FPTR_UNPROMOTED]], ptr %[[RET_ADDR]], align 2
-void fp16PtrUPreDec(__fp16 *f) {
- --(*f);
+void fp16PtrUPreDec(__fp16 *f, __fp16 *ret) {
+ *ret = --(*f);
}
-// CIR: cir.func{{.*}} @_Z14fp16PtrUPreDecPDh({{.*}})
+// CIR: cir.func{{.*}} @_Z14fp16PtrUPreDecPDhS_({{.*}})
// CIR: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
+// CIR: %[[FPTR_RET:.*]] = cir.alloca "ret" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
// CIR: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
// CIR: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
// CIR: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
// CIR: %[[FPTR_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.float
// CIR: %[[FPTR_DEC:.*]] = cir.fadd %[[FPTR_PROMOTED]], %[[FPTR_NEGONE]] : !cir.float
// CIR: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_DEC]] : !cir.float -> !cir.f16
-
-// LLVM: define{{.*}} void @_Z14fp16PtrUPreDecPDh({{.*}})
-// LLVM: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
+// CIR: cir.store{{.*}} %[[FPTR_UNPROMOTED]], %[[FPTR_DEREF]]
+// CIR: %[[RET_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_RET]]
+// CIR: cir.store{{.*}} %[[FPTR_UNPROMOTED]], %[[RET_DEREF]]
+
+// LLVM: define{{.*}} void @_Z14fp16PtrUPreDecPDhS_({{.*}})
+// LLVM: %[[F_ADDR:.*]] = alloca ptr, align 8
+// LLVM: %[[RET_ADDR_PTR:.*]] = alloca ptr, align 8
+// LLVM: store ptr %{{.*}}, ptr %[[F_ADDR]], align 8
+// LLVM: store ptr %{{.*}}, ptr %[[RET_ADDR_PTR]], align 8
+// LLVM: %[[F_PTR:.*]] = load ptr, ptr %[[F_ADDR]], align 8
+// LLVM: %[[FPTR_LOAD:.*]] = load half, ptr %[[F_PTR]], align 2
// LLVM: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
// LLVM: %[[FPTR_DEC:.*]] = fadd float %[[FPTR_PROMOTED]], -1.000000e+00
// LLVM: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_DEC]] to half
-
-// OGCG: define{{.*}} void @_Z14fp16PtrUPreDecPDh({{.*}})
-// OGCG: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
+// LLVM: store half %[[FPTR_UNPROMOTED]], ptr %[[F_PTR]], align 2
+// LLVM: %[[RET_ADDR:.*]] = load ptr, ptr %[[RET_ADDR_PTR]], align 8
+// LLVM: store half %[[FPTR_UNPROMOTED]], ptr %[[RET_ADDR]], align 2
+
+// OGCG: define{{.*}} void @_Z14fp16PtrUPreDecPDhS_({{.*}})
+// OGCG: %[[F_ADDR:.*]] = alloca ptr, align 8
+// OGCG: %[[RET_ADDR_PTR:.*]] = alloca ptr, align 8
+// OGCG: store ptr %{{.*}}, ptr %[[F_ADDR]], align 8
+// OGCG: store ptr %{{.*}}, ptr %[[RET_ADDR_PTR]], align 8
+// OGCG: %[[F_PTR:.*]] = load ptr, ptr %[[F_ADDR]], align 8
+// OGCG: %[[FPTR_LOAD:.*]] = load half, ptr %[[F_PTR]], align 2
// OGCG: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
// OGCG: %[[FPTR_DEC:.*]] = fadd float %[[FPTR_PROMOTED]], -1.000000e+00
// OGCG: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_DEC]] to half
+// OGCG: store half %[[FPTR_UNPROMOTED]], ptr %[[F_PTR]], align 2
+// OGCG: %[[RET_ADDR:.*]] = load ptr, ptr %[[RET_ADDR_PTR]], align 8
+// OGCG: store half %[[FPTR_UNPROMOTED]], ptr %[[RET_ADDR]], align 2
-void fp16PtrUPostInc(__fp16 *f) {
- (*f)++;
+void fp16PtrUPostInc(__fp16 *f, __fp16 *ret) {
+ *ret = (*f)++;
}
-// CIR: cir.func{{.*}} @_Z15fp16PtrUPostIncPDh({{.*}})
+// CIR: cir.func{{.*}} @_Z15fp16PtrUPostIncPDhS_({{.*}})
// CIR: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
+// CIR: %[[FPTR_RET:.*]] = cir.alloca "ret" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
// CIR: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
// CIR: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
// CIR: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
// CIR: %[[FPTR_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
// CIR: %[[FPTR_INC:.*]] = cir.fadd %[[FPTR_PROMOTED]], %[[FPTR_ONE]] : !cir.float
-// CIR: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_DEC]] : !cir.float -> !cir.f16
-
-// LLVM: define{{.*}} void @_Z15fp16PtrUPostIncPDh({{.*}})
-// LLVM: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
+// CIR: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_INC]] : !cir.float -> !cir.f16
+// CIR: cir.store{{.*}} %[[FPTR_UNPROMOTED]], %[[FPTR_DEREF]]
+// CIR: %[[RET_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_RET]]
+// CIR: cir.store{{.*}} %[[FPTR_LOAD]], %[[RET_DEREF]]
+
+// LLVM: define{{.*}} void @_Z15fp16PtrUPostIncPDhS_({{.*}})
+// LLVM: %[[F_ADDR:.*]] = alloca ptr, align 8
+// LLVM: %[[RET_ADDR_PTR:.*]] = alloca ptr, align 8
+// LLVM: store ptr %{{.*}}, ptr %[[F_ADDR]], align 8
+// LLVM: store ptr %{{.*}}, ptr %[[RET_ADDR_PTR]], align 8
+// LLVM: %[[F_PTR:.*]] = load ptr, ptr %[[F_ADDR]], align 8
+// LLVM: %[[FPTR_LOAD:.*]] = load half, ptr %[[F_PTR]], align 2
// LLVM: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
// LLVM: %[[FPTR_INC:.*]] = fadd float %[[FPTR_PROMOTED]], 1.000000e+00
// LLVM: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_INC]] to half
-
-// OGCG: define{{.*}} void @_Z15fp16PtrUPostIncPDh({{.*}})
-// OGCG: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
+// LLVM: store half %[[FPTR_UNPROMOTED]], ptr %[[F_PTR]], align 2
+// LLVM: %[[RET_ADDR:.*]] = load ptr, ptr %[[RET_ADDR_PTR]], align 8
+// LLVM: store half %[[FPTR_LOAD]], ptr %[[RET_ADDR]], align 2
+
+// OGCG: define{{.*}} void @_Z15fp16PtrUPostIncPDhS_({{.*}})
+// OGCG: %[[F_ADDR:.*]] = alloca ptr, align 8
+// OGCG: %[[RET_ADDR_PTR:.*]] = alloca ptr, align 8
+// OGCG: store ptr %{{.*}}, ptr %[[F_ADDR]], align 8
+// OGCG: store ptr %{{.*}}, ptr %[[RET_ADDR_PTR]], align 8
+// OGCG: %[[F_PTR:.*]] = load ptr, ptr %[[F_ADDR]], align 8
+// OGCG: %[[FPTR_LOAD:.*]] = load half, ptr %[[F_PTR]], align 2
// OGCG: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
// OGCG: %[[FPTR_INC:.*]] = fadd float %[[FPTR_PROMOTED]], 1.000000e+00
// OGCG: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_INC]] to half
+// OGCG: store half %[[FPTR_UNPROMOTED]], ptr %[[F_PTR]], align 2
+// OGCG: %[[RET_ADDR:.*]] = load ptr, ptr %[[RET_ADDR_PTR]], align 8
+// OGCG: store half %[[FPTR_LOAD]], ptr %[[RET_ADDR]], align 2
-void fp16PtrUPostDec(__fp16 *f) {
- (*f)--;
+void fp16PtrUPostDec(__fp16 *f, __fp16 *ret) {
+ *ret = (*f)--;
}
-// CIR: cir.func{{.*}} @_Z15fp16PtrUPostDecPDh({{.*}})
+// CIR: cir.func{{.*}} @_Z15fp16PtrUPostDecPDhS_({{.*}})
// CIR: %[[FPTR_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
+// CIR: %[[FPTR_RET:.*]] = cir.alloca "ret" {{.*}} init : !cir.ptr<!cir.ptr<!cir.f16>>
// CIR: %[[FPTR_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_F]]
// CIR: %[[FPTR_LOAD:.*]] = cir.load{{.*}} %[[FPTR_DEREF]]
// CIR: %[[FPTR_PROMOTED:.*]] = cir.cast floating %[[FPTR_LOAD]] : !cir.f16 -> !cir.float
// CIR: %[[FPTR_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.float
// CIR: %[[FPTR_DEC:.*]] = cir.fadd %[[FPTR_PROMOTED]], %[[FPTR_NEGONE]] : !cir.float
// CIR: %[[FPTR_UNPROMOTED:.*]] = cir.cast floating %[[FPTR_DEC]] : !cir.float -> !cir.f16
-
-// LLVM: define{{.*}} void @_Z15fp16PtrUPostDecPDh({{.*}})
-// LLVM: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
+// CIR: cir.store{{.*}} %[[FPTR_UNPROMOTED]], %[[FPTR_DEREF]]
+// CIR: %[[RET_DEREF:.*]] = cir.load deref{{.*}} %[[FPTR_RET]]
+// CIR: cir.store{{.*}} %[[FPTR_LOAD]], %[[RET_DEREF]]
+
+// LLVM: define{{.*}} void @_Z15fp16PtrUPostDecPDhS_({{.*}})
+// LLVM: %[[F_ADDR:.*]] = alloca ptr, align 8
+// LLVM: %[[RET_ADDR_PTR:.*]] = alloca ptr, align 8
+// LLVM: store ptr %{{.*}}, ptr %[[F_ADDR]], align 8
+// LLVM: store ptr %{{.*}}, ptr %[[RET_ADDR_PTR]], align 8
+// LLVM: %[[F_PTR:.*]] = load ptr, ptr %[[F_ADDR]], align 8
+// LLVM: %[[FPTR_LOAD:.*]] = load half, ptr %[[F_PTR]], align 2
// LLVM: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
// LLVM: %[[FPTR_DEC:.*]] = fadd float %[[FPTR_PROMOTED]], -1.000000e+00
// LLVM: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_DEC]] to half
-
-// OGCG: define{{.*}} void @_Z15fp16PtrUPostDecPDh({{.*}})
-// OGCG: %[[FPTR_LOAD:.*]] = load half, ptr %{{.*}}, align 2
+// LLVM: store half %[[FPTR_UNPROMOTED]], ptr %[[F_PTR]], align 2
+// LLVM: %[[RET_ADDR:.*]] = load ptr, ptr %[[RET_ADDR_PTR]], align 8
+// LLVM: store half %[[FPTR_LOAD]], ptr %[[RET_ADDR]], align 2
+
+// OGCG: define{{.*}} void @_Z15fp16PtrUPostDecPDhS_({{.*}})
+// OGCG: %[[F_ADDR:.*]] = alloca ptr, align 8
+// OGCG: %[[RET_ADDR_PTR:.*]] = alloca ptr, align 8
+// OGCG: store ptr %{{.*}}, ptr %[[F_ADDR]], align 8
+// OGCG: store ptr %{{.*}}, ptr %[[RET_ADDR_PTR]], align 8
+// OGCG: %[[F_PTR:.*]] = load ptr, ptr %[[F_ADDR]], align 8
+// OGCG: %[[FPTR_LOAD:.*]] = load half, ptr %[[F_PTR]], align 2
// OGCG: %[[FPTR_PROMOTED:.*]] = fpext half %[[FPTR_LOAD]] to float
// OGCG: %[[FPTR_DEC:.*]] = fadd float %[[FPTR_PROMOTED]], -1.000000e+00
// OGCG: %[[FPTR_UNPROMOTED:.*]] = fptrunc float %[[FPTR_DEC]] to half
+// OGCG: store half %[[FPTR_UNPROMOTED]], ptr %[[F_PTR]], align 2
+// OGCG: %[[RET_ADDR:.*]] = load ptr, ptr %[[RET_ADDR_PTR]], align 8
+// OGCG: store half %[[FPTR_LOAD]], ptr %[[RET_ADDR]], align 2
// __bf16 unary operations
__bf16 bf16UPlus(__bf16 f) {
@@ -1077,16 +1445,33 @@ __bf16 bf16UPreInc(__bf16 f) {
// CIR: cir.func{{.*}} @_Z11bf16UPreIncDF16b({{.*}}) -> (!cir.bf16{{.*}})
// CIR: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.bf16>
// CIR: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
-// CIR: %[[BF16_INC:.*]] = cir.fadd %[[BF16_LOAD]], %{{.*}} : !cir.bf16
+// CIR: %[[BF16_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.bf16
+// CIR: %[[BF16_INC:.*]] = cir.fadd %[[BF16_LOAD]], %[[BF16_ONE]] : !cir.bf16
+// CIR: cir.store{{.*}} %[[BF16_INC]], %[[BF16_F]]
+// CIR: cir.store %[[BF16_INC]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.bf16>, !cir.bf16
+// CIR: cir.return %[[RV_LOAD]] : !cir.bf16
// LLVM: define{{.*}} bfloat @_Z11bf16UPreIncDF16b({{.*}})
-// LLVM: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
+// LLVM: %[[BF16_F:.*]] = alloca bfloat, align 2
+// LLVM: %[[RV:.*]] = alloca bfloat, align 2
+// LLVM: store bfloat %{{.*}}, ptr %[[BF16_F]], align 2
+// LLVM: %[[BF16_LOAD:.*]] = load bfloat, ptr %[[BF16_F]], align 2
// LLVM: %[[BF16_INC:.*]] = fadd bfloat %[[BF16_LOAD]], 1.000000e+00
+// LLVM: store bfloat %[[BF16_INC]], ptr %[[BF16_F]], align 2
+// LLVM: store bfloat %[[BF16_INC]], ptr %[[RV]], align 2
+// LLVM: %[[RV_LOAD:.*]] = load bfloat, ptr %[[RV]], align 2
+// LLVM: ret bfloat %[[RV_LOAD]]
// OGCG: define{{.*}} bfloat @_Z11bf16UPreIncDF16b({{.*}})
-// OGCG: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
+// OGCG: %[[BF16_F:.*]] = alloca bfloat, align 2
+// OGCG: store bfloat %{{.*}}, ptr %[[BF16_F]], align 2
+// OGCG: %[[BF16_LOAD:.*]] = load bfloat, ptr %[[BF16_F]], align 2
// OGCG: %[[BF16_INC:.*]] = fadd bfloat %[[BF16_LOAD]], 1.000000e+00
+// OGCG: store bfloat %[[BF16_INC]], ptr %[[BF16_F]], align 2
+// OGCG: ret bfloat %[[BF16_INC]]
__bf16 bf16UPreDec(__bf16 f) {
return --f;
@@ -1094,16 +1479,33 @@ __bf16 bf16UPreDec(__bf16 f) {
// CIR: cir.func{{.*}} @_Z11bf16UPreDecDF16b({{.*}}) -> (!cir.bf16{{.*}})
// CIR: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.bf16>
// CIR: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
-// CIR: %[[BF16_DEC:.*]] = cir.fadd %[[BF16_LOAD]], %{{.*}} : !cir.bf16
+// CIR: %[[BF16_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.bf16
+// CIR: %[[BF16_DEC:.*]] = cir.fadd %[[BF16_LOAD]], %[[BF16_NEGONE]] : !cir.bf16
+// CIR: cir.store{{.*}} %[[BF16_DEC]], %[[BF16_F]]
+// CIR: cir.store %[[BF16_DEC]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.bf16>, !cir.bf16
+// CIR: cir.return %[[RV_LOAD]] : !cir.bf16
// LLVM: define{{.*}} bfloat @_Z11bf16UPreDecDF16b({{.*}})
-// LLVM: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
+// LLVM: %[[BF16_F:.*]] = alloca bfloat, align 2
+// LLVM: %[[RV:.*]] = alloca bfloat, align 2
+// LLVM: store bfloat %{{.*}}, ptr %[[BF16_F]], align 2
+// LLVM: %[[BF16_LOAD:.*]] = load bfloat, ptr %[[BF16_F]], align 2
// LLVM: %[[BF16_DEC:.*]] = fadd bfloat %[[BF16_LOAD]], -1.000000e+00
+// LLVM: store bfloat %[[BF16_DEC]], ptr %[[BF16_F]], align 2
+// LLVM: store bfloat %[[BF16_DEC]], ptr %[[RV]], align 2
+// LLVM: %[[RV_LOAD:.*]] = load bfloat, ptr %[[RV]], align 2
+// LLVM: ret bfloat %[[RV_LOAD]]
// OGCG: define{{.*}} bfloat @_Z11bf16UPreDecDF16b({{.*}})
-// OGCG: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
+// OGCG: %[[BF16_F:.*]] = alloca bfloat, align 2
+// OGCG: store bfloat %{{.*}}, ptr %[[BF16_F]], align 2
+// OGCG: %[[BF16_LOAD:.*]] = load bfloat, ptr %[[BF16_F]], align 2
// OGCG: %[[BF16_DEC:.*]] = fadd bfloat %[[BF16_LOAD]], -1.000000e+00
+// OGCG: store bfloat %[[BF16_DEC]], ptr %[[BF16_F]], align 2
+// OGCG: ret bfloat %[[BF16_DEC]]
__bf16 bf16UPostInc(__bf16 f) {
return f++;
@@ -1111,16 +1513,33 @@ __bf16 bf16UPostInc(__bf16 f) {
// CIR: cir.func{{.*}} @_Z12bf16UPostIncDF16b({{.*}}) -> (!cir.bf16{{.*}})
// CIR: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.bf16>
// CIR: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
-// CIR: %[[BF16_INC:.*]] = cir.fadd %[[BF16_LOAD]], %{{.*}} : !cir.bf16
+// CIR: %[[BF16_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.bf16
+// CIR: %[[BF16_INC:.*]] = cir.fadd %[[BF16_LOAD]], %[[BF16_ONE]] : !cir.bf16
+// CIR: cir.store{{.*}} %[[BF16_INC]], %[[BF16_F]]
+// CIR: cir.store %[[BF16_LOAD]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.bf16>, !cir.bf16
+// CIR: cir.return %[[RV_LOAD]] : !cir.bf16
// LLVM: define{{.*}} bfloat @_Z12bf16UPostIncDF16b({{.*}})
-// LLVM: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
+// LLVM: %[[BF16_F:.*]] = alloca bfloat, align 2
+// LLVM: %[[RV:.*]] = alloca bfloat, align 2
+// LLVM: store bfloat %{{.*}}, ptr %[[BF16_F]], align 2
+// LLVM: %[[BF16_LOAD:.*]] = load bfloat, ptr %[[BF16_F]], align 2
// LLVM: %[[BF16_INC:.*]] = fadd bfloat %[[BF16_LOAD]], 1.000000e+00
+// LLVM: store bfloat %[[BF16_INC]], ptr %[[BF16_F]], align 2
+// LLVM: store bfloat %[[BF16_LOAD]], ptr %[[RV]], align 2
+// LLVM: %[[RV_LOAD:.*]] = load bfloat, ptr %[[RV]], align 2
+// LLVM: ret bfloat %[[RV_LOAD]]
// OGCG: define{{.*}} bfloat @_Z12bf16UPostIncDF16b({{.*}})
-// OGCG: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
+// OGCG: %[[BF16_F:.*]] = alloca bfloat, align 2
+// OGCG: store bfloat %{{.*}}, ptr %[[BF16_F]], align 2
+// OGCG: %[[BF16_LOAD:.*]] = load bfloat, ptr %[[BF16_F]], align 2
// OGCG: %[[BF16_INC:.*]] = fadd bfloat %[[BF16_LOAD]], 1.000000e+00
+// OGCG: store bfloat %[[BF16_INC]], ptr %[[BF16_F]], align 2
+// OGCG: ret bfloat %[[BF16_LOAD]]
__bf16 bf16UPostDec(__bf16 f) {
return f--;
@@ -1128,16 +1547,33 @@ __bf16 bf16UPostDec(__bf16 f) {
// CIR: cir.func{{.*}} @_Z12bf16UPostDecDF16b({{.*}}) -> (!cir.bf16{{.*}})
// CIR: %[[BF16_F:.*]] = cir.alloca "f" {{.*}} init : !cir.ptr<!cir.bf16>
+// CIR: %[[RV:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.bf16>
// CIR: %[[BF16_LOAD:.*]] = cir.load{{.*}} %[[BF16_F]]
-// CIR: %[[BF16_DEC:.*]] = cir.fadd %[[BF16_LOAD]], %{{.*}} : !cir.bf16
+// CIR: %[[BF16_NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.bf16
+// CIR: %[[BF16_DEC:.*]] = cir.fadd %[[BF16_LOAD]], %[[BF16_NEGONE]] : !cir.bf16
+// CIR: cir.store{{.*}} %[[BF16_DEC]], %[[BF16_F]]
+// CIR: cir.store %[[BF16_LOAD]], %[[RV]]
+// CIR: %[[RV_LOAD:.*]] = cir.load %[[RV]] : !cir.ptr<!cir.bf16>, !cir.bf16
+// CIR: cir.return %[[RV_LOAD]] : !cir.bf16
// LLVM: define{{.*}} bfloat @_Z12bf16UPostDecDF16b({{.*}})
-// LLVM: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
+// LLVM: %[[BF16_F:.*]] = alloca bfloat, align 2
+// LLVM: %[[RV:.*]] = alloca bfloat, align 2
+// LLVM: store bfloat %{{.*}}, ptr %[[BF16_F]], align 2
+// LLVM: %[[BF16_LOAD:.*]] = load bfloat, ptr %[[BF16_F]], align 2
// LLVM: %[[BF16_DEC:.*]] = fadd bfloat %[[BF16_LOAD]], -1.000000e+00
+// LLVM: store bfloat %[[BF16_DEC]], ptr %[[BF16_F]], align 2
+// LLVM: store bfloat %[[BF16_LOAD]], ptr %[[RV]], align 2
+// LLVM: %[[RV_LOAD:.*]] = load bfloat, ptr %[[RV]], align 2
+// LLVM: ret bfloat %[[RV_LOAD]]
// OGCG: define{{.*}} bfloat @_Z12bf16UPostDecDF16b({{.*}})
-// OGCG: %[[BF16_LOAD:.*]] = load bfloat, ptr %{{.*}}, align 2
+// OGCG: %[[BF16_F:.*]] = alloca bfloat, align 2
+// OGCG: store bfloat %{{.*}}, ptr %[[BF16_F]], align 2
+// OGCG: %[[BF16_LOAD:.*]] = load bfloat, ptr %[[BF16_F]], align 2
// OGCG: %[[BF16_DEC:.*]] = fadd bfloat %[[BF16_LOAD]], -1.000000e+00
+// OGCG: store bfloat %[[BF16_DEC]], ptr %[[BF16_F]], align 2
+// OGCG: ret bfloat %[[BF16_LOAD]]
void test_logical_not() {
int a = 5;
@@ -1304,138 +1740,638 @@ typedef short vsh8 __attribute__((vector_size(16)));
typedef float vf4 __attribute__((vector_size(16)));
typedef double vd2 __attribute__((vector_size(16)));
-void vecIntIncDec(vi4 a) {
- ++a;
- --a;
- a++;
- a--;
+vi4 vecIntPreInc(vi4 a) {
+ return ++a;
}
-// CIR-LABEL: @_Z12vecIntIncDecDv4_i
-// CIR: cir.inc %{{.+}} : !cir.vector<4 x !s32i>
-// CIR: cir.dec %{{.+}} : !cir.vector<4 x !s32i>
-// CIR: cir.inc %{{.+}} : !cir.vector<4 x !s32i>
-// CIR: cir.dec %{{.+}} : !cir.vector<4 x !s32i>
-
-// LLVM-LABEL: @_Z12vecIntIncDecDv4_i
-// LLVM: add <4 x i32> %{{.+}}, splat (i32 1)
-// LLVM: sub <4 x i32> %{{.+}}, splat (i32 1)
-// LLVM: add <4 x i32> %{{.+}}, splat (i32 1)
-// LLVM: sub <4 x i32> %{{.+}}, splat (i32 1)
-
-// OGCG-LABEL: @_Z12vecIntIncDecDv4_i
-// OGCG: add <4 x i32> %{{.+}}, splat (i32 1)
-// OGCG: add <4 x i32> %{{.+}}, splat (i32 -1)
-// OGCG: add <4 x i32> %{{.+}}, splat (i32 1)
-// OGCG: add <4 x i32> %{{.+}}, splat (i32 -1)
-
-void vecUIntIncDec(uvi4 b) {
- ++b;
- --b;
- b++;
- b--;
-}
-// CIR-LABEL: @_Z13vecUIntIncDecDv4_j
-// CIR: cir.inc %{{.+}} : !cir.vector<4 x !u32i>
-// CIR: cir.dec %{{.+}} : !cir.vector<4 x !u32i>
-// CIR: cir.inc %{{.+}} : !cir.vector<4 x !u32i>
-// CIR: cir.dec %{{.+}} : !cir.vector<4 x !u32i>
-
-// LLVM-LABEL: @_Z13vecUIntIncDecDv4_j
-// LLVM: add <4 x i32> %{{.+}}, splat (i32 1)
-// LLVM: sub <4 x i32> %{{.+}}, splat (i32 1)
-// LLVM: add <4 x i32> %{{.+}}, splat (i32 1)
-// LLVM: sub <4 x i32> %{{.+}}, splat (i32 1)
-
-// OGCG-LABEL: @_Z13vecUIntIncDecDv4_j
-// OGCG: add <4 x i32> %{{.+}}, splat (i32 1)
-// OGCG: add <4 x i32> %{{.+}}, splat (i32 -1)
-// OGCG: add <4 x i32> %{{.+}}, splat (i32 1)
-// OGCG: add <4 x i32> %{{.+}}, splat (i32 -1)
-
-void vecShortIncDec(vsh8 c) {
- ++c;
- --c;
- c++;
- c--;
+// CIR-LABEL: @_Z12vecIntPreIncDv4_i
+// CIR: %[[A:.+]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.vector<4 x !s32i>>
+// CIR: %[[RV:.+]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<4 x !s32i>>
+// CIR: %[[INPUT:.+]] = cir.load{{.*}} %[[A]]
+// CIR: %[[INCREMENTED:.+]] = cir.inc %[[INPUT]] : !cir.vector<4 x !s32i>
+// CIR: cir.store{{.*}} %[[INCREMENTED]], %[[A]]
+// CIR: cir.store %[[INCREMENTED]], %[[RV]]
+// CIR: %[[RV_LOAD:.+]] = cir.load %[[RV]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i>
+// CIR: cir.return %[[RV_LOAD]] : !cir.vector<4 x !s32i>
+
+// LLVM-LABEL: @_Z12vecIntPreIncDv4_i
+// LLVM: %[[A:.+]] = alloca <4 x i32>, align 16
+// LLVM: %[[RVPTR:.+]] = alloca <4 x i32>, align 16
+// LLVM: store <4 x i32> %{{.+}}, ptr %[[A]], align 16
+// LLVM: %[[INPUT:.+]] = load <4 x i32>, ptr %[[A]], align 16
+// LLVM: %[[INCREMENTED:.+]] = add <4 x i32> %[[INPUT]], splat (i32 1)
+// LLVM: store <4 x i32> %[[INCREMENTED]], ptr %[[A]]
+// LLVM: store <4 x i32> %[[INCREMENTED]], ptr %[[RVPTR]]
+// LLVM: %[[RV:.+]] = load <4 x i32>, ptr %[[RVPTR]], align 16
+// LLVM: ret <4 x i32> %[[RV]]
+
+// OGCG-LABEL: @_Z12vecIntPreIncDv4_i
+// OGCG: %[[A:.+]] = alloca <4 x i32>, align 16
+// OGCG: store <4 x i32> %{{.+}}, ptr %[[A]], align 16
+// OGCG: %[[INPUT:.+]] = load <4 x i32>, ptr %[[A]], align 16
+// OGCG: %[[INCREMENTED:.+]] = add <4 x i32> %[[INPUT]], splat (i32 1)
+// OGCG: ret <4 x i32> %[[INCREMENTED]]
+
+vi4 vecIntPreDec(vi4 a) {
+ return --a;
}
-// CIR-LABEL: @_Z14vecShortIncDecDv8_s
-// CIR: cir.inc %{{.+}} : !cir.vector<8 x !s16i>
-// CIR: cir.dec %{{.+}} : !cir.vector<8 x !s16i>
-// CIR: cir.inc %{{.+}} : !cir.vector<8 x !s16i>
-// CIR: cir.dec %{{.+}} : !cir.vector<8 x !s16i>
-
-// LLVM-LABEL: @_Z14vecShortIncDecDv8_s
-// LLVM: add <8 x i16> %{{.+}}, splat (i16 1)
-// LLVM: sub <8 x i16> %{{.+}}, splat (i16 1)
-// LLVM: add <8 x i16> %{{.+}}, splat (i16 1)
-// LLVM: sub <8 x i16> %{{.+}}, splat (i16 1)
-
-// OGCG-LABEL: @_Z14vecShortIncDecDv8_s
-// OGCG: add <8 x i16> %{{.+}}, splat (i16 1)
-// OGCG: add <8 x i16> %{{.+}}, splat (i16 -1)
-// OGCG: add <8 x i16> %{{.+}}, splat (i16 1)
-// OGCG: add <8 x i16> %{{.+}}, splat (i16 -1)
-
-void vecFloatIncDec(vf4 a) {
- ++a;
- --a;
- a++;
- a--;
+// CIR-LABEL: @_Z12vecIntPreDecDv4_i
+// CIR: %[[A:.+]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.vector<4 x !s32i>>
+// CIR: %[[RV:.+]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<4 x !s32i>>
+// CIR: %[[INPUT:.+]] = cir.load{{.*}} %[[A]]
+// CIR: %[[DECREMENTED:.+]] = cir.dec %[[INPUT]] : !cir.vector<4 x !s32i>
+// CIR: cir.store{{.*}} %[[DECREMENTED]], %[[A]]
+// CIR: cir.store %[[DECREMENTED]], %[[RV]]
+// CIR: %[[RV_LOAD:.+]] = cir.load %[[RV]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i>
+// CIR: cir.return %[[RV_LOAD]] : !cir.vector<4 x !s32i>
+
+// LLVM-LABEL: @_Z12vecIntPreDecDv4_i
+// LLVM: %[[A:.+]] = alloca <4 x i32>, align 16
+// LLVM: %[[RVPTR:.+]] = alloca <4 x i32>, align 16
+// LLVM: store <4 x i32> %{{.+}}, ptr %[[A]], align 16
+// LLVM: %[[INPUT:.+]] = load <4 x i32>, ptr %[[A]], align 16
+// LLVM: %[[DECREMENTED:.+]] = sub <4 x i32> %[[INPUT]], splat (i32 1)
+// LLVM: store <4 x i32> %[[DECREMENTED]], ptr %[[A]]
+// LLVM: store <4 x i32> %[[DECREMENTED]], ptr %[[RVPTR]]
+// LLVM: %[[RV:.+]] = load <4 x i32>, ptr %[[RVPTR]], align 16
+// LLVM: ret <4 x i32> %[[RV]]
+
+// OGCG-LABEL: @_Z12vecIntPreDecDv4_i
+// OGCG: %[[A:.+]] = alloca <4 x i32>, align 16
+// OGCG: store <4 x i32> %{{.+}}, ptr %[[A]], align 16
+// OGCG: %[[INPUT:.+]] = load <4 x i32>, ptr %[[A]], align 16
+// OGCG: %[[DECREMENTED:.+]] = add <4 x i32> %[[INPUT]], splat (i32 -1)
+// OGCG: ret <4 x i32> %[[DECREMENTED]]
+
+vi4 vecIntPostInc(vi4 a) {
+ return a++;
}
-// CIR-LABEL: @_Z14vecFloatIncDecDv4_f
+// CIR-LABEL: @_Z13vecIntPostIncDv4_i
+// CIR: %[[A:.+]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.vector<4 x !s32i>>
+// CIR: %[[RV:.+]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<4 x !s32i>>
+// CIR: %[[INPUT:.+]] = cir.load{{.*}} %[[A]]
+// CIR: %[[INCREMENTED:.+]] = cir.inc %[[INPUT]] : !cir.vector<4 x !s32i>
+// CIR: cir.store{{.*}} %[[INCREMENTED]], %[[A]]
+// CIR: cir.store %[[INPUT]], %[[RV]]
+// CIR: %[[RV_LOAD:.+]] = cir.load %[[RV]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i>
+// CIR: cir.return %[[RV_LOAD]] : !cir.vector<4 x !s32i>
+
+// LLVM-LABEL: @_Z13vecIntPostIncDv4_i
+// LLVM: %[[A:.+]] = alloca <4 x i32>, align 16
+// LLVM: %[[RVPTR:.+]] = alloca <4 x i32>, align 16
+// LLVM: store <4 x i32> %{{.+}}, ptr %[[A]], align 16
+// LLVM: %[[INPUT:.+]] = load <4 x i32>, ptr %[[A]], align 16
+// LLVM: %[[INCREMENTED:.+]] = add <4 x i32> %[[INPUT]], splat (i32 1)
+// LLVM: store <4 x i32> %[[INCREMENTED]], ptr %[[A]]
+// LLVM: store <4 x i32> %[[INPUT]], ptr %[[RVPTR]]
+// LLVM: %[[RV:.+]] = load <4 x i32>, ptr %[[RVPTR]], align 16
+// LLVM: ret <4 x i32> %[[RV]]
+
+// OGCG-LABEL: @_Z13vecIntPostIncDv4_i
+// OGCG: %[[A:.+]] = alloca <4 x i32>, align 16
+// OGCG: store <4 x i32> %{{.+}}, ptr %[[A]], align 16
+// OGCG: %[[INPUT:.+]] = load <4 x i32>, ptr %[[A]], align 16
+// OGCG: add <4 x i32> %[[INPUT]], splat (i32 1)
+// OGCG: ret <4 x i32> %[[INPUT]]
+
+vi4 vecIntPostDec(vi4 a) {
+ return a--;
+}
+// CIR-LABEL: @_Z13vecIntPostDecDv4_i
+// CIR: %[[A:.+]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.vector<4 x !s32i>>
+// CIR: %[[RV:.+]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<4 x !s32i>>
+// CIR: %[[INPUT:.+]] = cir.load{{.*}} %[[A]]
+// CIR: %[[DECREMENTED:.+]] = cir.dec %[[INPUT]] : !cir.vector<4 x !s32i>
+// CIR: cir.store{{.*}} %[[DECREMENTED]], %[[A]]
+// CIR: cir.store %[[INPUT]], %[[RV]]
+// CIR: %[[RV_LOAD:.+]] = cir.load %[[RV]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i>
+// CIR: cir.return %[[RV_LOAD]] : !cir.vector<4 x !s32i>
+
+// LLVM-LABEL: @_Z13vecIntPostDecDv4_i
+// LLVM: %[[A:.+]] = alloca <4 x i32>, align 16
+// LLVM: %[[RVPTR:.+]] = alloca <4 x i32>, align 16
+// LLVM: store <4 x i32> %{{.+}}, ptr %[[A]], align 16
+// LLVM: %[[INPUT:.+]] = load <4 x i32>, ptr %[[A]], align 16
+// LLVM: %[[DECREMENTED:.+]] = sub <4 x i32> %[[INPUT]], splat (i32 1)
+// LLVM: store <4 x i32> %[[DECREMENTED]], ptr %[[A]]
+// LLVM: store <4 x i32> %[[INPUT]], ptr %[[RVPTR]]
+// LLVM: %[[RV:.+]] = load <4 x i32>, ptr %[[RVPTR]], align 16
+// LLVM: ret <4 x i32> %[[RV]]
+
+// OGCG-LABEL: @_Z13vecIntPostDecDv4_i
+// OGCG: %[[A:.+]] = alloca <4 x i32>, align 16
+// OGCG: store <4 x i32> %{{.+}}, ptr %[[A]], align 16
+// OGCG: %[[INPUT:.+]] = load <4 x i32>, ptr %[[A]], align 16
+// OGCG: add <4 x i32> %[[INPUT]], splat (i32 -1)
+// OGCG: ret <4 x i32> %[[INPUT]]
+
+uvi4 vecUIntPreInc(uvi4 b) {
+ return ++b;
+}
+// CIR-LABEL: @_Z13vecUIntPreIncDv4_j
+// CIR: %[[B:.+]] = cir.alloca "b" {{.*}} init : !cir.ptr<!cir.vector<4 x !u32i>>
+// CIR: %[[RV:.+]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<4 x !u32i>>
+// CIR: %[[INPUT:.+]] = cir.load{{.*}} %[[B]]
+// CIR: %[[INCREMENTED:.+]] = cir.inc %[[INPUT]] : !cir.vector<4 x !u32i>
+// CIR: cir.store{{.*}} %[[INCREMENTED]], %[[B]]
+// CIR: cir.store %[[INCREMENTED]], %[[RV]]
+// CIR: %[[RV_LOAD:.+]] = cir.load %[[RV]] : !cir.ptr<!cir.vector<4 x !u32i>>, !cir.vector<4 x !u32i>
+// CIR: cir.return %[[RV_LOAD]] : !cir.vector<4 x !u32i>
+
+// LLVM-LABEL: @_Z13vecUIntPreIncDv4_j
+// LLVM: %[[B:.+]] = alloca <4 x i32>, align 16
+// LLVM: %[[RVPTR:.+]] = alloca <4 x i32>, align 16
+// LLVM: store <4 x i32> %{{.+}}, ptr %[[B]], align 16
+// LLVM: %[[INPUT:.+]] = load <4 x i32>, ptr %[[B]], align 16
+// LLVM: %[[INCREMENTED:.+]] = add <4 x i32> %[[INPUT]], splat (i32 1)
+// LLVM: store <4 x i32> %[[INCREMENTED]], ptr %[[B]]
+// LLVM: store <4 x i32> %[[INCREMENTED]], ptr %[[RVPTR]]
+// LLVM: %[[RV:.+]] = load <4 x i32>, ptr %[[RVPTR]], align 16
+// LLVM: ret <4 x i32> %[[RV]]
+
+// OGCG-LABEL: @_Z13vecUIntPreIncDv4_j
+// OGCG: %[[B:.+]] = alloca <4 x i32>, align 16
+// OGCG: store <4 x i32> %{{.+}}, ptr %[[B]], align 16
+// OGCG: %[[INPUT:.+]] = load <4 x i32>, ptr %[[B]], align 16
+// OGCG: %[[INCREMENTED:.+]] = add <4 x i32> %[[INPUT]], splat (i32 1)
+// OGCG: ret <4 x i32> %[[INCREMENTED]]
+
+uvi4 vecUIntPreDec(uvi4 b) {
+ return --b;
+}
+// CIR-LABEL: @_Z13vecUIntPreDecDv4_j
+// CIR: %[[B:.+]] = cir.alloca "b" {{.*}} init : !cir.ptr<!cir.vector<4 x !u32i>>
+// CIR: %[[RV:.+]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<4 x !u32i>>
+// CIR: %[[INPUT:.+]] = cir.load{{.*}} %[[B]]
+// CIR: %[[DECREMENTED:.+]] = cir.dec %[[INPUT]] : !cir.vector<4 x !u32i>
+// CIR: cir.store{{.*}} %[[DECREMENTED]], %[[B]]
+// CIR: cir.store %[[DECREMENTED]], %[[RV]]
+// CIR: %[[RV_LOAD:.+]] = cir.load %[[RV]] : !cir.ptr<!cir.vector<4 x !u32i>>, !cir.vector<4 x !u32i>
+// CIR: cir.return %[[RV_LOAD]] : !cir.vector<4 x !u32i>
+
+// LLVM-LABEL: @_Z13vecUIntPreDecDv4_j
+// LLVM: %[[B:.+]] = alloca <4 x i32>, align 16
+// LLVM: %[[RVPTR:.+]] = alloca <4 x i32>, align 16
+// LLVM: store <4 x i32> %{{.+}}, ptr %[[B]], align 16
+// LLVM: %[[INPUT:.+]] = load <4 x i32>, ptr %[[B]], align 16
+// LLVM: %[[DECREMENTED:.+]] = sub <4 x i32> %[[INPUT]], splat (i32 1)
+// LLVM: store <4 x i32> %[[DECREMENTED]], ptr %[[B]]
+// LLVM: store <4 x i32> %[[DECREMENTED]], ptr %[[RVPTR]]
+// LLVM: %[[RV:.+]] = load <4 x i32>, ptr %[[RVPTR]], align 16
+// LLVM: ret <4 x i32> %[[RV]]
+
+// OGCG-LABEL: @_Z13vecUIntPreDecDv4_j
+// OGCG: %[[B:.+]] = alloca <4 x i32>, align 16
+// OGCG: store <4 x i32> %{{.+}}, ptr %[[B]], align 16
+// OGCG: %[[INPUT:.+]] = load <4 x i32>, ptr %[[B]], align 16
+// OGCG: %[[DECREMENTED:.+]] = add <4 x i32> %[[INPUT]], splat (i32 -1)
+// OGCG: ret <4 x i32> %[[DECREMENTED]]
+
+uvi4 vecUIntPostInc(uvi4 b) {
+ return b++;
+}
+// CIR-LABEL: @_Z14vecUIntPostIncDv4_j
+// CIR: %[[B:.+]] = cir.alloca "b" {{.*}} init : !cir.ptr<!cir.vector<4 x !u32i>>
+// CIR: %[[RV:.+]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<4 x !u32i>>
+// CIR: %[[INPUT:.+]] = cir.load{{.*}} %[[B]]
+// CIR: %[[INCREMENTED:.+]] = cir.inc %[[INPUT]] : !cir.vector<4 x !u32i>
+// CIR: cir.store{{.*}} %[[INCREMENTED]], %[[B]]
+// CIR: cir.store %[[INPUT]], %[[RV]]
+// CIR: %[[RV_LOAD:.+]] = cir.load %[[RV]] : !cir.ptr<!cir.vector<4 x !u32i>>, !cir.vector<4 x !u32i>
+// CIR: cir.return %[[RV_LOAD]] : !cir.vector<4 x !u32i>
+
+// LLVM-LABEL: @_Z14vecUIntPostIncDv4_j
+// LLVM: %[[B:.+]] = alloca <4 x i32>, align 16
+// LLVM: %[[RVPTR:.+]] = alloca <4 x i32>, align 16
+// LLVM: store <4 x i32> %{{.+}}, ptr %[[B]], align 16
+// LLVM: %[[INPUT:.+]] = load <4 x i32>, ptr %[[B]], align 16
+// LLVM: %[[INCREMENTED:.+]] = add <4 x i32> %[[INPUT]], splat (i32 1)
+// LLVM: store <4 x i32> %[[INCREMENTED]], ptr %[[B]]
+// LLVM: store <4 x i32> %[[INPUT]], ptr %[[RVPTR]]
+// LLVM: %[[RV:.+]] = load <4 x i32>, ptr %[[RVPTR]], align 16
+// LLVM: ret <4 x i32> %[[RV]]
+
+// OGCG-LABEL: @_Z14vecUIntPostIncDv4_j
+// OGCG: %[[B:.+]] = alloca <4 x i32>, align 16
+// OGCG: store <4 x i32> %{{.+}}, ptr %[[B]], align 16
+// OGCG: %[[INPUT:.+]] = load <4 x i32>, ptr %[[B]], align 16
+// OGCG: add <4 x i32> %[[INPUT]], splat (i32 1)
+// OGCG: ret <4 x i32> %[[INPUT]]
+
+uvi4 vecUIntPostDec(uvi4 b) {
+ return b--;
+}
+// CIR-LABEL: @_Z14vecUIntPostDecDv4_j
+// CIR: %[[B:.+]] = cir.alloca "b" {{.*}} init : !cir.ptr<!cir.vector<4 x !u32i>>
+// CIR: %[[RV:.+]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<4 x !u32i>>
+// CIR: %[[INPUT:.+]] = cir.load{{.*}} %[[B]]
+// CIR: %[[DECREMENTED:.+]] = cir.dec %[[INPUT]] : !cir.vector<4 x !u32i>
+// CIR: cir.store{{.*}} %[[DECREMENTED]], %[[B]]
+// CIR: cir.store %[[INPUT]], %[[RV]]
+// CIR: %[[RV_LOAD:.+]] = cir.load %[[RV]] : !cir.ptr<!cir.vector<4 x !u32i>>, !cir.vector<4 x !u32i>
+// CIR: cir.return %[[RV_LOAD]] : !cir.vector<4 x !u32i>
+
+// LLVM-LABEL: @_Z14vecUIntPostDecDv4_j
+// LLVM: %[[B:.+]] = alloca <4 x i32>, align 16
+// LLVM: %[[RVPTR:.+]] = alloca <4 x i32>, align 16
+// LLVM: store <4 x i32> %{{.+}}, ptr %[[B]], align 16
+// LLVM: %[[INPUT:.+]] = load <4 x i32>, ptr %[[B]], align 16
+// LLVM: %[[DECREMENTED:.+]] = sub <4 x i32> %[[INPUT]], splat (i32 1)
+// LLVM: store <4 x i32> %[[DECREMENTED]], ptr %[[B]]
+// LLVM: store <4 x i32> %[[INPUT]], ptr %[[RVPTR]]
+// LLVM: %[[RV:.+]] = load <4 x i32>, ptr %[[RVPTR]], align 16
+// LLVM: ret <4 x i32> %[[RV]]
+
+// OGCG-LABEL: @_Z14vecUIntPostDecDv4_j
+// OGCG: %[[B:.+]] = alloca <4 x i32>, align 16
+// OGCG: store <4 x i32> %{{.+}}, ptr %[[B]], align 16
+// OGCG: %[[INPUT:.+]] = load <4 x i32>, ptr %[[B]], align 16
+// OGCG: add <4 x i32> %[[INPUT]], splat (i32 -1)
+// OGCG: ret <4 x i32> %[[INPUT]]
+
+vsh8 vecShortPreInc(vsh8 c) {
+ return ++c;
+}
+// CIR-LABEL: @_Z14vecShortPreIncDv8_s
+// CIR: %[[C:.+]] = cir.alloca "c" {{.*}} init : !cir.ptr<!cir.vector<8 x !s16i>>
+// CIR: %[[RV:.+]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<8 x !s16i>>
+// CIR: %[[INPUT:.+]] = cir.load{{.*}} %[[C]]
+// CIR: %[[INCREMENTED:.+]] = cir.inc %[[INPUT]] : !cir.vector<8 x !s16i>
+// CIR: cir.store{{.*}} %[[INCREMENTED]], %[[C]]
+// CIR: cir.store %[[INCREMENTED]], %[[RV]]
+// CIR: %[[RV_LOAD:.+]] = cir.load %[[RV]] : !cir.ptr<!cir.vector<8 x !s16i>>, !cir.vector<8 x !s16i>
+// CIR: cir.return %[[RV_LOAD]] : !cir.vector<8 x !s16i>
+
+// LLVM-LABEL: @_Z14vecShortPreIncDv8_s
+// LLVM: %[[C:.+]] = alloca <8 x i16>, align 16
+// LLVM: %[[RVPTR:.+]] = alloca <8 x i16>, align 16
+// LLVM: store <8 x i16> %{{.+}}, ptr %[[C]], align 16
+// LLVM: %[[INPUT:.+]] = load <8 x i16>, ptr %[[C]], align 16
+// LLVM: %[[INCREMENTED:.+]] = add <8 x i16> %[[INPUT]], splat (i16 1)
+// LLVM: store <8 x i16> %[[INCREMENTED]], ptr %[[C]]
+// LLVM: store <8 x i16> %[[INCREMENTED]], ptr %[[RVPTR]]
+// LLVM: %[[RV:.+]] = load <8 x i16>, ptr %[[RVPTR]], align 16
+// LLVM: ret <8 x i16> %[[RV]]
+
+// OGCG-LABEL: @_Z14vecShortPreIncDv8_s
+// OGCG: %[[C:.+]] = alloca <8 x i16>, align 16
+// OGCG: store <8 x i16> %{{.+}}, ptr %[[C]], align 16
+// OGCG: %[[INPUT:.+]] = load <8 x i16>, ptr %[[C]], align 16
+// OGCG: %[[INCREMENTED:.+]] = add <8 x i16> %[[INPUT]], splat (i16 1)
+// OGCG: ret <8 x i16> %[[INCREMENTED]]
+
+vsh8 vecShortPreDec(vsh8 c) {
+ return --c;
+}
+// CIR-LABEL: @_Z14vecShortPreDecDv8_s
+// CIR: %[[C:.+]] = cir.alloca "c" {{.*}} init : !cir.ptr<!cir.vector<8 x !s16i>>
+// CIR: %[[RV:.+]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<8 x !s16i>>
+// CIR: %[[INPUT:.+]] = cir.load{{.*}} %[[C]]
+// CIR: %[[DECREMENTED:.+]] = cir.dec %[[INPUT]] : !cir.vector<8 x !s16i>
+// CIR: cir.store{{.*}} %[[DECREMENTED]], %[[C]]
+// CIR: cir.store %[[DECREMENTED]], %[[RV]]
+// CIR: %[[RV_LOAD:.+]] = cir.load %[[RV]] : !cir.ptr<!cir.vector<8 x !s16i>>, !cir.vector<8 x !s16i>
+// CIR: cir.return %[[RV_LOAD]] : !cir.vector<8 x !s16i>
+
+// LLVM-LABEL: @_Z14vecShortPreDecDv8_s
+// LLVM: %[[C:.+]] = alloca <8 x i16>, align 16
+// LLVM: %[[RVPTR:.+]] = alloca <8 x i16>, align 16
+// LLVM: store <8 x i16> %{{.+}}, ptr %[[C]], align 16
+// LLVM: %[[INPUT:.+]] = load <8 x i16>, ptr %[[C]], align 16
+// LLVM: %[[DECREMENTED:.+]] = sub <8 x i16> %[[INPUT]], splat (i16 1)
+// LLVM: store <8 x i16> %[[DECREMENTED]], ptr %[[C]]
+// LLVM: store <8 x i16> %[[DECREMENTED]], ptr %[[RVPTR]]
+// LLVM: %[[RV:.+]] = load <8 x i16>, ptr %[[RVPTR]], align 16
+// LLVM: ret <8 x i16> %[[RV]]
+
+// OGCG-LABEL: @_Z14vecShortPreDecDv8_s
+// OGCG: %[[C:.+]] = alloca <8 x i16>, align 16
+// OGCG: store <8 x i16> %{{.+}}, ptr %[[C]], align 16
+// OGCG: %[[INPUT:.+]] = load <8 x i16>, ptr %[[C]], align 16
+// OGCG: %[[DECREMENTED:.+]] = add <8 x i16> %[[INPUT]], splat (i16 -1)
+// OGCG: ret <8 x i16> %[[DECREMENTED]]
+
+vsh8 vecShortPostInc(vsh8 c) {
+ return c++;
+}
+// CIR-LABEL: @_Z15vecShortPostIncDv8_s
+// CIR: %[[C:.+]] = cir.alloca "c" {{.*}} init : !cir.ptr<!cir.vector<8 x !s16i>>
+// CIR: %[[RV:.+]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<8 x !s16i>>
+// CIR: %[[INPUT:.+]] = cir.load{{.*}} %[[C]]
+// CIR: %[[INCREMENTED:.+]] = cir.inc %[[INPUT]] : !cir.vector<8 x !s16i>
+// CIR: cir.store{{.*}} %[[INCREMENTED]], %[[C]]
+// CIR: cir.store %[[INPUT]], %[[RV]]
+// CIR: %[[RV_LOAD:.+]] = cir.load %[[RV]] : !cir.ptr<!cir.vector<8 x !s16i>>, !cir.vector<8 x !s16i>
+// CIR: cir.return %[[RV_LOAD]] : !cir.vector<8 x !s16i>
+
+// LLVM-LABEL: @_Z15vecShortPostIncDv8_s
+// LLVM: %[[C:.+]] = alloca <8 x i16>, align 16
+// LLVM: %[[RVPTR:.+]] = alloca <8 x i16>, align 16
+// LLVM: store <8 x i16> %{{.+}}, ptr %[[C]], align 16
+// LLVM: %[[INPUT:.+]] = load <8 x i16>, ptr %[[C]], align 16
+// LLVM: %[[INCREMENTED:.+]] = add <8 x i16> %[[INPUT]], splat (i16 1)
+// LLVM: store <8 x i16> %[[INCREMENTED]], ptr %[[C]]
+// LLVM: store <8 x i16> %[[INPUT]], ptr %[[RVPTR]]
+// LLVM: %[[RV:.+]] = load <8 x i16>, ptr %[[RVPTR]], align 16
+// LLVM: ret <8 x i16> %[[RV]]
+
+// OGCG-LABEL: @_Z15vecShortPostIncDv8_s
+// OGCG: %[[C:.+]] = alloca <8 x i16>, align 16
+// OGCG: store <8 x i16> %{{.+}}, ptr %[[C]], align 16
+// OGCG: %[[INPUT:.+]] = load <8 x i16>, ptr %[[C]], align 16
+// OGCG: add <8 x i16> %[[INPUT]], splat (i16 1)
+// OGCG: ret <8 x i16> %[[INPUT]]
+
+vsh8 vecShortPostDec(vsh8 c) {
+ return c--;
+}
+// CIR-LABEL: @_Z15vecShortPostDecDv8_s
+// CIR: %[[C:.+]] = cir.alloca "c" {{.*}} init : !cir.ptr<!cir.vector<8 x !s16i>>
+// CIR: %[[RV:.+]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<8 x !s16i>>
+// CIR: %[[INPUT:.+]] = cir.load{{.*}} %[[C]]
+// CIR: %[[DECREMENTED:.+]] = cir.dec %[[INPUT]] : !cir.vector<8 x !s16i>
+// CIR: cir.store{{.*}} %[[DECREMENTED]], %[[C]]
+// CIR: cir.store %[[INPUT]], %[[RV]]
+// CIR: %[[RV_LOAD:.+]] = cir.load %[[RV]] : !cir.ptr<!cir.vector<8 x !s16i>>, !cir.vector<8 x !s16i>
+// CIR: cir.return %[[RV_LOAD]] : !cir.vector<8 x !s16i>
+
+// LLVM-LABEL: @_Z15vecShortPostDecDv8_s
+// LLVM: %[[C:.+]] = alloca <8 x i16>, align 16
+// LLVM: %[[RVPTR:.+]] = alloca <8 x i16>, align 16
+// LLVM: store <8 x i16> %{{.+}}, ptr %[[C]], align 16
+// LLVM: %[[INPUT:.+]] = load <8 x i16>, ptr %[[C]], align 16
+// LLVM: %[[DECREMENTED:.+]] = sub <8 x i16> %[[INPUT]], splat (i16 1)
+// LLVM: store <8 x i16> %[[DECREMENTED]], ptr %[[C]]
+// LLVM: store <8 x i16> %[[INPUT]], ptr %[[RVPTR]]
+// LLVM: %[[RV:.+]] = load <8 x i16>, ptr %[[RVPTR]], align 16
+// LLVM: ret <8 x i16> %[[RV]]
+
+// OGCG-LABEL: @_Z15vecShortPostDecDv8_s
+// OGCG: %[[C:.+]] = alloca <8 x i16>, align 16
+// OGCG: store <8 x i16> %{{.+}}, ptr %[[C]], align 16
+// OGCG: %[[INPUT:.+]] = load <8 x i16>, ptr %[[C]], align 16
+// OGCG: add <8 x i16> %[[INPUT]], splat (i16 -1)
+// OGCG: ret <8 x i16> %[[INPUT]]
+
+vf4 vecFloatPreInc(vf4 a) {
+ return ++a;
+}
+// CIR-LABEL: @_Z14vecFloatPreIncDv4_f
+// CIR: %[[A:.+]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.vector<4 x !cir.float>>
+// CIR: %[[RVPTR:.+]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<4 x !cir.float>>
+// CIR: %[[INPUT:.+]] = cir.load{{.*}} %[[A]]
// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.float, !cir.vector<4 x !cir.float>
-// CIR: cir.fadd %{{.+}}, %[[ONEVEC]] : !cir.vector<4 x !cir.float>
+// CIR: %[[INCREMENTED:.+]] = cir.fadd %[[INPUT]], %[[ONEVEC]] : !cir.vector<4 x !cir.float>
+// CIR: cir.store{{.*}} %[[INCREMENTED]], %[[A]]
+// CIR: cir.store %[[INCREMENTED]], %[[RVPTR]]
+// CIR: %[[RV:.+]] = cir.load %[[RVPTR]] : !cir.ptr<!cir.vector<4 x !cir.float>>, !cir.vector<4 x !cir.float>
+// CIR: cir.return %[[RV]] : !cir.vector<4 x !cir.float>
+
+// LLVM-LABEL: @_Z14vecFloatPreIncDv4_f
+// LLVM: %[[A:.+]] = alloca <4 x float>, align 16
+// LLVM: %[[RVPTR:.+]] = alloca <4 x float>, align 16
+// LLVM: store <4 x float> %{{.+}}, ptr %[[A]], align 16
+// LLVM: %[[INPUT:.+]] = load <4 x float>, ptr %[[A]], align 16
+// LLVM: %[[INCREMENTED:.+]] = fadd <4 x float> %[[INPUT]], splat (float 1.000000e+00)
+// LLVM: store <4 x float> %[[INCREMENTED]], ptr %[[A]]
+// LLVM: store <4 x float> %[[INCREMENTED]], ptr %[[RVPTR]]
+// LLVM: %[[RV:.+]] = load <4 x float>, ptr %[[RVPTR]], align 16
+// LLVM: ret <4 x float> %[[RV]]
+
+// OGCG-LABEL: @_Z14vecFloatPreIncDv4_f
+// OGCG: %[[A:.+]] = alloca <4 x float>, align 16
+// OGCG: store <4 x float> %{{.+}}, ptr %[[A]], align 16
+// OGCG: %[[INPUT:.+]] = load <4 x float>, ptr %[[A]], align 16
+// OGCG: %[[INCREMENTED:.+]] = fadd <4 x float> %[[INPUT]], splat (float 1.000000e+00)
+// OGCG: ret <4 x float> %[[INCREMENTED]]
+
+vf4 vecFloatPreDec(vf4 a) {
+ return --a;
+}
+// CIR-LABEL: @_Z14vecFloatPreDecDv4_f
+// CIR: %[[A:.+]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.vector<4 x !cir.float>>
+// CIR: %[[RVPTR:.+]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<4 x !cir.float>>
+// CIR: %[[INPUT:.+]] = cir.load{{.*}} %[[A]]
// CIR: %[[NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.float
// CIR: %[[NEGONEVEC:.*]] = cir.vec.splat %[[NEGONE]] : !cir.float, !cir.vector<4 x !cir.float>
-// CIR: cir.fadd %{{.+}}, %[[NEGONEVEC]] : !cir.vector<4 x !cir.float>
+// CIR: %[[DECREMENTED:.+]] = cir.fadd %[[INPUT]], %[[NEGONEVEC]] : !cir.vector<4 x !cir.float>
+// CIR: cir.store{{.*}} %[[DECREMENTED]], %[[A]]
+// CIR: cir.store %[[DECREMENTED]], %[[RVPTR]]
+// CIR: %[[RV:.+]] = cir.load %[[RVPTR]] : !cir.ptr<!cir.vector<4 x !cir.float>>, !cir.vector<4 x !cir.float>
+// CIR: cir.return %[[RV]] : !cir.vector<4 x !cir.float>
+
+// LLVM-LABEL: @_Z14vecFloatPreDecDv4_f
+// LLVM: %[[A:.+]] = alloca <4 x float>, align 16
+// LLVM: %[[RVPTR:.+]] = alloca <4 x float>, align 16
+// LLVM: store <4 x float> %{{.+}}, ptr %[[A]], align 16
+// LLVM: %[[INPUT:.+]] = load <4 x float>, ptr %[[A]], align 16
+// LLVM: %[[DECREMENTED:.+]] = fadd <4 x float> %[[INPUT]], splat (float -1.000000e+00)
+// LLVM: store <4 x float> %[[DECREMENTED]], ptr %[[A]]
+// LLVM: store <4 x float> %[[DECREMENTED]], ptr %[[RVPTR]]
+// LLVM: %[[RV:.+]] = load <4 x float>, ptr %[[RVPTR]], align 16
+// LLVM: ret <4 x float> %[[RV]]
+
+// OGCG-LABEL: @_Z14vecFloatPreDecDv4_f
+// OGCG: %[[A:.+]] = alloca <4 x float>, align 16
+// OGCG: store <4 x float> %{{.+}}, ptr %[[A]], align 16
+// OGCG: %[[INPUT:.+]] = load <4 x float>, ptr %[[A]], align 16
+// OGCG: %[[DECREMENTED:.+]] = fadd <4 x float> %[[INPUT]], splat (float -1.000000e+00)
+// OGCG: ret <4 x float> %[[DECREMENTED]]
+
+vf4 vecFloatPostInc(vf4 a) {
+ return a++;
+}
+// CIR-LABEL: @_Z15vecFloatPostIncDv4_f
+// CIR: %[[A:.+]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.vector<4 x !cir.float>>
+// CIR: %[[RVPTR:.+]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<4 x !cir.float>>
+// CIR: %[[INPUT:.+]] = cir.load{{.*}} %[[A]]
// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.float, !cir.vector<4 x !cir.float>
-// CIR: cir.fadd %{{.+}}, %[[ONEVEC]] : !cir.vector<4 x !cir.float>
+// CIR: %[[INCREMENTED:.+]] = cir.fadd %[[INPUT]], %[[ONEVEC]] : !cir.vector<4 x !cir.float>
+// CIR: cir.store{{.*}} %[[INCREMENTED]], %[[A]]
+// CIR: cir.store %[[INPUT]], %[[RVPTR]]
+// CIR: %[[RV:.+]] = cir.load %[[RVPTR]] : !cir.ptr<!cir.vector<4 x !cir.float>>, !cir.vector<4 x !cir.float>
+// CIR: cir.return %[[RV]] : !cir.vector<4 x !cir.float>
+
+// LLVM-LABEL: @_Z15vecFloatPostIncDv4_f
+// LLVM: %[[A:.+]] = alloca <4 x float>, align 16
+// LLVM: %[[RVPTR:.+]] = alloca <4 x float>, align 16
+// LLVM: store <4 x float> %{{.+}}, ptr %[[A]], align 16
+// LLVM: %[[INPUT:.+]] = load <4 x float>, ptr %[[A]], align 16
+// LLVM: %[[INCREMENTED:.+]] = fadd <4 x float> %[[INPUT]], splat (float 1.000000e+00)
+// LLVM: store <4 x float> %[[INCREMENTED]], ptr %[[A]]
+// LLVM: store <4 x float> %[[INPUT]], ptr %[[RVPTR]]
+// LLVM: %[[RV:.+]] = load <4 x float>, ptr %[[RVPTR]], align 16
+// LLVM: ret <4 x float> %[[RV]]
+
+// OGCG-LABEL: @_Z15vecFloatPostIncDv4_f
+// OGCG: %[[A:.+]] = alloca <4 x float>, align 16
+// OGCG: store <4 x float> %{{.+}}, ptr %[[A]], align 16
+// OGCG: %[[INPUT:.+]] = load <4 x float>, ptr %[[A]], align 16
+// OGCG: fadd <4 x float> %[[INPUT]], splat (float 1.000000e+00)
+// OGCG: ret <4 x float> %[[INPUT]]
+
+vf4 vecFloatPostDec(vf4 a) {
+ return a--;
+}
+// CIR-LABEL: @_Z15vecFloatPostDecDv4_f
+// CIR: %[[A:.+]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.vector<4 x !cir.float>>
+// CIR: %[[RVPTR:.+]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<4 x !cir.float>>
+// CIR: %[[INPUT:.+]] = cir.load{{.*}} %[[A]]
// CIR: %[[NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.float
// CIR: %[[NEGONEVEC:.*]] = cir.vec.splat %[[NEGONE]] : !cir.float, !cir.vector<4 x !cir.float>
-// CIR: cir.fadd %{{.+}}, %[[NEGONEVEC]] : !cir.vector<4 x !cir.float>
-
-// LLVM-LABEL: @_Z14vecFloatIncDecDv4_f
-// LLVM: fadd <4 x float> %{{.+}}, splat (float 1.000000e+00)
-// LLVM: fadd <4 x float> %{{.+}}, splat (float -1.000000e+00)
-// LLVM: fadd <4 x float> %{{.+}}, splat (float 1.000000e+00)
-// LLVM: fadd <4 x float> %{{.+}}, splat (float -1.000000e+00)
-
-// OGCG-LABEL: @_Z14vecFloatIncDecDv4_f
-// OGCG: fadd <4 x float> %{{.+}}, splat (float 1.000000e+00)
-// OGCG: fadd <4 x float> %{{.+}}, splat (float -1.000000e+00)
-// OGCG: fadd <4 x float> %{{.+}}, splat (float 1.000000e+00)
-// OGCG: fadd <4 x float> %{{.+}}, splat (float -1.000000e+00)
-
-void vecDoubleIncDec(vd2 b) {
- ++b;
- --b;
- b++;
- b--;
-}
-// CIR-LABEL: @_Z15vecDoubleIncDecDv2_d
+// CIR: %[[DECREMENTED:.+]] = cir.fadd %[[INPUT]], %[[NEGONEVEC]] : !cir.vector<4 x !cir.float>
+// CIR: cir.store{{.*}} %[[DECREMENTED]], %[[A]]
+// CIR: cir.store %[[INPUT]], %[[RVPTR]]
+// CIR: %[[RV:.+]] = cir.load %[[RVPTR]] : !cir.ptr<!cir.vector<4 x !cir.float>>, !cir.vector<4 x !cir.float>
+// CIR: cir.return %[[RV]] : !cir.vector<4 x !cir.float>
+
+// LLVM-LABEL: @_Z15vecFloatPostDecDv4_f
+// LLVM: %[[A:.+]] = alloca <4 x float>, align 16
+// LLVM: %[[RVPTR:.+]] = alloca <4 x float>, align 16
+// LLVM: store <4 x float> %{{.+}}, ptr %[[A]], align 16
+// LLVM: %[[INPUT:.+]] = load <4 x float>, ptr %[[A]], align 16
+// LLVM: %[[DECREMENTED:.+]] = fadd <4 x float> %[[INPUT]], splat (float -1.000000e+00)
+// LLVM: store <4 x float> %[[DECREMENTED]], ptr %[[A]]
+// LLVM: store <4 x float> %[[INPUT]], ptr %[[RVPTR]]
+// LLVM: %[[RV:.+]] = load <4 x float>, ptr %[[RVPTR]], align 16
+// LLVM: ret <4 x float> %[[RV]]
+
+// OGCG-LABEL: @_Z15vecFloatPostDecDv4_f
+// OGCG: %[[A:.+]] = alloca <4 x float>, align 16
+// OGCG: store <4 x float> %{{.+}}, ptr %[[A]], align 16
+// OGCG: %[[INPUT:.+]] = load <4 x float>, ptr %[[A]], align 16
+// OGCG: fadd <4 x float> %[[INPUT]], splat (float -1.000000e+00)
+// OGCG: ret <4 x float> %[[INPUT]]
+
+vd2 vecDoublePreInc(vd2 b) {
+ return ++b;
+}
+// CIR-LABEL: @_Z15vecDoublePreIncDv2_d
+// CIR: %[[B:.+]] = cir.alloca "b" {{.*}} init : !cir.ptr<!cir.vector<2 x !cir.double>>
+// CIR: %[[RVPTR:.+]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<2 x !cir.double>>
+// CIR: %[[INPUT:.+]] = cir.load{{.*}} %[[B]]
// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.double, !cir.vector<2 x !cir.double>
-// CIR: cir.fadd %{{.+}}, %[[ONEVEC]] : !cir.vector<2 x !cir.double>
+// CIR: %[[INCREMENTED:.+]] = cir.fadd %[[INPUT]], %[[ONEVEC]] : !cir.vector<2 x !cir.double>
+// CIR: cir.store{{.*}} %[[INCREMENTED]], %[[B]]
+// CIR: cir.store %[[INCREMENTED]], %[[RVPTR]]
+// CIR: %[[RV:.+]] = cir.load %[[RVPTR]] : !cir.ptr<!cir.vector<2 x !cir.double>>, !cir.vector<2 x !cir.double>
+// CIR: cir.return %[[RV]] : !cir.vector<2 x !cir.double>
+
+// LLVM-LABEL: @_Z15vecDoublePreIncDv2_d
+// LLVM: %[[B:.+]] = alloca <2 x double>, align 16
+// LLVM: %[[RVPTR:.+]] = alloca <2 x double>, align 16
+// LLVM: store <2 x double> %{{.+}}, ptr %[[B]], align 16
+// LLVM: %[[INPUT:.+]] = load <2 x double>, ptr %[[B]], align 16
+// LLVM: %[[INCREMENTED:.+]] = fadd <2 x double> %[[INPUT]], splat (double 1.000000e+00)
+// LLVM: store <2 x double> %[[INCREMENTED]], ptr %[[B]]
+// LLVM: store <2 x double> %[[INCREMENTED]], ptr %[[RVPTR]]
+// LLVM: %[[RV:.+]] = load <2 x double>, ptr %[[RVPTR]], align 16
+// LLVM: ret <2 x double> %[[RV]]
+
+// OGCG-LABEL: @_Z15vecDoublePreIncDv2_d
+// OGCG: %[[B:.+]] = alloca <2 x double>, align 16
+// OGCG: store <2 x double> %{{.+}}, ptr %[[B]], align 16
+// OGCG: %[[INPUT:.+]] = load <2 x double>, ptr %[[B]], align 16
+// OGCG: %[[INCREMENTED:.+]] = fadd <2 x double> %[[INPUT]], splat (double 1.000000e+00)
+// OGCG: ret <2 x double> %[[INCREMENTED]]
+
+vd2 vecDoublePreDec(vd2 b) {
+ return --b;
+}
+// CIR-LABEL: @_Z15vecDoublePreDecDv2_d
+// CIR: %[[B:.+]] = cir.alloca "b" {{.*}} init : !cir.ptr<!cir.vector<2 x !cir.double>>
+// CIR: %[[RVPTR:.+]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<2 x !cir.double>>
+// CIR: %[[INPUT:.+]] = cir.load{{.*}} %[[B]]
// CIR: %[[NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.double
// CIR: %[[NEGONEVEC:.*]] = cir.vec.splat %[[NEGONE]] : !cir.double, !cir.vector<2 x !cir.double>
-// CIR: cir.fadd %{{.+}}, %[[NEGONEVEC]] : !cir.vector<2 x !cir.double>
+// CIR: %[[DECREMENTED:.+]] = cir.fadd %[[INPUT]], %[[NEGONEVEC]] : !cir.vector<2 x !cir.double>
+// CIR: cir.store{{.*}} %[[DECREMENTED]], %[[B]]
+// CIR: cir.store %[[DECREMENTED]], %[[RVPTR]]
+// CIR: %[[RV:.+]] = cir.load %[[RVPTR]] : !cir.ptr<!cir.vector<2 x !cir.double>>, !cir.vector<2 x !cir.double>
+// CIR: cir.return %[[RV]] : !cir.vector<2 x !cir.double>
+
+// LLVM-LABEL: @_Z15vecDoublePreDecDv2_d
+// LLVM: %[[B:.+]] = alloca <2 x double>, align 16
+// LLVM: %[[RVPTR:.+]] = alloca <2 x double>, align 16
+// LLVM: store <2 x double> %{{.+}}, ptr %[[B]], align 16
+// LLVM: %[[INPUT:.+]] = load <2 x double>, ptr %[[B]], align 16
+// LLVM: %[[DECREMENTED:.+]] = fadd <2 x double> %[[INPUT]], splat (double -1.000000e+00)
+// LLVM: store <2 x double> %[[DECREMENTED]], ptr %[[B]]
+// LLVM: store <2 x double> %[[DECREMENTED]], ptr %[[RVPTR]]
+// LLVM: %[[RV:.+]] = load <2 x double>, ptr %[[RVPTR]], align 16
+// LLVM: ret <2 x double> %[[RV]]
+
+// OGCG-LABEL: @_Z15vecDoublePreDecDv2_d
+// OGCG: %[[B:.+]] = alloca <2 x double>, align 16
+// OGCG: store <2 x double> %{{.+}}, ptr %[[B]], align 16
+// OGCG: %[[INPUT:.+]] = load <2 x double>, ptr %[[B]], align 16
+// OGCG: %[[DECREMENTED:.+]] = fadd <2 x double> %[[INPUT]], splat (double -1.000000e+00)
+// OGCG: ret <2 x double> %[[DECREMENTED]]
+
+vd2 vecDoublePostInc(vd2 b) {
+ return b++;
+}
+// CIR-LABEL: @_Z16vecDoublePostIncDv2_d
+// CIR: %[[B:.+]] = cir.alloca "b" {{.*}} init : !cir.ptr<!cir.vector<2 x !cir.double>>
+// CIR: %[[RVPTR:.+]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<2 x !cir.double>>
+// CIR: %[[INPUT:.+]] = cir.load{{.*}} %[[B]]
// CIR: %[[ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double
// CIR: %[[ONEVEC:.*]] = cir.vec.splat %[[ONE]] : !cir.double, !cir.vector<2 x !cir.double>
-// CIR: cir.fadd %{{.+}}, %[[ONEVEC]] : !cir.vector<2 x !cir.double>
+// CIR: %[[INCREMENTED:.+]] = cir.fadd %[[INPUT]], %[[ONEVEC]] : !cir.vector<2 x !cir.double>
+// CIR: cir.store{{.*}} %[[INCREMENTED]], %[[B]]
+// CIR: cir.store %[[INPUT]], %[[RVPTR]]
+// CIR: %[[RV:.+]] = cir.load %[[RVPTR]] : !cir.ptr<!cir.vector<2 x !cir.double>>, !cir.vector<2 x !cir.double>
+// CIR: cir.return %[[RV]] : !cir.vector<2 x !cir.double>
+
+// LLVM-LABEL: @_Z16vecDoublePostIncDv2_d
+// LLVM: %[[B:.+]] = alloca <2 x double>, align 16
+// LLVM: %[[RVPTR:.+]] = alloca <2 x double>, align 16
+// LLVM: store <2 x double> %{{.+}}, ptr %[[B]], align 16
+// LLVM: %[[INPUT:.+]] = load <2 x double>, ptr %[[B]], align 16
+// LLVM: %[[INCREMENTED:.+]] = fadd <2 x double> %[[INPUT]], splat (double 1.000000e+00)
+// LLVM: store <2 x double> %[[INCREMENTED]], ptr %[[B]]
+// LLVM: store <2 x double> %[[INPUT]], ptr %[[RVPTR]]
+// LLVM: %[[RV:.+]] = load <2 x double>, ptr %[[RVPTR]], align 16
+// LLVM: ret <2 x double> %[[RV]]
+
+// OGCG-LABEL: @_Z16vecDoublePostIncDv2_d
+// OGCG: %[[B:.+]] = alloca <2 x double>, align 16
+// OGCG: store <2 x double> %{{.+}}, ptr %[[B]], align 16
+// OGCG: %[[INPUT:.+]] = load <2 x double>, ptr %[[B]], align 16
+// OGCG: fadd <2 x double> %[[INPUT]], splat (double 1.000000e+00)
+// OGCG: ret <2 x double> %[[INPUT]]
+
+vd2 vecDoublePostDec(vd2 b) {
+ return b--;
+}
+// CIR-LABEL: @_Z16vecDoublePostDecDv2_d
+// CIR: %[[B:.+]] = cir.alloca "b" {{.*}} init : !cir.ptr<!cir.vector<2 x !cir.double>>
+// CIR: %[[RVPTR:.+]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<2 x !cir.double>>
+// CIR: %[[INPUT:.+]] = cir.load{{.*}} %[[B]]
// CIR: %[[NEGONE:.*]] = cir.const #cir.fp<-1.000000e+00> : !cir.double
// CIR: %[[NEGONEVEC:.*]] = cir.vec.splat %[[NEGONE]] : !cir.double, !cir.vector<2 x !cir.double>
-// CIR: cir.fadd %{{.+}}, %[[NEGONEVEC]] : !cir.vector<2 x !cir.double>
-
-// LLVM-LABEL: @_Z15vecDoubleIncDecDv2_d
-// LLVM: fadd <2 x double> %{{.+}}, splat (double 1.000000e+00)
-// LLVM: fadd <2 x double> %{{.+}}, splat (double -1.000000e+00)
-// LLVM: fadd <2 x double> %{{.+}}, splat (double 1.000000e+00)
-// LLVM: fadd <2 x double> %{{.+}}, splat (double -1.000000e+00)
-
-// OGCG-LABEL: @_Z15vecDoubleIncDecDv2_d
-// OGCG: fadd <2 x double> %{{.+}}, splat (double 1.000000e+00)
-// OGCG: fadd <2 x double> %{{.+}}, splat (double -1.000000e+00)
-// OGCG: fadd <2 x double> %{{.+}}, splat (double 1.000000e+00)
-// OGCG: fadd <2 x double> %{{.+}}, splat (double -1.000000e+00)
+// CIR: %[[DECREMENTED:.+]] = cir.fadd %[[INPUT]], %[[NEGONEVEC]] : !cir.vector<2 x !cir.double>
+// CIR: cir.store{{.*}} %[[DECREMENTED]], %[[B]]
+// CIR: cir.store %[[INPUT]], %[[RVPTR]]
+// CIR: %[[RV:.+]] = cir.load %[[RVPTR]] : !cir.ptr<!cir.vector<2 x !cir.double>>, !cir.vector<2 x !cir.double>
+// CIR: cir.return %[[RV]] : !cir.vector<2 x !cir.double>
+
+// LLVM-LABEL: @_Z16vecDoublePostDecDv2_d
+// LLVM: %[[B:.+]] = alloca <2 x double>, align 16
+// LLVM: %[[RVPTR:.+]] = alloca <2 x double>, align 16
+// LLVM: store <2 x double> %{{.+}}, ptr %[[B]], align 16
+// LLVM: %[[INPUT:.+]] = load <2 x double>, ptr %[[B]], align 16
+// LLVM: %[[DECREMENTED:.+]] = fadd <2 x double> %[[INPUT]], splat (double -1.000000e+00)
+// LLVM: store <2 x double> %[[DECREMENTED]], ptr %[[B]]
+// LLVM: store <2 x double> %[[INPUT]], ptr %[[RVPTR]]
+// LLVM: %[[RV:.+]] = load <2 x double>, ptr %[[RVPTR]], align 16
+// LLVM: ret <2 x double> %[[RV]]
+
+// OGCG-LABEL: @_Z16vecDoublePostDecDv2_d
+// OGCG: %[[B:.+]] = alloca <2 x double>, align 16
+// OGCG: store <2 x double> %{{.+}}, ptr %[[B]], align 16
+// OGCG: %[[INPUT:.+]] = load <2 x double>, ptr %[[B]], align 16
+// OGCG: fadd <2 x double> %[[INPUT]], splat (double -1.000000e+00)
+// OGCG: ret <2 x double> %[[INPUT]]
>From 3b9d1532a132221c5bc83f7dc0acea3c0bc8cf5c Mon Sep 17 00:00:00 2001
From: Haocong Lu <haocong.lu at witintech.com>
Date: Fri, 18 Sep 2026 08:18:37 +0800
Subject: [PATCH 5/6] [CIR] rebase
---
clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
index 5308475f490f6d8..93b3827f6030438 100644
--- a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
@@ -685,7 +685,7 @@ class ScalarExprEmitter : public StmtVisitor<ScalarExprEmitter, mlir::Value> {
lv.isVolatileQualified(), /*fetch_first=*/true);
mlir::Value oldVal = rmw->getResult(0);
// Prefix returns new value; postfix returns old value.
- return isPre ? emitIncOrDec(e, oldVal) : oldVal;
+ return isPre ? emitIntIncOrDec(e, oldVal) : oldVal;
}
// Special case for atomic increment/decrement on floats.
>From 34f99cad793885ce7d1ba4f3224fa6f809c68fe6 Mon Sep 17 00:00:00 2001
From: Haocong Lu <haocong.lu at witintech.com>
Date: Wed, 23 Sep 2026 13:59:53 +0800
Subject: [PATCH 6/6] [CIR] address comment and rebase
---
clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp | 28 +++++++++++-----------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
index 93b3827f6030438..6cae1200e6e2348 100644
--- a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
@@ -915,23 +915,23 @@ class ScalarExprEmitter : public StmtVisitor<ScalarExprEmitter, mlir::Value> {
mlir::Value amtValue = builder.getConstFP(loc, fpScalarType, amount);
amtValue = cir::VecSplatOp::create(builder, loc, vecType, amtValue);
return builder.createFAdd(loc, input, amtValue);
- } else {
- QualType type = e->getSubExpr()->getType();
- // Another special case: half FP increment should be done via float.
- if (type->isHalfType() && !cgf.getContext().getLangOpts().NativeHalfType)
- input = builder.createFloatingCast(input, builder.getSingleTy());
+ }
- auto fpInterface = mlir::cast<cir::FPTypeInterface>(input.getType());
- auto amount = llvm::APFloat::getOne(fpInterface.getFloatSemantics(),
- /*Negative=*/e->isDecrementOp());
- mlir::Value amtValue = builder.getConstFP(loc, input.getType(), amount);
- mlir::Value output = builder.createFAdd(loc, input, amtValue);
+ QualType type = e->getSubExpr()->getType();
+ // Another special case: half FP increment should be done via float.
+ if (type->isHalfType() && !cgf.getContext().getLangOpts().NativeHalfType)
+ input = builder.createFloatingCast(input, builder.getSingleTy());
- if (type->isHalfType() && !cgf.getContext().getLangOpts().NativeHalfType)
- output = builder.createFloatingCast(output, builder.getFp16Ty());
+ auto fpInterface = mlir::cast<cir::FPTypeInterface>(input.getType());
+ auto amount = llvm::APFloat::getOne(fpInterface.getFloatSemantics(),
+ /*Negative=*/e->isDecrementOp());
+ mlir::Value amtValue = builder.getConstFP(loc, input.getType(), amount);
+ mlir::Value output = builder.createFAdd(loc, input, amtValue);
- return output;
- }
+ if (type->isHalfType() && !cgf.getContext().getLangOpts().NativeHalfType)
+ output = builder.createFloatingCast(output, builder.getFp16Ty());
+
+ return output;
}
mlir::Value VisitUnaryNot(const UnaryOperator *e) {
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