[clang] [clang][CIR] Add tests for SVE ANDV intrinsics (PR #227657)
Chibuoyim Ogbonna via cfe-commits
cfe-commits at lists.llvm.org
Wed Sep 30 04:01:16 PDT 2026
https://github.com/bruteforceboy created https://github.com/llvm/llvm-project/pull/227657
This adds CIR tests for `svandv` (plain SVE) intrinsics.
Moves and adapts `sve-intrinsics/acle_sve_andv.c` to `sve/andv.c`.
>From 19ea98fe6e6aca868de6122fccd8f3c10baa5185 Mon Sep 17 00:00:00 2001
From: bruteforceboy <chibuoyim.faith.ogbonna at huawei.com>
Date: Tue, 29 Sep 2026 09:51:07 +0100
Subject: [PATCH] [clang][CIR] Add tests for SVE ANDV intrinsics
---
.../AArch64/sve-intrinsics/acle_sve_andv.c | 155 -----------------
clang/test/CodeGen/AArch64/sve/andv.c | 157 ++++++++++++++++++
2 files changed, 157 insertions(+), 155 deletions(-)
delete mode 100644 clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_andv.c
create mode 100644 clang/test/CodeGen/AArch64/sve/andv.c
diff --git a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_andv.c b/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_andv.c
deleted file mode 100644
index 73e7267c24ee8..0000000000000
--- a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_andv.c
+++ /dev/null
@@ -1,155 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
-// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
-// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
-
-#include <arm_sve.h>
-
-#if defined __ARM_FEATURE_SME
-#define MODE_ATTR __arm_streaming
-#else
-#define MODE_ATTR
-#endif
-
-#ifdef SVE_OVERLOADED_FORMS
-// A simple used,unused... macro, long enough to represent any SVE builtin.
-#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
-#else
-#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
-#endif
-
-// CHECK-LABEL: @test_svandv_s8(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
-// CHECK-NEXT: ret i8 [[TMP0]]
-//
-// CPP-CHECK-LABEL: @_Z14test_svandv_s8u10__SVBool_tu10__SVInt8_t(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
-// CPP-CHECK-NEXT: ret i8 [[TMP0]]
-//
-int8_t test_svandv_s8(svbool_t pg, svint8_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svandv,_s8,,)(pg, op);
-}
-
-// CHECK-LABEL: @test_svandv_s16(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
-// CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]])
-// CHECK-NEXT: ret i16 [[TMP1]]
-//
-// CPP-CHECK-LABEL: @_Z15test_svandv_s16u10__SVBool_tu11__SVInt16_t(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
-// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]])
-// CPP-CHECK-NEXT: ret i16 [[TMP1]]
-//
-int16_t test_svandv_s16(svbool_t pg, svint16_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svandv,_s16,,)(pg, op);
-}
-
-// CHECK-LABEL: @test_svandv_s32(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
-// CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]])
-// CHECK-NEXT: ret i32 [[TMP1]]
-//
-// CPP-CHECK-LABEL: @_Z15test_svandv_s32u10__SVBool_tu11__SVInt32_t(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
-// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]])
-// CPP-CHECK-NEXT: ret i32 [[TMP1]]
-//
-int32_t test_svandv_s32(svbool_t pg, svint32_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svandv,_s32,,)(pg, op);
-}
-
-// CHECK-LABEL: @test_svandv_s64(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
-// CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]])
-// CHECK-NEXT: ret i64 [[TMP1]]
-//
-// CPP-CHECK-LABEL: @_Z15test_svandv_s64u10__SVBool_tu11__SVInt64_t(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
-// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]])
-// CPP-CHECK-NEXT: ret i64 [[TMP1]]
-//
-int64_t test_svandv_s64(svbool_t pg, svint64_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svandv,_s64,,)(pg, op);
-}
-
-// CHECK-LABEL: @test_svandv_u8(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
-// CHECK-NEXT: ret i8 [[TMP0]]
-//
-// CPP-CHECK-LABEL: @_Z14test_svandv_u8u10__SVBool_tu11__SVUint8_t(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
-// CPP-CHECK-NEXT: ret i8 [[TMP0]]
-//
-uint8_t test_svandv_u8(svbool_t pg, svuint8_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svandv,_u8,,)(pg, op);
-}
-
-// CHECK-LABEL: @test_svandv_u16(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
-// CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]])
-// CHECK-NEXT: ret i16 [[TMP1]]
-//
-// CPP-CHECK-LABEL: @_Z15test_svandv_u16u10__SVBool_tu12__SVUint16_t(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
-// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]])
-// CPP-CHECK-NEXT: ret i16 [[TMP1]]
-//
-uint16_t test_svandv_u16(svbool_t pg, svuint16_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svandv,_u16,,)(pg, op);
-}
-
-// CHECK-LABEL: @test_svandv_u32(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
-// CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]])
-// CHECK-NEXT: ret i32 [[TMP1]]
-//
-// CPP-CHECK-LABEL: @_Z15test_svandv_u32u10__SVBool_tu12__SVUint32_t(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
-// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]])
-// CPP-CHECK-NEXT: ret i32 [[TMP1]]
-//
-uint32_t test_svandv_u32(svbool_t pg, svuint32_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svandv,_u32,,)(pg, op);
-}
-
-// CHECK-LABEL: @test_svandv_u64(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
-// CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]])
-// CHECK-NEXT: ret i64 [[TMP1]]
-//
-// CPP-CHECK-LABEL: @_Z15test_svandv_u64u10__SVBool_tu12__SVUint64_t(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
-// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]])
-// CPP-CHECK-NEXT: ret i64 [[TMP1]]
-//
-uint64_t test_svandv_u64(svbool_t pg, svuint64_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svandv,_u64,,)(pg, op);
-}
diff --git a/clang/test/CodeGen/AArch64/sve/andv.c b/clang/test/CodeGen/AArch64/sve/andv.c
new file mode 100644
index 0000000000000..fd4d623bd561f
--- /dev/null
+++ b/clang/test/CodeGen/AArch64/sve/andv.c
@@ -0,0 +1,157 @@
+// REQUIRES: aarch64-registered-target
+
+// DEFINE: %{optimize} = opt -passes=mem2reg,instcombine,tailcallelim -S
+
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -fclangir -emit-cir -disable-O0-optnone -o - %s | FileCheck %s --check-prefixes=C,CIR %}
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-cir -disable-O0-optnone -o - %s | FileCheck %s --check-prefixes=C,CIR %}
+
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -fclangir -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM %}
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM %}
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-llvm -disable-O0-optnone -o - -x c++ %s | %{optimize} | FileCheck %s --check-prefixes=CPP,LLVM %}
+
+// RUN: %clang_cc1_cg_arm64_sve -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM
+// RUN: %clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM
+// RUN: %clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -emit-llvm -disable-O0-optnone -o - -x c++ %s | %{optimize} | FileCheck %s --check-prefixes=CPP,LLVM
+
+//=============================================================================
+// NOTES
+//
+// Tests for SVE ANDV intrinsics
+//=============================================================================
+
+#include <arm_sve.h>
+
+#if defined __ARM_FEATURE_SME
+#define MODE_ATTR __arm_streaming
+#else
+#define MODE_ATTR
+#endif
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+// C-LABEL: @test_svandv_s8(
+// CPP-LABEL: @_Z14test_svandv_s8u10__SVBool_tu10__SVInt8_t(
+int8_t test_svandv_s8(svbool_t pg, svint8_t op) MODE_ATTR
+{
+// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.andv" %{{.*}}, %{{.*}} :
+// CIR-SAME: -> !s8i
+
+// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
+// LLVM: [[TMP0:%.*]] = tail call i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[OP]])
+// LLVM: ret i8 [[TMP0]]
+ return SVE_ACLE_FUNC(svandv,_s8,,)(pg, op);
+}
+
+// C-LABEL: @test_svandv_s16(
+// CPP-LABEL: @_Z15test_svandv_s16u10__SVBool_tu11__SVInt16_t(
+int16_t test_svandv_s16(svbool_t pg, svint16_t op) MODE_ATTR
+{
+// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} :
+// CIR-SAME: -> !cir.vector<[8] x !cir.int<u, 1>>
+// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.andv" %[[CONVERT_PG]], %{{.*}} :
+// CIR-SAME: -> !s16i
+
+// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 8 x i16> [[OP:%.*]])
+// LLVM: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
+// LLVM: [[TMP1:%.*]] = tail call i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP]])
+// LLVM: ret i16 [[TMP1]]
+ return SVE_ACLE_FUNC(svandv,_s16,,)(pg, op);
+}
+
+// C-LABEL: @test_svandv_s32(
+// CPP-LABEL: @_Z15test_svandv_s32u10__SVBool_tu11__SVInt32_t(
+int32_t test_svandv_s32(svbool_t pg, svint32_t op) MODE_ATTR
+{
+// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} :
+// CIR-SAME: -> !cir.vector<[4] x !cir.int<u, 1>>
+// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.andv" %[[CONVERT_PG]], %{{.*}} :
+// CIR-SAME: -> !s32i
+
+// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 4 x i32> [[OP:%.*]])
+// LLVM: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
+// LLVM: [[TMP1:%.*]] = tail call i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP]])
+// LLVM: ret i32 [[TMP1]]
+ return SVE_ACLE_FUNC(svandv,_s32,,)(pg, op);
+}
+
+// C-LABEL: @test_svandv_s64(
+// CPP-LABEL: @_Z15test_svandv_s64u10__SVBool_tu11__SVInt64_t(
+int64_t test_svandv_s64(svbool_t pg, svint64_t op) MODE_ATTR
+{
+// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} :
+// CIR-SAME: -> !cir.vector<[2] x !cir.int<u, 1>>
+// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.andv" %[[CONVERT_PG]], %{{.*}} :
+// CIR-SAME: -> !s64i
+
+// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 2 x i64> [[OP:%.*]])
+// LLVM: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
+// LLVM: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP]])
+// LLVM: ret i64 [[TMP1]]
+ return SVE_ACLE_FUNC(svandv,_s64,,)(pg, op);
+}
+
+// C-LABEL: @test_svandv_u8(
+// CPP-LABEL: @_Z14test_svandv_u8u10__SVBool_tu11__SVUint8_t(
+uint8_t test_svandv_u8(svbool_t pg, svuint8_t op) MODE_ATTR
+{
+// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.andv" %{{.*}}, %{{.*}} :
+// CIR-SAME: -> !u8i
+
+// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
+// LLVM: [[TMP0:%.*]] = tail call i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[OP]])
+// LLVM: ret i8 [[TMP0]]
+ return SVE_ACLE_FUNC(svandv,_u8,,)(pg, op);
+}
+
+// C-LABEL: @test_svandv_u16(
+// CPP-LABEL: @_Z15test_svandv_u16u10__SVBool_tu12__SVUint16_t(
+uint16_t test_svandv_u16(svbool_t pg, svuint16_t op) MODE_ATTR
+{
+// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} :
+// CIR-SAME: -> !cir.vector<[8] x !cir.int<u, 1>>
+// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.andv" %[[CONVERT_PG]], %{{.*}} :
+// CIR-SAME: -> !u16i
+
+// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 8 x i16> [[OP:%.*]])
+// LLVM: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
+// LLVM: [[TMP1:%.*]] = tail call i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP]])
+// LLVM: ret i16 [[TMP1]]
+ return SVE_ACLE_FUNC(svandv,_u16,,)(pg, op);
+}
+
+// C-LABEL: @test_svandv_u32(
+// CPP-LABEL: @_Z15test_svandv_u32u10__SVBool_tu12__SVUint32_t(
+uint32_t test_svandv_u32(svbool_t pg, svuint32_t op) MODE_ATTR
+{
+// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} :
+// CIR-SAME: -> !cir.vector<[4] x !cir.int<u, 1>>
+// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.andv" %[[CONVERT_PG]], %{{.*}} :
+// CIR-SAME: -> !u32i
+
+// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 4 x i32> [[OP:%.*]])
+// LLVM: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
+// LLVM: [[TMP1:%.*]] = tail call i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP]])
+// LLVM: ret i32 [[TMP1]]
+ return SVE_ACLE_FUNC(svandv,_u32,,)(pg, op);
+}
+
+// C-LABEL: @test_svandv_u64(
+// CPP-LABEL: @_Z15test_svandv_u64u10__SVBool_tu12__SVUint64_t(
+uint64_t test_svandv_u64(svbool_t pg, svuint64_t op) MODE_ATTR
+{
+// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} :
+// CIR-SAME: -> !cir.vector<[2] x !cir.int<u, 1>>
+// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.andv" %[[CONVERT_PG]], %{{.*}} :
+// CIR-SAME: -> !u64i
+
+// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 2 x i64> [[OP:%.*]])
+// LLVM: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
+// LLVM: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP]])
+// LLVM: ret i64 [[TMP1]]
+ return SVE_ACLE_FUNC(svandv,_u64,,)(pg, op);
+}
More information about the cfe-commits
mailing list