[clang] ef45ca7 - [RISCV] Add common check-prefix to rvp-intrinsics.c. NFC (#227044)
via cfe-commits
cfe-commits at lists.llvm.org
Mon Sep 28 22:11:00 PDT 2026
Author: Craig Topper
Date: 2026-09-29T05:10:48Z
New Revision: ef45ca75ce721745b997db165f18e4fdf9e93294
URL: https://github.com/llvm/llvm-project/commit/ef45ca75ce721745b997db165f18e4fdf9e93294
DIFF: https://github.com/llvm/llvm-project/commit/ef45ca75ce721745b997db165f18e4fdf9e93294.diff
LOG: [RISCV] Add common check-prefix to rvp-intrinsics.c. NFC (#227044)
A large number of test cases have the same IR for RV32 and RV64.
Added:
Modified:
clang/test/CodeGen/RISCV/rvp-intrinsics.c
Removed:
################################################################################
diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
index 59893ce3358c2..873400da8c6d1 100644
--- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c
+++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
@@ -1,10 +1,10 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-p \
// RUN: -disable-O0-optnone -emit-llvm -o - %s \
-// RUN: | opt -S -passes=sroa,instcombine | FileCheck %s --check-prefix=RV32
+// RUN: | opt -S -passes=sroa,instcombine | FileCheck %s --check-prefixes=CHECK,RV32
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-p \
// RUN: -disable-O0-optnone -emit-llvm -o - %s \
-// RUN: | opt -S -passes=sroa,instcombine | FileCheck %s --check-prefix=RV64
+// RUN: | opt -S -passes=sroa,instcombine | FileCheck %s --check-prefixes=CHECK,RV64
#include <riscv_packed_simd.h>
@@ -136,81 +136,49 @@ uint64_t test_abs_u64(int64_t a) {
/* Packed Splat (32-bit) */
-// RV32-LABEL: define dso_local i32 @test_pmv_s_u8x4(
-// RV32-SAME: i8 noundef zeroext [[X:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[X]], i64 0
-// RV32-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
-// RV32-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[VECINIT3_I]] to i32
-// RV32-NEXT: ret i32 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmv_s_u8x4(
-// RV64-SAME: i8 noundef zeroext [[X:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[X]], i64 0
-// RV64-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
-// RV64-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[VECINIT3_I]] to i32
-// RV64-NEXT: ret i32 [[TMP0]]
+// CHECK-LABEL: define dso_local i32 @test_pmv_s_u8x4(
+// CHECK-SAME: i8 noundef zeroext [[X:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[X]], i64 0
+// CHECK-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[VECINIT3_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP0]]
//
uint8x4_t test_pmv_s_u8x4(uint8_t x) {
return __riscv_pmv_s_u8x4(x);
}
-// RV32-LABEL: define dso_local i32 @test_pmv_s_i8x4(
-// RV32-SAME: i8 noundef signext [[X:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[X]], i64 0
-// RV32-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
-// RV32-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[VECINIT3_I]] to i32
-// RV32-NEXT: ret i32 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmv_s_i8x4(
-// RV64-SAME: i8 noundef signext [[X:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[X]], i64 0
-// RV64-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
-// RV64-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[VECINIT3_I]] to i32
-// RV64-NEXT: ret i32 [[TMP0]]
+// CHECK-LABEL: define dso_local i32 @test_pmv_s_i8x4(
+// CHECK-SAME: i8 noundef signext [[X:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[X]], i64 0
+// CHECK-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[VECINIT3_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP0]]
//
int8x4_t test_pmv_s_i8x4(int8_t x) {
return __riscv_pmv_s_i8x4(x);
}
-// RV32-LABEL: define dso_local i32 @test_pmv_s_u16x2(
-// RV32-SAME: i16 noundef zeroext [[X:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[X]], i64 0
-// RV32-NEXT: [[VECINIT1_I:%.*]] = shufflevector <2 x i16> [[VECINIT_I]], <2 x i16> poison, <2 x i32> zeroinitializer
-// RV32-NEXT: [[TMP0:%.*]] = bitcast <2 x i16> [[VECINIT1_I]] to i32
-// RV32-NEXT: ret i32 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmv_s_u16x2(
-// RV64-SAME: i16 noundef zeroext [[X:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[X]], i64 0
-// RV64-NEXT: [[VECINIT1_I:%.*]] = shufflevector <2 x i16> [[VECINIT_I]], <2 x i16> poison, <2 x i32> zeroinitializer
-// RV64-NEXT: [[TMP0:%.*]] = bitcast <2 x i16> [[VECINIT1_I]] to i32
-// RV64-NEXT: ret i32 [[TMP0]]
+// CHECK-LABEL: define dso_local i32 @test_pmv_s_u16x2(
+// CHECK-SAME: i16 noundef zeroext [[X:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[X]], i64 0
+// CHECK-NEXT: [[VECINIT1_I:%.*]] = shufflevector <2 x i16> [[VECINIT_I]], <2 x i16> poison, <2 x i32> zeroinitializer
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i16> [[VECINIT1_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP0]]
//
uint16x2_t test_pmv_s_u16x2(uint16_t x) {
return __riscv_pmv_s_u16x2(x);
}
-// RV32-LABEL: define dso_local i32 @test_pmv_s_i16x2(
-// RV32-SAME: i16 noundef signext [[X:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[X]], i64 0
-// RV32-NEXT: [[VECINIT1_I:%.*]] = shufflevector <2 x i16> [[VECINIT_I]], <2 x i16> poison, <2 x i32> zeroinitializer
-// RV32-NEXT: [[TMP0:%.*]] = bitcast <2 x i16> [[VECINIT1_I]] to i32
-// RV32-NEXT: ret i32 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmv_s_i16x2(
-// RV64-SAME: i16 noundef signext [[X:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[X]], i64 0
-// RV64-NEXT: [[VECINIT1_I:%.*]] = shufflevector <2 x i16> [[VECINIT_I]], <2 x i16> poison, <2 x i32> zeroinitializer
-// RV64-NEXT: [[TMP0:%.*]] = bitcast <2 x i16> [[VECINIT1_I]] to i32
-// RV64-NEXT: ret i32 [[TMP0]]
+// CHECK-LABEL: define dso_local i32 @test_pmv_s_i16x2(
+// CHECK-SAME: i16 noundef signext [[X:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[X]], i64 0
+// CHECK-NEXT: [[VECINIT1_I:%.*]] = shufflevector <2 x i16> [[VECINIT_I]], <2 x i16> poison, <2 x i32> zeroinitializer
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i16> [[VECINIT1_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP0]]
//
int16x2_t test_pmv_s_i16x2(int16_t x) {
return __riscv_pmv_s_i16x2(x);
@@ -218,81 +186,49 @@ int16x2_t test_pmv_s_i16x2(int16_t x) {
/* Packed Splat (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_pmv_s_u8x8(
-// RV32-SAME: i8 noundef zeroext [[X:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[X]], i64 0
-// RV32-NEXT: [[VECINIT7_I:%.*]] = shufflevector <8 x i8> [[VECINIT_I]], <8 x i8> poison, <8 x i32> zeroinitializer
-// RV32-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[VECINIT7_I]] to i64
-// RV32-NEXT: ret i64 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmv_s_u8x8(
-// RV64-SAME: i8 noundef zeroext [[X:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[X]], i64 0
-// RV64-NEXT: [[VECINIT7_I:%.*]] = shufflevector <8 x i8> [[VECINIT_I]], <8 x i8> poison, <8 x i32> zeroinitializer
-// RV64-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[VECINIT7_I]] to i64
-// RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-LABEL: define dso_local i64 @test_pmv_s_u8x8(
+// CHECK-SAME: i8 noundef zeroext [[X:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[X]], i64 0
+// CHECK-NEXT: [[VECINIT7_I:%.*]] = shufflevector <8 x i8> [[VECINIT_I]], <8 x i8> poison, <8 x i32> zeroinitializer
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[VECINIT7_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP0]]
//
uint8x8_t test_pmv_s_u8x8(uint8_t x) {
return __riscv_pmv_s_u8x8(x);
}
-// RV32-LABEL: define dso_local i64 @test_pmv_s_i8x8(
-// RV32-SAME: i8 noundef signext [[X:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[X]], i64 0
-// RV32-NEXT: [[VECINIT7_I:%.*]] = shufflevector <8 x i8> [[VECINIT_I]], <8 x i8> poison, <8 x i32> zeroinitializer
-// RV32-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[VECINIT7_I]] to i64
-// RV32-NEXT: ret i64 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmv_s_i8x8(
-// RV64-SAME: i8 noundef signext [[X:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[X]], i64 0
-// RV64-NEXT: [[VECINIT7_I:%.*]] = shufflevector <8 x i8> [[VECINIT_I]], <8 x i8> poison, <8 x i32> zeroinitializer
-// RV64-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[VECINIT7_I]] to i64
-// RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-LABEL: define dso_local i64 @test_pmv_s_i8x8(
+// CHECK-SAME: i8 noundef signext [[X:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[X]], i64 0
+// CHECK-NEXT: [[VECINIT7_I:%.*]] = shufflevector <8 x i8> [[VECINIT_I]], <8 x i8> poison, <8 x i32> zeroinitializer
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[VECINIT7_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP0]]
//
int8x8_t test_pmv_s_i8x8(int8_t x) {
return __riscv_pmv_s_i8x8(x);
}
-// RV32-LABEL: define dso_local i64 @test_pmv_s_u16x4(
-// RV32-SAME: i16 noundef zeroext [[X:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[X]], i64 0
-// RV32-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i16> [[VECINIT_I]], <4 x i16> poison, <4 x i32> zeroinitializer
-// RV32-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to i64
-// RV32-NEXT: ret i64 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmv_s_u16x4(
-// RV64-SAME: i16 noundef zeroext [[X:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[X]], i64 0
-// RV64-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i16> [[VECINIT_I]], <4 x i16> poison, <4 x i32> zeroinitializer
-// RV64-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to i64
-// RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-LABEL: define dso_local i64 @test_pmv_s_u16x4(
+// CHECK-SAME: i16 noundef zeroext [[X:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[X]], i64 0
+// CHECK-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i16> [[VECINIT_I]], <4 x i16> poison, <4 x i32> zeroinitializer
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP0]]
//
uint16x4_t test_pmv_s_u16x4(uint16_t x) {
return __riscv_pmv_s_u16x4(x);
}
-// RV32-LABEL: define dso_local i64 @test_pmv_s_i16x4(
-// RV32-SAME: i16 noundef signext [[X:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[X]], i64 0
-// RV32-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i16> [[VECINIT_I]], <4 x i16> poison, <4 x i32> zeroinitializer
-// RV32-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to i64
-// RV32-NEXT: ret i64 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmv_s_i16x4(
-// RV64-SAME: i16 noundef signext [[X:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[X]], i64 0
-// RV64-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i16> [[VECINIT_I]], <4 x i16> poison, <4 x i32> zeroinitializer
-// RV64-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to i64
-// RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-LABEL: define dso_local i64 @test_pmv_s_i16x4(
+// CHECK-SAME: i16 noundef signext [[X:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[X]], i64 0
+// CHECK-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i16> [[VECINIT_I]], <4 x i16> poison, <4 x i32> zeroinitializer
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP0]]
//
int16x4_t test_pmv_s_i16x4(int16_t x) {
return __riscv_pmv_s_i16x4(x);
@@ -340,217 +276,129 @@ int32x2_t test_pmv_s_i32x2(int32_t x) {
/* Packed Addition and Subtraction (32-bit) */
-// RV32-LABEL: define dso_local i32 @test_padd_i8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ADD_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_padd_i8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ADD_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_padd_i8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ADD_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int8x4_t test_padd_i8x4(int8x4_t a, int8x4_t b) {
return __riscv_padd_i8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_padd_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ADD_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_padd_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ADD_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_padd_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ADD_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_padd_u8x4(uint8x4_t a, uint8x4_t b) {
return __riscv_padd_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_padd_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_padd_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_padd_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int16x2_t test_padd_i16x2(int16x2_t a, int16x2_t b) {
return __riscv_padd_i16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_padd_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_padd_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_padd_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_padd_u16x2(uint16x2_t a, uint16x2_t b) {
return __riscv_padd_u16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_psub_i8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SUB_I:%.*]] = sub <4 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SUB_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_psub_i8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SUB_I:%.*]] = sub <4 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SUB_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_psub_i8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SUB_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int8x4_t test_psub_i8x4(int8x4_t a, int8x4_t b) {
return __riscv_psub_i8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_psub_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SUB_I:%.*]] = sub <4 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SUB_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_psub_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SUB_I:%.*]] = sub <4 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SUB_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_psub_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SUB_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_psub_u8x4(uint8x4_t a, uint8x4_t b) {
return __riscv_psub_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_psub_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SUB_I:%.*]] = sub <2 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SUB_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_psub_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SUB_I:%.*]] = sub <2 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SUB_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_psub_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SUB_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int16x2_t test_psub_i16x2(int16x2_t a, int16x2_t b) {
return __riscv_psub_i16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_psub_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SUB_I:%.*]] = sub <2 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SUB_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_psub_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SUB_I:%.*]] = sub <2 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SUB_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_psub_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SUB_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_psub_u16x2(uint16x2_t a, uint16x2_t b) {
return __riscv_psub_u16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pneg_i8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SUB_I:%.*]] = sub <4 x i8> zeroinitializer, [[TMP0]]
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SUB_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pneg_i8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SUB_I:%.*]] = sub <4 x i8> zeroinitializer, [[TMP0]]
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SUB_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_pneg_i8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i8> zeroinitializer, [[TMP0]]
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SUB_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
int8x4_t test_pneg_i8x4(int8x4_t a) {
return __riscv_pneg_i8x4(a);
}
-// RV32-LABEL: define dso_local i32 @test_pneg_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SUB_I:%.*]] = sub <2 x i16> zeroinitializer, [[TMP0]]
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SUB_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pneg_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SUB_I:%.*]] = sub <2 x i16> zeroinitializer, [[TMP0]]
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SUB_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_pneg_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i16> zeroinitializer, [[TMP0]]
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SUB_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
int16x2_t test_pneg_i16x2(int16x2_t a) {
return __riscv_pneg_i16x2(a);
@@ -558,325 +406,193 @@ int16x2_t test_pneg_i16x2(int16x2_t a) {
/* Packed Addition and Subtraction (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_padd_i8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ADD_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_padd_i8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ADD_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_padd_i8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ADD_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int8x8_t test_padd_i8x8(int8x8_t a, int8x8_t b) {
return __riscv_padd_i8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_padd_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ADD_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_padd_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ADD_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_padd_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ADD_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_padd_u8x8(uint8x8_t a, uint8x8_t b) {
return __riscv_padd_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_padd_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_padd_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_padd_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_padd_i16x4(int16x4_t a, int16x4_t b) {
return __riscv_padd_i16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_padd_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_padd_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_padd_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_padd_u16x4(uint16x4_t a, uint16x4_t b) {
return __riscv_padd_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_padd_i32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_padd_i32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_padd_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int32x2_t test_padd_i32x2(int32x2_t a, int32x2_t b) {
return __riscv_padd_i32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_padd_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_padd_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_padd_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_padd_u32x2(uint32x2_t a, uint32x2_t b) {
return __riscv_padd_u32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_psub_i8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SUB_I:%.*]] = sub <8 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SUB_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psub_i8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SUB_I:%.*]] = sub <8 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SUB_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psub_i8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub <8 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SUB_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int8x8_t test_psub_i8x8(int8x8_t a, int8x8_t b) {
return __riscv_psub_i8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_psub_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SUB_I:%.*]] = sub <8 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SUB_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psub_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SUB_I:%.*]] = sub <8 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SUB_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psub_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub <8 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SUB_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_psub_u8x8(uint8x8_t a, uint8x8_t b) {
return __riscv_psub_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_psub_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psub_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psub_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_psub_i16x4(int16x4_t a, int16x4_t b) {
return __riscv_psub_i16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_psub_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psub_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psub_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_psub_u16x4(uint16x4_t a, uint16x4_t b) {
return __riscv_psub_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_psub_i32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psub_i32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psub_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int32x2_t test_psub_i32x2(int32x2_t a, int32x2_t b) {
return __riscv_psub_i32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_psub_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psub_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psub_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_psub_u32x2(uint32x2_t a, uint32x2_t b) {
return __riscv_psub_u32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pneg_i8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SUB_I:%.*]] = sub <8 x i8> zeroinitializer, [[TMP0]]
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SUB_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pneg_i8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SUB_I:%.*]] = sub <8 x i8> zeroinitializer, [[TMP0]]
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SUB_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pneg_i8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub <8 x i8> zeroinitializer, [[TMP0]]
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SUB_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
int8x8_t test_pneg_i8x8(int8x8_t a) {
return __riscv_pneg_i8x8(a);
}
-// RV32-LABEL: define dso_local i64 @test_pneg_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SUB_I:%.*]] = sub <4 x i16> zeroinitializer, [[TMP0]]
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pneg_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SUB_I:%.*]] = sub <4 x i16> zeroinitializer, [[TMP0]]
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pneg_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i16> zeroinitializer, [[TMP0]]
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
int16x4_t test_pneg_i16x4(int16x4_t a) {
return __riscv_pneg_i16x4(a);
}
-// RV32-LABEL: define dso_local i64 @test_pneg_i32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[SUB_I:%.*]] = sub <2 x i32> zeroinitializer, [[TMP0]]
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pneg_i32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[SUB_I:%.*]] = sub <2 x i32> zeroinitializer, [[TMP0]]
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pneg_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i32> zeroinitializer, [[TMP0]]
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
int32x2_t test_pneg_i32x2(int32x2_t a) {
return __riscv_pneg_i32x2(a);
@@ -884,97 +600,57 @@ int32x2_t test_pneg_i32x2(int32x2_t a) {
/* Packed Addition with Scalar (32-bit) */
-// RV32-LABEL: define dso_local i32 @test_padd_s_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i8 noundef zeroext [[B:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[B]], i64 0
-// RV32-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
-// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i8> [[VECINIT4_I]], [[TMP0]]
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[ADD_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_padd_s_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i8 noundef zeroext [[B:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[B]], i64 0
-// RV64-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
-// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i8> [[VECINIT4_I]], [[TMP0]]
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[ADD_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_padd_s_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i8 noundef zeroext [[B:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[B]], i64 0
+// CHECK-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
+// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i8> [[VECINIT4_I]], [[TMP0]]
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[ADD_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
uint8x4_t test_padd_s_u8x4(uint8x4_t a, uint8_t b) {
return __riscv_padd_s_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_padd_s_i8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i8 noundef signext [[B:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[B]], i64 0
-// RV32-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
-// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i8> [[VECINIT4_I]], [[TMP0]]
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[ADD_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_padd_s_i8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i8 noundef signext [[B:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[B]], i64 0
-// RV64-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
-// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i8> [[VECINIT4_I]], [[TMP0]]
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[ADD_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_padd_s_i8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i8 noundef signext [[B:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[B]], i64 0
+// CHECK-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
+// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i8> [[VECINIT4_I]], [[TMP0]]
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[ADD_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
int8x4_t test_padd_s_i8x4(int8x4_t a, int8_t b) {
return __riscv_padd_s_i8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_padd_s_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i16 noundef zeroext [[B:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[B]], i64 0
-// RV32-NEXT: [[VECINIT2_I:%.*]] = shufflevector <2 x i16> [[VECINIT_I]], <2 x i16> poison, <2 x i32> zeroinitializer
-// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[VECINIT2_I]], [[TMP0]]
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_padd_s_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i16 noundef zeroext [[B:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[B]], i64 0
-// RV64-NEXT: [[VECINIT2_I:%.*]] = shufflevector <2 x i16> [[VECINIT_I]], <2 x i16> poison, <2 x i32> zeroinitializer
-// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[VECINIT2_I]], [[TMP0]]
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_padd_s_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i16 noundef zeroext [[B:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[B]], i64 0
+// CHECK-NEXT: [[VECINIT2_I:%.*]] = shufflevector <2 x i16> [[VECINIT_I]], <2 x i16> poison, <2 x i32> zeroinitializer
+// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[VECINIT2_I]], [[TMP0]]
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
uint16x2_t test_padd_s_u16x2(uint16x2_t a, uint16_t b) {
return __riscv_padd_s_u16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_padd_s_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i16 noundef signext [[B:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[B]], i64 0
-// RV32-NEXT: [[VECINIT2_I:%.*]] = shufflevector <2 x i16> [[VECINIT_I]], <2 x i16> poison, <2 x i32> zeroinitializer
-// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[VECINIT2_I]], [[TMP0]]
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_padd_s_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i16 noundef signext [[B:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[B]], i64 0
-// RV64-NEXT: [[VECINIT2_I:%.*]] = shufflevector <2 x i16> [[VECINIT_I]], <2 x i16> poison, <2 x i32> zeroinitializer
-// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[VECINIT2_I]], [[TMP0]]
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_padd_s_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i16 noundef signext [[B:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[B]], i64 0
+// CHECK-NEXT: [[VECINIT2_I:%.*]] = shufflevector <2 x i16> [[VECINIT_I]], <2 x i16> poison, <2 x i32> zeroinitializer
+// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[VECINIT2_I]], [[TMP0]]
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
int16x2_t test_padd_s_i16x2(int16x2_t a, int16_t b) {
return __riscv_padd_s_i16x2(a, b);
@@ -982,97 +658,57 @@ int16x2_t test_padd_s_i16x2(int16x2_t a, int16_t b) {
/* Packed Addition with Scalar (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_padd_s_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i8 noundef zeroext [[B:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0
-// RV32-NEXT: [[VECINIT8_I:%.*]] = shufflevector <8 x i8> [[VECINIT_I]], <8 x i8> poison, <8 x i32> zeroinitializer
-// RV32-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[VECINIT8_I]], [[TMP0]]
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[ADD_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_padd_s_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i8 noundef zeroext [[B:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0
-// RV64-NEXT: [[VECINIT8_I:%.*]] = shufflevector <8 x i8> [[VECINIT_I]], <8 x i8> poison, <8 x i32> zeroinitializer
-// RV64-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[VECINIT8_I]], [[TMP0]]
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[ADD_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_padd_s_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i8 noundef zeroext [[B:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0
+// CHECK-NEXT: [[VECINIT8_I:%.*]] = shufflevector <8 x i8> [[VECINIT_I]], <8 x i8> poison, <8 x i32> zeroinitializer
+// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[VECINIT8_I]], [[TMP0]]
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[ADD_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
uint8x8_t test_padd_s_u8x8(uint8x8_t a, uint8_t b) {
return __riscv_padd_s_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_padd_s_i8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i8 noundef signext [[B:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0
-// RV32-NEXT: [[VECINIT8_I:%.*]] = shufflevector <8 x i8> [[VECINIT_I]], <8 x i8> poison, <8 x i32> zeroinitializer
-// RV32-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[VECINIT8_I]], [[TMP0]]
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[ADD_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_padd_s_i8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i8 noundef signext [[B:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0
-// RV64-NEXT: [[VECINIT8_I:%.*]] = shufflevector <8 x i8> [[VECINIT_I]], <8 x i8> poison, <8 x i32> zeroinitializer
-// RV64-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[VECINIT8_I]], [[TMP0]]
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[ADD_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_padd_s_i8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i8 noundef signext [[B:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0
+// CHECK-NEXT: [[VECINIT8_I:%.*]] = shufflevector <8 x i8> [[VECINIT_I]], <8 x i8> poison, <8 x i32> zeroinitializer
+// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[VECINIT8_I]], [[TMP0]]
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[ADD_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
int8x8_t test_padd_s_i8x8(int8x8_t a, int8_t b) {
return __riscv_padd_s_i8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_padd_s_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i16 noundef zeroext [[B:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0
-// RV32-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i16> [[VECINIT_I]], <4 x i16> poison, <4 x i32> zeroinitializer
-// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[VECINIT4_I]], [[TMP0]]
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_padd_s_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i16 noundef zeroext [[B:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0
-// RV64-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i16> [[VECINIT_I]], <4 x i16> poison, <4 x i32> zeroinitializer
-// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[VECINIT4_I]], [[TMP0]]
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_padd_s_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i16 noundef zeroext [[B:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0
+// CHECK-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i16> [[VECINIT_I]], <4 x i16> poison, <4 x i32> zeroinitializer
+// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[VECINIT4_I]], [[TMP0]]
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
uint16x4_t test_padd_s_u16x4(uint16x4_t a, uint16_t b) {
return __riscv_padd_s_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_padd_s_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i16 noundef signext [[B:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0
-// RV32-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i16> [[VECINIT_I]], <4 x i16> poison, <4 x i32> zeroinitializer
-// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[VECINIT4_I]], [[TMP0]]
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_padd_s_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i16 noundef signext [[B:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0
-// RV64-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i16> [[VECINIT_I]], <4 x i16> poison, <4 x i32> zeroinitializer
-// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[VECINIT4_I]], [[TMP0]]
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_padd_s_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i16 noundef signext [[B:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0
+// CHECK-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i16> [[VECINIT_I]], <4 x i16> poison, <4 x i32> zeroinitializer
+// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[VECINIT4_I]], [[TMP0]]
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
int16x4_t test_padd_s_i16x4(int16x4_t a, int16_t b) {
return __riscv_padd_s_i16x4(a, b);
@@ -1128,177 +764,105 @@ int32x2_t test_padd_s_i32x2(int32x2_t a, int32_t b) {
/* Packed Saturating Addition and Subtraction (32-bit) */
-// RV32-LABEL: define dso_local i32 @test_psadd_i8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_SAT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_psadd_i8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_SAT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_psadd_i8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_SAT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int8x4_t test_psadd_i8x4(int8x4_t a, int8x4_t b) {
return __riscv_psadd_i8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_psadd_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_psadd_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_psadd_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int16x2_t test_psadd_i16x2(int16x2_t a, int16x2_t b) {
return __riscv_psadd_i16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_psaddu_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_SAT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_psaddu_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_SAT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_psaddu_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_SAT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_psaddu_u8x4(uint8x4_t a, uint8x4_t b) {
return __riscv_psaddu_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_psaddu_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_psaddu_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_psaddu_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_psaddu_u16x2(uint16x2_t a, uint16x2_t b) {
return __riscv_psaddu_u16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pssub_i8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_SAT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pssub_i8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_SAT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pssub_i8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_SAT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int8x4_t test_pssub_i8x4(int8x4_t a, int8x4_t b) {
return __riscv_pssub_i8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pssub_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pssub_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pssub_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int16x2_t test_pssub_i16x2(int16x2_t a, int16x2_t b) {
return __riscv_pssub_i16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pssubu_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_SAT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pssubu_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_SAT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pssubu_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_SAT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_pssubu_u8x4(uint8x4_t a, uint8x4_t b) {
return __riscv_pssubu_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pssubu_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pssubu_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pssubu_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_pssubu_u16x2(uint16x2_t a, uint16x2_t b) {
return __riscv_pssubu_u16x2(a, b);
@@ -1306,265 +870,157 @@ uint16x2_t test_pssubu_u16x2(uint16x2_t a, uint16x2_t b) {
/* Packed Saturating Addition and Subtraction (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_psadd_i8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_SAT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psadd_i8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_SAT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psadd_i8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_SAT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int8x8_t test_psadd_i8x8(int8x8_t a, int8x8_t b) {
return __riscv_psadd_i8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_psadd_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psadd_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psadd_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_psadd_i16x4(int16x4_t a, int16x4_t b) {
return __riscv_psadd_i16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_psadd_i32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psadd_i32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psadd_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int32x2_t test_psadd_i32x2(int32x2_t a, int32x2_t b) {
return __riscv_psadd_i32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_psaddu_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_SAT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psaddu_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_SAT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psaddu_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_SAT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_psaddu_u8x8(uint8x8_t a, uint8x8_t b) {
return __riscv_psaddu_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_psaddu_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psaddu_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psaddu_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_psaddu_u16x4(uint16x4_t a, uint16x4_t b) {
return __riscv_psaddu_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_psaddu_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psaddu_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psaddu_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_psaddu_u32x2(uint32x2_t a, uint32x2_t b) {
return __riscv_psaddu_u32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pssub_i8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_SAT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pssub_i8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_SAT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pssub_i8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_SAT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int8x8_t test_pssub_i8x8(int8x8_t a, int8x8_t b) {
return __riscv_pssub_i8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pssub_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pssub_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pssub_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_pssub_i16x4(int16x4_t a, int16x4_t b) {
return __riscv_pssub_i16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pssub_i32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pssub_i32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pssub_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int32x2_t test_pssub_i32x2(int32x2_t a, int32x2_t b) {
return __riscv_pssub_i32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pssubu_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <8 x i8> @llvm.usub.sat.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_SAT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pssubu_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <8 x i8> @llvm.usub.sat.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_SAT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pssubu_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <8 x i8> @llvm.usub.sat.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_SAT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_pssubu_u8x8(uint8x8_t a, uint8x8_t b) {
return __riscv_pssubu_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pssubu_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pssubu_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pssubu_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pssubu_u16x4(uint16x4_t a, uint16x4_t b) {
return __riscv_pssubu_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pssubu_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pssubu_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pssubu_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_pssubu_u32x2(uint32x2_t a, uint32x2_t b) {
return __riscv_pssubu_u32x2(a, b);
@@ -1572,73 +1028,43 @@ uint32x2_t test_pssubu_u32x2(uint32x2_t a, uint32x2_t b) {
/* Packed Shift-Add (32-bit) */
-// RV32-LABEL: define dso_local i32 @test_psh1add_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHL_I:%.*]] = shl <2 x i16> [[TMP0]], splat (i16 1)
-// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[SHL_I]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_psh1add_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHL_I:%.*]] = shl <2 x i16> [[TMP0]], splat (i16 1)
-// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[SHL_I]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_psh1add_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHL_I:%.*]] = shl <2 x i16> [[TMP0]], splat (i16 1)
+// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[SHL_I]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int16x2_t test_psh1add_i16x2(int16x2_t a, int16x2_t b) {
return __riscv_psh1add_i16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_psh1add_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHL_I:%.*]] = shl <2 x i16> [[TMP0]], splat (i16 1)
-// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[SHL_I]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_psh1add_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHL_I:%.*]] = shl <2 x i16> [[TMP0]], splat (i16 1)
-// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[SHL_I]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_psh1add_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHL_I:%.*]] = shl <2 x i16> [[TMP0]], splat (i16 1)
+// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[SHL_I]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_psh1add_u16x2(uint16x2_t a, uint16x2_t b) {
return __riscv_psh1add_u16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pssh1sadd_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP0]])
-// RV32-NEXT: [[ELT_SAT3_I:%.*]] = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> [[ELT_SAT_I]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT3_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pssh1sadd_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP0]])
-// RV64-NEXT: [[ELT_SAT3_I:%.*]] = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> [[ELT_SAT_I]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT3_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pssh1sadd_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP0]])
+// CHECK-NEXT: [[ELT_SAT3_I:%.*]] = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> [[ELT_SAT_I]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT3_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int16x2_t test_pssh1sadd_i16x2(int16x2_t a, int16x2_t b) {
return __riscv_pssh1sadd_i16x2(a, b);
@@ -1646,543 +1072,321 @@ int16x2_t test_pssh1sadd_i16x2(int16x2_t a, int16x2_t b) {
/* Packed Shift-Add (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_psh1add_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHL_I:%.*]] = shl <4 x i16> [[TMP0]], splat (i16 1)
-// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[SHL_I]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psh1add_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHL_I:%.*]] = shl <4 x i16> [[TMP0]], splat (i16 1)
-// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[SHL_I]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psh1add_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHL_I:%.*]] = shl <4 x i16> [[TMP0]], splat (i16 1)
+// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[SHL_I]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_psh1add_i16x4(int16x4_t a, int16x4_t b) {
return __riscv_psh1add_i16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_psh1add_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHL_I:%.*]] = shl <4 x i16> [[TMP0]], splat (i16 1)
-// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[SHL_I]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psh1add_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHL_I:%.*]] = shl <4 x i16> [[TMP0]], splat (i16 1)
-// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[SHL_I]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psh1add_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHL_I:%.*]] = shl <4 x i16> [[TMP0]], splat (i16 1)
+// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[SHL_I]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_psh1add_u16x4(uint16x4_t a, uint16x4_t b) {
return __riscv_psh1add_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_psh1add_i32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[SHL_I:%.*]] = shl <2 x i32> [[TMP0]], splat (i32 1)
-// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[SHL_I]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psh1add_i32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[SHL_I:%.*]] = shl <2 x i32> [[TMP0]], splat (i32 1)
-// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[SHL_I]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psh1add_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[SHL_I:%.*]] = shl <2 x i32> [[TMP0]], splat (i32 1)
+// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[SHL_I]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int32x2_t test_psh1add_i32x2(int32x2_t a, int32x2_t b) {
return __riscv_psh1add_i32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_psh1add_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[SHL_I:%.*]] = shl <2 x i32> [[TMP0]], splat (i32 1)
-// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[SHL_I]], [[TMP1]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psh1add_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[SHL_I:%.*]] = shl <2 x i32> [[TMP0]], splat (i32 1)
-// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[SHL_I]], [[TMP1]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psh1add_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[SHL_I:%.*]] = shl <2 x i32> [[TMP0]], splat (i32 1)
+// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[SHL_I]], [[TMP1]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_psh1add_u32x2(uint32x2_t a, uint32x2_t b) {
return __riscv_psh1add_u32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pssh1sadd_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP0]])
-// RV32-NEXT: [[ELT_SAT3_I:%.*]] = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> [[ELT_SAT_I]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT3_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pssh1sadd_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP0]])
-// RV64-NEXT: [[ELT_SAT3_I:%.*]] = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> [[ELT_SAT_I]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT3_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pssh1sadd_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP0]])
+// CHECK-NEXT: [[ELT_SAT3_I:%.*]] = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> [[ELT_SAT_I]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT3_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_pssh1sadd_i16x4(int16x4_t a, int16x4_t b) {
return __riscv_pssh1sadd_i16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pssh1sadd_i32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP0]])
-// RV32-NEXT: [[ELT_SAT3_I:%.*]] = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> [[ELT_SAT_I]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT3_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pssh1sadd_i32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP0]])
-// RV64-NEXT: [[ELT_SAT3_I:%.*]] = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> [[ELT_SAT_I]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT3_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pssh1sadd_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP0]])
+// CHECK-NEXT: [[ELT_SAT3_I:%.*]] = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> [[ELT_SAT_I]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT3_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int32x2_t test_pssh1sadd_i32x2(int32x2_t a, int32x2_t b) {
return __riscv_pssh1sadd_i32x2(a, b);
}
/* Packed Exchanged Addition and Subtraction (32-bit) */
-// RV32-LABEL: define dso_local i32 @test_pas_x_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pas.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_pas_x_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pas.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_pas_x_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pas.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
int16x2_t test_pas_x_i16x2(int16x2_t a, int16x2_t b) {
return __riscv_pas_x_i16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_psa_x_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.psa.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_psa_x_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.psa.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_psa_x_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.psa.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
int16x2_t test_psa_x_i16x2(int16x2_t a, int16x2_t b) {
return __riscv_psa_x_i16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_psas_x_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.psas.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_psas_x_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.psas.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_psas_x_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.psas.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
int16x2_t test_psas_x_i16x2(int16x2_t a, int16x2_t b) {
return __riscv_psas_x_i16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pssa_x_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pssa.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_pssa_x_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pssa.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_pssa_x_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pssa.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
int16x2_t test_pssa_x_i16x2(int16x2_t a, int16x2_t b) {
return __riscv_pssa_x_i16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_paas_x_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.paas.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_paas_x_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.paas.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_paas_x_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.paas.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
int16x2_t test_paas_x_i16x2(int16x2_t a, int16x2_t b) {
return __riscv_paas_x_i16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pasa_x_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pasa.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_pasa_x_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pasa.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_pasa_x_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pasa.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
int16x2_t test_pasa_x_i16x2(int16x2_t a, int16x2_t b) {
return __riscv_pasa_x_i16x2(a, b);
}
/* Packed Exchanged Addition and Subtraction (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_pas_x_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pas.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pas_x_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pas.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pas_x_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pas.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int16x4_t test_pas_x_i16x4(int16x4_t a, int16x4_t b) {
return __riscv_pas_x_i16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_psa_x_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.psa.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_psa_x_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.psa.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_psa_x_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.psa.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int16x4_t test_psa_x_i16x4(int16x4_t a, int16x4_t b) {
return __riscv_psa_x_i16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_psas_x_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.psas.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_psas_x_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.psas.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_psas_x_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.psas.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int16x4_t test_psas_x_i16x4(int16x4_t a, int16x4_t b) {
return __riscv_psas_x_i16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pssa_x_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pssa.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pssa_x_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pssa.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pssa_x_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pssa.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int16x4_t test_pssa_x_i16x4(int16x4_t a, int16x4_t b) {
return __riscv_pssa_x_i16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_paas_x_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.paas.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_paas_x_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.paas.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_paas_x_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.paas.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int16x4_t test_paas_x_i16x4(int16x4_t a, int16x4_t b) {
return __riscv_paas_x_i16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pasa_x_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pasa.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pasa_x_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pasa.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pasa_x_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pasa.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int16x4_t test_pasa_x_i16x4(int16x4_t a, int16x4_t b) {
return __riscv_pasa_x_i16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pas_x_i32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pas.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pas_x_i32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pas.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pas_x_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pas.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int32x2_t test_pas_x_i32x2(int32x2_t a, int32x2_t b) {
return __riscv_pas_x_i32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_psa_x_i32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.psa.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_psa_x_i32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.psa.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_psa_x_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.psa.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int32x2_t test_psa_x_i32x2(int32x2_t a, int32x2_t b) {
return __riscv_psa_x_i32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_psas_x_i32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.psas.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_psas_x_i32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.psas.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_psas_x_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.psas.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int32x2_t test_psas_x_i32x2(int32x2_t a, int32x2_t b) {
return __riscv_psas_x_i32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pssa_x_i32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pssa.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pssa_x_i32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pssa.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pssa_x_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pssa.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int32x2_t test_pssa_x_i32x2(int32x2_t a, int32x2_t b) {
return __riscv_pssa_x_i32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_paas_x_i32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.paas.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_paas_x_i32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.paas.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_paas_x_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.paas.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int32x2_t test_paas_x_i32x2(int32x2_t a, int32x2_t b) {
return __riscv_paas_x_i32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pasa_x_i32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pasa.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pasa_x_i32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pasa.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pasa_x_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pasa.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int32x2_t test_pasa_x_i32x2(int32x2_t a, int32x2_t b) {
return __riscv_pasa_x_i32x2(a, b);
@@ -2190,177 +1394,105 @@ int32x2_t test_pasa_x_i32x2(int32x2_t a, int32x2_t b) {
/* Packed Minimum and Maximum (32-bit) */
-// RV32-LABEL: define dso_local i32 @test_pmin_i8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[ELT_MIN_I:%.*]] = call <4 x i8> @llvm.smin.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_MIN_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmin_i8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[ELT_MIN_I:%.*]] = call <4 x i8> @llvm.smin.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_MIN_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmin_i8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[ELT_MIN_I:%.*]] = call <4 x i8> @llvm.smin.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_MIN_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int8x4_t test_pmin_i8x4(int8x4_t a, int8x4_t b) {
return __riscv_pmin_i8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmin_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[ELT_MIN_I:%.*]] = call <2 x i16> @llvm.smin.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_MIN_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmin_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[ELT_MIN_I:%.*]] = call <2 x i16> @llvm.smin.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_MIN_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmin_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[ELT_MIN_I:%.*]] = call <2 x i16> @llvm.smin.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_MIN_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int16x2_t test_pmin_i16x2(int16x2_t a, int16x2_t b) {
return __riscv_pmin_i16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pminu_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[ELT_MIN_I:%.*]] = call <4 x i8> @llvm.umin.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_MIN_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pminu_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[ELT_MIN_I:%.*]] = call <4 x i8> @llvm.umin.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_MIN_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pminu_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[ELT_MIN_I:%.*]] = call <4 x i8> @llvm.umin.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_MIN_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_pminu_u8x4(uint8x4_t a, uint8x4_t b) {
return __riscv_pminu_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pminu_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[ELT_MIN_I:%.*]] = call <2 x i16> @llvm.umin.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_MIN_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pminu_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[ELT_MIN_I:%.*]] = call <2 x i16> @llvm.umin.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_MIN_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pminu_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[ELT_MIN_I:%.*]] = call <2 x i16> @llvm.umin.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_MIN_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_pminu_u16x2(uint16x2_t a, uint16x2_t b) {
return __riscv_pminu_u16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmax_i8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[ELT_MAX_I:%.*]] = call <4 x i8> @llvm.smax.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_MAX_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmax_i8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[ELT_MAX_I:%.*]] = call <4 x i8> @llvm.smax.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_MAX_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmax_i8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[ELT_MAX_I:%.*]] = call <4 x i8> @llvm.smax.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_MAX_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int8x4_t test_pmax_i8x4(int8x4_t a, int8x4_t b) {
return __riscv_pmax_i8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmax_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[ELT_MAX_I:%.*]] = call <2 x i16> @llvm.smax.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_MAX_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmax_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[ELT_MAX_I:%.*]] = call <2 x i16> @llvm.smax.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_MAX_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmax_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[ELT_MAX_I:%.*]] = call <2 x i16> @llvm.smax.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_MAX_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int16x2_t test_pmax_i16x2(int16x2_t a, int16x2_t b) {
return __riscv_pmax_i16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmaxu_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[ELT_MAX_I:%.*]] = call <4 x i8> @llvm.umax.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_MAX_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmaxu_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[ELT_MAX_I:%.*]] = call <4 x i8> @llvm.umax.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_MAX_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmaxu_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[ELT_MAX_I:%.*]] = call <4 x i8> @llvm.umax.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_MAX_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_pmaxu_u8x4(uint8x4_t a, uint8x4_t b) {
return __riscv_pmaxu_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmaxu_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[ELT_MAX_I:%.*]] = call <2 x i16> @llvm.umax.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_MAX_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmaxu_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[ELT_MAX_I:%.*]] = call <2 x i16> @llvm.umax.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_MAX_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmaxu_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[ELT_MAX_I:%.*]] = call <2 x i16> @llvm.umax.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_MAX_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_pmaxu_u16x2(uint16x2_t a, uint16x2_t b) {
return __riscv_pmaxu_u16x2(a, b);
@@ -2368,842 +1500,494 @@ uint16x2_t test_pmaxu_u16x2(uint16x2_t a, uint16x2_t b) {
/* Packed Minimum and Maximum (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_pmin_i8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[ELT_MIN_I:%.*]] = call <8 x i8> @llvm.smin.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_MIN_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmin_i8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[ELT_MIN_I:%.*]] = call <8 x i8> @llvm.smin.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_MIN_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmin_i8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[ELT_MIN_I:%.*]] = call <8 x i8> @llvm.smin.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_MIN_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int8x8_t test_pmin_i8x8(int8x8_t a, int8x8_t b) {
return __riscv_pmin_i8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmin_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[ELT_MIN_I:%.*]] = call <4 x i16> @llvm.smin.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_MIN_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmin_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[ELT_MIN_I:%.*]] = call <4 x i16> @llvm.smin.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_MIN_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmin_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[ELT_MIN_I:%.*]] = call <4 x i16> @llvm.smin.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_MIN_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_pmin_i16x4(int16x4_t a, int16x4_t b) {
return __riscv_pmin_i16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmin_i32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[ELT_MIN_I:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_MIN_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmin_i32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[ELT_MIN_I:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_MIN_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmin_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[ELT_MIN_I:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_MIN_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int32x2_t test_pmin_i32x2(int32x2_t a, int32x2_t b) {
return __riscv_pmin_i32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pminu_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[ELT_MIN_I:%.*]] = call <8 x i8> @llvm.umin.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_MIN_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pminu_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[ELT_MIN_I:%.*]] = call <8 x i8> @llvm.umin.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_MIN_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pminu_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[ELT_MIN_I:%.*]] = call <8 x i8> @llvm.umin.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_MIN_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_pminu_u8x8(uint8x8_t a, uint8x8_t b) {
return __riscv_pminu_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pminu_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[ELT_MIN_I:%.*]] = call <4 x i16> @llvm.umin.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_MIN_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pminu_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[ELT_MIN_I:%.*]] = call <4 x i16> @llvm.umin.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_MIN_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pminu_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[ELT_MIN_I:%.*]] = call <4 x i16> @llvm.umin.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_MIN_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pminu_u16x4(uint16x4_t a, uint16x4_t b) {
return __riscv_pminu_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pminu_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[ELT_MIN_I:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_MIN_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pminu_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[ELT_MIN_I:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_MIN_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pminu_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[ELT_MIN_I:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_MIN_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_pminu_u32x2(uint32x2_t a, uint32x2_t b) {
return __riscv_pminu_u32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmax_i8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[ELT_MAX_I:%.*]] = call <8 x i8> @llvm.smax.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_MAX_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmax_i8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[ELT_MAX_I:%.*]] = call <8 x i8> @llvm.smax.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_MAX_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmax_i8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[ELT_MAX_I:%.*]] = call <8 x i8> @llvm.smax.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_MAX_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int8x8_t test_pmax_i8x8(int8x8_t a, int8x8_t b) {
return __riscv_pmax_i8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmax_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[ELT_MAX_I:%.*]] = call <4 x i16> @llvm.smax.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_MAX_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmax_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[ELT_MAX_I:%.*]] = call <4 x i16> @llvm.smax.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_MAX_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmax_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[ELT_MAX_I:%.*]] = call <4 x i16> @llvm.smax.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_MAX_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_pmax_i16x4(int16x4_t a, int16x4_t b) {
return __riscv_pmax_i16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmax_i32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[ELT_MAX_I:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_MAX_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmax_i32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[ELT_MAX_I:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_MAX_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmax_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[ELT_MAX_I:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_MAX_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int32x2_t test_pmax_i32x2(int32x2_t a, int32x2_t b) {
return __riscv_pmax_i32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmaxu_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[ELT_MAX_I:%.*]] = call <8 x i8> @llvm.umax.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_MAX_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmaxu_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[ELT_MAX_I:%.*]] = call <8 x i8> @llvm.umax.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_MAX_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmaxu_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[ELT_MAX_I:%.*]] = call <8 x i8> @llvm.umax.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_MAX_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_pmaxu_u8x8(uint8x8_t a, uint8x8_t b) {
return __riscv_pmaxu_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmaxu_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[ELT_MAX_I:%.*]] = call <4 x i16> @llvm.umax.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_MAX_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmaxu_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[ELT_MAX_I:%.*]] = call <4 x i16> @llvm.umax.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_MAX_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmaxu_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[ELT_MAX_I:%.*]] = call <4 x i16> @llvm.umax.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_MAX_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pmaxu_u16x4(uint16x4_t a, uint16x4_t b) {
return __riscv_pmaxu_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmaxu_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[ELT_MAX_I:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_MAX_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmaxu_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[ELT_MAX_I:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_MAX_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmaxu_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[ELT_MAX_I:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_MAX_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_pmaxu_u32x2(uint32x2_t a, uint32x2_t b) {
return __riscv_pmaxu_u32x2(a, b);
}
/* Packed Comparison (32-bit) */
-// RV32-LABEL: define dso_local i32 @test_pmseq_i8x4_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmseq_i8x4_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmseq_i8x4_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_pmseq_i8x4_u8x4(int8x4_t a, int8x4_t b) {
return __riscv_pmseq_i8x4_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmseq_u8x4_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmseq_u8x4_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmseq_u8x4_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_pmseq_u8x4_u8x4(uint8x4_t a, uint8x4_t b) {
return __riscv_pmseq_u8x4_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmsne_i8x4_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ne <4 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmsne_i8x4_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ne <4 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmsne_i8x4_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ne <4 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_pmsne_i8x4_u8x4(int8x4_t a, int8x4_t b) {
return __riscv_pmsne_i8x4_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmsne_u8x4_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ne <4 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmsne_u8x4_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ne <4 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmsne_u8x4_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ne <4 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_pmsne_u8x4_u8x4(uint8x4_t a, uint8x4_t b) {
return __riscv_pmsne_u8x4_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmslt_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp slt <4 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmslt_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp slt <4 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmslt_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp slt <4 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_pmslt_u8x4(int8x4_t a, int8x4_t b) {
return __riscv_pmslt_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmsltu_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ult <4 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmsltu_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ult <4 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmsltu_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ult <4 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_pmsltu_u8x4(uint8x4_t a, uint8x4_t b) {
return __riscv_pmsltu_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmsgt_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp sgt <4 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmsgt_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp sgt <4 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmsgt_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp sgt <4 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_pmsgt_u8x4(int8x4_t a, int8x4_t b) {
return __riscv_pmsgt_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmsgtu_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ugt <4 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmsgtu_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ugt <4 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmsgtu_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ugt <4 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_pmsgtu_u8x4(uint8x4_t a, uint8x4_t b) {
return __riscv_pmsgtu_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmsge_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp sge <4 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmsge_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp sge <4 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmsge_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp sge <4 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_pmsge_u8x4(int8x4_t a, int8x4_t b) {
return __riscv_pmsge_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmsgeu_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp uge <4 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmsgeu_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp uge <4 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmsgeu_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp uge <4 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_pmsgeu_u8x4(uint8x4_t a, uint8x4_t b) {
return __riscv_pmsgeu_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmsle_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp sle <4 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmsle_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp sle <4 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmsle_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp sle <4 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_pmsle_u8x4(int8x4_t a, int8x4_t b) {
return __riscv_pmsle_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmsleu_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ule <4 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmsleu_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ule <4 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmsleu_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule <4 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_pmsleu_u8x4(uint8x4_t a, uint8x4_t b) {
return __riscv_pmsleu_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmseq_i16x2_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmseq_i16x2_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmseq_i16x2_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_pmseq_i16x2_u16x2(int16x2_t a, int16x2_t b) {
return __riscv_pmseq_i16x2_u16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmseq_u16x2_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmseq_u16x2_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmseq_u16x2_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_pmseq_u16x2_u16x2(uint16x2_t a, uint16x2_t b) {
return __riscv_pmseq_u16x2_u16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmsne_i16x2_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ne <2 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmsne_i16x2_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ne <2 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmsne_i16x2_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ne <2 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_pmsne_i16x2_u16x2(int16x2_t a, int16x2_t b) {
return __riscv_pmsne_i16x2_u16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmsne_u16x2_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ne <2 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmsne_u16x2_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ne <2 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmsne_u16x2_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ne <2 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_pmsne_u16x2_u16x2(uint16x2_t a, uint16x2_t b) {
return __riscv_pmsne_u16x2_u16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmslt_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp slt <2 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmslt_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp slt <2 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmslt_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp slt <2 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_pmslt_u16x2(int16x2_t a, int16x2_t b) {
return __riscv_pmslt_u16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmsltu_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ult <2 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmsltu_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ult <2 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmsltu_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ult <2 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_pmsltu_u16x2(uint16x2_t a, uint16x2_t b) {
return __riscv_pmsltu_u16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmsgt_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp sgt <2 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmsgt_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp sgt <2 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmsgt_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp sgt <2 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_pmsgt_u16x2(int16x2_t a, int16x2_t b) {
return __riscv_pmsgt_u16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmsgtu_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ugt <2 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmsgtu_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ugt <2 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmsgtu_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ugt <2 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_pmsgtu_u16x2(uint16x2_t a, uint16x2_t b) {
return __riscv_pmsgtu_u16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmsge_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp sge <2 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmsge_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp sge <2 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmsge_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp sge <2 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_pmsge_u16x2(int16x2_t a, int16x2_t b) {
return __riscv_pmsge_u16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmsgeu_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp uge <2 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmsgeu_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp uge <2 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmsgeu_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp uge <2 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_pmsgeu_u16x2(uint16x2_t a, uint16x2_t b) {
return __riscv_pmsgeu_u16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmsle_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp sle <2 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmsle_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp sle <2 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmsle_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp sle <2 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_pmsle_u16x2(int16x2_t a, int16x2_t b) {
return __riscv_pmsle_u16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pmsleu_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ule <2 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmsleu_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ule <2 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pmsleu_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule <2 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_pmsleu_u16x2(uint16x2_t a, uint16x2_t b) {
return __riscv_pmsleu_u16x2(a, b);
@@ -3211,865 +1995,505 @@ uint16x2_t test_pmsleu_u16x2(uint16x2_t a, uint16x2_t b) {
/* Packed Comparison (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_pmseq_i8x8_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp eq <8 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmseq_i8x8_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp eq <8 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmseq_i8x8_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <8 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_pmseq_i8x8_u8x8(int8x8_t a, int8x8_t b) {
return __riscv_pmseq_i8x8_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmseq_u8x8_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp eq <8 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmseq_u8x8_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp eq <8 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmseq_u8x8_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <8 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_pmseq_u8x8_u8x8(uint8x8_t a, uint8x8_t b) {
return __riscv_pmseq_u8x8_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsne_i8x8_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ne <8 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsne_i8x8_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ne <8 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsne_i8x8_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ne <8 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_pmsne_i8x8_u8x8(int8x8_t a, int8x8_t b) {
return __riscv_pmsne_i8x8_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsne_u8x8_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ne <8 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsne_u8x8_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ne <8 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsne_u8x8_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ne <8 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_pmsne_u8x8_u8x8(uint8x8_t a, uint8x8_t b) {
return __riscv_pmsne_u8x8_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmslt_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp slt <8 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmslt_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp slt <8 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmslt_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp slt <8 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_pmslt_u8x8(int8x8_t a, int8x8_t b) {
return __riscv_pmslt_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsltu_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ult <8 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsltu_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ult <8 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsltu_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ult <8 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_pmsltu_u8x8(uint8x8_t a, uint8x8_t b) {
return __riscv_pmsltu_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsgt_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp sgt <8 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsgt_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp sgt <8 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsgt_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp sgt <8 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_pmsgt_u8x8(int8x8_t a, int8x8_t b) {
return __riscv_pmsgt_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsgtu_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ugt <8 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsgtu_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ugt <8 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsgtu_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ugt <8 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_pmsgtu_u8x8(uint8x8_t a, uint8x8_t b) {
return __riscv_pmsgtu_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsge_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp sge <8 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsge_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp sge <8 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsge_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp sge <8 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_pmsge_u8x8(int8x8_t a, int8x8_t b) {
return __riscv_pmsge_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsgeu_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp uge <8 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsgeu_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp uge <8 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsgeu_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp uge <8 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_pmsgeu_u8x8(uint8x8_t a, uint8x8_t b) {
return __riscv_pmsgeu_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsle_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp sle <8 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsle_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp sle <8 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsle_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp sle <8 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_pmsle_u8x8(int8x8_t a, int8x8_t b) {
return __riscv_pmsle_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsleu_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ule <8 x i8> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsleu_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ule <8 x i8> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsleu_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule <8 x i8> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_pmsleu_u8x8(uint8x8_t a, uint8x8_t b) {
return __riscv_pmsleu_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmseq_i16x4_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmseq_i16x4_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmseq_i16x4_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pmseq_i16x4_u16x4(int16x4_t a, int16x4_t b) {
return __riscv_pmseq_i16x4_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmseq_u16x4_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmseq_u16x4_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmseq_u16x4_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pmseq_u16x4_u16x4(uint16x4_t a, uint16x4_t b) {
return __riscv_pmseq_u16x4_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsne_i16x4_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ne <4 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsne_i16x4_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ne <4 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsne_i16x4_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ne <4 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pmsne_i16x4_u16x4(int16x4_t a, int16x4_t b) {
return __riscv_pmsne_i16x4_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsne_u16x4_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ne <4 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsne_u16x4_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ne <4 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsne_u16x4_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ne <4 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pmsne_u16x4_u16x4(uint16x4_t a, uint16x4_t b) {
return __riscv_pmsne_u16x4_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmslt_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp slt <4 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmslt_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp slt <4 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmslt_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp slt <4 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pmslt_u16x4(int16x4_t a, int16x4_t b) {
return __riscv_pmslt_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsltu_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ult <4 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsltu_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ult <4 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsltu_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ult <4 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pmsltu_u16x4(uint16x4_t a, uint16x4_t b) {
return __riscv_pmsltu_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsgt_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp sgt <4 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsgt_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp sgt <4 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsgt_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp sgt <4 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pmsgt_u16x4(int16x4_t a, int16x4_t b) {
return __riscv_pmsgt_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsgtu_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ugt <4 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsgtu_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ugt <4 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsgtu_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ugt <4 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pmsgtu_u16x4(uint16x4_t a, uint16x4_t b) {
return __riscv_pmsgtu_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsge_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp sge <4 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsge_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp sge <4 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsge_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp sge <4 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pmsge_u16x4(int16x4_t a, int16x4_t b) {
return __riscv_pmsge_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsgeu_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp uge <4 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsgeu_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp uge <4 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsgeu_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp uge <4 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pmsgeu_u16x4(uint16x4_t a, uint16x4_t b) {
return __riscv_pmsgeu_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsle_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp sle <4 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsle_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp sle <4 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsle_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp sle <4 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pmsle_u16x4(int16x4_t a, int16x4_t b) {
return __riscv_pmsle_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsleu_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ule <4 x i16> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsleu_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ule <4 x i16> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsleu_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule <4 x i16> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pmsleu_u16x4(uint16x4_t a, uint16x4_t b) {
return __riscv_pmsleu_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmseq_i32x2_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i32> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmseq_i32x2_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i32> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmseq_i32x2_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i32> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_pmseq_i32x2_u32x2(int32x2_t a, int32x2_t b) {
return __riscv_pmseq_i32x2_u32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmseq_u32x2_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i32> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmseq_u32x2_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i32> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmseq_u32x2_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i32> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_pmseq_u32x2_u32x2(uint32x2_t a, uint32x2_t b) {
return __riscv_pmseq_u32x2_u32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsne_i32x2_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ne <2 x i32> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsne_i32x2_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ne <2 x i32> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsne_i32x2_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ne <2 x i32> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_pmsne_i32x2_u32x2(int32x2_t a, int32x2_t b) {
return __riscv_pmsne_i32x2_u32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsne_u32x2_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ne <2 x i32> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsne_u32x2_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ne <2 x i32> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsne_u32x2_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ne <2 x i32> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_pmsne_u32x2_u32x2(uint32x2_t a, uint32x2_t b) {
return __riscv_pmsne_u32x2_u32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmslt_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp slt <2 x i32> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmslt_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp slt <2 x i32> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmslt_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp slt <2 x i32> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_pmslt_u32x2(int32x2_t a, int32x2_t b) {
return __riscv_pmslt_u32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsltu_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ult <2 x i32> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsltu_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ult <2 x i32> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsltu_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ult <2 x i32> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_pmsltu_u32x2(uint32x2_t a, uint32x2_t b) {
return __riscv_pmsltu_u32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsgt_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp sgt <2 x i32> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsgt_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp sgt <2 x i32> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsgt_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp sgt <2 x i32> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_pmsgt_u32x2(int32x2_t a, int32x2_t b) {
return __riscv_pmsgt_u32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsgtu_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ugt <2 x i32> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsgtu_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ugt <2 x i32> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsgtu_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ugt <2 x i32> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_pmsgtu_u32x2(uint32x2_t a, uint32x2_t b) {
return __riscv_pmsgtu_u32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsge_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp sge <2 x i32> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsge_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp sge <2 x i32> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsge_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp sge <2 x i32> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_pmsge_u32x2(int32x2_t a, int32x2_t b) {
return __riscv_pmsge_u32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsgeu_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp uge <2 x i32> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsgeu_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp uge <2 x i32> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsgeu_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp uge <2 x i32> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_pmsgeu_u32x2(uint32x2_t a, uint32x2_t b) {
return __riscv_pmsgeu_u32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsle_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp sle <2 x i32> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsle_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp sle <2 x i32> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsle_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp sle <2 x i32> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_pmsle_u32x2(int32x2_t a, int32x2_t b) {
return __riscv_pmsle_u32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pmsleu_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV32-NEXT: [[CMP_I:%.*]] = icmp ule <2 x i32> [[TMP0]], [[TMP1]]
-// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmsleu_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
-// RV64-NEXT: [[CMP_I:%.*]] = icmp ule <2 x i32> [[TMP0]], [[TMP1]]
-// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pmsleu_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule <2 x i32> [[TMP0]], [[TMP1]]
+// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_pmsleu_u32x2(uint32x2_t a, uint32x2_t b) {
return __riscv_pmsleu_u32x2(a, b);
@@ -4726,273 +3150,169 @@ uint32x2_t test_psshlr_s_u32x2(uint32x2_t a, int shamt) {
/* Packed Logical Operations (32-bit) */
-// RV32-LABEL: define dso_local i32 @test_pand_i8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[AND_I1:%.*]] = and i32 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i32 [[AND_I1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pand_i8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[AND_I1:%.*]] = and i32 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i32 [[AND_I1]]
+// CHECK-LABEL: define dso_local i32 @test_pand_i8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[AND_I1:%.*]] = and i32 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i32 [[AND_I1]]
//
int8x4_t test_pand_i8x4(int8x4_t a, int8x4_t b) {
return __riscv_pand_i8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pand_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[AND_I1:%.*]] = and i32 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i32 [[AND_I1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pand_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[AND_I1:%.*]] = and i32 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i32 [[AND_I1]]
+// CHECK-LABEL: define dso_local i32 @test_pand_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[AND_I1:%.*]] = and i32 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i32 [[AND_I1]]
//
uint8x4_t test_pand_u8x4(uint8x4_t a, uint8x4_t b) {
return __riscv_pand_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pand_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[AND_I1:%.*]] = and i32 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i32 [[AND_I1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pand_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[AND_I1:%.*]] = and i32 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i32 [[AND_I1]]
+// CHECK-LABEL: define dso_local i32 @test_pand_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[AND_I1:%.*]] = and i32 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i32 [[AND_I1]]
//
int16x2_t test_pand_i16x2(int16x2_t a, int16x2_t b) {
return __riscv_pand_i16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pand_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[AND_I1:%.*]] = and i32 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i32 [[AND_I1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pand_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[AND_I1:%.*]] = and i32 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i32 [[AND_I1]]
+// CHECK-LABEL: define dso_local i32 @test_pand_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[AND_I1:%.*]] = and i32 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i32 [[AND_I1]]
//
uint16x2_t test_pand_u16x2(uint16x2_t a, uint16x2_t b) {
return __riscv_pand_u16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_por_i8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[OR_I1:%.*]] = or i32 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i32 [[OR_I1]]
-//
-// RV64-LABEL: define dso_local i32 @test_por_i8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[OR_I1:%.*]] = or i32 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i32 [[OR_I1]]
+// CHECK-LABEL: define dso_local i32 @test_por_i8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[OR_I1:%.*]] = or i32 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i32 [[OR_I1]]
//
int8x4_t test_por_i8x4(int8x4_t a, int8x4_t b) {
return __riscv_por_i8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_por_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[OR_I1:%.*]] = or i32 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i32 [[OR_I1]]
-//
-// RV64-LABEL: define dso_local i32 @test_por_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[OR_I1:%.*]] = or i32 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i32 [[OR_I1]]
+// CHECK-LABEL: define dso_local i32 @test_por_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[OR_I1:%.*]] = or i32 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i32 [[OR_I1]]
//
uint8x4_t test_por_u8x4(uint8x4_t a, uint8x4_t b) {
return __riscv_por_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_por_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[OR_I1:%.*]] = or i32 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i32 [[OR_I1]]
-//
-// RV64-LABEL: define dso_local i32 @test_por_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[OR_I1:%.*]] = or i32 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i32 [[OR_I1]]
+// CHECK-LABEL: define dso_local i32 @test_por_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[OR_I1:%.*]] = or i32 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i32 [[OR_I1]]
//
int16x2_t test_por_i16x2(int16x2_t a, int16x2_t b) {
return __riscv_por_i16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_por_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[OR_I1:%.*]] = or i32 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i32 [[OR_I1]]
-//
-// RV64-LABEL: define dso_local i32 @test_por_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[OR_I1:%.*]] = or i32 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i32 [[OR_I1]]
+// CHECK-LABEL: define dso_local i32 @test_por_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[OR_I1:%.*]] = or i32 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i32 [[OR_I1]]
//
uint16x2_t test_por_u16x2(uint16x2_t a, uint16x2_t b) {
return __riscv_por_u16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pxor_i8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[XOR_I1:%.*]] = xor i32 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i32 [[XOR_I1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pxor_i8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[XOR_I1:%.*]] = xor i32 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i32 [[XOR_I1]]
+// CHECK-LABEL: define dso_local i32 @test_pxor_i8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[XOR_I1:%.*]] = xor i32 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i32 [[XOR_I1]]
//
int8x4_t test_pxor_i8x4(int8x4_t a, int8x4_t b) {
return __riscv_pxor_i8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pxor_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[XOR_I1:%.*]] = xor i32 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i32 [[XOR_I1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pxor_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[XOR_I1:%.*]] = xor i32 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i32 [[XOR_I1]]
+// CHECK-LABEL: define dso_local i32 @test_pxor_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[XOR_I1:%.*]] = xor i32 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i32 [[XOR_I1]]
//
uint8x4_t test_pxor_u8x4(uint8x4_t a, uint8x4_t b) {
return __riscv_pxor_u8x4(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pxor_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[XOR_I1:%.*]] = xor i32 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i32 [[XOR_I1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pxor_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[XOR_I1:%.*]] = xor i32 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i32 [[XOR_I1]]
+// CHECK-LABEL: define dso_local i32 @test_pxor_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[XOR_I1:%.*]] = xor i32 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i32 [[XOR_I1]]
//
int16x2_t test_pxor_i16x2(int16x2_t a, int16x2_t b) {
return __riscv_pxor_i16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pxor_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[XOR_I1:%.*]] = xor i32 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i32 [[XOR_I1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pxor_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[XOR_I1:%.*]] = xor i32 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i32 [[XOR_I1]]
+// CHECK-LABEL: define dso_local i32 @test_pxor_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[XOR_I1:%.*]] = xor i32 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i32 [[XOR_I1]]
//
uint16x2_t test_pxor_u16x2(uint16x2_t a, uint16x2_t b) {
return __riscv_pxor_u16x2(a, b);
}
-// RV32-LABEL: define dso_local i32 @test_pnot_i8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[NOT_I:%.*]] = xor <4 x i8> [[TMP0]], splat (i8 -1)
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[NOT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pnot_i8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[NOT_I:%.*]] = xor <4 x i8> [[TMP0]], splat (i8 -1)
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[NOT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_pnot_i8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[NOT_I:%.*]] = xor <4 x i8> [[TMP0]], splat (i8 -1)
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[NOT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
int8x4_t test_pnot_i8x4(int8x4_t a) {
return __riscv_pnot_i8x4(a);
}
-// RV32-LABEL: define dso_local i32 @test_pnot_u8x4(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[NOT_I:%.*]] = xor <4 x i8> [[TMP0]], splat (i8 -1)
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[NOT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pnot_u8x4(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[NOT_I:%.*]] = xor <4 x i8> [[TMP0]], splat (i8 -1)
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[NOT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_pnot_u8x4(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[NOT_I:%.*]] = xor <4 x i8> [[TMP0]], splat (i8 -1)
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[NOT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
uint8x4_t test_pnot_u8x4(uint8x4_t a) {
return __riscv_pnot_u8x4(a);
}
-// RV32-LABEL: define dso_local i32 @test_pnot_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[NOT_I:%.*]] = xor <2 x i16> [[TMP0]], splat (i16 -1)
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[NOT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pnot_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[NOT_I:%.*]] = xor <2 x i16> [[TMP0]], splat (i16 -1)
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[NOT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_pnot_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[NOT_I:%.*]] = xor <2 x i16> [[TMP0]], splat (i16 -1)
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[NOT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
int16x2_t test_pnot_i16x2(int16x2_t a) {
return __riscv_pnot_i16x2(a);
}
-// RV32-LABEL: define dso_local i32 @test_pnot_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[NOT_I:%.*]] = xor <2 x i16> [[TMP0]], splat (i16 -1)
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[NOT_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pnot_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[NOT_I:%.*]] = xor <2 x i16> [[TMP0]], splat (i16 -1)
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[NOT_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_pnot_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[NOT_I:%.*]] = xor <2 x i16> [[TMP0]], splat (i16 -1)
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[NOT_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
uint16x2_t test_pnot_u16x2(uint16x2_t a) {
return __riscv_pnot_u16x2(a);
@@ -5000,1109 +3320,669 @@ uint16x2_t test_pnot_u16x2(uint16x2_t a) {
/* Packed Logical Operations (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_pand_i8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i64 [[AND_I1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pand_i8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i64 [[AND_I1]]
+// CHECK-LABEL: define dso_local i64 @test_pand_i8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i64 [[AND_I1]]
//
int8x8_t test_pand_i8x8(int8x8_t a, int8x8_t b) {
return __riscv_pand_i8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pand_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i64 [[AND_I1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pand_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i64 [[AND_I1]]
+// CHECK-LABEL: define dso_local i64 @test_pand_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i64 [[AND_I1]]
//
uint8x8_t test_pand_u8x8(uint8x8_t a, uint8x8_t b) {
return __riscv_pand_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pand_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i64 [[AND_I1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pand_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i64 [[AND_I1]]
+// CHECK-LABEL: define dso_local i64 @test_pand_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i64 [[AND_I1]]
//
int16x4_t test_pand_i16x4(int16x4_t a, int16x4_t b) {
return __riscv_pand_i16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pand_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i64 [[AND_I1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pand_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i64 [[AND_I1]]
+// CHECK-LABEL: define dso_local i64 @test_pand_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i64 [[AND_I1]]
//
uint16x4_t test_pand_u16x4(uint16x4_t a, uint16x4_t b) {
return __riscv_pand_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pand_i32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i64 [[AND_I1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pand_i32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i64 [[AND_I1]]
+// CHECK-LABEL: define dso_local i64 @test_pand_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i64 [[AND_I1]]
//
int32x2_t test_pand_i32x2(int32x2_t a, int32x2_t b) {
return __riscv_pand_i32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pand_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i64 [[AND_I1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pand_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i64 [[AND_I1]]
+// CHECK-LABEL: define dso_local i64 @test_pand_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i64 [[AND_I1]]
//
uint32x2_t test_pand_u32x2(uint32x2_t a, uint32x2_t b) {
return __riscv_pand_u32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_por_i8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i64 [[OR_I1]]
-//
-// RV64-LABEL: define dso_local i64 @test_por_i8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i64 [[OR_I1]]
+// CHECK-LABEL: define dso_local i64 @test_por_i8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i64 [[OR_I1]]
//
int8x8_t test_por_i8x8(int8x8_t a, int8x8_t b) {
return __riscv_por_i8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_por_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i64 [[OR_I1]]
-//
-// RV64-LABEL: define dso_local i64 @test_por_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i64 [[OR_I1]]
+// CHECK-LABEL: define dso_local i64 @test_por_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i64 [[OR_I1]]
//
uint8x8_t test_por_u8x8(uint8x8_t a, uint8x8_t b) {
return __riscv_por_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_por_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i64 [[OR_I1]]
-//
-// RV64-LABEL: define dso_local i64 @test_por_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i64 [[OR_I1]]
+// CHECK-LABEL: define dso_local i64 @test_por_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i64 [[OR_I1]]
//
int16x4_t test_por_i16x4(int16x4_t a, int16x4_t b) {
return __riscv_por_i16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_por_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i64 [[OR_I1]]
-//
-// RV64-LABEL: define dso_local i64 @test_por_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i64 [[OR_I1]]
+// CHECK-LABEL: define dso_local i64 @test_por_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i64 [[OR_I1]]
//
uint16x4_t test_por_u16x4(uint16x4_t a, uint16x4_t b) {
return __riscv_por_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_por_i32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i64 [[OR_I1]]
-//
-// RV64-LABEL: define dso_local i64 @test_por_i32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i64 [[OR_I1]]
+// CHECK-LABEL: define dso_local i64 @test_por_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i64 [[OR_I1]]
//
int32x2_t test_por_i32x2(int32x2_t a, int32x2_t b) {
return __riscv_por_i32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_por_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i64 [[OR_I1]]
-//
-// RV64-LABEL: define dso_local i64 @test_por_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i64 [[OR_I1]]
+// CHECK-LABEL: define dso_local i64 @test_por_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i64 [[OR_I1]]
//
uint32x2_t test_por_u32x2(uint32x2_t a, uint32x2_t b) {
return __riscv_por_u32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pxor_i8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i64 [[XOR_I1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pxor_i8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i64 [[XOR_I1]]
+// CHECK-LABEL: define dso_local i64 @test_pxor_i8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i64 [[XOR_I1]]
//
int8x8_t test_pxor_i8x8(int8x8_t a, int8x8_t b) {
return __riscv_pxor_i8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pxor_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i64 [[XOR_I1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pxor_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i64 [[XOR_I1]]
+// CHECK-LABEL: define dso_local i64 @test_pxor_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i64 [[XOR_I1]]
//
uint8x8_t test_pxor_u8x8(uint8x8_t a, uint8x8_t b) {
return __riscv_pxor_u8x8(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pxor_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i64 [[XOR_I1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pxor_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i64 [[XOR_I1]]
+// CHECK-LABEL: define dso_local i64 @test_pxor_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i64 [[XOR_I1]]
//
int16x4_t test_pxor_i16x4(int16x4_t a, int16x4_t b) {
return __riscv_pxor_i16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pxor_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i64 [[XOR_I1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pxor_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i64 [[XOR_I1]]
+// CHECK-LABEL: define dso_local i64 @test_pxor_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i64 [[XOR_I1]]
//
uint16x4_t test_pxor_u16x4(uint16x4_t a, uint16x4_t b) {
return __riscv_pxor_u16x4(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pxor_i32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i64 [[XOR_I1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pxor_i32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i64 [[XOR_I1]]
+// CHECK-LABEL: define dso_local i64 @test_pxor_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i64 [[XOR_I1]]
//
int32x2_t test_pxor_i32x2(int32x2_t a, int32x2_t b) {
return __riscv_pxor_i32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pxor_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
-// RV32-NEXT: ret i64 [[XOR_I1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pxor_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
-// RV64-NEXT: ret i64 [[XOR_I1]]
+// CHECK-LABEL: define dso_local i64 @test_pxor_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
+// CHECK-NEXT: ret i64 [[XOR_I1]]
//
uint32x2_t test_pxor_u32x2(uint32x2_t a, uint32x2_t b) {
return __riscv_pxor_u32x2(a, b);
}
-// RV32-LABEL: define dso_local i64 @test_pnot_i8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[NOT_I:%.*]] = xor <8 x i8> [[TMP0]], splat (i8 -1)
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[NOT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pnot_i8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[NOT_I:%.*]] = xor <8 x i8> [[TMP0]], splat (i8 -1)
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[NOT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pnot_i8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[NOT_I:%.*]] = xor <8 x i8> [[TMP0]], splat (i8 -1)
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[NOT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
int8x8_t test_pnot_i8x8(int8x8_t a) {
return __riscv_pnot_i8x8(a);
}
-// RV32-LABEL: define dso_local i64 @test_pnot_u8x8(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV32-NEXT: [[NOT_I:%.*]] = xor <8 x i8> [[TMP0]], splat (i8 -1)
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[NOT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pnot_u8x8(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
-// RV64-NEXT: [[NOT_I:%.*]] = xor <8 x i8> [[TMP0]], splat (i8 -1)
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[NOT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pnot_u8x8(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[NOT_I:%.*]] = xor <8 x i8> [[TMP0]], splat (i8 -1)
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[NOT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
uint8x8_t test_pnot_u8x8(uint8x8_t a) {
return __riscv_pnot_u8x8(a);
}
-// RV32-LABEL: define dso_local i64 @test_pnot_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[NOT_I:%.*]] = xor <4 x i16> [[TMP0]], splat (i16 -1)
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[NOT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pnot_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[NOT_I:%.*]] = xor <4 x i16> [[TMP0]], splat (i16 -1)
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[NOT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pnot_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[NOT_I:%.*]] = xor <4 x i16> [[TMP0]], splat (i16 -1)
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[NOT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
int16x4_t test_pnot_i16x4(int16x4_t a) {
return __riscv_pnot_i16x4(a);
}
-// RV32-LABEL: define dso_local i64 @test_pnot_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[NOT_I:%.*]] = xor <4 x i16> [[TMP0]], splat (i16 -1)
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[NOT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pnot_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[NOT_I:%.*]] = xor <4 x i16> [[TMP0]], splat (i16 -1)
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[NOT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pnot_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[NOT_I:%.*]] = xor <4 x i16> [[TMP0]], splat (i16 -1)
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[NOT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
uint16x4_t test_pnot_u16x4(uint16x4_t a) {
return __riscv_pnot_u16x4(a);
}
-// RV32-LABEL: define dso_local i64 @test_pnot_i32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[NOT_I:%.*]] = xor <2 x i32> [[TMP0]], splat (i32 -1)
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[NOT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pnot_i32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[NOT_I:%.*]] = xor <2 x i32> [[TMP0]], splat (i32 -1)
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[NOT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pnot_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[NOT_I:%.*]] = xor <2 x i32> [[TMP0]], splat (i32 -1)
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[NOT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
int32x2_t test_pnot_i32x2(int32x2_t a) {
return __riscv_pnot_i32x2(a);
}
-// RV32-LABEL: define dso_local i64 @test_pnot_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[NOT_I:%.*]] = xor <2 x i32> [[TMP0]], splat (i32 -1)
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[NOT_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pnot_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[NOT_I:%.*]] = xor <2 x i32> [[TMP0]], splat (i32 -1)
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[NOT_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pnot_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[NOT_I:%.*]] = xor <2 x i32> [[TMP0]], splat (i32 -1)
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[NOT_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
uint32x2_t test_pnot_u32x2(uint32x2_t a) {
return __riscv_pnot_u32x2(a);
}
-// RV32-LABEL: define dso_local i32 @test_paadd_i8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.paadd.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_paadd_i8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.paadd.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_paadd_i8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.paadd.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
int8x4_t test_paadd_i8x4(int8x4_t rs1, int8x4_t rs2) {
return __riscv_paadd_i8x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_paadd_i16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.paadd.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_paadd_i16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.paadd.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_paadd_i16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.paadd.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
int16x2_t test_paadd_i16x2(int16x2_t rs1, int16x2_t rs2) {
return __riscv_paadd_i16x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_paaddu_u8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.paaddu.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_paaddu_u8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.paaddu.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_paaddu_u8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.paaddu.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
uint8x4_t test_paaddu_u8x4(uint8x4_t rs1, uint8x4_t rs2) {
return __riscv_paaddu_u8x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_paaddu_u16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.paaddu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_paaddu_u16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.paaddu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_paaddu_u16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.paaddu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
uint16x2_t test_paaddu_u16x2(uint16x2_t rs1, uint16x2_t rs2) {
return __riscv_paaddu_u16x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_pasub_i8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pasub.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_pasub_i8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pasub.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_pasub_i8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pasub.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
int8x4_t test_pasub_i8x4(int8x4_t rs1, int8x4_t rs2) {
return __riscv_pasub_i8x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_pasub_i16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pasub.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_pasub_i16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pasub.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_pasub_i16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pasub.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
int16x2_t test_pasub_i16x2(int16x2_t rs1, int16x2_t rs2) {
return __riscv_pasub_i16x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_pasubu_u8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pasubu.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_pasubu_u8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pasubu.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_pasubu_u8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pasubu.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
uint8x4_t test_pasubu_u8x4(uint8x4_t rs1, uint8x4_t rs2) {
return __riscv_pasubu_u8x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_pasubu_u16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pasubu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_pasubu_u16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pasubu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_pasubu_u16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pasubu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
uint16x2_t test_pasubu_u16x2(uint16x2_t rs1, uint16x2_t rs2) {
return __riscv_pasubu_u16x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_paadd_i8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.paadd.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_paadd_i8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.paadd.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_paadd_i8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.paadd.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int8x8_t test_paadd_i8x8(int8x8_t rs1, int8x8_t rs2) {
return __riscv_paadd_i8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_paadd_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.paadd.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_paadd_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.paadd.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_paadd_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.paadd.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int16x4_t test_paadd_i16x4(int16x4_t rs1, int16x4_t rs2) {
return __riscv_paadd_i16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_paadd_i32x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.paadd.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_paadd_i32x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.paadd.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_paadd_i32x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.paadd.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int32x2_t test_paadd_i32x2(int32x2_t rs1, int32x2_t rs2) {
return __riscv_paadd_i32x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_paaddu_u8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.paaddu.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_paaddu_u8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.paaddu.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_paaddu_u8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.paaddu.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
uint8x8_t test_paaddu_u8x8(uint8x8_t rs1, uint8x8_t rs2) {
return __riscv_paaddu_u8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_paaddu_u16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.paaddu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_paaddu_u16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.paaddu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_paaddu_u16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.paaddu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
uint16x4_t test_paaddu_u16x4(uint16x4_t rs1, uint16x4_t rs2) {
return __riscv_paaddu_u16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_paaddu_u32x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.paaddu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_paaddu_u32x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.paaddu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_paaddu_u32x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.paaddu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
uint32x2_t test_paaddu_u32x2(uint32x2_t rs1, uint32x2_t rs2) {
return __riscv_paaddu_u32x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pasub_i8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pasub.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pasub_i8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pasub.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pasub_i8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pasub.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int8x8_t test_pasub_i8x8(int8x8_t rs1, int8x8_t rs2) {
return __riscv_pasub_i8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pasub_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pasub.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pasub_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pasub.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pasub_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pasub.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int16x4_t test_pasub_i16x4(int16x4_t rs1, int16x4_t rs2) {
return __riscv_pasub_i16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pasub_i32x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pasub.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pasub_i32x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pasub.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pasub_i32x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pasub.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int32x2_t test_pasub_i32x2(int32x2_t rs1, int32x2_t rs2) {
return __riscv_pasub_i32x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pasubu_u8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pasubu.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pasubu_u8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pasubu.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pasubu_u8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pasubu.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
uint8x8_t test_pasubu_u8x8(uint8x8_t rs1, uint8x8_t rs2) {
return __riscv_pasubu_u8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pasubu_u16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pasubu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pasubu_u16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pasubu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pasubu_u16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pasubu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
uint16x4_t test_pasubu_u16x4(uint16x4_t rs1, uint16x4_t rs2) {
return __riscv_pasubu_u16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pasubu_u32x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pasubu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pasubu_u32x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pasubu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pasubu_u32x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pasubu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
uint32x2_t test_pasubu_u32x2(uint32x2_t rs1, uint32x2_t rs2) {
return __riscv_pasubu_u32x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_pabs_i8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[ELT_ABS_I:%.*]] = call <4 x i8> @llvm.abs.v4i8(<4 x i8> [[TMP0]], i1 false)
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[ELT_ABS_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pabs_i8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[ELT_ABS_I:%.*]] = call <4 x i8> @llvm.abs.v4i8(<4 x i8> [[TMP0]], i1 false)
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[ELT_ABS_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_pabs_i8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[ELT_ABS_I:%.*]] = call <4 x i8> @llvm.abs.v4i8(<4 x i8> [[TMP0]], i1 false)
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[ELT_ABS_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
uint8x4_t test_pabs_i8x4(int8x4_t rs1) {
return __riscv_pabs_i8x4(rs1);
}
-// RV32-LABEL: define dso_local i32 @test_pabs_i16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[ELT_ABS_I:%.*]] = call <2 x i16> @llvm.abs.v2i16(<2 x i16> [[TMP0]], i1 false)
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[ELT_ABS_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pabs_i16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[ELT_ABS_I:%.*]] = call <2 x i16> @llvm.abs.v2i16(<2 x i16> [[TMP0]], i1 false)
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[ELT_ABS_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_pabs_i16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[ELT_ABS_I:%.*]] = call <2 x i16> @llvm.abs.v2i16(<2 x i16> [[TMP0]], i1 false)
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[ELT_ABS_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
uint16x2_t test_pabs_i16x2(int16x2_t rs1) {
return __riscv_pabs_i16x2(rs1);
}
-// RV32-LABEL: define dso_local i32 @test_pabd_i8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pabd.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_pabd_i8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pabd.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_pabd_i8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pabd.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
uint8x4_t test_pabd_i8x4(int8x4_t rs1, int8x4_t rs2) {
return __riscv_pabd_i8x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_pabd_i16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pabd.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_pabd_i16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pabd.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_pabd_i16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pabd.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
uint16x2_t test_pabd_i16x2(int16x2_t rs1, int16x2_t rs2) {
return __riscv_pabd_i16x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_pabdu_u8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pabdu.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_pabdu_u8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pabdu.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_pabdu_u8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pabdu.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
uint8x4_t test_pabdu_u8x4(uint8x4_t rs1, uint8x4_t rs2) {
return __riscv_pabdu_u8x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_pabdu_u16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pabdu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_pabdu_u16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pabdu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_pabdu_u16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pabdu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
uint16x2_t test_pabdu_u16x2(uint16x2_t rs1, uint16x2_t rs2) {
return __riscv_pabdu_u16x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pabs_i8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[ELT_ABS_I:%.*]] = call <8 x i8> @llvm.abs.v8i8(<8 x i8> [[TMP0]], i1 false)
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[ELT_ABS_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pabs_i8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[ELT_ABS_I:%.*]] = call <8 x i8> @llvm.abs.v8i8(<8 x i8> [[TMP0]], i1 false)
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[ELT_ABS_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pabs_i8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[ELT_ABS_I:%.*]] = call <8 x i8> @llvm.abs.v8i8(<8 x i8> [[TMP0]], i1 false)
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[ELT_ABS_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
uint8x8_t test_pabs_i8x8(int8x8_t rs1) {
return __riscv_pabs_i8x8(rs1);
}
-// RV32-LABEL: define dso_local i64 @test_pabs_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[ELT_ABS_I:%.*]] = call <4 x i16> @llvm.abs.v4i16(<4 x i16> [[TMP0]], i1 false)
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[ELT_ABS_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pabs_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[ELT_ABS_I:%.*]] = call <4 x i16> @llvm.abs.v4i16(<4 x i16> [[TMP0]], i1 false)
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[ELT_ABS_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pabs_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[ELT_ABS_I:%.*]] = call <4 x i16> @llvm.abs.v4i16(<4 x i16> [[TMP0]], i1 false)
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[ELT_ABS_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
uint16x4_t test_pabs_i16x4(int16x4_t rs1) {
return __riscv_pabs_i16x4(rs1);
}
-// RV32-LABEL: define dso_local i64 @test_pabd_i8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pabd.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pabd_i8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pabd.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pabd_i8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pabd.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
uint8x8_t test_pabd_i8x8(int8x8_t rs1, int8x8_t rs2) {
return __riscv_pabd_i8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pabd_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pabd.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pabd_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pabd.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pabd_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pabd.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
uint16x4_t test_pabd_i16x4(int16x4_t rs1, int16x4_t rs2) {
return __riscv_pabd_i16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pabdu_u8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pabdu.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pabdu_u8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pabdu.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pabdu_u8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pabdu.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
uint8x8_t test_pabdu_u8x8(uint8x8_t rs1, uint8x8_t rs2) {
return __riscv_pabdu_u8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pabdu_u16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pabdu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pabdu_u16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pabdu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pabdu_u16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pabdu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
uint16x4_t test_pabdu_u16x4(uint16x4_t rs1, uint16x4_t rs2) {
return __riscv_pabdu_u16x4(rs1, rs2);
@@ -6254,109 +4134,67 @@ uint32_t test_predsumu_u16x4_u32(uint16x4_t rs1, uint32_t rs2) {
return __riscv_predsumu_u16x4_u32(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_predsum_i8x8_i64(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsum.i64.v8i8(<8 x i8> [[TMP0]], i64 [[RS2]])
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_predsum_i8x8_i64(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsum.i64.v8i8(<8 x i8> [[TMP0]], i64 [[RS2]])
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_predsum_i8x8_i64(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsum.i64.v8i8(<8 x i8> [[TMP0]], i64 [[RS2]])
+// CHECK-NEXT: ret i64 [[TMP1]]
//
int64_t test_predsum_i8x8_i64(int8x8_t rs1, int64_t rs2) {
return __riscv_predsum_i8x8_i64(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_predsumu_u8x8_u64(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsumu.i64.v8i8(<8 x i8> [[TMP0]], i64 [[RS2]])
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_predsumu_u8x8_u64(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsumu.i64.v8i8(<8 x i8> [[TMP0]], i64 [[RS2]])
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_predsumu_u8x8_u64(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsumu.i64.v8i8(<8 x i8> [[TMP0]], i64 [[RS2]])
+// CHECK-NEXT: ret i64 [[TMP1]]
//
uint64_t test_predsumu_u8x8_u64(uint8x8_t rs1, uint64_t rs2) {
return __riscv_predsumu_u8x8_u64(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_predsum_i16x4_i64(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsum.i64.v4i16(<4 x i16> [[TMP0]], i64 [[RS2]])
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_predsum_i16x4_i64(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsum.i64.v4i16(<4 x i16> [[TMP0]], i64 [[RS2]])
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_predsum_i16x4_i64(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsum.i64.v4i16(<4 x i16> [[TMP0]], i64 [[RS2]])
+// CHECK-NEXT: ret i64 [[TMP1]]
//
int64_t test_predsum_i16x4_i64(int16x4_t rs1, int64_t rs2) {
return __riscv_predsum_i16x4_i64(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_predsumu_u16x4_u64(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsumu.i64.v4i16(<4 x i16> [[TMP0]], i64 [[RS2]])
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_predsumu_u16x4_u64(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsumu.i64.v4i16(<4 x i16> [[TMP0]], i64 [[RS2]])
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_predsumu_u16x4_u64(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsumu.i64.v4i16(<4 x i16> [[TMP0]], i64 [[RS2]])
+// CHECK-NEXT: ret i64 [[TMP1]]
//
uint64_t test_predsumu_u16x4_u64(uint16x4_t rs1, uint64_t rs2) {
return __riscv_predsumu_u16x4_u64(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_predsum_i32x2_i64(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsum.i64.v2i32(<2 x i32> [[TMP0]], i64 [[RS2]])
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_predsum_i32x2_i64(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsum.i64.v2i32(<2 x i32> [[TMP0]], i64 [[RS2]])
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_predsum_i32x2_i64(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsum.i64.v2i32(<2 x i32> [[TMP0]], i64 [[RS2]])
+// CHECK-NEXT: ret i64 [[TMP1]]
//
int64_t test_predsum_i32x2_i64(int32x2_t rs1, int64_t rs2) {
return __riscv_predsum_i32x2_i64(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_predsumu_u32x2_u64(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsumu.i64.v2i32(<2 x i32> [[TMP0]], i64 [[RS2]])
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_predsumu_u32x2_u64(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsumu.i64.v2i32(<2 x i32> [[TMP0]], i64 [[RS2]])
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_predsumu_u32x2_u64(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsumu.i64.v2i32(<2 x i32> [[TMP0]], i64 [[RS2]])
+// CHECK-NEXT: ret i64 [[TMP1]]
//
uint64_t test_predsumu_u32x2_u64(uint32x2_t rs1, uint64_t rs2) {
return __riscv_predsumu_u32x2_u64(rs1, rs2);
@@ -6364,97 +4202,57 @@ uint64_t test_predsumu_u32x2_u64(uint32x2_t rs1, uint64_t rs2) {
// Packed Merge (32-bit)
-// RV32-LABEL: define dso_local i32 @test_pmerge_u8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]], i32 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP3:%.*]] = call <4 x i8> @llvm.riscv.pmerge.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i8> [[TMP2]])
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[TMP3]] to i32
-// RV32-NEXT: ret i32 [[TMP4]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmerge_u8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]], i32 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP3:%.*]] = call <4 x i8> @llvm.riscv.pmerge.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i8> [[TMP2]])
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[TMP3]] to i32
-// RV64-NEXT: ret i32 [[TMP4]]
+// CHECK-LABEL: define dso_local i32 @test_pmerge_u8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]], i32 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i8> @llvm.riscv.pmerge.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i8> [[TMP2]])
+// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[TMP3]] to i32
+// CHECK-NEXT: ret i32 [[TMP4]]
//
uint8x4_t test_pmerge_u8x4(uint8x4_t rs1, uint8x4_t rs2, uint8x4_t rd) {
return __riscv_pmerge_u8x4(rs1, rs2, rd);
}
-// RV32-LABEL: define dso_local i32 @test_pmerge_i8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]], i32 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP3:%.*]] = call <4 x i8> @llvm.riscv.pmerge.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i8> [[TMP2]])
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[TMP3]] to i32
-// RV32-NEXT: ret i32 [[TMP4]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmerge_i8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]], i32 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP3:%.*]] = call <4 x i8> @llvm.riscv.pmerge.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i8> [[TMP2]])
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[TMP3]] to i32
-// RV64-NEXT: ret i32 [[TMP4]]
+// CHECK-LABEL: define dso_local i32 @test_pmerge_i8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]], i32 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i8> @llvm.riscv.pmerge.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i8> [[TMP2]])
+// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[TMP3]] to i32
+// CHECK-NEXT: ret i32 [[TMP4]]
//
int8x4_t test_pmerge_i8x4(int8x4_t rs1, int8x4_t rs2, uint8x4_t rd) {
return __riscv_pmerge_i8x4(rs1, rs2, rd);
}
-// RV32-LABEL: define dso_local i32 @test_pmerge_u16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]], i32 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmerge.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i16> [[TMP2]])
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32
-// RV32-NEXT: ret i32 [[TMP4]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmerge_u16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]], i32 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmerge.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i16> [[TMP2]])
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32
-// RV64-NEXT: ret i32 [[TMP4]]
+// CHECK-LABEL: define dso_local i32 @test_pmerge_u16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]], i32 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmerge.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i16> [[TMP2]])
+// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32
+// CHECK-NEXT: ret i32 [[TMP4]]
//
uint16x2_t test_pmerge_u16x2(uint16x2_t rs1, uint16x2_t rs2, uint16x2_t rd) {
return __riscv_pmerge_u16x2(rs1, rs2, rd);
}
-// RV32-LABEL: define dso_local i32 @test_pmerge_i16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]], i32 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmerge.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i16> [[TMP2]])
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32
-// RV32-NEXT: ret i32 [[TMP4]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmerge_i16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]], i32 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmerge.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i16> [[TMP2]])
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32
-// RV64-NEXT: ret i32 [[TMP4]]
+// CHECK-LABEL: define dso_local i32 @test_pmerge_i16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]], i32 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmerge.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i16> [[TMP2]])
+// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32
+// CHECK-NEXT: ret i32 [[TMP4]]
//
int16x2_t test_pmerge_i16x2(int16x2_t rs1, int16x2_t rs2, uint16x2_t rd) {
return __riscv_pmerge_i16x2(rs1, rs2, rd);
@@ -6462,217 +4260,129 @@ int16x2_t test_pmerge_i16x2(int16x2_t rs1, int16x2_t rs2, uint16x2_t rd) {
// Packed Merge (64-bit)
-// RV32-LABEL: define dso_local i64 @test_pmerge_u8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.riscv.pmerge.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]])
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to i64
-// RV32-NEXT: ret i64 [[TMP4]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmerge_u8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.riscv.pmerge.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]])
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to i64
-// RV64-NEXT: ret i64 [[TMP4]]
+// CHECK-LABEL: define dso_local i64 @test_pmerge_u8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.riscv.pmerge.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]])
+// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to i64
+// CHECK-NEXT: ret i64 [[TMP4]]
//
uint8x8_t test_pmerge_u8x8(uint8x8_t rs1, uint8x8_t rs2, uint8x8_t rd) {
return __riscv_pmerge_u8x8(rs1, rs2, rd);
}
-// RV32-LABEL: define dso_local i64 @test_pmerge_i8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.riscv.pmerge.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]])
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to i64
-// RV32-NEXT: ret i64 [[TMP4]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmerge_i8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.riscv.pmerge.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]])
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to i64
-// RV64-NEXT: ret i64 [[TMP4]]
+// CHECK-LABEL: define dso_local i64 @test_pmerge_i8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.riscv.pmerge.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]])
+// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to i64
+// CHECK-NEXT: ret i64 [[TMP4]]
//
int8x8_t test_pmerge_i8x8(int8x8_t rs1, int8x8_t rs2, uint8x8_t rd) {
return __riscv_pmerge_i8x8(rs1, rs2, rd);
}
-// RV32-LABEL: define dso_local i64 @test_pmerge_u16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmerge.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
-// RV32-NEXT: ret i64 [[TMP4]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmerge_u16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmerge.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
-// RV64-NEXT: ret i64 [[TMP4]]
+// CHECK-LABEL: define dso_local i64 @test_pmerge_u16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmerge.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
+// CHECK-NEXT: ret i64 [[TMP4]]
//
uint16x4_t test_pmerge_u16x4(uint16x4_t rs1, uint16x4_t rs2, uint16x4_t rd) {
return __riscv_pmerge_u16x4(rs1, rs2, rd);
}
-// RV32-LABEL: define dso_local i64 @test_pmerge_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmerge.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
-// RV32-NEXT: ret i64 [[TMP4]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmerge_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmerge.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
-// RV64-NEXT: ret i64 [[TMP4]]
+// CHECK-LABEL: define dso_local i64 @test_pmerge_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmerge.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
+// CHECK-NEXT: ret i64 [[TMP4]]
//
int16x4_t test_pmerge_i16x4(int16x4_t rs1, int16x4_t rs2, uint16x4_t rd) {
return __riscv_pmerge_i16x4(rs1, rs2, rd);
}
-// RV32-LABEL: define dso_local i64 @test_pmerge_u32x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmerge.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]])
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
-// RV32-NEXT: ret i64 [[TMP4]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmerge_u32x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmerge.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]])
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
-// RV64-NEXT: ret i64 [[TMP4]]
+// CHECK-LABEL: define dso_local i64 @test_pmerge_u32x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmerge.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]])
+// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT: ret i64 [[TMP4]]
//
uint32x2_t test_pmerge_u32x2(uint32x2_t rs1, uint32x2_t rs2, uint32x2_t rd) {
return __riscv_pmerge_u32x2(rs1, rs2, rd);
}
-// RV32-LABEL: define dso_local i64 @test_pmerge_i32x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmerge.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]])
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
-// RV32-NEXT: ret i64 [[TMP4]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmerge_i32x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmerge.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]])
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
-// RV64-NEXT: ret i64 [[TMP4]]
+// CHECK-LABEL: define dso_local i64 @test_pmerge_i32x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmerge.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]])
+// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT: ret i64 [[TMP4]]
//
int32x2_t test_pmerge_i32x2(int32x2_t rs1, int32x2_t rs2, uint32x2_t rd) {
return __riscv_pmerge_i32x2(rs1, rs2, rd);
}
-// RV32-LABEL: define dso_local i32 @test_prev_i8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[RS1_COERCE]])
-// RV32-NEXT: ret i32 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i32 @test_prev_i8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[RS1_COERCE]])
-// RV64-NEXT: ret i32 [[TMP0]]
+// CHECK-LABEL: define dso_local i32 @test_prev_i8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[RS1_COERCE]])
+// CHECK-NEXT: ret i32 [[TMP0]]
//
int8x4_t test_prev_i8x4(int8x4_t rs1) {
return __riscv_prev_i8x4(rs1);
}
-// RV32-LABEL: define dso_local i32 @test_prev_u8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[RS1_COERCE]])
-// RV32-NEXT: ret i32 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i32 @test_prev_u8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[RS1_COERCE]])
-// RV64-NEXT: ret i32 [[TMP0]]
+// CHECK-LABEL: define dso_local i32 @test_prev_u8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[RS1_COERCE]])
+// CHECK-NEXT: ret i32 [[TMP0]]
//
uint8x4_t test_prev_u8x4(uint8x4_t rs1) {
return __riscv_prev_u8x4(rs1);
}
-// RV32-LABEL: define dso_local i32 @test_prev_i16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> poison, <2 x i32> <i32 1, i32 0>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_prev_i16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> poison, <2 x i32> <i32 1, i32 0>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_prev_i16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> poison, <2 x i32> <i32 1, i32 0>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
int16x2_t test_prev_i16x2(int16x2_t rs1) {
return __riscv_prev_i16x2(rs1);
}
-// RV32-LABEL: define dso_local i32 @test_prev_u16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> poison, <2 x i32> <i32 1, i32 0>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_prev_u16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> poison, <2 x i32> <i32 1, i32 0>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_prev_u16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> poison, <2 x i32> <i32 1, i32 0>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
uint16x2_t test_prev_u16x2(uint16x2_t rs1) {
return __riscv_prev_u16x2(rs1);
@@ -6714,331 +4424,199 @@ uint8x8_t test_prev_u8x8(uint8x8_t rs1) {
return __riscv_prev_u8x8(rs1);
}
-// RV32-LABEL: define dso_local i64 @test_prev_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_prev_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_prev_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
int16x4_t test_prev_i16x4(int16x4_t rs1) {
return __riscv_prev_i16x4(rs1);
}
-// RV32-LABEL: define dso_local i64 @test_prev_u16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_prev_u16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_prev_u16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
uint16x4_t test_prev_u16x4(uint16x4_t rs1) {
return __riscv_prev_u16x4(rs1);
}
-// RV32-LABEL: define dso_local i64 @test_prev_i32x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> <i32 1, i32 0>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_prev_i32x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> <i32 1, i32 0>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_prev_i32x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> <i32 1, i32 0>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
int32x2_t test_prev_i32x2(int32x2_t rs1) {
return __riscv_prev_i32x2(rs1);
}
-// RV32-LABEL: define dso_local i64 @test_prev_u32x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> <i32 1, i32 0>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_prev_u32x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> <i32 1, i32 0>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_prev_u32x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> <i32 1, i32 0>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
uint32x2_t test_prev_u32x2(uint32x2_t rs1) {
return __riscv_prev_u32x2(rs1);
}
/* Packed Zip */
-// RV32-LABEL: define dso_local i64 @test_pzip_i8x8(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pzip_i8x8(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pzip_i8x8(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int8x8_t test_pzip_i8x8(int8x4_t rs1, int8x4_t rs2) {
return __riscv_pzip_i8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pzip_u8x8(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pzip_u8x8(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pzip_u8x8(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_pzip_u8x8(uint8x4_t rs1, uint8x4_t rs2) {
return __riscv_pzip_u8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pzip_i16x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pzip_i16x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pzip_i16x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_pzip_i16x4(int16x2_t rs1, int16x2_t rs2) {
return __riscv_pzip_i16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pzip_u16x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pzip_u16x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pzip_u16x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pzip_u16x4(uint16x2_t rs1, uint16x2_t rs2) {
return __riscv_pzip_u16x4(rs1, rs2);
}
/* Packed Unzip */
-// RV32-LABEL: define dso_local i32 @test_punzipe_i8x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_punzipe_i8x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_punzipe_i8x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
int8x4_t test_punzipe_i8x4(int8x8_t rs1) {
return __riscv_punzipe_i8x4(rs1);
}
-// RV32-LABEL: define dso_local i32 @test_punzipo_i8x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_punzipo_i8x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_punzipo_i8x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
int8x4_t test_punzipo_i8x4(int8x8_t rs1) {
return __riscv_punzipo_i8x4(rs1);
}
-// RV32-LABEL: define dso_local i32 @test_punzipe_u8x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_punzipe_u8x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_punzipe_u8x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
uint8x4_t test_punzipe_u8x4(uint8x8_t rs1) {
return __riscv_punzipe_u8x4(rs1);
}
-// RV32-LABEL: define dso_local i32 @test_punzipo_u8x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_punzipo_u8x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_punzipo_u8x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
uint8x4_t test_punzipo_u8x4(uint8x8_t rs1) {
return __riscv_punzipo_u8x4(rs1);
}
-// RV32-LABEL: define dso_local i32 @test_punzipe_i16x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 0, i32 2>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_punzipe_i16x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 0, i32 2>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_punzipe_i16x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 0, i32 2>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
int16x2_t test_punzipe_i16x2(int16x4_t rs1) {
return __riscv_punzipe_i16x2(rs1);
}
-// RV32-LABEL: define dso_local i32 @test_punzipo_i16x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_punzipo_i16x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_punzipo_i16x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
int16x2_t test_punzipo_i16x2(int16x4_t rs1) {
return __riscv_punzipo_i16x2(rs1);
}
-// RV32-LABEL: define dso_local i32 @test_punzipe_u16x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 0, i32 2>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_punzipe_u16x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 0, i32 2>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_punzipe_u16x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 0, i32 2>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
uint16x2_t test_punzipe_u16x2(uint16x4_t rs1) {
return __riscv_punzipe_u16x2(rs1);
}
-// RV32-LABEL: define dso_local i32 @test_punzipo_u16x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_punzipo_u16x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_punzipo_u16x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
uint16x2_t test_punzipo_u16x2(uint16x4_t rs1) {
return __riscv_punzipo_u16x2(rs1);
@@ -7046,705 +4624,417 @@ uint16x2_t test_punzipo_u16x2(uint16x4_t rs1) {
/* Packed Pair */
-// RV32-LABEL: define dso_local i32 @test_ppaire_i8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_ppaire_i8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_ppaire_i8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int8x4_t test_ppaire_i8x4(int8x4_t rs1, int8x4_t rs2) {
return __riscv_ppaire_i8x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_ppaire_u8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_ppaire_u8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_ppaire_u8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_ppaire_u8x4(uint8x4_t rs1, uint8x4_t rs2) {
return __riscv_ppaire_u8x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_ppaireo_i8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_ppaireo_i8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_ppaireo_i8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int8x4_t test_ppaireo_i8x4(int8x4_t rs1, int8x4_t rs2) {
return __riscv_ppaireo_i8x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_ppaireo_u8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_ppaireo_u8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_ppaireo_u8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_ppaireo_u8x4(uint8x4_t rs1, uint8x4_t rs2) {
return __riscv_ppaireo_u8x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_ppairoe_i8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_ppairoe_i8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_ppairoe_i8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int8x4_t test_ppairoe_i8x4(int8x4_t rs1, int8x4_t rs2) {
return __riscv_ppairoe_i8x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_ppairoe_u8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_ppairoe_u8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_ppairoe_u8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_ppairoe_u8x4(uint8x4_t rs1, uint8x4_t rs2) {
return __riscv_ppairoe_u8x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_ppairo_i8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_ppairo_i8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_ppairo_i8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int8x4_t test_ppairo_i8x4(int8x4_t rs1, int8x4_t rs2) {
return __riscv_ppairo_i8x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_ppairo_u8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_ppairo_u8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_ppairo_u8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_ppairo_u8x4(uint8x4_t rs1, uint8x4_t rs2) {
return __riscv_ppairo_u8x4(rs1, rs2);
-}
-
-// RV32-LABEL: define dso_local i32 @test_ppaire_i16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 0, i32 2>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_ppaire_i16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 0, i32 2>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+}
+
+// CHECK-LABEL: define dso_local i32 @test_ppaire_i16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 0, i32 2>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int16x2_t test_ppaire_i16x2(int16x2_t rs1, int16x2_t rs2) {
return __riscv_ppaire_i16x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_ppaire_u16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 0, i32 2>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_ppaire_u16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 0, i32 2>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_ppaire_u16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 0, i32 2>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_ppaire_u16x2(uint16x2_t rs1, uint16x2_t rs2) {
return __riscv_ppaire_u16x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_ppaireo_i16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 0, i32 3>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_ppaireo_i16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 0, i32 3>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_ppaireo_i16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 0, i32 3>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int16x2_t test_ppaireo_i16x2(int16x2_t rs1, int16x2_t rs2) {
return __riscv_ppaireo_i16x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_ppaireo_u16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 0, i32 3>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_ppaireo_u16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 0, i32 3>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_ppaireo_u16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 0, i32 3>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_ppaireo_u16x2(uint16x2_t rs1, uint16x2_t rs2) {
return __riscv_ppaireo_u16x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_ppairoe_i16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 1, i32 2>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_ppairoe_i16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 1, i32 2>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_ppairoe_i16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 1, i32 2>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int16x2_t test_ppairoe_i16x2(int16x2_t rs1, int16x2_t rs2) {
return __riscv_ppairoe_i16x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_ppairoe_u16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 1, i32 2>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_ppairoe_u16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 1, i32 2>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_ppairoe_u16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 1, i32 2>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_ppairoe_u16x2(uint16x2_t rs1, uint16x2_t rs2) {
return __riscv_ppairoe_u16x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_ppairo_i16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 1, i32 3>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_ppairo_i16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 1, i32 3>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_ppairo_i16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 1, i32 3>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int16x2_t test_ppairo_i16x2(int16x2_t rs1, int16x2_t rs2) {
return __riscv_ppairo_i16x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_ppairo_u16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 1, i32 3>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_ppairo_u16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 1, i32 3>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_ppairo_u16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i32> <i32 1, i32 3>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_ppairo_u16x2(uint16x2_t rs1, uint16x2_t rs2) {
return __riscv_ppairo_u16x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_ppaire_i8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_ppaire_i8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_ppaire_i8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int8x8_t test_ppaire_i8x8(int8x8_t rs1, int8x8_t rs2) {
return __riscv_ppaire_i8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_ppaire_u8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_ppaire_u8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_ppaire_u8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_ppaire_u8x8(uint8x8_t rs1, uint8x8_t rs2) {
return __riscv_ppaire_u8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_ppaireo_i8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_ppaireo_i8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_ppaireo_i8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int8x8_t test_ppaireo_i8x8(int8x8_t rs1, int8x8_t rs2) {
return __riscv_ppaireo_i8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_ppaireo_u8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_ppaireo_u8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_ppaireo_u8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_ppaireo_u8x8(uint8x8_t rs1, uint8x8_t rs2) {
return __riscv_ppaireo_u8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_ppairoe_i8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_ppairoe_i8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_ppairoe_i8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int8x8_t test_ppairoe_i8x8(int8x8_t rs1, int8x8_t rs2) {
return __riscv_ppairoe_i8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_ppairoe_u8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_ppairoe_u8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_ppairoe_u8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_ppairoe_u8x8(uint8x8_t rs1, uint8x8_t rs2) {
return __riscv_ppairoe_u8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_ppairo_i8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_ppairo_i8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_ppairo_i8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int8x8_t test_ppairo_i8x8(int8x8_t rs1, int8x8_t rs2) {
return __riscv_ppairo_i8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_ppairo_u8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_ppairo_u8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_ppairo_u8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_ppairo_u8x8(uint8x8_t rs1, uint8x8_t rs2) {
return __riscv_ppairo_u8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_ppaire_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_ppaire_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_ppaire_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_ppaire_i16x4(int16x4_t rs1, int16x4_t rs2) {
return __riscv_ppaire_i16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_ppaire_u16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_ppaire_u16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_ppaire_u16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_ppaire_u16x4(uint16x4_t rs1, uint16x4_t rs2) {
return __riscv_ppaire_u16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_ppaireo_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_ppaireo_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_ppaireo_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_ppaireo_i16x4(int16x4_t rs1, int16x4_t rs2) {
return __riscv_ppaireo_i16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_ppaireo_u16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_ppaireo_u16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_ppaireo_u16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_ppaireo_u16x4(uint16x4_t rs1, uint16x4_t rs2) {
return __riscv_ppaireo_u16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_ppairoe_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_ppairoe_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_ppairoe_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_ppairoe_i16x4(int16x4_t rs1, int16x4_t rs2) {
return __riscv_ppairoe_i16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_ppairoe_u16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_ppairoe_u16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_ppairoe_u16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_ppairoe_u16x4(uint16x4_t rs1, uint16x4_t rs2) {
return __riscv_ppairoe_u16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_ppairo_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_ppairo_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_ppairo_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_ppairo_i16x4(int16x4_t rs1, int16x4_t rs2) {
return __riscv_ppairo_i16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_ppairo_u16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_ppairo_u16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_ppairo_u16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_ppairo_u16x4(uint16x4_t rs1, uint16x4_t rs2) {
return __riscv_ppairo_u16x4(rs1, rs2);
@@ -7805,28 +5095,20 @@ uint32_t test_pabdsumau_u8x4_u32(uint32_t rd, uint8x4_t rs1, uint8x4_t rs2) {
// RV64-NEXT: [[ENTRY:.*:]]
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.pabdsumu.i32.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: ret i32 [[TMP2]]
-//
-uint32_t test_pabdsumu_u8x8_u32(uint8x8_t rs1, uint8x8_t rs2) {
- return __riscv_pabdsumu_u8x8_u32(rs1, rs2);
-}
-
-// RV32-LABEL: define dso_local i64 @test_pabdsumu_u8x8_u64(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.pabdsumu.i64.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pabdsumu_u8x8_u64(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.pabdsumu.i64.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: ret i64 [[TMP2]]
+// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.pabdsumu.i32.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// RV64-NEXT: ret i32 [[TMP2]]
+//
+uint32_t test_pabdsumu_u8x8_u32(uint8x8_t rs1, uint8x8_t rs2) {
+ return __riscv_pabdsumu_u8x8_u32(rs1, rs2);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pabdsumu_u8x8_u64(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.pabdsumu.i64.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint64_t test_pabdsumu_u8x8_u64(uint8x8_t rs1, uint8x8_t rs2) {
return __riscv_pabdsumu_u8x8_u64(rs1, rs2);
@@ -7852,21 +5134,13 @@ uint32_t test_pabdsumau_u8x8_u32(uint32_t rd, uint8x8_t rs1, uint8x8_t rs2) {
return __riscv_pabdsumau_u8x8_u32(rd, rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pabdsumau_u8x8_u64(
-// RV32-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.pabdsumau.i64.v8i8(i64 [[RD]], <8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pabdsumau_u8x8_u64(
-// RV64-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.pabdsumau.i64.v8i8(i64 [[RD]], <8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pabdsumau_u8x8_u64(
+// CHECK-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.pabdsumau.i64.v8i8(i64 [[RD]], <8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint64_t test_pabdsumau_u8x8_u64(uint64_t rd, uint8x8_t rs1, uint8x8_t rs2) {
return __riscv_pabdsumau_u8x8_u64(rd, rs1, rs2);
@@ -7874,41 +5148,25 @@ uint64_t test_pabdsumau_u8x8_u64(uint64_t rd, uint8x8_t rs1, uint8x8_t rs2) {
/* Packed Saturating Absolute Value (32-bit) */
-// RV32-LABEL: define dso_local i32 @test_psabs_i8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.psabs.v4i8(<4 x i8> [[TMP0]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_psabs_i8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.psabs.v4i8(<4 x i8> [[TMP0]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_psabs_i8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.psabs.v4i8(<4 x i8> [[TMP0]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int8x4_t test_psabs_i8x4(int8x4_t rs1) {
return __riscv_psabs_i8x4(rs1);
}
-// RV32-LABEL: define dso_local i32 @test_psabs_i16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.psabs.v2i16(<2 x i16> [[TMP0]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_psabs_i16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.psabs.v2i16(<2 x i16> [[TMP0]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_psabs_i16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.psabs.v2i16(<2 x i16> [[TMP0]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int16x2_t test_psabs_i16x2(int16x2_t rs1) {
return __riscv_psabs_i16x2(rs1);
@@ -7916,41 +5174,25 @@ int16x2_t test_psabs_i16x2(int16x2_t rs1) {
/* Packed Saturating Absolute Value (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_psabs_i8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = call <8 x i8> @llvm.riscv.psabs.v8i8(<8 x i8> [[TMP0]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psabs_i8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = call <8 x i8> @llvm.riscv.psabs.v8i8(<8 x i8> [[TMP0]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psabs_i8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i8> @llvm.riscv.psabs.v8i8(<8 x i8> [[TMP0]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int8x8_t test_psabs_i8x8(int8x8_t rs1) {
return __riscv_psabs_i8x8(rs1);
}
-// RV32-LABEL: define dso_local i64 @test_psabs_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.psabs.v4i16(<4 x i16> [[TMP0]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psabs_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.psabs.v4i16(<4 x i16> [[TMP0]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psabs_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.psabs.v4i16(<4 x i16> [[TMP0]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_psabs_i16x4(int16x4_t rs1) {
return __riscv_psabs_i16x4(rs1);
@@ -7958,41 +5200,25 @@ int16x4_t test_psabs_i16x4(int16x4_t rs1) {
/* Packed Sign and Zero Extend (32-bit) */
-// RV32-LABEL: define dso_local i32 @test_psext_b_i16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.psext.b.v2i16(<2 x i16> [[TMP0]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_psext_b_i16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.psext.b.v2i16(<2 x i16> [[TMP0]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_psext_b_i16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.psext.b.v2i16(<2 x i16> [[TMP0]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int16x2_t test_psext_b_i16x2(int16x2_t rs1) {
return __riscv_psext_b_i16x2(rs1);
}
-// RV32-LABEL: define dso_local i32 @test_pzext_b_u16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pzext.b.v2i16(<2 x i16> [[TMP0]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pzext_b_u16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pzext.b.v2i16(<2 x i16> [[TMP0]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pzext_b_u16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pzext.b.v2i16(<2 x i16> [[TMP0]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_pzext_b_u16x2(uint16x2_t rs1) {
return __riscv_pzext_b_u16x2(rs1);
@@ -8000,101 +5226,61 @@ uint16x2_t test_pzext_b_u16x2(uint16x2_t rs1) {
/* Packed Sign and Zero Extend (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_psext_b_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.psext.b.v4i16(<4 x i16> [[TMP0]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psext_b_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.psext.b.v4i16(<4 x i16> [[TMP0]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psext_b_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.psext.b.v4i16(<4 x i16> [[TMP0]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_psext_b_i16x4(int16x4_t rs1) {
return __riscv_psext_b_i16x4(rs1);
}
-// RV32-LABEL: define dso_local i64 @test_psext_b_i32x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.psext.b.v2i32(<2 x i32> [[TMP0]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psext_b_i32x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.psext.b.v2i32(<2 x i32> [[TMP0]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psext_b_i32x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.psext.b.v2i32(<2 x i32> [[TMP0]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int32x2_t test_psext_b_i32x2(int32x2_t rs1) {
return __riscv_psext_b_i32x2(rs1);
}
-// RV32-LABEL: define dso_local i64 @test_psext_h_i32x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.psext.h.v2i32(<2 x i32> [[TMP0]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psext_h_i32x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.psext.h.v2i32(<2 x i32> [[TMP0]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psext_h_i32x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.psext.h.v2i32(<2 x i32> [[TMP0]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int32x2_t test_psext_h_i32x2(int32x2_t rs1) {
return __riscv_psext_h_i32x2(rs1);
}
-// RV32-LABEL: define dso_local i64 @test_pzext_b_u16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.pzext.b.v4i16(<4 x i16> [[TMP0]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pzext_b_u16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.pzext.b.v4i16(<4 x i16> [[TMP0]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pzext_b_u16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.pzext.b.v4i16(<4 x i16> [[TMP0]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pzext_b_u16x4(uint16x4_t rs1) {
return __riscv_pzext_b_u16x4(rs1);
}
-// RV32-LABEL: define dso_local i64 @test_pzext_h_u32x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.pzext.h.v2i32(<2 x i32> [[TMP0]])
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pzext_h_u32x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.pzext.h.v2i32(<2 x i32> [[TMP0]])
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pzext_h_u32x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.pzext.h.v2i32(<2 x i32> [[TMP0]])
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_pzext_h_u32x2(uint32x2_t rs1) {
return __riscv_pzext_h_u32x2(rs1);
@@ -8102,81 +5288,49 @@ uint32x2_t test_pzext_h_u32x2(uint32x2_t rs1) {
/* Packed Widening Convert */
-// RV32-LABEL: define dso_local i64 @test_pwcvt_i16x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[CONV_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwcvt_i16x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[CONV_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pwcvt_i16x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[CONV_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
int16x4_t test_pwcvt_i16x4(int8x4_t rs1) {
return __riscv_pwcvt_i16x4(rs1);
}
-// RV32-LABEL: define dso_local i64 @test_pwcvt_i32x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[CONV_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwcvt_i32x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[CONV_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pwcvt_i32x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[CONV_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
int32x2_t test_pwcvt_i32x2(int16x2_t rs1) {
return __riscv_pwcvt_i32x2(rs1);
}
-// RV32-LABEL: define dso_local i64 @test_pwcvtu_u16x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[CONV_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwcvtu_u16x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[CONV_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pwcvtu_u16x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[CONV_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
uint16x4_t test_pwcvtu_u16x4(uint8x4_t rs1) {
return __riscv_pwcvtu_u16x4(rs1);
}
-// RV32-LABEL: define dso_local i64 @test_pwcvtu_u32x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[CONV_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwcvtu_u32x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[CONV_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pwcvtu_u32x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[CONV_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
uint32x2_t test_pwcvtu_u32x2(uint16x2_t rs1) {
return __riscv_pwcvtu_u32x2(rs1);
@@ -8262,688 +5416,398 @@ int32x2_t test_pwsla_s_i32x2(int16x2_t rs1, unsigned shamt) {
return __riscv_pwsla_s_i32x2(rs1, shamt);
}
-// RV32-LABEL: define dso_local i64 @test_pwadd_i16x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16>
-// RV32-NEXT: [[CONV3_I:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i16>
-// RV32-NEXT: [[ADD_I:%.*]] = add nsw <4 x i16> [[CONV_I]], [[CONV3_I]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwadd_i16x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16>
-// RV64-NEXT: [[CONV3_I:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i16>
-// RV64-NEXT: [[ADD_I:%.*]] = add nsw <4 x i16> [[CONV_I]], [[CONV3_I]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pwadd_i16x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16>
+// CHECK-NEXT: [[CONV3_I:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i16>
+// CHECK-NEXT: [[ADD_I:%.*]] = add nsw <4 x i16> [[CONV_I]], [[CONV3_I]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_pwadd_i16x4(int8x4_t rs1, int8x4_t rs2) {
return __riscv_pwadd_i16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pwadd_i32x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32>
-// RV32-NEXT: [[CONV3_I:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32>
-// RV32-NEXT: [[ADD_I:%.*]] = add nsw <2 x i32> [[CONV_I]], [[CONV3_I]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwadd_i32x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32>
-// RV64-NEXT: [[CONV3_I:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32>
-// RV64-NEXT: [[ADD_I:%.*]] = add nsw <2 x i32> [[CONV_I]], [[CONV3_I]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pwadd_i32x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32>
+// CHECK-NEXT: [[CONV3_I:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32>
+// CHECK-NEXT: [[ADD_I:%.*]] = add nsw <2 x i32> [[CONV_I]], [[CONV3_I]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int32x2_t test_pwadd_i32x2(int16x2_t rs1, int16x2_t rs2) {
return __riscv_pwadd_i32x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pwaddu_u16x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i16>
-// RV32-NEXT: [[CONV3_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16>
-// RV32-NEXT: [[ADD_I:%.*]] = add nuw nsw <4 x i16> [[CONV_I]], [[CONV3_I]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwaddu_u16x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i16>
-// RV64-NEXT: [[CONV3_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16>
-// RV64-NEXT: [[ADD_I:%.*]] = add nuw nsw <4 x i16> [[CONV_I]], [[CONV3_I]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pwaddu_u16x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i16>
+// CHECK-NEXT: [[CONV3_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16>
+// CHECK-NEXT: [[ADD_I:%.*]] = add nuw nsw <4 x i16> [[CONV_I]], [[CONV3_I]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pwaddu_u16x4(uint8x4_t rs1, uint8x4_t rs2) {
return __riscv_pwaddu_u16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pwaddu_u32x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32>
-// RV32-NEXT: [[CONV3_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32>
-// RV32-NEXT: [[ADD_I:%.*]] = add nuw nsw <2 x i32> [[CONV_I]], [[CONV3_I]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwaddu_u32x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32>
-// RV64-NEXT: [[CONV3_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32>
-// RV64-NEXT: [[ADD_I:%.*]] = add nuw nsw <2 x i32> [[CONV_I]], [[CONV3_I]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pwaddu_u32x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32>
+// CHECK-NEXT: [[CONV3_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32>
+// CHECK-NEXT: [[ADD_I:%.*]] = add nuw nsw <2 x i32> [[CONV_I]], [[CONV3_I]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_pwaddu_u32x2(uint16x2_t rs1, uint16x2_t rs2) {
return __riscv_pwaddu_u32x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pwadda_i16x4(
-// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i16>
-// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[CONV_I]]
-// RV32-NEXT: [[CONV4_I:%.*]] = sext <4 x i8> [[TMP2]] to <4 x i16>
-// RV32-NEXT: [[ADD5_I:%.*]] = add <4 x i16> [[ADD_I]], [[CONV4_I]]
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[ADD5_I]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwadda_i16x4(
-// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i16>
-// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[CONV_I]]
-// RV64-NEXT: [[CONV4_I:%.*]] = sext <4 x i8> [[TMP2]] to <4 x i16>
-// RV64-NEXT: [[ADD5_I:%.*]] = add <4 x i16> [[ADD_I]], [[CONV4_I]]
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[ADD5_I]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pwadda_i16x4(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i16>
+// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[CONV_I]]
+// CHECK-NEXT: [[CONV4_I:%.*]] = sext <4 x i8> [[TMP2]] to <4 x i16>
+// CHECK-NEXT: [[ADD5_I:%.*]] = add <4 x i16> [[ADD_I]], [[CONV4_I]]
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[ADD5_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int16x4_t test_pwadda_i16x4(int16x4_t rd, int8x4_t rs1, int8x4_t rs2) {
return __riscv_pwadda_i16x4(rd, rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pwadda_i32x2(
-// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32>
-// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[CONV_I]]
-// RV32-NEXT: [[CONV4_I:%.*]] = sext <2 x i16> [[TMP2]] to <2 x i32>
-// RV32-NEXT: [[ADD5_I:%.*]] = add <2 x i32> [[ADD_I]], [[CONV4_I]]
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[ADD5_I]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwadda_i32x2(
-// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32>
-// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[CONV_I]]
-// RV64-NEXT: [[CONV4_I:%.*]] = sext <2 x i16> [[TMP2]] to <2 x i32>
-// RV64-NEXT: [[ADD5_I:%.*]] = add <2 x i32> [[ADD_I]], [[CONV4_I]]
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[ADD5_I]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pwadda_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32>
+// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[CONV_I]]
+// CHECK-NEXT: [[CONV4_I:%.*]] = sext <2 x i16> [[TMP2]] to <2 x i32>
+// CHECK-NEXT: [[ADD5_I:%.*]] = add <2 x i32> [[ADD_I]], [[CONV4_I]]
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[ADD5_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int32x2_t test_pwadda_i32x2(int32x2_t rd, int16x2_t rs1, int16x2_t rs2) {
return __riscv_pwadda_i32x2(rd, rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pwaddau_u16x4(
-// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16>
-// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[CONV_I]]
-// RV32-NEXT: [[CONV4_I:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i16>
-// RV32-NEXT: [[ADD5_I:%.*]] = add <4 x i16> [[ADD_I]], [[CONV4_I]]
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[ADD5_I]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwaddau_u16x4(
-// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16>
-// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[CONV_I]]
-// RV64-NEXT: [[CONV4_I:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i16>
-// RV64-NEXT: [[ADD5_I:%.*]] = add <4 x i16> [[ADD_I]], [[CONV4_I]]
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[ADD5_I]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pwaddau_u16x4(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16>
+// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[CONV_I]]
+// CHECK-NEXT: [[CONV4_I:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i16>
+// CHECK-NEXT: [[ADD5_I:%.*]] = add <4 x i16> [[ADD_I]], [[CONV4_I]]
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[ADD5_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
uint16x4_t test_pwaddau_u16x4(uint16x4_t rd, uint8x4_t rs1,
uint8x4_t rs2) {
return __riscv_pwaddau_u16x4(rd, rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pwaddau_u32x2(
-// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32>
-// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[CONV_I]]
-// RV32-NEXT: [[CONV4_I:%.*]] = zext <2 x i16> [[TMP2]] to <2 x i32>
-// RV32-NEXT: [[ADD5_I:%.*]] = add <2 x i32> [[ADD_I]], [[CONV4_I]]
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[ADD5_I]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwaddau_u32x2(
-// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32>
-// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[CONV_I]]
-// RV64-NEXT: [[CONV4_I:%.*]] = zext <2 x i16> [[TMP2]] to <2 x i32>
-// RV64-NEXT: [[ADD5_I:%.*]] = add <2 x i32> [[ADD_I]], [[CONV4_I]]
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[ADD5_I]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pwaddau_u32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32>
+// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[CONV_I]]
+// CHECK-NEXT: [[CONV4_I:%.*]] = zext <2 x i16> [[TMP2]] to <2 x i32>
+// CHECK-NEXT: [[ADD5_I:%.*]] = add <2 x i32> [[ADD_I]], [[CONV4_I]]
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[ADD5_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
uint32x2_t test_pwaddau_u32x2(uint32x2_t rd, uint16x2_t rs1,
uint16x2_t rs2) {
return __riscv_pwaddau_u32x2(rd, rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pwsuba_i16x4(
-// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i16>
-// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[CONV_I]]
-// RV32-NEXT: [[CONV4_I:%.*]] = sext <4 x i8> [[TMP2]] to <4 x i16>
-// RV32-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[ADD_I]], [[CONV4_I]]
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwsuba_i16x4(
-// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i16>
-// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[CONV_I]]
-// RV64-NEXT: [[CONV4_I:%.*]] = sext <4 x i8> [[TMP2]] to <4 x i16>
-// RV64-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[ADD_I]], [[CONV4_I]]
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pwsuba_i16x4(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i16>
+// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[CONV_I]]
+// CHECK-NEXT: [[CONV4_I:%.*]] = sext <4 x i8> [[TMP2]] to <4 x i16>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[ADD_I]], [[CONV4_I]]
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int16x4_t test_pwsuba_i16x4(int16x4_t rd, int8x4_t rs1, int8x4_t rs2) {
return __riscv_pwsuba_i16x4(rd, rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pwsuba_i32x2(
-// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32>
-// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[CONV_I]]
-// RV32-NEXT: [[CONV4_I:%.*]] = sext <2 x i16> [[TMP2]] to <2 x i32>
-// RV32-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[ADD_I]], [[CONV4_I]]
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwsuba_i32x2(
-// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32>
-// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[CONV_I]]
-// RV64-NEXT: [[CONV4_I:%.*]] = sext <2 x i16> [[TMP2]] to <2 x i32>
-// RV64-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[ADD_I]], [[CONV4_I]]
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pwsuba_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32>
+// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[CONV_I]]
+// CHECK-NEXT: [[CONV4_I:%.*]] = sext <2 x i16> [[TMP2]] to <2 x i32>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[ADD_I]], [[CONV4_I]]
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int32x2_t test_pwsuba_i32x2(int32x2_t rd, int16x2_t rs1, int16x2_t rs2) {
return __riscv_pwsuba_i32x2(rd, rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pwsubau_u16x4(
-// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16>
-// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[CONV_I]]
-// RV32-NEXT: [[CONV4_I:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i16>
-// RV32-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[ADD_I]], [[CONV4_I]]
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwsubau_u16x4(
-// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16>
-// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[CONV_I]]
-// RV64-NEXT: [[CONV4_I:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i16>
-// RV64-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[ADD_I]], [[CONV4_I]]
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pwsubau_u16x4(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16>
+// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[CONV_I]]
+// CHECK-NEXT: [[CONV4_I:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i16>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[ADD_I]], [[CONV4_I]]
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
uint16x4_t test_pwsubau_u16x4(uint16x4_t rd, uint8x4_t rs1, uint8x4_t rs2) {
return __riscv_pwsubau_u16x4(rd, rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pwsubau_u32x2(
-// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32>
-// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[CONV_I]]
-// RV32-NEXT: [[CONV4_I:%.*]] = zext <2 x i16> [[TMP2]] to <2 x i32>
-// RV32-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[ADD_I]], [[CONV4_I]]
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwsubau_u32x2(
-// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32>
-// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[CONV_I]]
-// RV64-NEXT: [[CONV4_I:%.*]] = zext <2 x i16> [[TMP2]] to <2 x i32>
-// RV64-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[ADD_I]], [[CONV4_I]]
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pwsubau_u32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32>
+// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[CONV_I]]
+// CHECK-NEXT: [[CONV4_I:%.*]] = zext <2 x i16> [[TMP2]] to <2 x i32>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[ADD_I]], [[CONV4_I]]
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
uint32x2_t test_pwsubau_u32x2(uint32x2_t rd, uint16x2_t rs1,
uint16x2_t rs2) {
return __riscv_pwsubau_u32x2(rd, rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pwsub_i16x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16>
-// RV32-NEXT: [[CONV3_I:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i16>
-// RV32-NEXT: [[SUB_I:%.*]] = sub nsw <4 x i16> [[CONV_I]], [[CONV3_I]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwsub_i16x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16>
-// RV64-NEXT: [[CONV3_I:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i16>
-// RV64-NEXT: [[SUB_I:%.*]] = sub nsw <4 x i16> [[CONV_I]], [[CONV3_I]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pwsub_i16x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16>
+// CHECK-NEXT: [[CONV3_I:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i16>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub nsw <4 x i16> [[CONV_I]], [[CONV3_I]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_pwsub_i16x4(int8x4_t rs1, int8x4_t rs2) {
return __riscv_pwsub_i16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pwsub_i32x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32>
-// RV32-NEXT: [[CONV3_I:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32>
-// RV32-NEXT: [[SUB_I:%.*]] = sub nsw <2 x i32> [[CONV_I]], [[CONV3_I]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwsub_i32x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32>
-// RV64-NEXT: [[CONV3_I:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32>
-// RV64-NEXT: [[SUB_I:%.*]] = sub nsw <2 x i32> [[CONV_I]], [[CONV3_I]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pwsub_i32x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32>
+// CHECK-NEXT: [[CONV3_I:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub nsw <2 x i32> [[CONV_I]], [[CONV3_I]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int32x2_t test_pwsub_i32x2(int16x2_t rs1, int16x2_t rs2) {
return __riscv_pwsub_i32x2(rs1, rs2);
}
-
-// RV32-LABEL: define dso_local i64 @test_pwsubu_u16x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i16>
-// RV32-NEXT: [[CONV3_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16>
-// RV32-NEXT: [[SUB_I:%.*]] = sub nsw <4 x i16> [[CONV_I]], [[CONV3_I]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwsubu_u16x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i16>
-// RV64-NEXT: [[CONV3_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16>
-// RV64-NEXT: [[SUB_I:%.*]] = sub nsw <4 x i16> [[CONV_I]], [[CONV3_I]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
-//
-uint16x4_t test_pwsubu_u16x4(uint8x4_t rs1, uint8x4_t rs2) {
- return __riscv_pwsubu_u16x4(rs1, rs2);
-}
-
-// RV32-LABEL: define dso_local i64 @test_pwsubu_u32x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32>
-// RV32-NEXT: [[CONV3_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32>
-// RV32-NEXT: [[SUB_I:%.*]] = sub nsw <2 x i32> [[CONV_I]], [[CONV3_I]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
+
+// CHECK-LABEL: define dso_local i64 @test_pwsubu_u16x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i16>
+// CHECK-NEXT: [[CONV3_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub nsw <4 x i16> [[CONV_I]], [[CONV3_I]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
-// RV64-LABEL: define dso_local i64 @test_pwsubu_u32x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32>
-// RV64-NEXT: [[CONV3_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32>
-// RV64-NEXT: [[SUB_I:%.*]] = sub nsw <2 x i32> [[CONV_I]], [[CONV3_I]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+uint16x4_t test_pwsubu_u16x4(uint8x4_t rs1, uint8x4_t rs2) {
+ return __riscv_pwsubu_u16x4(rs1, rs2);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pwsubu_u32x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32>
+// CHECK-NEXT: [[CONV3_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32>
+// CHECK-NEXT: [[SUB_I:%.*]] = sub nsw <2 x i32> [[CONV_I]], [[CONV3_I]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_pwsubu_u32x2(uint16x2_t rs1, uint16x2_t rs2) {
return __riscv_pwsubu_u32x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pwmul_i16x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16>
-// RV32-NEXT: [[CONV3_I:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i16>
-// RV32-NEXT: [[MUL_I:%.*]] = mul nsw <4 x i16> [[CONV_I]], [[CONV3_I]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[MUL_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwmul_i16x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16>
-// RV64-NEXT: [[CONV3_I:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i16>
-// RV64-NEXT: [[MUL_I:%.*]] = mul nsw <4 x i16> [[CONV_I]], [[CONV3_I]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[MUL_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pwmul_i16x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16>
+// CHECK-NEXT: [[CONV3_I:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i16>
+// CHECK-NEXT: [[MUL_I:%.*]] = mul nsw <4 x i16> [[CONV_I]], [[CONV3_I]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[MUL_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_pwmul_i16x4(int8x4_t rs1, int8x4_t rs2) {
return __riscv_pwmul_i16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pwmul_i32x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32>
-// RV32-NEXT: [[CONV3_I:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32>
-// RV32-NEXT: [[MUL_I:%.*]] = mul nsw <2 x i32> [[CONV_I]], [[CONV3_I]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[MUL_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwmul_i32x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32>
-// RV64-NEXT: [[CONV3_I:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32>
-// RV64-NEXT: [[MUL_I:%.*]] = mul nsw <2 x i32> [[CONV_I]], [[CONV3_I]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[MUL_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pwmul_i32x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32>
+// CHECK-NEXT: [[CONV3_I:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32>
+// CHECK-NEXT: [[MUL_I:%.*]] = mul nsw <2 x i32> [[CONV_I]], [[CONV3_I]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[MUL_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int32x2_t test_pwmul_i32x2(int16x2_t rs1, int16x2_t rs2) {
return __riscv_pwmul_i32x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pwmulu_u16x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i16>
-// RV32-NEXT: [[CONV3_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16>
-// RV32-NEXT: [[MUL_I:%.*]] = mul nuw <4 x i16> [[CONV_I]], [[CONV3_I]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[MUL_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwmulu_u16x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i16>
-// RV64-NEXT: [[CONV3_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16>
-// RV64-NEXT: [[MUL_I:%.*]] = mul nuw <4 x i16> [[CONV_I]], [[CONV3_I]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[MUL_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pwmulu_u16x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i16>
+// CHECK-NEXT: [[CONV3_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16>
+// CHECK-NEXT: [[MUL_I:%.*]] = mul nuw <4 x i16> [[CONV_I]], [[CONV3_I]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[MUL_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pwmulu_u16x4(uint8x4_t rs1, uint8x4_t rs2) {
return __riscv_pwmulu_u16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pwmulu_u32x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32>
-// RV32-NEXT: [[CONV3_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32>
-// RV32-NEXT: [[MUL_I:%.*]] = mul nuw <2 x i32> [[CONV_I]], [[CONV3_I]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[MUL_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwmulu_u32x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32>
-// RV64-NEXT: [[CONV3_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32>
-// RV64-NEXT: [[MUL_I:%.*]] = mul nuw <2 x i32> [[CONV_I]], [[CONV3_I]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[MUL_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pwmulu_u32x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32>
+// CHECK-NEXT: [[CONV3_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32>
+// CHECK-NEXT: [[MUL_I:%.*]] = mul nuw <2 x i32> [[CONV_I]], [[CONV3_I]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[MUL_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_pwmulu_u32x2(uint16x2_t rs1, uint16x2_t rs2) {
return __riscv_pwmulu_u32x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pwmulsu_i16x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16>
-// RV32-NEXT: [[CONV3_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16>
-// RV32-NEXT: [[MUL_I:%.*]] = mul nsw <4 x i16> [[CONV_I]], [[CONV3_I]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[MUL_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwmulsu_i16x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16>
-// RV64-NEXT: [[CONV3_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16>
-// RV64-NEXT: [[MUL_I:%.*]] = mul nsw <4 x i16> [[CONV_I]], [[CONV3_I]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[MUL_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pwmulsu_i16x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16>
+// CHECK-NEXT: [[CONV3_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16>
+// CHECK-NEXT: [[MUL_I:%.*]] = mul nsw <4 x i16> [[CONV_I]], [[CONV3_I]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[MUL_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_pwmulsu_i16x4(int8x4_t rs1, uint8x4_t rs2) {
return __riscv_pwmulsu_i16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pwmulsu_i32x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32>
-// RV32-NEXT: [[CONV3_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32>
-// RV32-NEXT: [[MUL_I:%.*]] = mul nsw <2 x i32> [[CONV_I]], [[CONV3_I]]
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[MUL_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwmulsu_i32x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32>
-// RV64-NEXT: [[CONV3_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32>
-// RV64-NEXT: [[MUL_I:%.*]] = mul nsw <2 x i32> [[CONV_I]], [[CONV3_I]]
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[MUL_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pwmulsu_i32x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32>
+// CHECK-NEXT: [[CONV3_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32>
+// CHECK-NEXT: [[MUL_I:%.*]] = mul nsw <2 x i32> [[CONV_I]], [[CONV3_I]]
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[MUL_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int32x2_t test_pwmulsu_i32x2(int16x2_t rs1, uint16x2_t rs2) {
return __riscv_pwmulsu_i32x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pwcvth_i16x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> zeroinitializer, <4 x i8> [[TMP0]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwcvth_i16x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> zeroinitializer, <4 x i8> [[TMP0]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pwcvth_i16x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> zeroinitializer, <4 x i8> [[TMP0]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
int16x4_t test_pwcvth_i16x4(int8x4_t rs1) {
return __riscv_pwcvth_i16x4(rs1);
}
-// RV32-LABEL: define dso_local i64 @test_pwcvth_u16x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> zeroinitializer, <4 x i8> [[TMP0]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwcvth_u16x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> zeroinitializer, <4 x i8> [[TMP0]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pwcvth_u16x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> zeroinitializer, <4 x i8> [[TMP0]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
uint16x4_t test_pwcvth_u16x4(uint8x4_t rs1) {
return __riscv_pwcvth_u16x4(rs1);
}
-// RV32-LABEL: define dso_local i64 @test_pwcvth_i32x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> zeroinitializer, <2 x i16> [[TMP0]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwcvth_i32x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> zeroinitializer, <2 x i16> [[TMP0]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pwcvth_i32x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> zeroinitializer, <2 x i16> [[TMP0]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
int32x2_t test_pwcvth_i32x2(int16x2_t rs1) {
return __riscv_pwcvth_i32x2(rs1);
}
-// RV32-LABEL: define dso_local i64 @test_pwcvth_u32x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> zeroinitializer, <2 x i16> [[TMP0]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pwcvth_u32x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> zeroinitializer, <2 x i16> [[TMP0]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pwcvth_u32x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> zeroinitializer, <2 x i16> [[TMP0]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
uint32x2_t test_pwcvth_u32x2(uint16x2_t rs1) {
return __riscv_pwcvth_u32x2(rs1);
@@ -8951,153 +5815,89 @@ uint32x2_t test_pwcvth_u32x2(uint16x2_t rs1) {
/* Packed Narrowing Convert */
-// RV32-LABEL: define dso_local i32 @test_pncvt_i8x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[CONV_I:%.*]] = trunc <4 x i16> [[TMP0]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[CONV_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pncvt_i8x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[CONV_I:%.*]] = trunc <4 x i16> [[TMP0]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[CONV_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_pncvt_i8x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[CONV_I:%.*]] = trunc <4 x i16> [[TMP0]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[CONV_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
int8x4_t test_pncvt_i8x4(int16x4_t rs1) { return __riscv_pncvt_i8x4(rs1); }
-// RV32-LABEL: define dso_local i32 @test_pncvt_u8x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[CONV_I:%.*]] = trunc <4 x i16> [[TMP0]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[CONV_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pncvt_u8x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[CONV_I:%.*]] = trunc <4 x i16> [[TMP0]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[CONV_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_pncvt_u8x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[CONV_I:%.*]] = trunc <4 x i16> [[TMP0]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[CONV_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
uint8x4_t test_pncvt_u8x4(uint16x4_t rs1) { return __riscv_pncvt_u8x4(rs1); }
-// RV32-LABEL: define dso_local i32 @test_pncvt_i16x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[CONV_I:%.*]] = trunc <2 x i32> [[TMP0]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[CONV_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pncvt_i16x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[CONV_I:%.*]] = trunc <2 x i32> [[TMP0]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[CONV_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_pncvt_i16x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[CONV_I:%.*]] = trunc <2 x i32> [[TMP0]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[CONV_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
int16x2_t test_pncvt_i16x2(int32x2_t rs1) { return __riscv_pncvt_i16x2(rs1); }
-// RV32-LABEL: define dso_local i32 @test_pncvt_u16x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[CONV_I:%.*]] = trunc <2 x i32> [[TMP0]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[CONV_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pncvt_u16x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[CONV_I:%.*]] = trunc <2 x i32> [[TMP0]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[CONV_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_pncvt_u16x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[CONV_I:%.*]] = trunc <2 x i32> [[TMP0]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[CONV_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
uint16x2_t test_pncvt_u16x2(uint32x2_t rs1) {
return __riscv_pncvt_u16x2(rs1);
}
-// RV32-LABEL: define dso_local i32 @test_pncvth_i8x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pncvth_i8x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_pncvth_i8x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
int8x4_t test_pncvth_i8x4(int16x4_t rs1) { return __riscv_pncvth_i8x4(rs1); }
-// RV32-LABEL: define dso_local i32 @test_pncvth_u8x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pncvth_u8x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_pncvth_u8x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
uint8x4_t test_pncvth_u8x4(uint16x4_t rs1) {
return __riscv_pncvth_u8x4(rs1);
}
-// RV32-LABEL: define dso_local i32 @test_pncvth_i16x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pncvth_i16x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_pncvth_i16x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
int16x2_t test_pncvth_i16x2(int32x2_t rs1) {
return __riscv_pncvth_i16x2(rs1);
}
-// RV32-LABEL: define dso_local i32 @test_pncvth_u16x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pncvth_u16x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_pncvth_u16x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
uint16x2_t test_pncvth_u16x2(uint32x2_t rs1) {
return __riscv_pncvth_u16x2(rs1);
@@ -9105,45 +5905,27 @@ uint16x2_t test_pncvth_u16x2(uint32x2_t rs1) {
/* Packed "Q-format" Multiplication (32-bit) */
-// RV32-LABEL: define dso_local i32 @test_pmulq_i16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulq.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmulq_i16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulq.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_pmulq_i16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulq.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
int16x2_t test_pmulq_i16x2(int16x2_t rs1, int16x2_t rs2) {
return __riscv_pmulq_i16x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_pmulqr_i16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulqr.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmulqr_i16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulqr.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_pmulqr_i16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulqr.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
int16x2_t test_pmulqr_i16x2(int16x2_t rs1, int16x2_t rs2) {
return __riscv_pmulqr_i16x2(rs1, rs2);
@@ -9151,89 +5933,53 @@ int16x2_t test_pmulqr_i16x2(int16x2_t rs1, int16x2_t rs2) {
/* Packed "Q-format" Multiplication (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_pmulq_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulq.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmulq_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulq.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pmulq_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulq.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int16x4_t test_pmulq_i16x4(int16x4_t rs1, int16x4_t rs2) {
return __riscv_pmulq_i16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pmulqr_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulqr.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmulqr_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulqr.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pmulqr_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulqr.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int16x4_t test_pmulqr_i16x4(int16x4_t rs1, int16x4_t rs2) {
return __riscv_pmulqr_i16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pmulq_i32x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulq.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmulq_i32x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulq.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pmulq_i32x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulq.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int32x2_t test_pmulq_i32x2(int32x2_t rs1, int32x2_t rs2) {
return __riscv_pmulq_i32x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pmulqr_i32x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulqr.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmulqr_i32x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulqr.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pmulqr_i32x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulqr.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int32x2_t test_pmulqr_i32x2(int32x2_t rs1, int32x2_t rs2) {
return __riscv_pmulqr_i32x2(rs1, rs2);
@@ -9450,864 +6196,534 @@ int16x2_t test_preinterpret_i32_i16x2(int32_t x) {
}
/* Reinterpret Casts, Packed <-> Scalar (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u8x8_u64(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u8x8_u64(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u8x8_u64(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint64_t test_preinterpret_u8x8_u64(uint8x8_t x) {
return __riscv_preinterpret_u8x8_u64(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u16x4_u64(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u16x4_u64(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u16x4_u64(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint64_t test_preinterpret_u16x4_u64(uint16x4_t x) {
return __riscv_preinterpret_u16x4_u64(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u32x2_u64(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u32x2_u64(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u32x2_u64(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint64_t test_preinterpret_u32x2_u64(uint32x2_t x) {
return __riscv_preinterpret_u32x2_u64(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i8x8_u64(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i8x8_u64(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i8x8_u64(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint64_t test_preinterpret_i8x8_u64(int8x8_t x) {
return __riscv_preinterpret_i8x8_u64(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i16x4_u64(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i16x4_u64(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i16x4_u64(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint64_t test_preinterpret_i16x4_u64(int16x4_t x) {
return __riscv_preinterpret_i16x4_u64(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i32x2_u64(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i32x2_u64(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i32x2_u64(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint64_t test_preinterpret_i32x2_u64(int32x2_t x) {
return __riscv_preinterpret_i32x2_u64(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u8x8_i64(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u8x8_i64(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u8x8_i64(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int64_t test_preinterpret_u8x8_i64(uint8x8_t x) {
return __riscv_preinterpret_u8x8_i64(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u16x4_i64(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u16x4_i64(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u16x4_i64(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int64_t test_preinterpret_u16x4_i64(uint16x4_t x) {
return __riscv_preinterpret_u16x4_i64(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u32x2_i64(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u32x2_i64(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u32x2_i64(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int64_t test_preinterpret_u32x2_i64(uint32x2_t x) {
return __riscv_preinterpret_u32x2_i64(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i8x8_i64(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i8x8_i64(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i8x8_i64(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int64_t test_preinterpret_i8x8_i64(int8x8_t x) {
return __riscv_preinterpret_i8x8_i64(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i16x4_i64(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i16x4_i64(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i16x4_i64(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int64_t test_preinterpret_i16x4_i64(int16x4_t x) {
return __riscv_preinterpret_i16x4_i64(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i32x2_i64(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i32x2_i64(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i32x2_i64(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int64_t test_preinterpret_i32x2_i64(int32x2_t x) {
return __riscv_preinterpret_i32x2_i64(x);
-}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u64_u8x8(
-// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u64_u8x8(
-// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X]]
+}
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u64_u8x8(
+// CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X]]
//
uint8x8_t test_preinterpret_u64_u8x8(uint64_t x) {
return __riscv_preinterpret_u64_u8x8(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u64_u16x4(
-// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u64_u16x4(
-// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u64_u16x4(
+// CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X]]
//
uint16x4_t test_preinterpret_u64_u16x4(uint64_t x) {
return __riscv_preinterpret_u64_u16x4(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u64_u32x2(
-// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u64_u32x2(
-// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u64_u32x2(
+// CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X]]
//
uint32x2_t test_preinterpret_u64_u32x2(uint64_t x) {
return __riscv_preinterpret_u64_u32x2(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u64_i8x8(
-// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u64_i8x8(
-// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u64_i8x8(
+// CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X]]
//
int8x8_t test_preinterpret_u64_i8x8(uint64_t x) {
return __riscv_preinterpret_u64_i8x8(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u64_i16x4(
-// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u64_i16x4(
-// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u64_i16x4(
+// CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X]]
//
int16x4_t test_preinterpret_u64_i16x4(uint64_t x) {
return __riscv_preinterpret_u64_i16x4(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u64_i32x2(
-// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u64_i32x2(
-// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u64_i32x2(
+// CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X]]
//
int32x2_t test_preinterpret_u64_i32x2(uint64_t x) {
return __riscv_preinterpret_u64_i32x2(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i64_u8x8(
-// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i64_u8x8(
-// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i64_u8x8(
+// CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X]]
//
uint8x8_t test_preinterpret_i64_u8x8(int64_t x) {
return __riscv_preinterpret_i64_u8x8(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i64_u16x4(
-// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i64_u16x4(
-// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i64_u16x4(
+// CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X]]
//
uint16x4_t test_preinterpret_i64_u16x4(int64_t x) {
return __riscv_preinterpret_i64_u16x4(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i64_u32x2(
-// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i64_u32x2(
-// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i64_u32x2(
+// CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X]]
//
uint32x2_t test_preinterpret_i64_u32x2(int64_t x) {
return __riscv_preinterpret_i64_u32x2(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i64_i8x8(
-// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i64_i8x8(
-// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i64_i8x8(
+// CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X]]
//
int8x8_t test_preinterpret_i64_i8x8(int64_t x) {
return __riscv_preinterpret_i64_i8x8(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i64_i16x4(
-// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i64_i16x4(
-// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i64_i16x4(
+// CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X]]
//
int16x4_t test_preinterpret_i64_i16x4(int64_t x) {
return __riscv_preinterpret_i64_i16x4(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i64_i32x2(
-// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i64_i32x2(
-// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i64_i32x2(
+// CHECK-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X]]
//
int32x2_t test_preinterpret_i64_i32x2(int64_t x) {
return __riscv_preinterpret_i64_i32x2(x);
}
/* Reinterpret Casts, Packed <-> Packed (32-bit) */
-// RV32-LABEL: define dso_local i32 @test_preinterpret_i8x4_u8x4(
-// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i32 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i32 @test_preinterpret_i8x4_u8x4(
-// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i32 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i32 @test_preinterpret_i8x4_u8x4(
+// CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i32 [[X_COERCE]]
//
uint8x4_t test_preinterpret_i8x4_u8x4(int8x4_t x) {
return __riscv_preinterpret_i8x4_u8x4(x);
}
-// RV32-LABEL: define dso_local i32 @test_preinterpret_u16x2_u8x4(
-// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i32 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i32 @test_preinterpret_u16x2_u8x4(
-// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i32 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i32 @test_preinterpret_u16x2_u8x4(
+// CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i32 [[X_COERCE]]
//
uint8x4_t test_preinterpret_u16x2_u8x4(uint16x2_t x) {
return __riscv_preinterpret_u16x2_u8x4(x);
}
-// RV32-LABEL: define dso_local i32 @test_preinterpret_i16x2_u8x4(
-// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i32 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i32 @test_preinterpret_i16x2_u8x4(
-// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i32 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i32 @test_preinterpret_i16x2_u8x4(
+// CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i32 [[X_COERCE]]
//
uint8x4_t test_preinterpret_i16x2_u8x4(int16x2_t x) {
return __riscv_preinterpret_i16x2_u8x4(x);
}
-// RV32-LABEL: define dso_local i32 @test_preinterpret_u8x4_i8x4(
-// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i32 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i32 @test_preinterpret_u8x4_i8x4(
-// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i32 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i32 @test_preinterpret_u8x4_i8x4(
+// CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i32 [[X_COERCE]]
//
int8x4_t test_preinterpret_u8x4_i8x4(uint8x4_t x) {
return __riscv_preinterpret_u8x4_i8x4(x);
}
-// RV32-LABEL: define dso_local i32 @test_preinterpret_u16x2_i8x4(
-// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i32 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i32 @test_preinterpret_u16x2_i8x4(
-// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i32 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i32 @test_preinterpret_u16x2_i8x4(
+// CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i32 [[X_COERCE]]
//
int8x4_t test_preinterpret_u16x2_i8x4(uint16x2_t x) {
return __riscv_preinterpret_u16x2_i8x4(x);
}
-// RV32-LABEL: define dso_local i32 @test_preinterpret_i16x2_i8x4(
-// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i32 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i32 @test_preinterpret_i16x2_i8x4(
-// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i32 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i32 @test_preinterpret_i16x2_i8x4(
+// CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i32 [[X_COERCE]]
//
int8x4_t test_preinterpret_i16x2_i8x4(int16x2_t x) {
return __riscv_preinterpret_i16x2_i8x4(x);
}
-// RV32-LABEL: define dso_local i32 @test_preinterpret_u8x4_u16x2(
-// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i32 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i32 @test_preinterpret_u8x4_u16x2(
-// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i32 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i32 @test_preinterpret_u8x4_u16x2(
+// CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i32 [[X_COERCE]]
//
uint16x2_t test_preinterpret_u8x4_u16x2(uint8x4_t x) {
return __riscv_preinterpret_u8x4_u16x2(x);
}
-// RV32-LABEL: define dso_local i32 @test_preinterpret_i8x4_u16x2(
-// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i32 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i32 @test_preinterpret_i8x4_u16x2(
-// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i32 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i32 @test_preinterpret_i8x4_u16x2(
+// CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i32 [[X_COERCE]]
//
uint16x2_t test_preinterpret_i8x4_u16x2(int8x4_t x) {
return __riscv_preinterpret_i8x4_u16x2(x);
}
-// RV32-LABEL: define dso_local i32 @test_preinterpret_i16x2_u16x2(
-// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i32 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i32 @test_preinterpret_i16x2_u16x2(
-// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i32 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i32 @test_preinterpret_i16x2_u16x2(
+// CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i32 [[X_COERCE]]
//
uint16x2_t test_preinterpret_i16x2_u16x2(int16x2_t x) {
return __riscv_preinterpret_i16x2_u16x2(x);
}
-// RV32-LABEL: define dso_local i32 @test_preinterpret_u8x4_i16x2(
-// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i32 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i32 @test_preinterpret_u8x4_i16x2(
-// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i32 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i32 @test_preinterpret_u8x4_i16x2(
+// CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i32 [[X_COERCE]]
//
int16x2_t test_preinterpret_u8x4_i16x2(uint8x4_t x) {
return __riscv_preinterpret_u8x4_i16x2(x);
}
-// RV32-LABEL: define dso_local i32 @test_preinterpret_i8x4_i16x2(
-// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i32 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i32 @test_preinterpret_i8x4_i16x2(
-// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i32 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i32 @test_preinterpret_i8x4_i16x2(
+// CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i32 [[X_COERCE]]
//
int16x2_t test_preinterpret_i8x4_i16x2(int8x4_t x) {
return __riscv_preinterpret_i8x4_i16x2(x);
}
-// RV32-LABEL: define dso_local i32 @test_preinterpret_u16x2_i16x2(
-// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i32 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i32 @test_preinterpret_u16x2_i16x2(
-// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i32 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i32 @test_preinterpret_u16x2_i16x2(
+// CHECK-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i32 [[X_COERCE]]
//
int16x2_t test_preinterpret_u16x2_i16x2(uint16x2_t x) {
return __riscv_preinterpret_u16x2_i16x2(x);
}
/* Reinterpret Casts, Packed <-> Packed (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i8x8_u8x8(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i8x8_u8x8(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i8x8_u8x8(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint8x8_t test_preinterpret_i8x8_u8x8(int8x8_t x) {
return __riscv_preinterpret_i8x8_u8x8(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u16x4_u8x8(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u16x4_u8x8(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u16x4_u8x8(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint8x8_t test_preinterpret_u16x4_u8x8(uint16x4_t x) {
return __riscv_preinterpret_u16x4_u8x8(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i16x4_u8x8(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i16x4_u8x8(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i16x4_u8x8(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint8x8_t test_preinterpret_i16x4_u8x8(int16x4_t x) {
return __riscv_preinterpret_i16x4_u8x8(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u32x2_u8x8(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u32x2_u8x8(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u32x2_u8x8(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint8x8_t test_preinterpret_u32x2_u8x8(uint32x2_t x) {
return __riscv_preinterpret_u32x2_u8x8(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i32x2_u8x8(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i32x2_u8x8(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i32x2_u8x8(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint8x8_t test_preinterpret_i32x2_u8x8(int32x2_t x) {
return __riscv_preinterpret_i32x2_u8x8(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u8x8_i8x8(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u8x8_i8x8(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u8x8_i8x8(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int8x8_t test_preinterpret_u8x8_i8x8(uint8x8_t x) {
return __riscv_preinterpret_u8x8_i8x8(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u16x4_i8x8(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u16x4_i8x8(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u16x4_i8x8(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int8x8_t test_preinterpret_u16x4_i8x8(uint16x4_t x) {
return __riscv_preinterpret_u16x4_i8x8(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i16x4_i8x8(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i16x4_i8x8(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i16x4_i8x8(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int8x8_t test_preinterpret_i16x4_i8x8(int16x4_t x) {
return __riscv_preinterpret_i16x4_i8x8(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u32x2_i8x8(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u32x2_i8x8(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u32x2_i8x8(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int8x8_t test_preinterpret_u32x2_i8x8(uint32x2_t x) {
return __riscv_preinterpret_u32x2_i8x8(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i32x2_i8x8(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i32x2_i8x8(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i32x2_i8x8(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int8x8_t test_preinterpret_i32x2_i8x8(int32x2_t x) {
return __riscv_preinterpret_i32x2_i8x8(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u8x8_u16x4(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u8x8_u16x4(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u8x8_u16x4(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint16x4_t test_preinterpret_u8x8_u16x4(uint8x8_t x) {
return __riscv_preinterpret_u8x8_u16x4(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i8x8_u16x4(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i8x8_u16x4(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i8x8_u16x4(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint16x4_t test_preinterpret_i8x8_u16x4(int8x8_t x) {
return __riscv_preinterpret_i8x8_u16x4(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i16x4_u16x4(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i16x4_u16x4(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i16x4_u16x4(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint16x4_t test_preinterpret_i16x4_u16x4(int16x4_t x) {
return __riscv_preinterpret_i16x4_u16x4(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u32x2_u16x4(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u32x2_u16x4(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u32x2_u16x4(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint16x4_t test_preinterpret_u32x2_u16x4(uint32x2_t x) {
return __riscv_preinterpret_u32x2_u16x4(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i32x2_u16x4(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i32x2_u16x4(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i32x2_u16x4(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint16x4_t test_preinterpret_i32x2_u16x4(int32x2_t x) {
return __riscv_preinterpret_i32x2_u16x4(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u8x8_i16x4(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u8x8_i16x4(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u8x8_i16x4(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int16x4_t test_preinterpret_u8x8_i16x4(uint8x8_t x) {
return __riscv_preinterpret_u8x8_i16x4(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i8x8_i16x4(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i8x8_i16x4(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i8x8_i16x4(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int16x4_t test_preinterpret_i8x8_i16x4(int8x8_t x) {
return __riscv_preinterpret_i8x8_i16x4(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u16x4_i16x4(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u16x4_i16x4(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u16x4_i16x4(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int16x4_t test_preinterpret_u16x4_i16x4(uint16x4_t x) {
return __riscv_preinterpret_u16x4_i16x4(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u32x2_i16x4(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u32x2_i16x4(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u32x2_i16x4(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int16x4_t test_preinterpret_u32x2_i16x4(uint32x2_t x) {
return __riscv_preinterpret_u32x2_i16x4(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i32x2_i16x4(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i32x2_i16x4(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i32x2_i16x4(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int16x4_t test_preinterpret_i32x2_i16x4(int32x2_t x) {
return __riscv_preinterpret_i32x2_i16x4(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u8x8_u32x2(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u8x8_u32x2(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u8x8_u32x2(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint32x2_t test_preinterpret_u8x8_u32x2(uint8x8_t x) {
return __riscv_preinterpret_u8x8_u32x2(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i8x8_u32x2(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i8x8_u32x2(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i8x8_u32x2(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint32x2_t test_preinterpret_i8x8_u32x2(int8x8_t x) {
return __riscv_preinterpret_i8x8_u32x2(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u16x4_u32x2(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u16x4_u32x2(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u16x4_u32x2(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint32x2_t test_preinterpret_u16x4_u32x2(uint16x4_t x) {
return __riscv_preinterpret_u16x4_u32x2(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i16x4_u32x2(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i16x4_u32x2(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i16x4_u32x2(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint32x2_t test_preinterpret_i16x4_u32x2(int16x4_t x) {
return __riscv_preinterpret_i16x4_u32x2(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i32x2_u32x2(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i32x2_u32x2(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i32x2_u32x2(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
uint32x2_t test_preinterpret_i32x2_u32x2(int32x2_t x) {
return __riscv_preinterpret_i32x2_u32x2(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u8x8_i32x2(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u8x8_i32x2(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u8x8_i32x2(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int32x2_t test_preinterpret_u8x8_i32x2(uint8x8_t x) {
return __riscv_preinterpret_u8x8_i32x2(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i8x8_i32x2(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i8x8_i32x2(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i8x8_i32x2(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int32x2_t test_preinterpret_i8x8_i32x2(int8x8_t x) {
return __riscv_preinterpret_i8x8_i32x2(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u16x4_i32x2(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u16x4_i32x2(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u16x4_i32x2(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int32x2_t test_preinterpret_u16x4_i32x2(uint16x4_t x) {
return __riscv_preinterpret_u16x4_i32x2(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_i16x4_i32x2(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_i16x4_i32x2(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_i16x4_i32x2(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int32x2_t test_preinterpret_i16x4_i32x2(int16x4_t x) {
return __riscv_preinterpret_i16x4_i32x2(x);
}
-// RV32-LABEL: define dso_local i64 @test_preinterpret_u32x2_i32x2(
-// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: ret i64 [[X_COERCE]]
-//
-// RV64-LABEL: define dso_local i64 @test_preinterpret_u32x2_i32x2(
-// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: ret i64 [[X_COERCE]]
+// CHECK-LABEL: define dso_local i64 @test_preinterpret_u32x2_i32x2(
+// CHECK-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: ret i64 [[X_COERCE]]
//
int32x2_t test_preinterpret_u32x2_i32x2(uint32x2_t x) {
return __riscv_preinterpret_u32x2_i32x2(x);
@@ -10315,265 +6731,157 @@ int32x2_t test_preinterpret_u32x2_i32x2(uint32x2_t x) {
/* Packed Narrowing Zip */
-// RV32-LABEL: define dso_local i32 @test_pnzip_i8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pnzip_i8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pnzip_i8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int8x4_t test_pnzip_i8x4(int16x2_t rs1, int16x2_t rs2) {
return __riscv_pnzip_i8x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_pnzip_u8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pnzip_u8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pnzip_u8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_pnzip_u8x4(uint16x2_t rs1, uint16x2_t rs2) {
return __riscv_pnzip_u8x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_pnziph_i8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pnziph_i8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
-//
-int8x4_t test_pnziph_i8x4(int16x2_t rs1, int16x2_t rs2) {
- return __riscv_pnziph_i8x4(rs1, rs2);
-}
-
-// RV32-LABEL: define dso_local i32 @test_pnziph_u8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pnziph_i8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
-// RV64-LABEL: define dso_local i32 @test_pnziph_u8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+int8x4_t test_pnziph_i8x4(int16x2_t rs1, int16x2_t rs2) {
+ return __riscv_pnziph_i8x4(rs1, rs2);
+}
+
+// CHECK-LABEL: define dso_local i32 @test_pnziph_u8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_pnziph_u8x4(uint16x2_t rs1, uint16x2_t rs2) {
return __riscv_pnziph_u8x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pnzip_i8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pnzip_i8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pnzip_i8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int8x8_t test_pnzip_i8x8(int16x4_t rs1, int16x4_t rs2) {
return __riscv_pnzip_i8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pnzip_u8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pnzip_u8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pnzip_u8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_pnzip_u8x8(uint16x4_t rs1, uint16x4_t rs2) {
return __riscv_pnzip_u8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pnzip_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pnzip_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pnzip_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_pnzip_i16x4(int32x2_t rs1, int32x2_t rs2) {
return __riscv_pnzip_i16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pnzip_u16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pnzip_u16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pnzip_u16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pnzip_u16x4(uint32x2_t rs1, uint32x2_t rs2) {
return __riscv_pnzip_u16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pnziph_i8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pnziph_i8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pnziph_i8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int8x8_t test_pnziph_i8x8(int16x4_t rs1, int16x4_t rs2) {
return __riscv_pnziph_i8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pnziph_u8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pnziph_u8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pnziph_u8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_pnziph_u8x8(uint16x4_t rs1, uint16x4_t rs2) {
return __riscv_pnziph_u8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pnziph_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pnziph_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pnziph_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_pnziph_i16x4(int32x2_t rs1, int32x2_t rs2) {
return __riscv_pnziph_i16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pnziph_u16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pnziph_u16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pnziph_u16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pnziph_u16x4(uint32x2_t rs1, uint32x2_t rs2) {
return __riscv_pnziph_u16x4(rs1, rs2);
@@ -10581,45 +6889,27 @@ uint16x4_t test_pnziph_u16x4(uint32x2_t rs1, uint32x2_t rs2) {
/* Packed Narrowing Clip Pair (32-bit) */
-// RV32-LABEL: define dso_local i32 @test_pnclipp_i8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pnclipp.v4i8.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_pnclipp_i8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pnclipp.v4i8.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_pnclipp_i8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pnclipp.v4i8.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
int8x4_t test_pnclipp_i8x4(int16x2_t rs1, int16x2_t rs2) {
return __riscv_pnclipp_i8x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_pnclipup_u8x4(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pnclipup.v4i8.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_pnclipup_u8x4(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pnclipup.v4i8.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_pnclipup_u8x4(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pnclipup.v4i8.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
uint8x4_t test_pnclipup_u8x4(uint16x2_t rs1, uint16x2_t rs2) {
return __riscv_pnclipup_u8x4(rs1, rs2);
@@ -10663,125 +6953,75 @@ uint16x2_t test_pnclipup_u16x2(uint32_t rs1, uint32_t rs2) {
/* Packed Narrowing Clip Pair (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_pnclipp_i8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pnclipp.v8i8.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pnclipp_i8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pnclipp.v8i8.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pnclipp_i8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pnclipp.v8i8.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int8x8_t test_pnclipp_i8x8(int16x4_t rs1, int16x4_t rs2) {
return __riscv_pnclipp_i8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pnclipup_u8x8(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pnclipup.v8i8.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pnclipup_u8x8(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pnclipup.v8i8.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pnclipup_u8x8(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pnclipup.v8i8.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
uint8x8_t test_pnclipup_u8x8(uint16x4_t rs1, uint16x4_t rs2) {
return __riscv_pnclipup_u8x8(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pnclipp_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pnclipp.v4i16.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pnclipp_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pnclipp.v4i16.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pnclipp_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pnclipp.v4i16.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int16x4_t test_pnclipp_i16x4(int32x2_t rs1, int32x2_t rs2) {
return __riscv_pnclipp_i16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pnclipup_u16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pnclipup.v4i16.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pnclipup_u16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pnclipup.v4i16.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pnclipup_u16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pnclipup.v4i16.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
uint16x4_t test_pnclipup_u16x4(uint32x2_t rs1, uint32x2_t rs2) {
return __riscv_pnclipup_u16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pnclipp_i32x2(
-// RV32-SAME: i64 noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.riscv.pnclipp.v2i32.i64(i64 [[RS1]], i64 [[RS2]])
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pnclipp_i32x2(
-// RV64-SAME: i64 noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.riscv.pnclipp.v2i32.i64(i64 [[RS1]], i64 [[RS2]])
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pnclipp_i32x2(
+// CHECK-SAME: i64 noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.riscv.pnclipp.v2i32.i64(i64 [[RS1]], i64 [[RS2]])
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
int32x2_t test_pnclipp_i32x2(int64_t rs1, int64_t rs2) {
return __riscv_pnclipp_i32x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pnclipup_u32x2(
-// RV32-SAME: i64 noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.riscv.pnclipup.v2i32.i64(i64 [[RS1]], i64 [[RS2]])
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pnclipup_u32x2(
-// RV64-SAME: i64 noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.riscv.pnclipup.v2i32.i64(i64 [[RS1]], i64 [[RS2]])
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pnclipup_u32x2(
+// CHECK-SAME: i64 noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.riscv.pnclipup.v2i32.i64(i64 [[RS1]], i64 [[RS2]])
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
uint32x2_t test_pnclipup_u32x2(uint64_t rs1, uint64_t rs2) {
return __riscv_pnclipup_u32x2(rs1, rs2);
@@ -10910,265 +7150,157 @@ int32_t test_mqracc_h11_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) {
/* Packed "Q-format" Multiply Parts Accumulate (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_pmqacc_h00_i32x2(
-// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqacc.h00.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
-// RV32-NEXT: ret i64 [[TMP4]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmqacc_h00_i32x2(
-// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqacc.h00.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
-// RV64-NEXT: ret i64 [[TMP4]]
+// CHECK-LABEL: define dso_local i64 @test_pmqacc_h00_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqacc.h00.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT: ret i64 [[TMP4]]
//
int32x2_t test_pmqacc_h00_i32x2(int32x2_t rd, int16x4_t rs1, int16x4_t rs2) {
return __riscv_pmqacc_h00_i32x2(rd, rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pmqacc_h01_i32x2(
-// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqacc.h01.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
-// RV32-NEXT: ret i64 [[TMP4]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmqacc_h01_i32x2(
-// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqacc.h01.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
-// RV64-NEXT: ret i64 [[TMP4]]
+// CHECK-LABEL: define dso_local i64 @test_pmqacc_h01_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqacc.h01.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT: ret i64 [[TMP4]]
//
int32x2_t test_pmqacc_h01_i32x2(int32x2_t rd, int16x4_t rs1, int16x4_t rs2) {
return __riscv_pmqacc_h01_i32x2(rd, rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pmqacc_h11_i32x2(
-// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqacc.h11.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
-// RV32-NEXT: ret i64 [[TMP4]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmqacc_h11_i32x2(
-// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqacc.h11.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
-// RV64-NEXT: ret i64 [[TMP4]]
+// CHECK-LABEL: define dso_local i64 @test_pmqacc_h11_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqacc.h11.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT: ret i64 [[TMP4]]
//
int32x2_t test_pmqacc_h11_i32x2(int32x2_t rd, int16x4_t rs1, int16x4_t rs2) {
return __riscv_pmqacc_h11_i32x2(rd, rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pmqracc_h00_i32x2(
-// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqracc.h00.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
-// RV32-NEXT: ret i64 [[TMP4]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmqracc_h00_i32x2(
-// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqracc.h00.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
-// RV64-NEXT: ret i64 [[TMP4]]
+// CHECK-LABEL: define dso_local i64 @test_pmqracc_h00_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqracc.h00.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT: ret i64 [[TMP4]]
//
int32x2_t test_pmqracc_h00_i32x2(int32x2_t rd, int16x4_t rs1, int16x4_t rs2) {
return __riscv_pmqracc_h00_i32x2(rd, rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pmqracc_h01_i32x2(
-// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqracc.h01.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
-// RV32-NEXT: ret i64 [[TMP4]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmqracc_h01_i32x2(
-// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqracc.h01.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
-// RV64-NEXT: ret i64 [[TMP4]]
+// CHECK-LABEL: define dso_local i64 @test_pmqracc_h01_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqracc.h01.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT: ret i64 [[TMP4]]
//
int32x2_t test_pmqracc_h01_i32x2(int32x2_t rd, int16x4_t rs1, int16x4_t rs2) {
return __riscv_pmqracc_h01_i32x2(rd, rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pmqracc_h11_i32x2(
-// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqracc.h11.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
-// RV32-NEXT: ret i64 [[TMP4]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmqracc_h11_i32x2(
-// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqracc.h11.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
-// RV64-NEXT: ret i64 [[TMP4]]
+// CHECK-LABEL: define dso_local i64 @test_pmqracc_h11_i32x2(
+// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmqracc.h11.v2i32.v4i16(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
+// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
+// CHECK-NEXT: ret i64 [[TMP4]]
//
int32x2_t test_pmqracc_h11_i32x2(int32x2_t rd, int16x4_t rs1, int16x4_t rs2) {
return __riscv_pmqracc_h11_i32x2(rd, rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_mqacc_w00_i64(
-// RV32-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.00.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_mqacc_w00_i64(
-// RV64-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.00.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_mqacc_w00_i64(
+// CHECK-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.00.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int64_t test_mqacc_w00_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) {
return __riscv_mqacc_w00_i64(rd, rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_mqacc_w01_i64(
-// RV32-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.01.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_mqacc_w01_i64(
-// RV64-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.01.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_mqacc_w01_i64(
+// CHECK-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.01.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int64_t test_mqacc_w01_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) {
return __riscv_mqacc_w01_i64(rd, rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_mqacc_w11_i64(
-// RV32-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.11.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_mqacc_w11_i64(
-// RV64-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.11.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_mqacc_w11_i64(
+// CHECK-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.11.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int64_t test_mqacc_w11_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) {
return __riscv_mqacc_w11_i64(rd, rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_mqracc_w00_i64(
-// RV32-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.00.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_mqracc_w00_i64(
-// RV64-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.00.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_mqracc_w00_i64(
+// CHECK-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.00.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int64_t test_mqracc_w00_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) {
return __riscv_mqracc_w00_i64(rd, rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_mqracc_w01_i64(
-// RV32-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.01.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_mqracc_w01_i64(
-// RV64-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.01.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_mqracc_w01_i64(
+// CHECK-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.01.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int64_t test_mqracc_w01_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) {
return __riscv_mqracc_w01_i64(rd, rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_mqracc_w11_i64(
-// RV32-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.11.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_mqracc_w11_i64(
-// RV64-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.11.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_mqracc_w11_i64(
+// CHECK-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.11.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int64_t test_mqracc_w11_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) {
return __riscv_mqracc_w11_i64(rd, rs1, rs2);
@@ -11176,89 +7308,53 @@ int64_t test_mqracc_w11_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) {
/* Packed Multiply High Parts (32-bit) */
-// RV32-LABEL: define dso_local i32 @test_pmulh_b0_i16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulh.b0.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmulh_b0_i16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulh.b0.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_pmulh_b0_i16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulh.b0.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
int16x2_t test_pmulh_b0_i16x2(int16x2_t rs1, int8x4_t rs2) {
return __riscv_pmulh_b0_i16x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_pmulh_b1_i16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulh.b1.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmulh_b1_i16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulh.b1.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_pmulh_b1_i16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulh.b1.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
int16x2_t test_pmulh_b1_i16x2(int16x2_t rs1, int8x4_t rs2) {
return __riscv_pmulh_b1_i16x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_pmulhsu_b0_i16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.b0.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmulhsu_b0_i16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.b0.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_pmulhsu_b0_i16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.b0.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
int16x2_t test_pmulhsu_b0_i16x2(int16x2_t rs1, uint8x4_t rs2) {
return __riscv_pmulhsu_b0_i16x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i32 @test_pmulhsu_b1_i16x2(
-// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.b1.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV32-NEXT: ret i32 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i32 @test_pmulhsu_b1_i16x2(
-// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.b1.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
-// RV64-NEXT: ret i32 [[TMP3]]
+// CHECK-LABEL: define dso_local i32 @test_pmulhsu_b1_i16x2(
+// CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.b1.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// CHECK-NEXT: ret i32 [[TMP3]]
//
int16x2_t test_pmulhsu_b1_i16x2(int16x2_t rs1, uint8x4_t rs2) {
return __riscv_pmulhsu_b1_i16x2(rs1, rs2);
@@ -11338,177 +7434,105 @@ int32_t test_mulhsu_h1_i32(int32_t rs1, uint16x2_t rs2) {
/* Packed Multiply High Parts (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_pmulh_b0_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulh.b0.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmulh_b0_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulh.b0.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pmulh_b0_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulh.b0.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int16x4_t test_pmulh_b0_i16x4(int16x4_t rs1, int8x8_t rs2) {
return __riscv_pmulh_b0_i16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pmulh_b1_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulh.b1.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmulh_b1_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulh.b1.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pmulh_b1_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulh.b1.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int16x4_t test_pmulh_b1_i16x4(int16x4_t rs1, int8x8_t rs2) {
return __riscv_pmulh_b1_i16x4(rs1, rs2);
}
-
-// RV32-LABEL: define dso_local i64 @test_pmulhsu_b0_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhsu.b0.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmulhsu_b0_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhsu.b0.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
-//
-int16x4_t test_pmulhsu_b0_i16x4(int16x4_t rs1, uint8x8_t rs2) {
- return __riscv_pmulhsu_b0_i16x4(rs1, rs2);
-}
-
-// RV32-LABEL: define dso_local i64 @test_pmulhsu_b1_i16x4(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhsu.b1.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmulhsu_b1_i16x4(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
-// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhsu.b1.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+
+// CHECK-LABEL: define dso_local i64 @test_pmulhsu_b0_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhsu.b0.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
+//
+int16x4_t test_pmulhsu_b0_i16x4(int16x4_t rs1, uint8x8_t rs2) {
+ return __riscv_pmulhsu_b0_i16x4(rs1, rs2);
+}
+
+// CHECK-LABEL: define dso_local i64 @test_pmulhsu_b1_i16x4(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhsu.b1.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int16x4_t test_pmulhsu_b1_i16x4(int16x4_t rs1, uint8x8_t rs2) {
return __riscv_pmulhsu_b1_i16x4(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pmulh_h0_i32x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulh.h0.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmulh_h0_i32x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulh.h0.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pmulh_h0_i32x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulh.h0.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int32x2_t test_pmulh_h0_i32x2(int32x2_t rs1, int16x4_t rs2) {
return __riscv_pmulh_h0_i32x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pmulh_h1_i32x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulh.h1.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmulh_h1_i32x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulh.h1.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pmulh_h1_i32x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulh.h1.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int32x2_t test_pmulh_h1_i32x2(int32x2_t rs1, int16x4_t rs2) {
return __riscv_pmulh_h1_i32x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pmulhsu_h0_i32x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhsu.h0.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmulhsu_h0_i32x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhsu.h0.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pmulhsu_h0_i32x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhsu.h0.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int32x2_t test_pmulhsu_h0_i32x2(int32x2_t rs1, uint16x4_t rs2) {
return __riscv_pmulhsu_h0_i32x2(rs1, rs2);
}
-// RV32-LABEL: define dso_local i64 @test_pmulhsu_h1_i32x2(
-// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhsu.h1.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]])
-// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pmulhsu_h1_i32x2(
-// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhsu.h1.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]])
-// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pmulhsu_h1_i32x2(
+// CHECK-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhsu.h1.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]])
+// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int32x2_t test_pmulhsu_h1_i32x2(int32x2_t rs1, uint16x4_t rs2) {
return __riscv_pmulhsu_h1_i32x2(rs1, rs2);
@@ -11516,73 +7540,45 @@ int32x2_t test_pmulhsu_h1_i32x2(int32x2_t rs1, uint16x4_t rs2) {
/* Packed Element Extract */
-// RV32-LABEL: define dso_local signext i8 @test_pget_i8x4_i8(
-// RV32-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[V_COERCE]], 24
-// RV32-NEXT: [[VECEXT_I:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i8
-// RV32-NEXT: ret i8 [[VECEXT_I]]
-//
-// RV64-LABEL: define dso_local signext i8 @test_pget_i8x4_i8(
-// RV64-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[V_COERCE]], 24
-// RV64-NEXT: [[VECEXT_I:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i8
-// RV64-NEXT: ret i8 [[VECEXT_I]]
+// CHECK-LABEL: define dso_local signext i8 @test_pget_i8x4_i8(
+// CHECK-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[V_COERCE]], 24
+// CHECK-NEXT: [[VECEXT_I:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i8
+// CHECK-NEXT: ret i8 [[VECEXT_I]]
//
int8_t test_pget_i8x4_i8(int8x4_t v) {
return __riscv_pget_i8x4_i8(v, 3);
}
-// RV32-LABEL: define dso_local zeroext i8 @test_pget_u8x4_u8(
-// RV32-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[V_COERCE]], 24
-// RV32-NEXT: [[VECEXT_I:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i8
-// RV32-NEXT: ret i8 [[VECEXT_I]]
-//
-// RV64-LABEL: define dso_local zeroext i8 @test_pget_u8x4_u8(
-// RV64-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[V_COERCE]], 24
-// RV64-NEXT: [[VECEXT_I:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i8
-// RV64-NEXT: ret i8 [[VECEXT_I]]
+// CHECK-LABEL: define dso_local zeroext i8 @test_pget_u8x4_u8(
+// CHECK-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[V_COERCE]], 24
+// CHECK-NEXT: [[VECEXT_I:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i8
+// CHECK-NEXT: ret i8 [[VECEXT_I]]
//
uint8_t test_pget_u8x4_u8(uint8x4_t v) {
return __riscv_pget_u8x4_u8(v, 3);
}
-// RV32-LABEL: define dso_local signext i16 @test_pget_i16x2_i16(
-// RV32-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[V_COERCE]], 16
-// RV32-NEXT: [[VECEXT_I:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i16
-// RV32-NEXT: ret i16 [[VECEXT_I]]
-//
-// RV64-LABEL: define dso_local signext i16 @test_pget_i16x2_i16(
-// RV64-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[V_COERCE]], 16
-// RV64-NEXT: [[VECEXT_I:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i16
-// RV64-NEXT: ret i16 [[VECEXT_I]]
+// CHECK-LABEL: define dso_local signext i16 @test_pget_i16x2_i16(
+// CHECK-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[V_COERCE]], 16
+// CHECK-NEXT: [[VECEXT_I:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i16
+// CHECK-NEXT: ret i16 [[VECEXT_I]]
//
int16_t test_pget_i16x2_i16(int16x2_t v) {
return __riscv_pget_i16x2_i16(v, 1);
}
-// RV32-LABEL: define dso_local zeroext i16 @test_pget_u16x2_u16(
-// RV32-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[V_COERCE]], 16
-// RV32-NEXT: [[VECEXT_I:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i16
-// RV32-NEXT: ret i16 [[VECEXT_I]]
-//
-// RV64-LABEL: define dso_local zeroext i16 @test_pget_u16x2_u16(
-// RV64-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[V_COERCE]], 16
-// RV64-NEXT: [[VECEXT_I:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i16
-// RV64-NEXT: ret i16 [[VECEXT_I]]
+// CHECK-LABEL: define dso_local zeroext i16 @test_pget_u16x2_u16(
+// CHECK-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[V_COERCE]], 16
+// CHECK-NEXT: [[VECEXT_I:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i16
+// CHECK-NEXT: ret i16 [[VECEXT_I]]
//
uint16_t test_pget_u16x2_u16(uint16x2_t v) {
return __riscv_pget_u16x2_u16(v, 1);
@@ -11698,145 +7694,85 @@ uint32_t test_pget_u32x2_u32(uint32x2_t v) {
/* Packed Store (32-bit) */
-// RV32-LABEL: define dso_local void @test_pst_i8x4(
-// RV32-SAME: ptr noundef [[P:%.*]], i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: store i32 [[V_COERCE]], ptr [[P]], align 1
-// RV32-NEXT: ret void
-//
-// RV64-LABEL: define dso_local void @test_pst_i8x4(
-// RV64-SAME: ptr noundef [[P:%.*]], i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: store i32 [[V_COERCE]], ptr [[P]], align 1
-// RV64-NEXT: ret void
+// CHECK-LABEL: define dso_local void @test_pst_i8x4(
+// CHECK-SAME: ptr noundef [[P:%.*]], i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: store i32 [[V_COERCE]], ptr [[P]], align 1
+// CHECK-NEXT: ret void
//
void test_pst_i8x4(int8_t *p, int8x4_t v) { __riscv_pst_i8x4(p, v); }
-// RV32-LABEL: define dso_local void @test_pst_u8x4(
-// RV32-SAME: ptr noundef [[P:%.*]], i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: store i32 [[V_COERCE]], ptr [[P]], align 1
-// RV32-NEXT: ret void
-//
-// RV64-LABEL: define dso_local void @test_pst_u8x4(
-// RV64-SAME: ptr noundef [[P:%.*]], i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: store i32 [[V_COERCE]], ptr [[P]], align 1
-// RV64-NEXT: ret void
+// CHECK-LABEL: define dso_local void @test_pst_u8x4(
+// CHECK-SAME: ptr noundef [[P:%.*]], i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: store i32 [[V_COERCE]], ptr [[P]], align 1
+// CHECK-NEXT: ret void
//
void test_pst_u8x4(uint8_t *p, uint8x4_t v) { __riscv_pst_u8x4(p, v); }
-// RV32-LABEL: define dso_local void @test_pst_i16x2(
-// RV32-SAME: ptr noundef [[P:%.*]], i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: store i32 [[V_COERCE]], ptr [[P]], align 1
-// RV32-NEXT: ret void
-//
-// RV64-LABEL: define dso_local void @test_pst_i16x2(
-// RV64-SAME: ptr noundef [[P:%.*]], i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: store i32 [[V_COERCE]], ptr [[P]], align 1
-// RV64-NEXT: ret void
+// CHECK-LABEL: define dso_local void @test_pst_i16x2(
+// CHECK-SAME: ptr noundef [[P:%.*]], i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: store i32 [[V_COERCE]], ptr [[P]], align 1
+// CHECK-NEXT: ret void
//
void test_pst_i16x2(int16_t *p, int16x2_t v) { __riscv_pst_i16x2(p, v); }
-// RV32-LABEL: define dso_local void @test_pst_u16x2(
-// RV32-SAME: ptr noundef [[P:%.*]], i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: store i32 [[V_COERCE]], ptr [[P]], align 1
-// RV32-NEXT: ret void
-//
-// RV64-LABEL: define dso_local void @test_pst_u16x2(
-// RV64-SAME: ptr noundef [[P:%.*]], i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: store i32 [[V_COERCE]], ptr [[P]], align 1
-// RV64-NEXT: ret void
+// CHECK-LABEL: define dso_local void @test_pst_u16x2(
+// CHECK-SAME: ptr noundef [[P:%.*]], i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: store i32 [[V_COERCE]], ptr [[P]], align 1
+// CHECK-NEXT: ret void
//
void test_pst_u16x2(uint16_t *p, uint16x2_t v) { __riscv_pst_u16x2(p, v); }
/* Packed Store (64-bit) */
-// RV32-LABEL: define dso_local void @test_pst_i8x8(
-// RV32-SAME: ptr noundef [[P:%.*]], i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: store i64 [[V_COERCE]], ptr [[P]], align 1
-// RV32-NEXT: ret void
-//
-// RV64-LABEL: define dso_local void @test_pst_i8x8(
-// RV64-SAME: ptr noundef [[P:%.*]], i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: store i64 [[V_COERCE]], ptr [[P]], align 1
-// RV64-NEXT: ret void
+// CHECK-LABEL: define dso_local void @test_pst_i8x8(
+// CHECK-SAME: ptr noundef [[P:%.*]], i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: store i64 [[V_COERCE]], ptr [[P]], align 1
+// CHECK-NEXT: ret void
//
void test_pst_i8x8(int8_t *p, int8x8_t v) { __riscv_pst_i8x8(p, v); }
-// RV32-LABEL: define dso_local void @test_pst_u8x8(
-// RV32-SAME: ptr noundef [[P:%.*]], i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: store i64 [[V_COERCE]], ptr [[P]], align 1
-// RV32-NEXT: ret void
-//
-// RV64-LABEL: define dso_local void @test_pst_u8x8(
-// RV64-SAME: ptr noundef [[P:%.*]], i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: store i64 [[V_COERCE]], ptr [[P]], align 1
-// RV64-NEXT: ret void
+// CHECK-LABEL: define dso_local void @test_pst_u8x8(
+// CHECK-SAME: ptr noundef [[P:%.*]], i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: store i64 [[V_COERCE]], ptr [[P]], align 1
+// CHECK-NEXT: ret void
//
void test_pst_u8x8(uint8_t *p, uint8x8_t v) { __riscv_pst_u8x8(p, v); }
-// RV32-LABEL: define dso_local void @test_pst_i16x4(
-// RV32-SAME: ptr noundef [[P:%.*]], i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: store i64 [[V_COERCE]], ptr [[P]], align 1
-// RV32-NEXT: ret void
-//
-// RV64-LABEL: define dso_local void @test_pst_i16x4(
-// RV64-SAME: ptr noundef [[P:%.*]], i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: store i64 [[V_COERCE]], ptr [[P]], align 1
-// RV64-NEXT: ret void
+// CHECK-LABEL: define dso_local void @test_pst_i16x4(
+// CHECK-SAME: ptr noundef [[P:%.*]], i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: store i64 [[V_COERCE]], ptr [[P]], align 1
+// CHECK-NEXT: ret void
//
void test_pst_i16x4(int16_t *p, int16x4_t v) { __riscv_pst_i16x4(p, v); }
-// RV32-LABEL: define dso_local void @test_pst_u16x4(
-// RV32-SAME: ptr noundef [[P:%.*]], i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: store i64 [[V_COERCE]], ptr [[P]], align 1
-// RV32-NEXT: ret void
-//
-// RV64-LABEL: define dso_local void @test_pst_u16x4(
-// RV64-SAME: ptr noundef [[P:%.*]], i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: store i64 [[V_COERCE]], ptr [[P]], align 1
-// RV64-NEXT: ret void
+// CHECK-LABEL: define dso_local void @test_pst_u16x4(
+// CHECK-SAME: ptr noundef [[P:%.*]], i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: store i64 [[V_COERCE]], ptr [[P]], align 1
+// CHECK-NEXT: ret void
//
void test_pst_u16x4(uint16_t *p, uint16x4_t v) { __riscv_pst_u16x4(p, v); }
-// RV32-LABEL: define dso_local void @test_pst_i32x2(
-// RV32-SAME: ptr noundef [[P:%.*]], i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: store i64 [[V_COERCE]], ptr [[P]], align 1
-// RV32-NEXT: ret void
-//
-// RV64-LABEL: define dso_local void @test_pst_i32x2(
-// RV64-SAME: ptr noundef [[P:%.*]], i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: store i64 [[V_COERCE]], ptr [[P]], align 1
-// RV64-NEXT: ret void
+// CHECK-LABEL: define dso_local void @test_pst_i32x2(
+// CHECK-SAME: ptr noundef [[P:%.*]], i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: store i64 [[V_COERCE]], ptr [[P]], align 1
+// CHECK-NEXT: ret void
//
void test_pst_i32x2(int32_t *p, int32x2_t v) { __riscv_pst_i32x2(p, v); }
-// RV32-LABEL: define dso_local void @test_pst_u32x2(
-// RV32-SAME: ptr noundef [[P:%.*]], i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: store i64 [[V_COERCE]], ptr [[P]], align 1
-// RV32-NEXT: ret void
-//
-// RV64-LABEL: define dso_local void @test_pst_u32x2(
-// RV64-SAME: ptr noundef [[P:%.*]], i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: store i64 [[V_COERCE]], ptr [[P]], align 1
-// RV64-NEXT: ret void
+// CHECK-LABEL: define dso_local void @test_pst_u32x2(
+// CHECK-SAME: ptr noundef [[P:%.*]], i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: store i64 [[V_COERCE]], ptr [[P]], align 1
+// CHECK-NEXT: ret void
//
void test_pst_u32x2(uint32_t *p, uint32x2_t v) { __riscv_pst_u32x2(p, v); }
@@ -11881,81 +7817,49 @@ void test_pst_i32x2_aligned(int32_t *p, int32x2_t v) {
/* Packed Element Insert (32-bit) */
-// RV32-LABEL: define dso_local i32 @test_pset_i8_i8x4(
-// RV32-SAME: i32 noundef [[V_COERCE:%.*]], i8 noundef signext [[E:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[V_COERCE]] to <4 x i8>
-// RV32-NEXT: [[VECINS_I:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[E]], i64 2
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[VECINS_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pset_i8_i8x4(
-// RV64-SAME: i32 noundef [[V_COERCE:%.*]], i8 noundef signext [[E:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[V_COERCE]] to <4 x i8>
-// RV64-NEXT: [[VECINS_I:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[E]], i64 2
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[VECINS_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_pset_i8_i8x4(
+// CHECK-SAME: i32 noundef [[V_COERCE:%.*]], i8 noundef signext [[E:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[V_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[VECINS_I:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[E]], i64 2
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[VECINS_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
int8x4_t test_pset_i8_i8x4(int8x4_t v, int8_t e) {
return __riscv_pset_i8_i8x4(v, e, 2);
}
-// RV32-LABEL: define dso_local i32 @test_pset_u8_u8x4(
-// RV32-SAME: i32 noundef [[V_COERCE:%.*]], i8 noundef zeroext [[E:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[V_COERCE]] to <4 x i8>
-// RV32-NEXT: [[VECINS_I:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[E]], i64 3
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[VECINS_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pset_u8_u8x4(
-// RV64-SAME: i32 noundef [[V_COERCE:%.*]], i8 noundef zeroext [[E:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[V_COERCE]] to <4 x i8>
-// RV64-NEXT: [[VECINS_I:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[E]], i64 3
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[VECINS_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_pset_u8_u8x4(
+// CHECK-SAME: i32 noundef [[V_COERCE:%.*]], i8 noundef zeroext [[E:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[V_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[VECINS_I:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[E]], i64 3
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[VECINS_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
uint8x4_t test_pset_u8_u8x4(uint8x4_t v, uint8_t e) {
return __riscv_pset_u8_u8x4(v, e, 3);
}
-// RV32-LABEL: define dso_local i32 @test_pset_i16_i16x2(
-// RV32-SAME: i32 noundef [[V_COERCE:%.*]], i16 noundef signext [[E:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[V_COERCE]] to <2 x i16>
-// RV32-NEXT: [[VECINS_I:%.*]] = insertelement <2 x i16> [[TMP0]], i16 [[E]], i64 1
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[VECINS_I]] to i32
-// RV32-NEXT: ret i32 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i32 @test_pset_i16_i16x2(
-// RV64-SAME: i32 noundef [[V_COERCE:%.*]], i16 noundef signext [[E:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[V_COERCE]] to <2 x i16>
-// RV64-NEXT: [[VECINS_I:%.*]] = insertelement <2 x i16> [[TMP0]], i16 [[E]], i64 1
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[VECINS_I]] to i32
-// RV64-NEXT: ret i32 [[TMP1]]
+// CHECK-LABEL: define dso_local i32 @test_pset_i16_i16x2(
+// CHECK-SAME: i32 noundef [[V_COERCE:%.*]], i16 noundef signext [[E:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[V_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[VECINS_I:%.*]] = insertelement <2 x i16> [[TMP0]], i16 [[E]], i64 1
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[VECINS_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP1]]
//
int16x2_t test_pset_i16_i16x2(int16x2_t v, int16_t e) {
return __riscv_pset_i16_i16x2(v, e, 1);
}
-// RV32-LABEL: define dso_local i32 @test_pset_u16_u16x2(
-// RV32-SAME: i32 noundef [[V_COERCE:%.*]], i16 noundef zeroext [[E:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = and i32 [[V_COERCE]], -65536
-// RV32-NEXT: [[TMP1:%.*]] = zext i16 [[E]] to i32
-// RV32-NEXT: [[TMP2:%.*]] = or disjoint i32 [[TMP0]], [[TMP1]]
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pset_u16_u16x2(
-// RV64-SAME: i32 noundef [[V_COERCE:%.*]], i16 noundef zeroext [[E:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = and i32 [[V_COERCE]], -65536
-// RV64-NEXT: [[TMP1:%.*]] = zext i16 [[E]] to i32
-// RV64-NEXT: [[TMP2:%.*]] = or disjoint i32 [[TMP0]], [[TMP1]]
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pset_u16_u16x2(
+// CHECK-SAME: i32 noundef [[V_COERCE:%.*]], i16 noundef zeroext [[E:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = and i32 [[V_COERCE]], -65536
+// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[E]] to i32
+// CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[TMP0]], [[TMP1]]
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_pset_u16_u16x2(uint16x2_t v, uint16_t e) {
return __riscv_pset_u16_u16x2(v, e, 0);
@@ -11963,81 +7867,49 @@ uint16x2_t test_pset_u16_u16x2(uint16x2_t v, uint16_t e) {
/* Packed Element Insert (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_pset_i8_i8x8(
-// RV32-SAME: i64 noundef [[V_COERCE:%.*]], i8 noundef signext [[E:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8>
-// RV32-NEXT: [[VECINS_I:%.*]] = insertelement <8 x i8> [[TMP0]], i8 [[E]], i64 5
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VECINS_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pset_i8_i8x8(
-// RV64-SAME: i64 noundef [[V_COERCE:%.*]], i8 noundef signext [[E:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8>
-// RV64-NEXT: [[VECINS_I:%.*]] = insertelement <8 x i8> [[TMP0]], i8 [[E]], i64 5
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VECINS_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pset_i8_i8x8(
+// CHECK-SAME: i64 noundef [[V_COERCE:%.*]], i8 noundef signext [[E:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[VECINS_I:%.*]] = insertelement <8 x i8> [[TMP0]], i8 [[E]], i64 5
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VECINS_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
int8x8_t test_pset_i8_i8x8(int8x8_t v, int8_t e) {
return __riscv_pset_i8_i8x8(v, e, 5);
}
-// RV32-LABEL: define dso_local i64 @test_pset_u8_u8x8(
-// RV32-SAME: i64 noundef [[V_COERCE:%.*]], i8 noundef zeroext [[E:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8>
-// RV32-NEXT: [[VECINS_I:%.*]] = insertelement <8 x i8> [[TMP0]], i8 [[E]], i64 7
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VECINS_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pset_u8_u8x8(
-// RV64-SAME: i64 noundef [[V_COERCE:%.*]], i8 noundef zeroext [[E:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8>
-// RV64-NEXT: [[VECINS_I:%.*]] = insertelement <8 x i8> [[TMP0]], i8 [[E]], i64 7
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VECINS_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pset_u8_u8x8(
+// CHECK-SAME: i64 noundef [[V_COERCE:%.*]], i8 noundef zeroext [[E:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[VECINS_I:%.*]] = insertelement <8 x i8> [[TMP0]], i8 [[E]], i64 7
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VECINS_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
uint8x8_t test_pset_u8_u8x8(uint8x8_t v, uint8_t e) {
return __riscv_pset_u8_u8x8(v, e, 7);
}
-// RV32-LABEL: define dso_local i64 @test_pset_i16_i16x4(
-// RV32-SAME: i64 noundef [[V_COERCE:%.*]], i16 noundef signext [[E:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16>
-// RV32-NEXT: [[VECINS_I:%.*]] = insertelement <4 x i16> [[TMP0]], i16 [[E]], i64 3
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINS_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pset_i16_i16x4(
-// RV64-SAME: i64 noundef [[V_COERCE:%.*]], i16 noundef signext [[E:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16>
-// RV64-NEXT: [[VECINS_I:%.*]] = insertelement <4 x i16> [[TMP0]], i16 [[E]], i64 3
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINS_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pset_i16_i16x4(
+// CHECK-SAME: i64 noundef [[V_COERCE:%.*]], i16 noundef signext [[E:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[VECINS_I:%.*]] = insertelement <4 x i16> [[TMP0]], i16 [[E]], i64 3
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINS_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
int16x4_t test_pset_i16_i16x4(int16x4_t v, int16_t e) {
return __riscv_pset_i16_i16x4(v, e, 3);
}
-// RV32-LABEL: define dso_local i64 @test_pset_u16_u16x4(
-// RV32-SAME: i64 noundef [[V_COERCE:%.*]], i16 noundef zeroext [[E:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16>
-// RV32-NEXT: [[VECINS_I:%.*]] = insertelement <4 x i16> [[TMP0]], i16 [[E]], i64 2
-// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINS_I]] to i64
-// RV32-NEXT: ret i64 [[TMP1]]
-//
-// RV64-LABEL: define dso_local i64 @test_pset_u16_u16x4(
-// RV64-SAME: i64 noundef [[V_COERCE:%.*]], i16 noundef zeroext [[E:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16>
-// RV64-NEXT: [[VECINS_I:%.*]] = insertelement <4 x i16> [[TMP0]], i16 [[E]], i64 2
-// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINS_I]] to i64
-// RV64-NEXT: ret i64 [[TMP1]]
+// CHECK-LABEL: define dso_local i64 @test_pset_u16_u16x4(
+// CHECK-SAME: i64 noundef [[V_COERCE:%.*]], i16 noundef zeroext [[E:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[VECINS_I:%.*]] = insertelement <4 x i16> [[TMP0]], i16 [[E]], i64 2
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINS_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP1]]
//
uint16x4_t test_pset_u16_u16x4(uint16x4_t v, uint16_t e) {
return __riscv_pset_u16_u16x4(v, e, 2);
@@ -12085,89 +7957,53 @@ uint32x2_t test_pset_u32_u32x2(uint32x2_t v, uint32_t e) {
/* Packed Element Join (32-bit) */
-// RV32-LABEL: define dso_local i32 @test_pjoin4_i8x4(
-// RV32-SAME: i8 noundef signext [[E0:%.*]], i8 noundef signext [[E1:%.*]], i8 noundef signext [[E2:%.*]], i8 noundef signext [[E3:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[E0]], i64 0
-// RV32-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i8> [[VECINIT_I]], i8 [[E1]], i64 1
-// RV32-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i8> [[VECINIT1_I]], i8 [[E2]], i64 2
-// RV32-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i8> [[VECINIT2_I]], i8 [[E3]], i64 3
-// RV32-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[VECINIT3_I]] to i32
-// RV32-NEXT: ret i32 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i32 @test_pjoin4_i8x4(
-// RV64-SAME: i8 noundef signext [[E0:%.*]], i8 noundef signext [[E1:%.*]], i8 noundef signext [[E2:%.*]], i8 noundef signext [[E3:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[E0]], i64 0
-// RV64-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i8> [[VECINIT_I]], i8 [[E1]], i64 1
-// RV64-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i8> [[VECINIT1_I]], i8 [[E2]], i64 2
-// RV64-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i8> [[VECINIT2_I]], i8 [[E3]], i64 3
-// RV64-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[VECINIT3_I]] to i32
-// RV64-NEXT: ret i32 [[TMP0]]
+// CHECK-LABEL: define dso_local i32 @test_pjoin4_i8x4(
+// CHECK-SAME: i8 noundef signext [[E0:%.*]], i8 noundef signext [[E1:%.*]], i8 noundef signext [[E2:%.*]], i8 noundef signext [[E3:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[E0]], i64 0
+// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i8> [[VECINIT_I]], i8 [[E1]], i64 1
+// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i8> [[VECINIT1_I]], i8 [[E2]], i64 2
+// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i8> [[VECINIT2_I]], i8 [[E3]], i64 3
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[VECINIT3_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP0]]
//
int8x4_t test_pjoin4_i8x4(int8_t e0, int8_t e1, int8_t e2, int8_t e3) {
return __riscv_pjoin4_i8x4(e0, e1, e2, e3);
}
-// RV32-LABEL: define dso_local i32 @test_pjoin4_u8x4(
-// RV32-SAME: i8 noundef zeroext [[E0:%.*]], i8 noundef zeroext [[E1:%.*]], i8 noundef zeroext [[E2:%.*]], i8 noundef zeroext [[E3:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[E0]], i64 0
-// RV32-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i8> [[VECINIT_I]], i8 [[E1]], i64 1
-// RV32-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i8> [[VECINIT1_I]], i8 [[E2]], i64 2
-// RV32-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i8> [[VECINIT2_I]], i8 [[E3]], i64 3
-// RV32-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[VECINIT3_I]] to i32
-// RV32-NEXT: ret i32 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i32 @test_pjoin4_u8x4(
-// RV64-SAME: i8 noundef zeroext [[E0:%.*]], i8 noundef zeroext [[E1:%.*]], i8 noundef zeroext [[E2:%.*]], i8 noundef zeroext [[E3:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[E0]], i64 0
-// RV64-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i8> [[VECINIT_I]], i8 [[E1]], i64 1
-// RV64-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i8> [[VECINIT1_I]], i8 [[E2]], i64 2
-// RV64-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i8> [[VECINIT2_I]], i8 [[E3]], i64 3
-// RV64-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[VECINIT3_I]] to i32
-// RV64-NEXT: ret i32 [[TMP0]]
+// CHECK-LABEL: define dso_local i32 @test_pjoin4_u8x4(
+// CHECK-SAME: i8 noundef zeroext [[E0:%.*]], i8 noundef zeroext [[E1:%.*]], i8 noundef zeroext [[E2:%.*]], i8 noundef zeroext [[E3:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[E0]], i64 0
+// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i8> [[VECINIT_I]], i8 [[E1]], i64 1
+// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i8> [[VECINIT1_I]], i8 [[E2]], i64 2
+// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i8> [[VECINIT2_I]], i8 [[E3]], i64 3
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[VECINIT3_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP0]]
//
uint8x4_t test_pjoin4_u8x4(uint8_t e0, uint8_t e1, uint8_t e2, uint8_t e3) {
return __riscv_pjoin4_u8x4(e0, e1, e2, e3);
}
-// RV32-LABEL: define dso_local i32 @test_pjoin2_i16x2(
-// RV32-SAME: i16 noundef signext [[E0:%.*]], i16 noundef signext [[E1:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[E0]], i64 0
-// RV32-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i16> [[VECINIT_I]], i16 [[E1]], i64 1
-// RV32-NEXT: [[TMP0:%.*]] = bitcast <2 x i16> [[VECINIT1_I]] to i32
-// RV32-NEXT: ret i32 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i32 @test_pjoin2_i16x2(
-// RV64-SAME: i16 noundef signext [[E0:%.*]], i16 noundef signext [[E1:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[E0]], i64 0
-// RV64-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i16> [[VECINIT_I]], i16 [[E1]], i64 1
-// RV64-NEXT: [[TMP0:%.*]] = bitcast <2 x i16> [[VECINIT1_I]] to i32
-// RV64-NEXT: ret i32 [[TMP0]]
+// CHECK-LABEL: define dso_local i32 @test_pjoin2_i16x2(
+// CHECK-SAME: i16 noundef signext [[E0:%.*]], i16 noundef signext [[E1:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[E0]], i64 0
+// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i16> [[VECINIT_I]], i16 [[E1]], i64 1
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i16> [[VECINIT1_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP0]]
//
int16x2_t test_pjoin2_i16x2(int16_t e0, int16_t e1) {
return __riscv_pjoin2_i16x2(e0, e1);
}
-// RV32-LABEL: define dso_local i32 @test_pjoin2_u16x2(
-// RV32-SAME: i16 noundef zeroext [[E0:%.*]], i16 noundef zeroext [[E1:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[E0]], i64 0
-// RV32-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i16> [[VECINIT_I]], i16 [[E1]], i64 1
-// RV32-NEXT: [[TMP0:%.*]] = bitcast <2 x i16> [[VECINIT1_I]] to i32
-// RV32-NEXT: ret i32 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i32 @test_pjoin2_u16x2(
-// RV64-SAME: i16 noundef zeroext [[E0:%.*]], i16 noundef zeroext [[E1:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[E0]], i64 0
-// RV64-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i16> [[VECINIT_I]], i16 [[E1]], i64 1
-// RV64-NEXT: [[TMP0:%.*]] = bitcast <2 x i16> [[VECINIT1_I]] to i32
-// RV64-NEXT: ret i32 [[TMP0]]
+// CHECK-LABEL: define dso_local i32 @test_pjoin2_u16x2(
+// CHECK-SAME: i16 noundef zeroext [[E0:%.*]], i16 noundef zeroext [[E1:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[E0]], i64 0
+// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i16> [[VECINIT_I]], i16 [[E1]], i64 1
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i16> [[VECINIT1_I]] to i32
+// CHECK-NEXT: ret i32 [[TMP0]]
//
uint16x2_t test_pjoin2_u16x2(uint16_t e0, uint16_t e1) {
return __riscv_pjoin2_u16x2(e0, e1);
@@ -12175,50 +8011,30 @@ uint16x2_t test_pjoin2_u16x2(uint16_t e0, uint16_t e1) {
/* Packed Element Join (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_pjoin4_i16x4(
-// RV32-SAME: i16 noundef signext [[E0:%.*]], i16 noundef signext [[E1:%.*]], i16 noundef signext [[E2:%.*]], i16 noundef signext [[E3:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[E0]], i64 0
-// RV32-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[E1]], i64 1
-// RV32-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[E2]], i64 2
-// RV32-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[E3]], i64 3
-// RV32-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to i64
-// RV32-NEXT: ret i64 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i64 @test_pjoin4_i16x4(
-// RV64-SAME: i16 noundef signext [[E0:%.*]], i16 noundef signext [[E1:%.*]], i16 noundef signext [[E2:%.*]], i16 noundef signext [[E3:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[E0]], i64 0
-// RV64-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[E1]], i64 1
-// RV64-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[E2]], i64 2
-// RV64-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[E3]], i64 3
-// RV64-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to i64
-// RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-LABEL: define dso_local i64 @test_pjoin4_i16x4(
+// CHECK-SAME: i16 noundef signext [[E0:%.*]], i16 noundef signext [[E1:%.*]], i16 noundef signext [[E2:%.*]], i16 noundef signext [[E3:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[E0]], i64 0
+// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[E1]], i64 1
+// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[E2]], i64 2
+// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[E3]], i64 3
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP0]]
//
int16x4_t test_pjoin4_i16x4(int16_t e0, int16_t e1, int16_t e2,
int16_t e3) {
return __riscv_pjoin4_i16x4(e0, e1, e2, e3);
}
-// RV32-LABEL: define dso_local i64 @test_pjoin4_u16x4(
-// RV32-SAME: i16 noundef zeroext [[E0:%.*]], i16 noundef zeroext [[E1:%.*]], i16 noundef zeroext [[E2:%.*]], i16 noundef zeroext [[E3:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[E0]], i64 0
-// RV32-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[E1]], i64 1
-// RV32-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[E2]], i64 2
-// RV32-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[E3]], i64 3
-// RV32-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to i64
-// RV32-NEXT: ret i64 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i64 @test_pjoin4_u16x4(
-// RV64-SAME: i16 noundef zeroext [[E0:%.*]], i16 noundef zeroext [[E1:%.*]], i16 noundef zeroext [[E2:%.*]], i16 noundef zeroext [[E3:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[E0]], i64 0
-// RV64-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[E1]], i64 1
-// RV64-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[E2]], i64 2
-// RV64-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[E3]], i64 3
-// RV64-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to i64
-// RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-LABEL: define dso_local i64 @test_pjoin4_u16x4(
+// CHECK-SAME: i16 noundef zeroext [[E0:%.*]], i16 noundef zeroext [[E1:%.*]], i16 noundef zeroext [[E2:%.*]], i16 noundef zeroext [[E3:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[E0]], i64 0
+// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[E1]], i64 1
+// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[E2]], i64 2
+// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[E3]], i64 3
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP0]]
//
uint16x4_t test_pjoin4_u16x4(uint16_t e0, uint16_t e1, uint16_t e2,
uint16_t e3) {
@@ -12266,162 +8082,102 @@ uint32x2_t test_pjoin2_u32x2(uint32_t e0, uint32_t e1) {
}
/* Packed Load (32-bit) */
-// RV32-LABEL: define dso_local i32 @test_pld_i8x4(
-// RV32-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = load i32, ptr [[P]], align 1
-// RV32-NEXT: ret i32 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i32 @test_pld_i8x4(
-// RV64-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = load i32, ptr [[P]], align 1
-// RV64-NEXT: ret i32 [[TMP0]]
+// CHECK-LABEL: define dso_local i32 @test_pld_i8x4(
+// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[P]], align 1
+// CHECK-NEXT: ret i32 [[TMP0]]
//
int8x4_t test_pld_i8x4(int8_t *p) {
return __riscv_pld_i8x4(p);
}
-// RV32-LABEL: define dso_local i32 @test_pld_u8x4(
-// RV32-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = load i32, ptr [[P]], align 1
-// RV32-NEXT: ret i32 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i32 @test_pld_u8x4(
-// RV64-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = load i32, ptr [[P]], align 1
-// RV64-NEXT: ret i32 [[TMP0]]
+// CHECK-LABEL: define dso_local i32 @test_pld_u8x4(
+// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[P]], align 1
+// CHECK-NEXT: ret i32 [[TMP0]]
//
uint8x4_t test_pld_u8x4(uint8_t *p) {
return __riscv_pld_u8x4(p);
}
-// RV32-LABEL: define dso_local i32 @test_pld_i16x2(
-// RV32-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = load i32, ptr [[P]], align 1
-// RV32-NEXT: ret i32 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i32 @test_pld_i16x2(
-// RV64-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = load i32, ptr [[P]], align 1
-// RV64-NEXT: ret i32 [[TMP0]]
+// CHECK-LABEL: define dso_local i32 @test_pld_i16x2(
+// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[P]], align 1
+// CHECK-NEXT: ret i32 [[TMP0]]
//
int16x2_t test_pld_i16x2(int16_t *p) {
return __riscv_pld_i16x2(p);
}
-// RV32-LABEL: define dso_local i32 @test_pld_u16x2(
-// RV32-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = load i32, ptr [[P]], align 1
-// RV32-NEXT: ret i32 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i32 @test_pld_u16x2(
-// RV64-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = load i32, ptr [[P]], align 1
-// RV64-NEXT: ret i32 [[TMP0]]
+// CHECK-LABEL: define dso_local i32 @test_pld_u16x2(
+// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[P]], align 1
+// CHECK-NEXT: ret i32 [[TMP0]]
//
uint16x2_t test_pld_u16x2(uint16_t *p) {
return __riscv_pld_u16x2(p);
}
-/* Packed Load (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_pld_i8x8(
-// RV32-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = load i64, ptr [[P]], align 1
-// RV32-NEXT: ret i64 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i64 @test_pld_i8x8(
-// RV64-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = load i64, ptr [[P]], align 1
-// RV64-NEXT: ret i64 [[TMP0]]
+/* Packed Load (64-bit) */
+// CHECK-LABEL: define dso_local i64 @test_pld_i8x8(
+// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[P]], align 1
+// CHECK-NEXT: ret i64 [[TMP0]]
//
int8x8_t test_pld_i8x8(int8_t *p) {
return __riscv_pld_i8x8(p);
}
-// RV32-LABEL: define dso_local i64 @test_pld_u8x8(
-// RV32-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = load i64, ptr [[P]], align 1
-// RV32-NEXT: ret i64 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i64 @test_pld_u8x8(
-// RV64-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = load i64, ptr [[P]], align 1
-// RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-LABEL: define dso_local i64 @test_pld_u8x8(
+// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[P]], align 1
+// CHECK-NEXT: ret i64 [[TMP0]]
//
uint8x8_t test_pld_u8x8(uint8_t *p) {
return __riscv_pld_u8x8(p);
}
-// RV32-LABEL: define dso_local i64 @test_pld_i16x4(
-// RV32-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = load i64, ptr [[P]], align 1
-// RV32-NEXT: ret i64 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i64 @test_pld_i16x4(
-// RV64-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = load i64, ptr [[P]], align 1
-// RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-LABEL: define dso_local i64 @test_pld_i16x4(
+// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[P]], align 1
+// CHECK-NEXT: ret i64 [[TMP0]]
//
int16x4_t test_pld_i16x4(int16_t *p) {
return __riscv_pld_i16x4(p);
}
-// RV32-LABEL: define dso_local i64 @test_pld_u16x4(
-// RV32-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = load i64, ptr [[P]], align 1
-// RV32-NEXT: ret i64 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i64 @test_pld_u16x4(
-// RV64-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = load i64, ptr [[P]], align 1
-// RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-LABEL: define dso_local i64 @test_pld_u16x4(
+// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[P]], align 1
+// CHECK-NEXT: ret i64 [[TMP0]]
//
uint16x4_t test_pld_u16x4(uint16_t *p) {
return __riscv_pld_u16x4(p);
}
-// RV32-LABEL: define dso_local i64 @test_pld_i32x2(
-// RV32-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = load i64, ptr [[P]], align 1
-// RV32-NEXT: ret i64 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i64 @test_pld_i32x2(
-// RV64-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = load i64, ptr [[P]], align 1
-// RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-LABEL: define dso_local i64 @test_pld_i32x2(
+// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[P]], align 1
+// CHECK-NEXT: ret i64 [[TMP0]]
//
int32x2_t test_pld_i32x2(int32_t *p) {
return __riscv_pld_i32x2(p);
}
-// RV32-LABEL: define dso_local i64 @test_pld_u32x2(
-// RV32-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = load i64, ptr [[P]], align 1
-// RV32-NEXT: ret i64 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i64 @test_pld_u32x2(
-// RV64-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = load i64, ptr [[P]], align 1
-// RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-LABEL: define dso_local i64 @test_pld_u32x2(
+// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[P]], align 1
+// CHECK-NEXT: ret i64 [[TMP0]]
//
uint32x2_t test_pld_u32x2(uint32_t *p) {
return __riscv_pld_u32x2(p);
@@ -12467,89 +8223,53 @@ int32x2_t test_pld_i32x2_aligned(int32_t *p) {
/* Packed Subvector Join */
-// RV32-LABEL: define dso_local i64 @test_pjoin2_i8x8(
-// RV32-SAME: i32 noundef [[LO_COERCE:%.*]], i32 noundef [[HI_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[LO_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[HI_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pjoin2_i8x8(
-// RV64-SAME: i32 noundef [[LO_COERCE:%.*]], i32 noundef [[HI_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[LO_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[HI_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pjoin2_i8x8(
+// CHECK-SAME: i32 noundef [[LO_COERCE:%.*]], i32 noundef [[HI_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[LO_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[HI_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int8x8_t test_pjoin2_i8x8(int8x4_t lo, int8x4_t hi) {
return __riscv_pjoin2_i8x8(lo, hi);
}
-// RV32-LABEL: define dso_local i64 @test_pjoin2_u8x8(
-// RV32-SAME: i32 noundef [[LO_COERCE:%.*]], i32 noundef [[HI_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[LO_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[HI_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pjoin2_u8x8(
-// RV64-SAME: i32 noundef [[LO_COERCE:%.*]], i32 noundef [[HI_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[LO_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[HI_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pjoin2_u8x8(
+// CHECK-SAME: i32 noundef [[LO_COERCE:%.*]], i32 noundef [[HI_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[LO_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[HI_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint8x8_t test_pjoin2_u8x8(uint8x4_t lo, uint8x4_t hi) {
return __riscv_pjoin2_u8x8(lo, hi);
}
-// RV32-LABEL: define dso_local i64 @test_pjoin2_i16x4(
-// RV32-SAME: i32 noundef [[LO_COERCE:%.*]], i32 noundef [[HI_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[LO_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[HI_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pjoin2_i16x4(
-// RV64-SAME: i32 noundef [[LO_COERCE:%.*]], i32 noundef [[HI_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[LO_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[HI_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pjoin2_i16x4(
+// CHECK-SAME: i32 noundef [[LO_COERCE:%.*]], i32 noundef [[HI_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[LO_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[HI_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_pjoin2_i16x4(int16x2_t lo, int16x2_t hi) {
return __riscv_pjoin2_i16x4(lo, hi);
}
-// RV32-LABEL: define dso_local i64 @test_pjoin2_u16x4(
-// RV32-SAME: i32 noundef [[LO_COERCE:%.*]], i32 noundef [[HI_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[LO_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[HI_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pjoin2_u16x4(
-// RV64-SAME: i32 noundef [[LO_COERCE:%.*]], i32 noundef [[HI_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[LO_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[HI_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pjoin2_u16x4(
+// CHECK-SAME: i32 noundef [[LO_COERCE:%.*]], i32 noundef [[HI_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[LO_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[HI_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pjoin2_u16x4(uint16x2_t lo, uint16x2_t hi) {
return __riscv_pjoin2_u16x4(lo, hi);
@@ -12557,31 +8277,18 @@ uint16x4_t test_pjoin2_u16x4(uint16x2_t lo, uint16x2_t hi) {
/* Packed Subvector Extract */
-// RV32-LABEL: define dso_local i32 @test_pget_i8x8_i8x4(
-// RV32-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV32: [[COND_TRUE_I]]:
-// RV32-NEXT: br label %[[__RISCV_PGET_I8X8_I8X4_EXIT:.*]]
-// RV32: [[COND_FALSE_I]]:
-// RV32-NEXT: [[SHUFFLE2_I_EXTRACT:%.*]] = trunc i64 [[V_COERCE]] to i32
-// RV32-NEXT: br label %[[__RISCV_PGET_I8X8_I8X4_EXIT]]
-// RV32: [[__RISCV_PGET_I8X8_I8X4_EXIT]]:
-// RV32-NEXT: [[TMP0:%.*]] = phi i32 [ poison, %[[COND_TRUE_I]] ], [ [[SHUFFLE2_I_EXTRACT]], %[[COND_FALSE_I]] ]
-// RV32-NEXT: ret i32 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i32 @test_pget_i8x8_i8x4(
-// RV64-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV64: [[COND_TRUE_I]]:
-// RV64-NEXT: br label %[[__RISCV_PGET_I8X8_I8X4_EXIT:.*]]
-// RV64: [[COND_FALSE_I]]:
-// RV64-NEXT: [[SHUFFLE2_I_EXTRACT:%.*]] = trunc i64 [[V_COERCE]] to i32
-// RV64-NEXT: br label %[[__RISCV_PGET_I8X8_I8X4_EXIT]]
-// RV64: [[__RISCV_PGET_I8X8_I8X4_EXIT]]:
-// RV64-NEXT: [[TMP0:%.*]] = phi i32 [ poison, %[[COND_TRUE_I]] ], [ [[SHUFFLE2_I_EXTRACT]], %[[COND_FALSE_I]] ]
-// RV64-NEXT: ret i32 [[TMP0]]
+// CHECK-LABEL: define dso_local i32 @test_pget_i8x8_i8x4(
+// CHECK-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
+// CHECK: [[COND_TRUE_I]]:
+// CHECK-NEXT: br label %[[__RISCV_PGET_I8X8_I8X4_EXIT:.*]]
+// CHECK: [[COND_FALSE_I]]:
+// CHECK-NEXT: [[SHUFFLE2_I_EXTRACT:%.*]] = trunc i64 [[V_COERCE]] to i32
+// CHECK-NEXT: br label %[[__RISCV_PGET_I8X8_I8X4_EXIT]]
+// CHECK: [[__RISCV_PGET_I8X8_I8X4_EXIT]]:
+// CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ poison, %[[COND_TRUE_I]] ], [ [[SHUFFLE2_I_EXTRACT]], %[[COND_FALSE_I]] ]
+// CHECK-NEXT: ret i32 [[TMP0]]
//
int8x4_t test_pget_i8x8_i8x4(int8x8_t v) {
return __riscv_pget_i8x8_i8x4(v, 0);
@@ -12619,31 +8326,18 @@ int8x4_t test_pget_i8x8_i8x4_idx1(int8x8_t v) {
return __riscv_pget_i8x8_i8x4(v, 1);
}
-// RV32-LABEL: define dso_local i32 @test_pget_u8x8_u8x4(
-// RV32-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV32: [[COND_TRUE_I]]:
-// RV32-NEXT: br label %[[__RISCV_PGET_U8X8_U8X4_EXIT:.*]]
-// RV32: [[COND_FALSE_I]]:
-// RV32-NEXT: [[SHUFFLE2_I_EXTRACT:%.*]] = trunc i64 [[V_COERCE]] to i32
-// RV32-NEXT: br label %[[__RISCV_PGET_U8X8_U8X4_EXIT]]
-// RV32: [[__RISCV_PGET_U8X8_U8X4_EXIT]]:
-// RV32-NEXT: [[TMP0:%.*]] = phi i32 [ poison, %[[COND_TRUE_I]] ], [ [[SHUFFLE2_I_EXTRACT]], %[[COND_FALSE_I]] ]
-// RV32-NEXT: ret i32 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i32 @test_pget_u8x8_u8x4(
-// RV64-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV64: [[COND_TRUE_I]]:
-// RV64-NEXT: br label %[[__RISCV_PGET_U8X8_U8X4_EXIT:.*]]
-// RV64: [[COND_FALSE_I]]:
-// RV64-NEXT: [[SHUFFLE2_I_EXTRACT:%.*]] = trunc i64 [[V_COERCE]] to i32
-// RV64-NEXT: br label %[[__RISCV_PGET_U8X8_U8X4_EXIT]]
-// RV64: [[__RISCV_PGET_U8X8_U8X4_EXIT]]:
-// RV64-NEXT: [[TMP0:%.*]] = phi i32 [ poison, %[[COND_TRUE_I]] ], [ [[SHUFFLE2_I_EXTRACT]], %[[COND_FALSE_I]] ]
-// RV64-NEXT: ret i32 [[TMP0]]
+// CHECK-LABEL: define dso_local i32 @test_pget_u8x8_u8x4(
+// CHECK-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
+// CHECK: [[COND_TRUE_I]]:
+// CHECK-NEXT: br label %[[__RISCV_PGET_U8X8_U8X4_EXIT:.*]]
+// CHECK: [[COND_FALSE_I]]:
+// CHECK-NEXT: [[SHUFFLE2_I_EXTRACT:%.*]] = trunc i64 [[V_COERCE]] to i32
+// CHECK-NEXT: br label %[[__RISCV_PGET_U8X8_U8X4_EXIT]]
+// CHECK: [[__RISCV_PGET_U8X8_U8X4_EXIT]]:
+// CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ poison, %[[COND_TRUE_I]] ], [ [[SHUFFLE2_I_EXTRACT]], %[[COND_FALSE_I]] ]
+// CHECK-NEXT: ret i32 [[TMP0]]
//
uint8x4_t test_pget_u8x8_u8x4(uint8x8_t v) {
return __riscv_pget_u8x8_u8x4(v, 0);
@@ -12681,31 +8375,18 @@ uint8x4_t test_pget_u8x8_u8x4_idx1(uint8x8_t v) {
return __riscv_pget_u8x8_u8x4(v, 1);
}
-// RV32-LABEL: define dso_local i32 @test_pget_i16x4_i16x2(
-// RV32-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV32: [[COND_TRUE_I]]:
-// RV32-NEXT: br label %[[__RISCV_PGET_I16X4_I16X2_EXIT:.*]]
-// RV32: [[COND_FALSE_I]]:
-// RV32-NEXT: [[SHUFFLE2_I_EXTRACT:%.*]] = trunc i64 [[V_COERCE]] to i32
-// RV32-NEXT: br label %[[__RISCV_PGET_I16X4_I16X2_EXIT]]
-// RV32: [[__RISCV_PGET_I16X4_I16X2_EXIT]]:
-// RV32-NEXT: [[TMP0:%.*]] = phi i32 [ poison, %[[COND_TRUE_I]] ], [ [[SHUFFLE2_I_EXTRACT]], %[[COND_FALSE_I]] ]
-// RV32-NEXT: ret i32 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i32 @test_pget_i16x4_i16x2(
-// RV64-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV64: [[COND_TRUE_I]]:
-// RV64-NEXT: br label %[[__RISCV_PGET_I16X4_I16X2_EXIT:.*]]
-// RV64: [[COND_FALSE_I]]:
-// RV64-NEXT: [[SHUFFLE2_I_EXTRACT:%.*]] = trunc i64 [[V_COERCE]] to i32
-// RV64-NEXT: br label %[[__RISCV_PGET_I16X4_I16X2_EXIT]]
-// RV64: [[__RISCV_PGET_I16X4_I16X2_EXIT]]:
-// RV64-NEXT: [[TMP0:%.*]] = phi i32 [ poison, %[[COND_TRUE_I]] ], [ [[SHUFFLE2_I_EXTRACT]], %[[COND_FALSE_I]] ]
-// RV64-NEXT: ret i32 [[TMP0]]
+// CHECK-LABEL: define dso_local i32 @test_pget_i16x4_i16x2(
+// CHECK-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
+// CHECK: [[COND_TRUE_I]]:
+// CHECK-NEXT: br label %[[__RISCV_PGET_I16X4_I16X2_EXIT:.*]]
+// CHECK: [[COND_FALSE_I]]:
+// CHECK-NEXT: [[SHUFFLE2_I_EXTRACT:%.*]] = trunc i64 [[V_COERCE]] to i32
+// CHECK-NEXT: br label %[[__RISCV_PGET_I16X4_I16X2_EXIT]]
+// CHECK: [[__RISCV_PGET_I16X4_I16X2_EXIT]]:
+// CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ poison, %[[COND_TRUE_I]] ], [ [[SHUFFLE2_I_EXTRACT]], %[[COND_FALSE_I]] ]
+// CHECK-NEXT: ret i32 [[TMP0]]
//
int16x2_t test_pget_i16x4_i16x2(int16x4_t v) {
return __riscv_pget_i16x4_i16x2(v, 0);
@@ -12743,31 +8424,18 @@ int16x2_t test_pget_i16x4_i16x2_idx1(int16x4_t v) {
return __riscv_pget_i16x4_i16x2(v, 1);
}
-// RV32-LABEL: define dso_local i32 @test_pget_u16x4_u16x2(
-// RV32-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV32: [[COND_TRUE_I]]:
-// RV32-NEXT: br label %[[__RISCV_PGET_U16X4_U16X2_EXIT:.*]]
-// RV32: [[COND_FALSE_I]]:
-// RV32-NEXT: [[SHUFFLE2_I_EXTRACT:%.*]] = trunc i64 [[V_COERCE]] to i32
-// RV32-NEXT: br label %[[__RISCV_PGET_U16X4_U16X2_EXIT]]
-// RV32: [[__RISCV_PGET_U16X4_U16X2_EXIT]]:
-// RV32-NEXT: [[TMP0:%.*]] = phi i32 [ poison, %[[COND_TRUE_I]] ], [ [[SHUFFLE2_I_EXTRACT]], %[[COND_FALSE_I]] ]
-// RV32-NEXT: ret i32 [[TMP0]]
-//
-// RV64-LABEL: define dso_local i32 @test_pget_u16x4_u16x2(
-// RV64-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV64: [[COND_TRUE_I]]:
-// RV64-NEXT: br label %[[__RISCV_PGET_U16X4_U16X2_EXIT:.*]]
-// RV64: [[COND_FALSE_I]]:
-// RV64-NEXT: [[SHUFFLE2_I_EXTRACT:%.*]] = trunc i64 [[V_COERCE]] to i32
-// RV64-NEXT: br label %[[__RISCV_PGET_U16X4_U16X2_EXIT]]
-// RV64: [[__RISCV_PGET_U16X4_U16X2_EXIT]]:
-// RV64-NEXT: [[TMP0:%.*]] = phi i32 [ poison, %[[COND_TRUE_I]] ], [ [[SHUFFLE2_I_EXTRACT]], %[[COND_FALSE_I]] ]
-// RV64-NEXT: ret i32 [[TMP0]]
+// CHECK-LABEL: define dso_local i32 @test_pget_u16x4_u16x2(
+// CHECK-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
+// CHECK: [[COND_TRUE_I]]:
+// CHECK-NEXT: br label %[[__RISCV_PGET_U16X4_U16X2_EXIT:.*]]
+// CHECK: [[COND_FALSE_I]]:
+// CHECK-NEXT: [[SHUFFLE2_I_EXTRACT:%.*]] = trunc i64 [[V_COERCE]] to i32
+// CHECK-NEXT: br label %[[__RISCV_PGET_U16X4_U16X2_EXIT]]
+// CHECK: [[__RISCV_PGET_U16X4_U16X2_EXIT]]:
+// CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ poison, %[[COND_TRUE_I]] ], [ [[SHUFFLE2_I_EXTRACT]], %[[COND_FALSE_I]] ]
+// CHECK-NEXT: ret i32 [[TMP0]]
//
uint16x2_t test_pget_u16x4_u16x2(uint16x4_t v) {
return __riscv_pget_u16x4_u16x2(v, 0);
@@ -12807,416 +8475,232 @@ uint16x2_t test_pget_u16x4_u16x2_idx1(uint16x4_t v) {
/* Packed Subvector Insert */
-// RV32-LABEL: define dso_local i64 @test_pset_i8x4_i8x8_lo(
-// RV32-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV32: [[COND_TRUE_I]]:
-// RV32-NEXT: br label %[[__RISCV_PSET_I8X4_I8X8_EXIT:.*]]
-// RV32: [[COND_FALSE_I]]:
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE5_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> [[SHUFFLE5_I]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I_I]] to i64
-// RV32-NEXT: br label %[[__RISCV_PSET_I8X4_I8X8_EXIT]]
-// RV32: [[__RISCV_PSET_I8X4_I8X8_EXIT]]:
-// RV32-NEXT: [[TMP3:%.*]] = phi i64 [ poison, %[[COND_TRUE_I]] ], [ [[TMP2]], %[[COND_FALSE_I]] ]
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pset_i8x4_i8x8_lo(
-// RV64-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV64: [[COND_TRUE_I]]:
-// RV64-NEXT: br label %[[__RISCV_PSET_I8X4_I8X8_EXIT:.*]]
-// RV64: [[COND_FALSE_I]]:
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE5_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> [[SHUFFLE5_I]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I_I]] to i64
-// RV64-NEXT: br label %[[__RISCV_PSET_I8X4_I8X8_EXIT]]
-// RV64: [[__RISCV_PSET_I8X4_I8X8_EXIT]]:
-// RV64-NEXT: [[TMP3:%.*]] = phi i64 [ poison, %[[COND_TRUE_I]] ], [ [[TMP2]], %[[COND_FALSE_I]] ]
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pset_i8x4_i8x8_lo(
+// CHECK-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
+// CHECK: [[COND_TRUE_I]]:
+// CHECK-NEXT: br label %[[__RISCV_PSET_I8X4_I8X8_EXIT:.*]]
+// CHECK: [[COND_FALSE_I]]:
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE5_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> [[SHUFFLE5_I]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I_I]] to i64
+// CHECK-NEXT: br label %[[__RISCV_PSET_I8X4_I8X8_EXIT]]
+// CHECK: [[__RISCV_PSET_I8X4_I8X8_EXIT]]:
+// CHECK-NEXT: [[TMP3:%.*]] = phi i64 [ poison, %[[COND_TRUE_I]] ], [ [[TMP2]], %[[COND_FALSE_I]] ]
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int8x8_t test_pset_i8x4_i8x8_lo(int8x8_t v, int8x4_t s) {
return __riscv_pset_i8x4_i8x8(v, s, 0);
}
-// RV32-LABEL: define dso_local i64 @test_pset_i8x4_i8x8_hi(
-// RV32-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: br i1 true, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV32: [[COND_TRUE_I]]:
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I17_I:%.*]] = shufflevector <4 x i8> [[SHUFFLE_I]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I17_I]] to i64
-// RV32-NEXT: br label %[[__RISCV_PSET_I8X4_I8X8_EXIT:.*]]
-// RV32: [[COND_FALSE_I]]:
-// RV32-NEXT: br label %[[__RISCV_PSET_I8X4_I8X8_EXIT]]
-// RV32: [[__RISCV_PSET_I8X4_I8X8_EXIT]]:
-// RV32-NEXT: [[TMP3:%.*]] = phi i64 [ [[TMP2]], %[[COND_TRUE_I]] ], [ poison, %[[COND_FALSE_I]] ]
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pset_i8x4_i8x8_hi(
-// RV64-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: br i1 true, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV64: [[COND_TRUE_I]]:
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I17_I:%.*]] = shufflevector <4 x i8> [[SHUFFLE_I]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I17_I]] to i64
-// RV64-NEXT: br label %[[__RISCV_PSET_I8X4_I8X8_EXIT:.*]]
-// RV64: [[COND_FALSE_I]]:
-// RV64-NEXT: br label %[[__RISCV_PSET_I8X4_I8X8_EXIT]]
-// RV64: [[__RISCV_PSET_I8X4_I8X8_EXIT]]:
-// RV64-NEXT: [[TMP3:%.*]] = phi i64 [ [[TMP2]], %[[COND_TRUE_I]] ], [ poison, %[[COND_FALSE_I]] ]
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pset_i8x4_i8x8_hi(
+// CHECK-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: br i1 true, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
+// CHECK: [[COND_TRUE_I]]:
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I17_I:%.*]] = shufflevector <4 x i8> [[SHUFFLE_I]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I17_I]] to i64
+// CHECK-NEXT: br label %[[__RISCV_PSET_I8X4_I8X8_EXIT:.*]]
+// CHECK: [[COND_FALSE_I]]:
+// CHECK-NEXT: br label %[[__RISCV_PSET_I8X4_I8X8_EXIT]]
+// CHECK: [[__RISCV_PSET_I8X4_I8X8_EXIT]]:
+// CHECK-NEXT: [[TMP3:%.*]] = phi i64 [ [[TMP2]], %[[COND_TRUE_I]] ], [ poison, %[[COND_FALSE_I]] ]
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int8x8_t test_pset_i8x4_i8x8_hi(int8x8_t v, int8x4_t s) {
return __riscv_pset_i8x4_i8x8(v, s, 1);
}
-// RV32-LABEL: define dso_local i64 @test_pset_u8x4_u8x8_lo(
-// RV32-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV32: [[COND_TRUE_I]]:
-// RV32-NEXT: br label %[[__RISCV_PSET_U8X4_U8X8_EXIT:.*]]
-// RV32: [[COND_FALSE_I]]:
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE5_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> [[SHUFFLE5_I]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I_I]] to i64
-// RV32-NEXT: br label %[[__RISCV_PSET_U8X4_U8X8_EXIT]]
-// RV32: [[__RISCV_PSET_U8X4_U8X8_EXIT]]:
-// RV32-NEXT: [[TMP3:%.*]] = phi i64 [ poison, %[[COND_TRUE_I]] ], [ [[TMP2]], %[[COND_FALSE_I]] ]
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pset_u8x4_u8x8_lo(
-// RV64-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV64: [[COND_TRUE_I]]:
-// RV64-NEXT: br label %[[__RISCV_PSET_U8X4_U8X8_EXIT:.*]]
-// RV64: [[COND_FALSE_I]]:
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE5_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> [[SHUFFLE5_I]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I_I]] to i64
-// RV64-NEXT: br label %[[__RISCV_PSET_U8X4_U8X8_EXIT]]
-// RV64: [[__RISCV_PSET_U8X4_U8X8_EXIT]]:
-// RV64-NEXT: [[TMP3:%.*]] = phi i64 [ poison, %[[COND_TRUE_I]] ], [ [[TMP2]], %[[COND_FALSE_I]] ]
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pset_u8x4_u8x8_lo(
+// CHECK-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
+// CHECK: [[COND_TRUE_I]]:
+// CHECK-NEXT: br label %[[__RISCV_PSET_U8X4_U8X8_EXIT:.*]]
+// CHECK: [[COND_FALSE_I]]:
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE5_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> [[SHUFFLE5_I]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I_I]] to i64
+// CHECK-NEXT: br label %[[__RISCV_PSET_U8X4_U8X8_EXIT]]
+// CHECK: [[__RISCV_PSET_U8X4_U8X8_EXIT]]:
+// CHECK-NEXT: [[TMP3:%.*]] = phi i64 [ poison, %[[COND_TRUE_I]] ], [ [[TMP2]], %[[COND_FALSE_I]] ]
+// CHECK-NEXT: ret i64 [[TMP3]]
//
uint8x8_t test_pset_u8x4_u8x8_lo(uint8x8_t v, uint8x4_t s) {
return __riscv_pset_u8x4_u8x8(v, s, 0);
}
-// RV32-LABEL: define dso_local i64 @test_pset_u8x4_u8x8_hi(
-// RV32-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: br i1 true, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV32: [[COND_TRUE_I]]:
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <4 x i8>
-// RV32-NEXT: [[SHUFFLE_I17_I:%.*]] = shufflevector <4 x i8> [[SHUFFLE_I]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I17_I]] to i64
-// RV32-NEXT: br label %[[__RISCV_PSET_U8X4_U8X8_EXIT:.*]]
-// RV32: [[COND_FALSE_I]]:
-// RV32-NEXT: br label %[[__RISCV_PSET_U8X4_U8X8_EXIT]]
-// RV32: [[__RISCV_PSET_U8X4_U8X8_EXIT]]:
-// RV32-NEXT: [[TMP3:%.*]] = phi i64 [ [[TMP2]], %[[COND_TRUE_I]] ], [ poison, %[[COND_FALSE_I]] ]
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pset_u8x4_u8x8_hi(
-// RV64-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: br i1 true, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV64: [[COND_TRUE_I]]:
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <4 x i8>
-// RV64-NEXT: [[SHUFFLE_I17_I:%.*]] = shufflevector <4 x i8> [[SHUFFLE_I]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I17_I]] to i64
-// RV64-NEXT: br label %[[__RISCV_PSET_U8X4_U8X8_EXIT:.*]]
-// RV64: [[COND_FALSE_I]]:
-// RV64-NEXT: br label %[[__RISCV_PSET_U8X4_U8X8_EXIT]]
-// RV64: [[__RISCV_PSET_U8X4_U8X8_EXIT]]:
-// RV64-NEXT: [[TMP3:%.*]] = phi i64 [ [[TMP2]], %[[COND_TRUE_I]] ], [ poison, %[[COND_FALSE_I]] ]
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pset_u8x4_u8x8_hi(
+// CHECK-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: br i1 true, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
+// CHECK: [[COND_TRUE_I]]:
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <4 x i8>
+// CHECK-NEXT: [[SHUFFLE_I17_I:%.*]] = shufflevector <4 x i8> [[SHUFFLE_I]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I17_I]] to i64
+// CHECK-NEXT: br label %[[__RISCV_PSET_U8X4_U8X8_EXIT:.*]]
+// CHECK: [[COND_FALSE_I]]:
+// CHECK-NEXT: br label %[[__RISCV_PSET_U8X4_U8X8_EXIT]]
+// CHECK: [[__RISCV_PSET_U8X4_U8X8_EXIT]]:
+// CHECK-NEXT: [[TMP3:%.*]] = phi i64 [ [[TMP2]], %[[COND_TRUE_I]] ], [ poison, %[[COND_FALSE_I]] ]
+// CHECK-NEXT: ret i64 [[TMP3]]
//
uint8x8_t test_pset_u8x4_u8x8_hi(uint8x8_t v, uint8x4_t s) {
return __riscv_pset_u8x4_u8x8(v, s, 1);
}
-// RV32-LABEL: define dso_local i64 @test_pset_i16x2_i16x4_lo(
-// RV32-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV32: [[COND_TRUE_I]]:
-// RV32-NEXT: br label %[[__RISCV_PSET_I16X2_I16X4_EXIT:.*]]
-// RV32: [[COND_FALSE_I]]:
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE5_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 2, i32 3>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i16> [[TMP1]], <2 x i16> [[SHUFFLE5_I]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to i64
-// RV32-NEXT: br label %[[__RISCV_PSET_I16X2_I16X4_EXIT]]
-// RV32: [[__RISCV_PSET_I16X2_I16X4_EXIT]]:
-// RV32-NEXT: [[TMP3:%.*]] = phi i64 [ poison, %[[COND_TRUE_I]] ], [ [[TMP2]], %[[COND_FALSE_I]] ]
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pset_i16x2_i16x4_lo(
-// RV64-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV64: [[COND_TRUE_I]]:
-// RV64-NEXT: br label %[[__RISCV_PSET_I16X2_I16X4_EXIT:.*]]
-// RV64: [[COND_FALSE_I]]:
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE5_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 2, i32 3>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i16> [[TMP1]], <2 x i16> [[SHUFFLE5_I]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to i64
-// RV64-NEXT: br label %[[__RISCV_PSET_I16X2_I16X4_EXIT]]
-// RV64: [[__RISCV_PSET_I16X2_I16X4_EXIT]]:
-// RV64-NEXT: [[TMP3:%.*]] = phi i64 [ poison, %[[COND_TRUE_I]] ], [ [[TMP2]], %[[COND_FALSE_I]] ]
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pset_i16x2_i16x4_lo(
+// CHECK-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
+// CHECK: [[COND_TRUE_I]]:
+// CHECK-NEXT: br label %[[__RISCV_PSET_I16X2_I16X4_EXIT:.*]]
+// CHECK: [[COND_FALSE_I]]:
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE5_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 2, i32 3>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i16> [[TMP1]], <2 x i16> [[SHUFFLE5_I]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to i64
+// CHECK-NEXT: br label %[[__RISCV_PSET_I16X2_I16X4_EXIT]]
+// CHECK: [[__RISCV_PSET_I16X2_I16X4_EXIT]]:
+// CHECK-NEXT: [[TMP3:%.*]] = phi i64 [ poison, %[[COND_TRUE_I]] ], [ [[TMP2]], %[[COND_FALSE_I]] ]
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int16x4_t test_pset_i16x2_i16x4_lo(int16x4_t v, int16x2_t s) {
return __riscv_pset_i16x2_i16x4(v, s, 0);
}
-// RV32-LABEL: define dso_local i64 @test_pset_i16x2_i16x4_hi(
-// RV32-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: br i1 true, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV32: [[COND_TRUE_I]]:
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 0, i32 1>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHUFFLE_I17_I:%.*]] = shufflevector <2 x i16> [[SHUFFLE_I]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I17_I]] to i64
-// RV32-NEXT: br label %[[__RISCV_PSET_I16X2_I16X4_EXIT:.*]]
-// RV32: [[COND_FALSE_I]]:
-// RV32-NEXT: br label %[[__RISCV_PSET_I16X2_I16X4_EXIT]]
-// RV32: [[__RISCV_PSET_I16X2_I16X4_EXIT]]:
-// RV32-NEXT: [[TMP3:%.*]] = phi i64 [ [[TMP2]], %[[COND_TRUE_I]] ], [ poison, %[[COND_FALSE_I]] ]
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pset_i16x2_i16x4_hi(
-// RV64-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: br i1 true, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV64: [[COND_TRUE_I]]:
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 0, i32 1>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHUFFLE_I17_I:%.*]] = shufflevector <2 x i16> [[SHUFFLE_I]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I17_I]] to i64
-// RV64-NEXT: br label %[[__RISCV_PSET_I16X2_I16X4_EXIT:.*]]
-// RV64: [[COND_FALSE_I]]:
-// RV64-NEXT: br label %[[__RISCV_PSET_I16X2_I16X4_EXIT]]
-// RV64: [[__RISCV_PSET_I16X2_I16X4_EXIT]]:
-// RV64-NEXT: [[TMP3:%.*]] = phi i64 [ [[TMP2]], %[[COND_TRUE_I]] ], [ poison, %[[COND_FALSE_I]] ]
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pset_i16x2_i16x4_hi(
+// CHECK-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: br i1 true, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
+// CHECK: [[COND_TRUE_I]]:
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 0, i32 1>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHUFFLE_I17_I:%.*]] = shufflevector <2 x i16> [[SHUFFLE_I]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I17_I]] to i64
+// CHECK-NEXT: br label %[[__RISCV_PSET_I16X2_I16X4_EXIT:.*]]
+// CHECK: [[COND_FALSE_I]]:
+// CHECK-NEXT: br label %[[__RISCV_PSET_I16X2_I16X4_EXIT]]
+// CHECK: [[__RISCV_PSET_I16X2_I16X4_EXIT]]:
+// CHECK-NEXT: [[TMP3:%.*]] = phi i64 [ [[TMP2]], %[[COND_TRUE_I]] ], [ poison, %[[COND_FALSE_I]] ]
+// CHECK-NEXT: ret i64 [[TMP3]]
//
int16x4_t test_pset_i16x2_i16x4_hi(int16x4_t v, int16x2_t s) {
return __riscv_pset_i16x2_i16x4(v, s, 1);
}
-// RV32-LABEL: define dso_local i64 @test_pset_u16x2_u16x4_lo(
-// RV32-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV32: [[COND_TRUE_I]]:
-// RV32-NEXT: br label %[[__RISCV_PSET_U16X2_U16X4_EXIT:.*]]
-// RV32: [[COND_FALSE_I]]:
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE5_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 2, i32 3>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i16> [[TMP1]], <2 x i16> [[SHUFFLE5_I]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to i64
-// RV32-NEXT: br label %[[__RISCV_PSET_U16X2_U16X4_EXIT]]
-// RV32: [[__RISCV_PSET_U16X2_U16X4_EXIT]]:
-// RV32-NEXT: [[TMP3:%.*]] = phi i64 [ poison, %[[COND_TRUE_I]] ], [ [[TMP2]], %[[COND_FALSE_I]] ]
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pset_u16x2_u16x4_lo(
-// RV64-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV64: [[COND_TRUE_I]]:
-// RV64-NEXT: br label %[[__RISCV_PSET_U16X2_U16X4_EXIT:.*]]
-// RV64: [[COND_FALSE_I]]:
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE5_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 2, i32 3>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i16> [[TMP1]], <2 x i16> [[SHUFFLE5_I]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to i64
-// RV64-NEXT: br label %[[__RISCV_PSET_U16X2_U16X4_EXIT]]
-// RV64: [[__RISCV_PSET_U16X2_U16X4_EXIT]]:
-// RV64-NEXT: [[TMP3:%.*]] = phi i64 [ poison, %[[COND_TRUE_I]] ], [ [[TMP2]], %[[COND_FALSE_I]] ]
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pset_u16x2_u16x4_lo(
+// CHECK-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: br i1 false, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
+// CHECK: [[COND_TRUE_I]]:
+// CHECK-NEXT: br label %[[__RISCV_PSET_U16X2_U16X4_EXIT:.*]]
+// CHECK: [[COND_FALSE_I]]:
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE5_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 2, i32 3>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i16> [[TMP1]], <2 x i16> [[SHUFFLE5_I]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to i64
+// CHECK-NEXT: br label %[[__RISCV_PSET_U16X2_U16X4_EXIT]]
+// CHECK: [[__RISCV_PSET_U16X2_U16X4_EXIT]]:
+// CHECK-NEXT: [[TMP3:%.*]] = phi i64 [ poison, %[[COND_TRUE_I]] ], [ [[TMP2]], %[[COND_FALSE_I]] ]
+// CHECK-NEXT: ret i64 [[TMP3]]
//
uint16x4_t test_pset_u16x2_u16x4_lo(uint16x4_t v, uint16x2_t s) {
return __riscv_pset_u16x2_u16x4(v, s, 0);
}
-// RV32-LABEL: define dso_local i64 @test_pset_u16x2_u16x4_hi(
-// RV32-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: br i1 true, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV32: [[COND_TRUE_I]]:
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16>
-// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 0, i32 1>
-// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <2 x i16>
-// RV32-NEXT: [[SHUFFLE_I17_I:%.*]] = shufflevector <2 x i16> [[SHUFFLE_I]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I17_I]] to i64
-// RV32-NEXT: br label %[[__RISCV_PSET_U16X2_U16X4_EXIT:.*]]
-// RV32: [[COND_FALSE_I]]:
-// RV32-NEXT: br label %[[__RISCV_PSET_U16X2_U16X4_EXIT]]
-// RV32: [[__RISCV_PSET_U16X2_U16X4_EXIT]]:
-// RV32-NEXT: [[TMP3:%.*]] = phi i64 [ [[TMP2]], %[[COND_TRUE_I]] ], [ poison, %[[COND_FALSE_I]] ]
-// RV32-NEXT: ret i64 [[TMP3]]
-//
-// RV64-LABEL: define dso_local i64 @test_pset_u16x2_u16x4_hi(
-// RV64-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: br i1 true, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
-// RV64: [[COND_TRUE_I]]:
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16>
-// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 0, i32 1>
-// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <2 x i16>
-// RV64-NEXT: [[SHUFFLE_I17_I:%.*]] = shufflevector <2 x i16> [[SHUFFLE_I]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I17_I]] to i64
-// RV64-NEXT: br label %[[__RISCV_PSET_U16X2_U16X4_EXIT:.*]]
-// RV64: [[COND_FALSE_I]]:
-// RV64-NEXT: br label %[[__RISCV_PSET_U16X2_U16X4_EXIT]]
-// RV64: [[__RISCV_PSET_U16X2_U16X4_EXIT]]:
-// RV64-NEXT: [[TMP3:%.*]] = phi i64 [ [[TMP2]], %[[COND_TRUE_I]] ], [ poison, %[[COND_FALSE_I]] ]
-// RV64-NEXT: ret i64 [[TMP3]]
+// CHECK-LABEL: define dso_local i64 @test_pset_u16x2_u16x4_hi(
+// CHECK-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[S_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: br i1 true, label %[[COND_TRUE_I:.*]], label %[[COND_FALSE_I:.*]]
+// CHECK: [[COND_TRUE_I]]:
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 0, i32 1>
+// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[S_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[SHUFFLE_I17_I:%.*]] = shufflevector <2 x i16> [[SHUFFLE_I]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I17_I]] to i64
+// CHECK-NEXT: br label %[[__RISCV_PSET_U16X2_U16X4_EXIT:.*]]
+// CHECK: [[COND_FALSE_I]]:
+// CHECK-NEXT: br label %[[__RISCV_PSET_U16X2_U16X4_EXIT]]
+// CHECK: [[__RISCV_PSET_U16X2_U16X4_EXIT]]:
+// CHECK-NEXT: [[TMP3:%.*]] = phi i64 [ [[TMP2]], %[[COND_TRUE_I]] ], [ poison, %[[COND_FALSE_I]] ]
+// CHECK-NEXT: ret i64 [[TMP3]]
//
uint16x4_t test_pset_u16x2_u16x4_hi(uint16x4_t v, uint16x2_t s) {
return __riscv_pset_u16x2_u16x4(v, s, 1);
}
/* Packed Saturation (32-bit) */
-// RV32-LABEL: define dso_local i32 @test_pusati_u16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pusati.v2i16(<2 x i16> [[TMP0]], i32 8)
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_pusati_u16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pusati.v2i16(<2 x i16> [[TMP0]], i32 8)
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_pusati_u16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pusati.v2i16(<2 x i16> [[TMP0]], i32 8)
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_pusati_u16x2(int16x2_t a) { return __riscv_pusati_u16x2(a, 8); }
-// RV32-LABEL: define dso_local i32 @test_psati_i16x2(
-// RV32-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.psati.v2i16(<2 x i16> [[TMP0]], i32 8)
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-// RV32-NEXT: ret i32 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i32 @test_psati_i16x2(
-// RV64-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.psati.v2i16(<2 x i16> [[TMP0]], i32 8)
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-// RV64-NEXT: ret i32 [[TMP2]]
+// CHECK-LABEL: define dso_local i32 @test_psati_i16x2(
+// CHECK-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.psati.v2i16(<2 x i16> [[TMP0]], i32 8)
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
+// CHECK-NEXT: ret i32 [[TMP2]]
//
int16x2_t test_psati_i16x2(int16x2_t a) { return __riscv_psati_i16x2(a, 8); }
/* Packed Saturation (64-bit) */
-// RV32-LABEL: define dso_local i64 @test_pusati_u16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.pusati.v4i16(<4 x i16> [[TMP0]], i32 8)
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pusati_u16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.pusati.v4i16(<4 x i16> [[TMP0]], i32 8)
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pusati_u16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.pusati.v4i16(<4 x i16> [[TMP0]], i32 8)
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint16x4_t test_pusati_u16x4(int16x4_t a) { return __riscv_pusati_u16x4(a, 8); }
-// RV32-LABEL: define dso_local i64 @test_pusati_u32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.pusati.v2i32(<2 x i32> [[TMP0]], i32 16)
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_pusati_u32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.pusati.v2i32(<2 x i32> [[TMP0]], i32 16)
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_pusati_u32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.pusati.v2i32(<2 x i32> [[TMP0]], i32 16)
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
uint32x2_t test_pusati_u32x2(int32x2_t a) { return __riscv_pusati_u32x2(a, 16); }
-// RV32-LABEL: define dso_local i64 @test_psati_i16x4(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.psati.v4i16(<4 x i16> [[TMP0]], i32 8)
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psati_i16x4(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.psati.v4i16(<4 x i16> [[TMP0]], i32 8)
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psati_i16x4(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.psati.v4i16(<4 x i16> [[TMP0]], i32 8)
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int16x4_t test_psati_i16x4(int16x4_t a) { return __riscv_psati_i16x4(a, 8); }
-// RV32-LABEL: define dso_local i64 @test_psati_i32x2(
-// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV32-NEXT: [[ENTRY:.*:]]
-// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV32-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.psati.v2i32(<2 x i32> [[TMP0]], i32 16)
-// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64
-// RV32-NEXT: ret i64 [[TMP2]]
-//
-// RV64-LABEL: define dso_local i64 @test_psati_i32x2(
-// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
-// RV64-NEXT: [[ENTRY:.*:]]
-// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
-// RV64-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.psati.v2i32(<2 x i32> [[TMP0]], i32 16)
-// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64
-// RV64-NEXT: ret i64 [[TMP2]]
+// CHECK-LABEL: define dso_local i64 @test_psati_i32x2(
+// CHECK-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
+// CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.psati.v2i32(<2 x i32> [[TMP0]], i32 16)
+// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64
+// CHECK-NEXT: ret i64 [[TMP2]]
//
int32x2_t test_psati_i32x2(int32x2_t a) { return __riscv_psati_i32x2(a, 16); }
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