[clang] [llvm] [WIP] Add support for O64 Mips ABI (PR #223990)
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cfe-commits at lists.llvm.org
Thu Sep 17 11:20:49 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clang-driver
Author: Luna (LunaTheFoxgirl)
<details>
<summary>Changes</summary>
This PR adds support for the O64 ABI which sees use in console homebrew (eg. N64), convention was popularized by SGI.
---
Patch is 39.60 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/223990.diff
18 Files Affected:
- (modified) clang/include/clang/Options/Options.td (+4)
- (modified) clang/lib/Basic/Targets/Mips.cpp (+24-5)
- (modified) clang/lib/Basic/Targets/Mips.h (+44-4)
- (modified) clang/lib/Driver/ToolChains/Arch/Mips.cpp (+13)
- (modified) llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (+2)
- (modified) llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp (+13-2)
- (modified) llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h (+5-2)
- (modified) llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp (+2-2)
- (modified) llvm/lib/Target/Mips/Mips.td (+16-2)
- (modified) llvm/lib/Target/Mips/MipsAsmPrinter.cpp (+1)
- (modified) llvm/lib/Target/Mips/MipsCallingConv.td (+53)
- (modified) llvm/lib/Target/Mips/MipsFastISel.cpp (+17)
- (modified) llvm/lib/Target/Mips/MipsISelLowering.cpp (+153)
- (modified) llvm/lib/Target/Mips/MipsRegisterInfo.cpp (+29-14)
- (modified) llvm/lib/Target/Mips/MipsSubtarget.cpp (+29-2)
- (modified) llvm/lib/Target/Mips/MipsSubtarget.h (+16)
- (modified) llvm/lib/Target/Mips/MipsTargetMachine.cpp (+1-1)
- (modified) llvm/lib/TargetParser/TargetDataLayout.cpp (+8-2)
``````````diff
diff --git a/clang/include/clang/Options/Options.td b/clang/include/clang/Options/Options.td
index 06461acdf216e..6ae7dafb061e6 100644
--- a/clang/include/clang/Options/Options.td
+++ b/clang/include/clang/Options/Options.td
@@ -6477,6 +6477,10 @@ def mfp64 : Flag<["-"], "mfp64">, Group<m_mips_Features_Group>,
HelpText<"Use 64-bit floating point registers (MIPS only)">;
def mfp32 : Flag<["-"], "mfp32">, Group<m_mips_Features_Group>,
HelpText<"Use 32-bit floating point registers (MIPS only)">;
+def mlong32 : Flag<["-"], "mlong32">, Group<m_mips_Features_Group>,
+ HelpText<"Use 64-bit longs (MIPS only)">;
+def mlong64 : Flag<["-"], "mlong64">, Group<m_mips_Features_Group>,
+ HelpText<"Use 32-bit longs (MIPS only)">;
def mgpopt : Flag<["-"], "mgpopt">, Group<m_mips_Features_Group>,
HelpText<"Use GP relative accesses for symbols known to be in a small"
" data section (MIPS)">;
diff --git a/clang/lib/Basic/Targets/Mips.cpp b/clang/lib/Basic/Targets/Mips.cpp
index 76c9081567053..d9917c93561bb 100644
--- a/clang/lib/Basic/Targets/Mips.cpp
+++ b/clang/lib/Basic/Targets/Mips.cpp
@@ -46,6 +46,7 @@ bool MipsTargetInfo::processorSupportsGPR64() const {
.Case("mips64r6", true)
.Case("octeon", true)
.Case("octeon+", true)
+ .Case("r4300", true)
.Case("r5900", true)
.Case("i6400", true)
.Case("i6500", true)
@@ -56,8 +57,8 @@ static constexpr llvm::StringLiteral ValidCPUNames[] = {
{"mips1"}, {"mips2"}, {"mips3"}, {"mips4"}, {"mips5"},
{"mips32"}, {"mips32r2"}, {"mips32r3"}, {"mips32r5"}, {"mips32r6"},
{"mips64"}, {"mips64r2"}, {"mips64r3"}, {"mips64r5"}, {"mips64r6"},
- {"octeon"}, {"octeon+"}, {"p5600"}, {"r5900"}, {"i6400"},
- {"i6500"}};
+ {"octeon"}, {"octeon+"}, {"p5600"}, {"r4300"}, {"r5900"},
+ {"i6400"}, {"i6500"}};
bool MipsTargetInfo::isValidCPUName(StringRef Name) const {
return llvm::is_contained(ValidCPUNames, Name);
@@ -112,6 +113,10 @@ void MipsTargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__mips_o32");
Builder.defineMacro("_ABIO32", "1");
Builder.defineMacro("_MIPS_SIM", "_ABIO32");
+ } else if (ABI == "o64") {
+ Builder.defineMacro("__mips_o64");
+ Builder.defineMacro("_ABIO64", "4");
+ Builder.defineMacro("_MIPS_SIM", "_ABIO64");
} else if (ABI == "n32") {
Builder.defineMacro("__mips_n32");
Builder.defineMacro("_ABIN32", "2");
@@ -219,7 +224,7 @@ void MipsTargetInfo::getTargetDefines(const LangOptions &Opts,
// found in 64-bit processors. In the case of O32 on a 64-bit processor,
// the instructions exist but using them violates the ABI since they
// require 64-bit GPRs and O32 only supports 32-bit GPRs.
- if (ABI == "n32" || ABI == "n64")
+ if (ABI == "o64" || ABI == "n32" || ABI == "n64")
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
}
@@ -230,6 +235,8 @@ bool MipsTargetInfo::hasFeature(StringRef Feature) const {
.Case("dspr2", DspRev >= DSP2)
.Case("fp64", FPMode == FP64)
.Case("msa", HasMSA)
+ .Case("long32", LongABI == Long32)
+ .Case("long64", LongABI == Long64)
.Default(false);
}
@@ -241,6 +248,7 @@ MipsTargetInfo::getTargetBuiltins() const {
unsigned MipsTargetInfo::getUnwindWordWidth() const {
return llvm::StringSwitch<unsigned>(ABI)
.Case("o32", 32)
+ .Case("o64", 32)
.Case("n32", 64)
.Case("n64", 64)
.Default(getPointerWidth(LangAS::Default));
@@ -254,11 +262,22 @@ bool MipsTargetInfo::validateTarget(DiagnosticsEngine &Diags) const {
}
// 64-bit ABI's require 64-bit CPU's.
- if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) {
+ if (!processorSupportsGPR64() && (LongABI == Long64 || ABI == "n32" || ABI == "n64")) {
Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
return false;
}
+ // -longxx is valid only for the o32 and o64 ABI
+ if (LongABI == Long32 && !(ABI == "o64" || ABI == "o32")) {
+ Diags.Report(diag::err_unsupported_abi_for_opt) << "-mlong32" << "o32" << "o64";
+ return false;
+ }
+
+ if (LongABI == Long64 && !(ABI == "o64" || ABI == "o32")) {
+ Diags.Report(diag::err_unsupported_abi_for_opt) << "-mlong64" << "o32" << "o64";
+ return false;
+ }
+
// -fpxx is valid only for the o32 ABI
if (FPMode == FPXX && (ABI == "n32" || ABI == "n64")) {
Diags.Report(diag::err_unsupported_abi_for_opt) << "-mfpxx" << "o32";
@@ -297,7 +316,7 @@ bool MipsTargetInfo::validateTarget(DiagnosticsEngine &Diags) const {
}
// Option -mmsa permitted on Mips32 iff revision 2 or higher is present
if (HasMSA && (CPU == "mips1" || CPU == "mips2" || getISARev() < 2) &&
- ABI == "o32") {
+ (ABI == "o32" || ABI == "o64")) {
Diags.Report(diag::err_mips_fp64_req) << "-mmsa";
return false;
}
diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index 2f251c7eb8690..ff7eed8e47c6a 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -37,13 +37,14 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
bool DisableMadd4;
bool UseIndirectJumpHazard;
bool NoOddSpreg;
+ enum MipsLongABI { LongDefault, Long32, Long64 } LongABI;
protected:
enum FPModeEnum { FPXX, FP32, FP64 } FPMode;
std::string ABI;
public:
- MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
+ MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &TO)
: TargetInfo(Triple), IsMips16(false), IsMicromips(false),
IsNan2008(false), IsAbs2008(false), IsSingleFloat(false),
IsNoABICalls(false), CanUseBSDABICalls(false), FloatABI(HardFloat),
@@ -90,6 +91,11 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
ABI = Name;
return true;
}
+ if (Name == "o64") {
+ setO64ABITypes();
+ ABI = Name;
+ return true;
+ }
if (Name == "n32") {
setN32ABITypes();
@@ -104,19 +110,44 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
return false;
}
+ void setOABITypes() {
+ if (ABI == "o32" || ABI == "o64") {
+
+ // Default is 32-bit longs.
+ if (LongABI == LongDefault)
+ LongABI = Long32;
+
+ unsigned LongLength = (LongABI == Long64) ? 64 : 32;
+ LongWidth = LongAlign = LongLength;
+ PointerWidth = PointerAlign = LongLength;
+ }
+ }
+
void setO32ABITypes() {
+ setOABITypes();
+
Int64Type = SignedLongLong;
IntMaxType = Int64Type;
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
LongDoubleWidth = LongDoubleAlign = 64;
- LongWidth = LongAlign = 32;
MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
- PointerWidth = PointerAlign = 32;
PtrDiffType = IntPtrType = SignedInt;
SizeType = UnsignedInt;
SuitableAlign = 64;
}
+ void setO64ABITypes() {
+ setOABITypes();
+ Int64Type = SignedLongLong;
+ IntMaxType = Int64Type;
+ LongDoubleFormat = &llvm::APFloat::IEEEdouble();
+ LongDoubleWidth = LongDoubleAlign = 64;
+ MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
+ PtrDiffType = IntPtrType = SignedLong;
+ SizeType = UnsignedLong;
+ SuitableAlign = 64;
+ }
+
void setN32N64ABITypes() {
LongDoubleWidth = LongDoubleAlign = 128;
LongDoubleFormat = &llvm::APFloat::IEEEquad();
@@ -306,6 +337,7 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
DspRev = NoDSP;
NoOddSpreg = false;
FPMode = getDefaultFPMode();
+ LongABI = LongDefault;
bool OddSpregGiven = false;
bool StrictAlign = false;
bool FpGiven = false;
@@ -315,6 +347,14 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
IsSingleFloat = true;
else if (Feature == "+soft-float")
FloatABI = SoftFloat;
+ else if (Feature == "+long32") {
+ LongABI = Long32;
+ setOABITypes();
+ }
+ else if (Feature == "+long64") {
+ LongABI = Long64;
+ setOABITypes();
+ }
else if (Feature == "+mips16")
IsMips16 = true;
else if (Feature == "+micromips")
@@ -416,7 +456,7 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
{{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
{{"ra"}, "$31"}
};
- if (ABI == "o32")
+ if (ABI == "o64" || ABI == "o32")
return llvm::ArrayRef(O32RegAliases);
return llvm::ArrayRef(NewABIRegAliases);
}
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index e3187351a0b55..e0c956bc14f2e 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -12,6 +12,7 @@
#include "clang/Options/Options.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/Option/ArgList.h"
+#include "llvm/Option/OptSpecifier.h"
using namespace clang::driver;
using namespace clang::driver::tools;
@@ -104,6 +105,7 @@ void mips::getMipsCPUAndABI(const ArgList &Args, const llvm::Triple &Triple,
.Case("p5600", "o32")
.Case("i6400", "n64")
.Case("i6500", "n64")
+ .Case("r4300", "o64")
.Default("");
}
@@ -116,6 +118,7 @@ void mips::getMipsCPUAndABI(const ArgList &Args, const llvm::Triple &Triple,
// Deduce CPU name from ABI name.
CPUName = llvm::StringSwitch<const char *>(ABIName)
.Case("o32", DefMips32CPU)
+ .Case("o64", DefMips64CPU)
.Cases({"n32", "n64"}, DefMips64CPU)
.Default("");
}
@@ -129,6 +132,7 @@ std::string mips::getMipsABILibSuffix(const ArgList &Args,
tools::mips::getMipsCPUAndABI(Args, Triple, CPUName, ABIName);
return llvm::StringSwitch<std::string>(ABIName)
.Case("o32", "")
+ .Case("o64", "o64")
.Case("n32", "32")
.Case("n64", "64");
}
@@ -415,6 +419,15 @@ void mips::getMIPSTargetFeatures(const Driver &D, const llvm::Triple &Triple,
Features.push_back("+fp64");
}
+ // Add the last -mlong32/-mlong64, if none are given and the ABI is O32
+ // pass -mlong32.
+ if (Arg *A = Args.getLastArg(options::OPT_mlong32, options::OPT_mlong64)) {
+ if (A->getOption().matches(options::OPT_mlong32))
+ Features.push_back("+long32");
+ else if (A->getOption().matches(options::OPT_mlong64))
+ Features.push_back("+long64");
+ }
+
AddTargetFeature(Args, Features, options::OPT_mno_odd_spreg,
options::OPT_modd_spreg, "nooddspreg");
AddTargetFeature(Args, Features, options::OPT_mno_madd4, options::OPT_mmadd4,
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 0fe6b95e71148..2d7ea3a5a39b1 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -12,6 +12,7 @@
#include "MCTargetDesc/MipsMCAsmInfo.h"
#include "MCTargetDesc/MipsMCTargetDesc.h"
#include "MCTargetDesc/MipsTargetStreamer.h"
+#include "MipsRegisterInfo.h"
#include "TargetInfo/MipsTargetInfo.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/SmallVector.h"
@@ -599,6 +600,7 @@ class MipsAsmParser : public MCTargetAsmParser {
bool isABI_N32() const { return ABI.IsN32(); }
bool isABI_N64() const { return ABI.IsN64(); }
bool isABI_O32() const { return ABI.IsO32(); }
+ bool isABI_O64() const { return ABI.IsO64(); }
bool isABI_FPXX() const {
return getSTI().hasFeature(Mips::FeatureFPXX);
}
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
index 59c8e7c72224e..c9b24fb959387 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
@@ -27,6 +27,7 @@ cl::opt<bool>
namespace {
static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
+static const MCPhysReg O64IntRegs[4] = {Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64};
static const MCPhysReg Mips64IntRegs[8] = {
Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
@@ -36,6 +37,8 @@ static const MCPhysReg Mips64IntRegs[8] = {
ArrayRef<MCPhysReg> MipsABIInfo::GetByValArgRegs() const {
if (IsO32())
return ArrayRef(O32IntRegs);
+ if (IsO64())
+ return ArrayRef(O64IntRegs);
if (IsN32() || IsN64())
return ArrayRef(Mips64IntRegs);
llvm_unreachable("Unhandled ABI");
@@ -48,13 +51,19 @@ ArrayRef<MCPhysReg> MipsABIInfo::getVarArgRegs(bool isGP64bit) const {
else
return ArrayRef(O32IntRegs);
}
+ if (IsO64()) {
+ if (isGP64bit)
+ return ArrayRef(Mips64IntRegs);
+ else
+ return ArrayRef(O64IntRegs);
+ }
if (IsN32() || IsN64())
return ArrayRef(Mips64IntRegs);
llvm_unreachable("Unhandled ABI");
}
unsigned MipsABIInfo::GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const {
- if (IsO32())
+ if (IsO32() || IsO64())
return CC != CallingConv::Fast ? 16 : 0;
if (IsN32() || IsN64())
return 0;
@@ -64,6 +73,8 @@ unsigned MipsABIInfo::GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const {
MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef ABIName) {
if (ABIName.starts_with("o32"))
return MipsABIInfo::O32();
+ if (ABIName.starts_with("o64"))
+ return MipsABIInfo::O64();
if (ABIName.starts_with("n32"))
return MipsABIInfo::N32();
if (ABIName.starts_with("n64"))
@@ -129,5 +140,5 @@ unsigned MipsABIInfo::GetEhDataReg(unsigned I) const {
Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64
};
- return IsN64() ? EhDataReg64[I] : EhDataReg[I];
+ return (IsABI64()) ? EhDataReg64[I] : EhDataReg[I];
}
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
index d8003d2fcc164..e1ce417c228a4 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
@@ -21,7 +21,7 @@ class StringRef;
class MipsABIInfo {
public:
- enum class ABI { Unknown, O32, N32, N64 };
+ enum class ABI { Unknown, O32, O64, N32, N64 };
protected:
ABI ThisABI;
@@ -31,14 +31,17 @@ class MipsABIInfo {
static MipsABIInfo Unknown() { return MipsABIInfo(ABI::Unknown); }
static MipsABIInfo O32() { return MipsABIInfo(ABI::O32); }
+ static MipsABIInfo O64() { return MipsABIInfo(ABI::O64); }
static MipsABIInfo N32() { return MipsABIInfo(ABI::N32); }
static MipsABIInfo N64() { return MipsABIInfo(ABI::N64); }
static MipsABIInfo computeTargetABI(const Triple &TT, StringRef ABIName);
bool IsKnown() const { return ThisABI != ABI::Unknown; }
bool IsO32() const { return ThisABI == ABI::O32; }
+ bool IsO64() const { return ThisABI == ABI::O64; }
bool IsN32() const { return ThisABI == ABI::N32; }
bool IsN64() const { return ThisABI == ABI::N64; }
+ bool IsABI64() const { return ThisABI == ABI::N64 || ThisABI == ABI::O64; }
ABI GetEnumValue() const { return ThisABI; }
/// The registers to use for byval arguments.
@@ -69,7 +72,7 @@ class MipsABIInfo {
unsigned GetPtrSubuOp() const;
unsigned GetPtrAndOp() const;
unsigned GetGPRMoveOp() const;
- inline bool ArePtrs64bit() const { return IsN64(); }
+ inline bool ArePtrs64bit() const { return IsO64() || IsN64(); }
inline bool AreGprs64bit() const { return IsN32() || IsN64(); }
unsigned GetEhDataReg(unsigned I) const;
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
index dbb0af75f3651..762595ab323cd 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
@@ -28,10 +28,10 @@ MipsELFMCAsmInfo::MipsELFMCAsmInfo(const Triple &TheTriple,
MipsABIInfo ABI =
MipsABIInfo::computeTargetABI(TheTriple, Options.getABIName());
- if (TheTriple.isMIPS64() && !ABI.IsN32())
+ if (TheTriple.isMIPS64() && !(ABI.IsN32() || ABI.IsO64()))
CodePointerSize = CalleeSaveStackSlotSize = 8;
- if (ABI.IsO32())
+ if (ABI.IsO32() || ABI.IsO64())
InternalSymbolPrefix = "$";
else if (ABI.IsN32() || ABI.IsN64())
InternalSymbolPrefix = ".L";
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 3b78de8ec43ad..c84b9580d15a6 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -151,6 +151,12 @@ def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion",
def FeatureSym32 : SubtargetFeature<"sym32", "HasSym32", "true",
"Symbols are 32 bit on Mips64">;
+def FeatureLong32 : SubtargetFeature<"long32", "LongABI", "Long32",
+ "Longs are 32 bits on OABI">;
+def FeatureLong64 : SubtargetFeature<"long64", "LongABI", "Long64",
+ "Longs are 64 bits on OABI",
+ [FeatureGP64Bit, FeaturePTR64Bit]>;
+
def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
"Mips16 mode">;
@@ -186,9 +192,16 @@ def FeatureCnMipsP : SubtargetFeature<"cnmipsp", "HasCnMipsP",
"true", "Octeon+ cnMIPS Support",
[FeatureCnMips]>;
+def FeatureFixR4300 : SubtargetFeature<"fix-r4300", "FixR4300", "true",
+ "Enable R4300 mulmul erratum fix">;
+
def FeatureFixR5900 : SubtargetFeature<"fix-r5900", "FixR5900", "true",
"Enable R5900 short loop erratum fix">;
+def FeatureR4300 : SubtargetFeature<"r4300", "IsR4300", "true",
+ "R4300 (Nintendo 64 CPU-NUS) Support",
+ [FeatureMips64, FeatureFixR4300]>;
+
def FeatureR5900 : SubtargetFeature<"r5900", "IsR5900", "true",
"R5900 (PS2 Emotion Engine) Support",
[FeatureMips3, FeatureSingleFloat,
@@ -228,9 +241,9 @@ def FeatureUseCompactBranches
// Mips Instruction Predicate Definitions.
//===----------------------------------------------------------------------===//
-def IsPTR64bit : Predicate<"Subtarget->isABI_N64()">,
+def IsPTR64bit : Predicate<"Subtarget->isABI_64Bit()">,
AssemblerPredicate<(all_of FeaturePTR64Bit)>;
-def IsPTR32bit : Predicate<"!Subtarget->isABI_N64()">,
+def IsPTR32bit : Predicate<"!Subtarget->isABI_64Bit()">,
AssemblerPredicate<(all_of (not FeaturePTR64Bit))>;
def UseCompactBranches : Predicate<"Subtarget->useCompactBranches()">,
AssemblerPredicate<(all_of FeatureUseCompactBranches)>;
@@ -307,6 +320,7 @@ def : Proc<"mips64r5", [FeatureMips64r5]>;
def : Proc<"mips64r6", [FeatureMips64r6]>;
def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
def : Proc<"octeon+", [FeatureMips64r2, FeatureCnMips, FeatureCnMipsP]>;
+def : Proc<"r4300", [FeatureR4300]>;
def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
def : Proc<"r5900", [FeatureR5900]>;
def : ProcessorModel<"i6400", MipsI6400Model, [ImplI6400]>;
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
index adda6154e15a5..4ffc78d39928d 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -386,6 +386,7 @@ void MipsAsmPrinter::emitFrameDirective() {
const char *MipsAsmPrinter::getCurrentABIString() const {
switch (static_cast<MipsTargetMachine &>(TM).getABI().GetEnumValue()) {
case MipsABIInfo::ABI::O32: return "abi32";
+ case MipsABIInfo::ABI::O64: return "abiO64";
case MipsABIInfo::ABI::N32: return "abiN32";
case MipsABIInfo::ABI::N64: return "abi64";
default: llvm_unreachable("Unknown Mips ABI");
diff --git a/llvm/lib/Target/Mips/MipsCallingConv.td b/llvm/lib/Target/Mips/MipsCallingConv.td
index d3e552bc71ca9..10727c9ab6bfa 100644
--- a/llvm/lib/Target/Mips/MipsCallingConv.td
+++ b/llvm/lib/Target/Mips/MipsCallingConv.td
@@ -107,6 +107,49 @@ def CC_MipsO32_FP : CallingConv<[
CCIfSubtarget<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP64>>
]>;
+//===----------------------------------------------------------------------===//
+// Mips O64 Calling Convention...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/223990
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