[clang] [llvm] [RISCV][P-ext] Support Packed Subvector Join (PR #224233)
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Thu Sep 17 05:57:51 PDT 2026
https://github.com/Michael-Chen-NJU updated https://github.com/llvm/llvm-project/pull/224233
>From 95542cb014100252cfb112487f4ca6f07b6fe35b Mon Sep 17 00:00:00 2001
From: Michael-Chen-NJU <2802328816 at qq.com>
Date: Thu, 17 Sep 2026 16:18:40 +0800
Subject: [PATCH] [RISCV][P-ext] Support Packed Subvector Join
---
clang/lib/Headers/riscv_packed_simd.h | 17 ++++
clang/test/CodeGen/RISCV/rvp-intrinsics.c | 90 +++++++++++++++++++
.../riscv_packed_simd.c | 28 ++++++
3 files changed, 135 insertions(+)
diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h
index 097382c762df2..8c20d00e68652 100644
--- a/clang/lib/Headers/riscv_packed_simd.h
+++ b/clang/lib/Headers/riscv_packed_simd.h
@@ -251,6 +251,15 @@ typedef uint32_t uint32x2_t __attribute__((__vector_size__(8)));
return __builtin_shufflevector(__rs1, __rs1, 1, 3, 5, 7); \
}
+#define __packed_concat2(name, rty, ty) \
+ static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __lo, ty __hi) { \
+ return __builtin_shufflevector(__lo, __hi, 0, 1, 2, 3); \
+ }
+#define __packed_concat4(name, rty, ty) \
+ static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __lo, ty __hi) { \
+ return __builtin_shufflevector(__lo, __hi, 0, 1, 2, 3, 4, 5, 6, 7); \
+ }
+
#define __packed_pair_ee4(name, ty) \
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \
return __builtin_shufflevector(__rs1, __rs2, 0, 4, 2, 6); \
@@ -1099,6 +1108,12 @@ __packed_binary_builtin_cast(pnclipup_u16x4, uint32x2_t, uint16x4_t, __builtin_r
__packed_binary_builtin_cast(pnclipp_i32x2, int64_t, int32x2_t, __builtin_riscv_pnclipp_i32x2)
__packed_binary_builtin_cast(pnclipup_u32x2, uint64_t, uint32x2_t, __builtin_riscv_pnclipup_u32x2)
+/* Packed Subvector Join */
+__packed_concat4(pjoin2_i8x8, int8x8_t, int8x4_t)
+__packed_concat4(pjoin2_u8x8, uint8x8_t, uint8x4_t)
+__packed_concat2(pjoin2_i16x4, int16x4_t, int16x2_t)
+__packed_concat2(pjoin2_u16x4, uint16x4_t, uint16x2_t)
+
/* Packed Store (32-bit) */
__packed_store(pst_i8x4, int8x4_t, int8_t)
__packed_store(pst_u8x4, uint8x4_t, uint8_t)
@@ -1277,6 +1292,8 @@ __packed_reinterpret(u32x2_i32x2, int32x2_t, uint32x2_t)
#undef __packed_unzipe4
#undef __packed_unzipo2
#undef __packed_unzipo4
+#undef __packed_concat2
+#undef __packed_concat4
#undef __packed_pair_ee4
#undef __packed_pair_eo4
#undef __packed_pair_oe4
diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
index 0d3eee49a0ec5..b2b2b1b9a777b 100644
--- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c
+++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
@@ -11774,3 +11774,93 @@ int8x4_t test_pld_i8x4_aligned(int8_t *p) {
int32x2_t test_pld_i32x2_aligned(int32_t *p) {
return __riscv_pld_i32x2(__builtin_assume_aligned(p, 8));
}
+
+/* Packed Subvector Join */
+
+// RV32-LABEL: define dso_local i64 @test_pjoin2_i8x8(
+// RV32-SAME: i32 noundef [[LO_COERCE:%.*]], i32 noundef [[HI_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[LO_COERCE]] to <4 x i8>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[HI_COERCE]] to <4 x i8>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// RV32-NEXT: ret i64 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i64 @test_pjoin2_i8x8(
+// RV64-SAME: i32 noundef [[LO_COERCE:%.*]], i32 noundef [[HI_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[LO_COERCE]] to <4 x i8>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[HI_COERCE]] to <4 x i8>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// RV64-NEXT: ret i64 [[TMP2]]
+//
+int8x8_t test_pjoin2_i8x8(int8x4_t lo, int8x4_t hi) {
+ return __riscv_pjoin2_i8x8(lo, hi);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pjoin2_u8x8(
+// RV32-SAME: i32 noundef [[LO_COERCE:%.*]], i32 noundef [[HI_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[LO_COERCE]] to <4 x i8>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[HI_COERCE]] to <4 x i8>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// RV32-NEXT: ret i64 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i64 @test_pjoin2_u8x8(
+// RV64-SAME: i32 noundef [[LO_COERCE:%.*]], i32 noundef [[HI_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[LO_COERCE]] to <4 x i8>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[HI_COERCE]] to <4 x i8>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// RV64-NEXT: ret i64 [[TMP2]]
+//
+uint8x8_t test_pjoin2_u8x8(uint8x4_t lo, uint8x4_t hi) {
+ return __riscv_pjoin2_u8x8(lo, hi);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pjoin2_i16x4(
+// RV32-SAME: i32 noundef [[LO_COERCE:%.*]], i32 noundef [[HI_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[LO_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[HI_COERCE]] to <2 x i16>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// RV32-NEXT: ret i64 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i64 @test_pjoin2_i16x4(
+// RV64-SAME: i32 noundef [[LO_COERCE:%.*]], i32 noundef [[HI_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[LO_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[HI_COERCE]] to <2 x i16>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// RV64-NEXT: ret i64 [[TMP2]]
+//
+int16x4_t test_pjoin2_i16x4(int16x2_t lo, int16x2_t hi) {
+ return __riscv_pjoin2_i16x4(lo, hi);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pjoin2_u16x4(
+// RV32-SAME: i32 noundef [[LO_COERCE:%.*]], i32 noundef [[HI_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[LO_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[HI_COERCE]] to <2 x i16>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// RV32-NEXT: ret i64 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i64 @test_pjoin2_u16x4(
+// RV64-SAME: i32 noundef [[LO_COERCE:%.*]], i32 noundef [[HI_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[LO_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[HI_COERCE]] to <2 x i16>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// RV64-NEXT: ret i64 [[TMP2]]
+//
+uint16x4_t test_pjoin2_u16x4(uint16x2_t lo, uint16x2_t hi) {
+ return __riscv_pjoin2_u16x4(lo, hi);
+}
diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
index 5da623e723560..f3857cedc3b5a 100644
--- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
@@ -4743,3 +4743,31 @@ int8x8_t test_pld_i8x8_aligned(int8_t *p) {
uint32x2_t test_pld_u32x2_aligned(uint32_t *p) {
return __riscv_pld_u32x2(__builtin_assume_aligned(p, 8));
}
+
+// CHECK-LABEL: test_pjoin2_i8x8:
+// RV32: ret
+// RV64: pack
+int8x8_t test_pjoin2_i8x8(int8x4_t lo, int8x4_t hi) {
+ return __riscv_pjoin2_i8x8(lo, hi);
+}
+
+// CHECK-LABEL: test_pjoin2_u8x8:
+// RV32: ret
+// RV64: pack
+uint8x8_t test_pjoin2_u8x8(uint8x4_t lo, uint8x4_t hi) {
+ return __riscv_pjoin2_u8x8(lo, hi);
+}
+
+// CHECK-LABEL: test_pjoin2_i16x4:
+// RV32: ret
+// RV64: pack
+int16x4_t test_pjoin2_i16x4(int16x2_t lo, int16x2_t hi) {
+ return __riscv_pjoin2_i16x4(lo, hi);
+}
+
+// CHECK-LABEL: test_pjoin2_u16x4:
+// RV32: ret
+// RV64: pack
+uint16x4_t test_pjoin2_u16x4(uint16x2_t lo, uint16x2_t hi) {
+ return __riscv_pjoin2_u16x4(lo, hi);
+}
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