[clang] [compiler-rt] [llvm] Add SuperH (1-4a) target (PR #181287)
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Wed Sep 16 11:06:26 PDT 2026
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git-clang-format --diff origin/main HEAD --extensions h,cpp -- clang/lib/Basic/Targets/SuperH.cpp clang/lib/Basic/Targets/SuperH.h clang/lib/CodeGen/Targets/SuperH.cpp llvm/lib/Target/SuperH/AsmParser/SuperHAsmParser.cpp llvm/lib/Target/SuperH/MCTargetDesc/SuperHAsmBackend.cpp llvm/lib/Target/SuperH/MCTargetDesc/SuperHAsmBackend.h llvm/lib/Target/SuperH/MCTargetDesc/SuperHBaseInfo.h llvm/lib/Target/SuperH/MCTargetDesc/SuperHELFObjectWriter.cpp llvm/lib/Target/SuperH/MCTargetDesc/SuperHFixupKinds.h llvm/lib/Target/SuperH/MCTargetDesc/SuperHInstPrinter.cpp llvm/lib/Target/SuperH/MCTargetDesc/SuperHInstPrinter.h llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCAsmInfo.cpp llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCAsmInfo.h llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCCodeEmitter.cpp llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCTargetDesc.cpp llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCTargetDesc.h llvm/lib/Target/SuperH/MCTargetDesc/SuperHTargetStreamer.cpp llvm/lib/Target/SuperH/MCTargetDesc/SuperHTargetStreamer.h llvm/lib/Target/SuperH/SuperH.h llvm/lib/Target/SuperH/SuperHAsmPrinter.cpp llvm/lib/Target/SuperH/SuperHBasicBlockInfo.cpp llvm/lib/Target/SuperH/SuperHBasicBlockInfo.h llvm/lib/Target/SuperH/SuperHConstantIslandPass.cpp llvm/lib/Target/SuperH/SuperHConstantPoolValue.cpp llvm/lib/Target/SuperH/SuperHConstantPoolValue.h llvm/lib/Target/SuperH/SuperHExpandPseudoInsts.cpp llvm/lib/Target/SuperH/SuperHFillDelaySlots.cpp llvm/lib/Target/SuperH/SuperHFrameLowering.cpp llvm/lib/Target/SuperH/SuperHFrameLowering.h llvm/lib/Target/SuperH/SuperHISelDAGToDAG.cpp llvm/lib/Target/SuperH/SuperHISelLowering.cpp llvm/lib/Target/SuperH/SuperHISelLowering.h llvm/lib/Target/SuperH/SuperHInstrInfo.cpp llvm/lib/Target/SuperH/SuperHInstrInfo.h llvm/lib/Target/SuperH/SuperHMCInstLower.cpp llvm/lib/Target/SuperH/SuperHMCInstLower.h llvm/lib/Target/SuperH/SuperHMachineFunctionInfo.cpp llvm/lib/Target/SuperH/SuperHMachineFunctionInfo.h llvm/lib/Target/SuperH/SuperHRegisterInfo.cpp llvm/lib/Target/SuperH/SuperHRegisterInfo.h llvm/lib/Target/SuperH/SuperHSelectionDAGInfo.cpp llvm/lib/Target/SuperH/SuperHSelectionDAGInfo.h llvm/lib/Target/SuperH/SuperHSubtarget.cpp llvm/lib/Target/SuperH/SuperHSubtarget.h llvm/lib/Target/SuperH/SuperHTargetMachine.cpp llvm/lib/Target/SuperH/SuperHTargetMachine.h llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.cpp llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.h clang/include/clang/Basic/Specifiers.h clang/lib/Basic/Targets.cpp clang/lib/CodeGen/CodeGenModule.cpp clang/lib/CodeGen/TargetInfo.h llvm/include/llvm/BinaryFormat/ELF.h llvm/include/llvm/TargetParser/Triple.h llvm/lib/TargetParser/TargetDataLayout.cpp llvm/lib/TargetParser/Triple.cpp --diff_from_common_commit
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diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index a48e9fe06..74a821820 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -552,7 +552,7 @@ std::unique_ptr<TargetInfo> AllocateTarget(const llvm::Triple &Triple,
default:
return std::make_unique<SparcV9TargetInfo>(Triple, Opts);
}
-
+
case llvm::Triple::sh:
case llvm::Triple::shl:
switch (os) {
diff --git a/clang/lib/Basic/Targets/SuperH.cpp b/clang/lib/Basic/Targets/SuperH.cpp
index 62387f651..e259faa3b 100644
--- a/clang/lib/Basic/Targets/SuperH.cpp
+++ b/clang/lib/Basic/Targets/SuperH.cpp
@@ -22,20 +22,16 @@ struct LLVM_LIBRARY_VISIBILITY SHCPUInfo {
};
static constexpr SHCPUInfo CPUInfo[] = {
- {{"sh1"}},
- {{"sh2"}},
- {{"sh2a"}},
- {{"sh3"}},
- {{"sh4"}},
- {{"sh4a"}},
+ {{"sh1"}}, {{"sh2"}}, {{"sh2a"}}, {{"sh3"}}, {{"sh4"}}, {{"sh4a"}},
};
bool SuperHTargetInfo::isValidCPUName(StringRef Name) const {
- return llvm::any_of(
- CPUInfo, [&](const SHCPUInfo &Info) { return Info.Name == Name; });
+ return llvm::any_of(CPUInfo,
+ [&](const SHCPUInfo &Info) { return Info.Name == Name; });
}
-void SuperHTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
+void SuperHTargetInfo::fillValidCPUList(
+ SmallVectorImpl<StringRef> &Values) const {
for (const SHCPUInfo &Info : CPUInfo)
Values.push_back(Info.Name);
}
@@ -60,7 +56,7 @@ SuperHTargetInfo::handleAsmEscapedChar(char EscChar) const {
}
void SuperHTargetInfo::getTargetDefines(const LangOptions &Opts,
- MacroBuilder &Builder) const {
+ MacroBuilder &Builder) const {
Builder.defineMacro("SH");
Builder.defineMacro("__SH");
Builder.defineMacro("__SH__");
diff --git a/clang/lib/Basic/Targets/SuperH.h b/clang/lib/Basic/Targets/SuperH.h
index 974ea928e..11d51e9d6 100644
--- a/clang/lib/Basic/Targets/SuperH.h
+++ b/clang/lib/Basic/Targets/SuperH.h
@@ -77,9 +77,8 @@ public:
ArrayRef<const char *> getGCCRegNames() const override {
static const char *const GCCRegNames[] = {
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8",
- "r9", "r10", "r11", "r12", "r13", "r14", "r15"
- };
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
return llvm::ArrayRef(GCCRegNames);
}
@@ -107,7 +106,7 @@ protected:
StringRef ABI;
};
-}
-}
+} // namespace targets
+} // namespace clang
#endif
\ No newline at end of file
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp
index 7bb48593e..841034e6b 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -246,7 +246,7 @@ createTargetCodeGenInfo(CodeGenModule &CGM) {
bool EABI = ABIStr.ends_with("e");
return createRISCVTargetCodeGenInfo(CGM, XLen, ABIFLen, EABI);
}
-
+
case llvm::Triple::sh:
case llvm::Triple::shl: {
return createSuperHTargetCodeGenInfo(CGM);
diff --git a/clang/lib/CodeGen/Targets/SuperH.cpp b/clang/lib/CodeGen/Targets/SuperH.cpp
index eae3cd39d..3b2a15faa 100644
--- a/clang/lib/CodeGen/Targets/SuperH.cpp
+++ b/clang/lib/CodeGen/Targets/SuperH.cpp
@@ -22,15 +22,13 @@ using namespace clang::CodeGen;
namespace {
class SuperHABIInfo : public DefaultABIInfo {
public:
- SuperHABIInfo(CodeGenTypes &CGT)
- : DefaultABIInfo(CGT) {}
+ SuperHABIInfo(CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
ABIArgInfo classifyReturnType(QualType Ty, bool &LargeRet) const {
// We have a total of 64 bits of return space in R0 and R1,
// if we can fit a struct in there, do.
- if (isAggregateTypeForABI(Ty) &&
- getContext().getTypeSize(Ty) <= 64)
+ if (isAggregateTypeForABI(Ty) && getContext().getTypeSize(Ty) <= 64)
return ABIArgInfo::getDirect();
// Otherwise, we store a pointer to the struct in R2 and return that.
@@ -70,22 +68,20 @@ public:
bool LargeRet = false;
if (!getCXXABI().classifyReturnType(FI))
FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), LargeRet);
-
+
// Decide each argument type.
unsigned NumRegs = 4;
for (auto &I : FI.arguments())
I.info = classifyArgumentType(I.type, NumRegs);
}
-
};
class SuperHTargetCodeGenInfo : public TargetCodeGenInfo {
public:
SuperHTargetCodeGenInfo(CodeGenTypes &CGT)
: TargetCodeGenInfo(std::make_unique<SuperHABIInfo>(CGT)) {}
-
};
-}
+} // namespace
std::unique_ptr<TargetCodeGenInfo>
CodeGen::createSuperHTargetCodeGenInfo(CodeGenModule &CGM) {
diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h
index 475137cb3..edf253206 100644
--- a/llvm/include/llvm/TargetParser/Triple.h
+++ b/llvm/include/llvm/TargetParser/Triple.h
@@ -1193,7 +1193,7 @@ public:
bool isSPARC() const { return isSPARC32() || isSPARC64(); }
/// Tests whether the target is SuperH.
- bool isSuperH() const {
+ bool isSuperH() const {
return getArch() == Triple::sh || getArch() == Triple::shl;
}
diff --git a/llvm/lib/Target/SuperH/AsmParser/SuperHAsmParser.cpp b/llvm/lib/Target/SuperH/AsmParser/SuperHAsmParser.cpp
index e4921dbac..f5ff2b155 100644
--- a/llvm/lib/Target/SuperH/AsmParser/SuperHAsmParser.cpp
+++ b/llvm/lib/Target/SuperH/AsmParser/SuperHAsmParser.cpp
@@ -10,37 +10,34 @@
#include "MCTargetDesc/SuperHMCTargetDesc.h"
#include "SuperHRegisterInfo.h"
#include "TargetInfo/SuperHTargetInfo.h"
+#include "iostream"
#include "llvm/Analysis/Utils/TrainingLogger.h"
-#include "llvm/MC/MCELFStreamer.h"
-#include "llvm/MC/MCInstrAnalysis.h"
-#include "llvm/MC/MCInstPrinter.h"
-#include "llvm/MC/MCInstrInfo.h"
-#include "llvm/MC/MCRegister.h"
-#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCValue.h"
-#include "llvm/MC/TargetRegistry.h"
#include "llvm/MC/MCAsmMacro.h"
#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCELFStreamer.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstBuilder.h"
+#include "llvm/MC/MCInstPrinter.h"
+#include "llvm/MC/MCInstrAnalysis.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCObjectFileInfo.h"
#include "llvm/MC/MCParser/AsmLexer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
#include "llvm/MC/MCParser/MCTargetAsmParser.h"
+#include "llvm/MC/MCRegister.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
+#include "llvm/MC/MCValue.h"
+#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/DebugLog.h"
#include "llvm/Support/LogicalResult.h"
#include "llvm/Support/SMLoc.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Support/DebugLog.h"
-#include "iostream"
#include <cstddef>
#include <sstream>
#include <system_error>
@@ -54,7 +51,7 @@ using namespace llvm;
namespace llvm {
namespace SuperH {
- using namespace SH;
+using namespace SH;
} // end namespace SuperH
} // end namespace llvm
@@ -64,7 +61,7 @@ class SuperHOperand;
// Helper that gets a string from a SMLoc pair.
StringRef StrFromLoc(SMLoc StartLoc, SMLoc EndLoc) {
- ptrdiff_t Length = (ptrdiff_t)(EndLoc.getPointer()-StartLoc.getPointer());
+ ptrdiff_t Length = (ptrdiff_t)(EndLoc.getPointer() - StartLoc.getPointer());
return StringRef(StartLoc.getPointer(), Length);
}
@@ -75,24 +72,30 @@ class SuperHAsmParser : public MCTargetAsmParser {
#define GET_ASSEMBLER_HEADER
#include "SuperHGenAsmMatcher.inc"
- bool parseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override;
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ SMLoc NameLoc, OperandVector &Operands) override;
ParseStatus parseDirective(AsmToken DirectiveID) override;
bool parseGNUAttribute(SMLoc L);
bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
- OperandVector &Operands, MCStreamer &Out,
- uint64_t &ErrorInfo,
- bool MatchingInlineAsm) override;
+ OperandVector &Operands, MCStreamer &Out,
+ uint64_t &ErrorInfo,
+ bool MatchingInlineAsm) override;
// Register Parsing
- ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
+ ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
+ SMLoc &EndLoc) override;
bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
// Parser helpers.
MCRegister matchRegisterName(const AsmToken &Tok, unsigned &RegKind);
ParseStatus tryParseImm(int64_t &Imm, SMLoc &StartLoc, SMLoc &EndLoc);
- ParseStatus tryParseRegister(MCRegister &Reg, unsigned &RegKind, SMLoc &StartLoc, SMLoc &EndLoc);
- ParseStatus tryParseRegRelative(MCRegister &BaseReg, MCRegister &OffReg, const MCExpr *&Offset, SMLoc &StartLoc, SMLoc &EndLoc);
- ParseStatus tryParseRegIndirect(MCRegister &Reg, bool &IsInc, bool &IsDec, SMLoc &StartLoc, SMLoc &EndLoc);
+ ParseStatus tryParseRegister(MCRegister &Reg, unsigned &RegKind,
+ SMLoc &StartLoc, SMLoc &EndLoc);
+ ParseStatus tryParseRegRelative(MCRegister &BaseReg, MCRegister &OffReg,
+ const MCExpr *&Offset, SMLoc &StartLoc,
+ SMLoc &EndLoc);
+ ParseStatus tryParseRegIndirect(MCRegister &Reg, bool &IsInc, bool &IsDec,
+ SMLoc &StartLoc, SMLoc &EndLoc);
// Parser entry points
ParseStatus parseOperand(OperandVector &Operands);
@@ -103,8 +106,9 @@ class SuperHAsmParser : public MCTargetAsmParser {
ParseStatus parseDisp(OperandVector &Operands);
public:
- SuperHAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser, const MCInstrInfo &MII)
- : MCTargetAsmParser(sti, MII), Parser(parser),
+ SuperHAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
+ const MCInstrInfo &MII)
+ : MCTargetAsmParser(sti, MII), Parser(parser),
MRI(*Parser.getContext().getRegisterInfo()) {
setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
@@ -129,19 +133,18 @@ public:
};
private:
-
// These are set up as bitflags to allow general comparisons
// to happen with some simple bit masking.
enum KindTy {
- k_Token = 0x001,
- k_Register = 0x002,
- k_Immediate = 0x004,
- k_Displacement = 0x008,
- k_IndirectReg = 0x010,
- k_IndirectRegInc = 0x020,
- k_IndirectRegDec = 0x040,
- k_IndirectIndex = 0x080,
- k_Expression = 0x100
+ k_Token = 0x001,
+ k_Register = 0x002,
+ k_Immediate = 0x004,
+ k_Displacement = 0x008,
+ k_IndirectReg = 0x010,
+ k_IndirectRegInc = 0x020,
+ k_IndirectRegDec = 0x040,
+ k_IndirectIndex = 0x080,
+ k_Expression = 0x100
};
unsigned Kind;
@@ -189,11 +192,16 @@ public:
bool isImm() const override { return Kind == k_Immediate; }
bool isReg() const override { return Kind == k_Register; }
bool isDisp() const { return Kind == k_Displacement; }
- bool isMem() const override { return (Kind & (k_IndirectReg | k_IndirectRegInc | k_IndirectRegDec | k_IndirectIndex)) != 0; }
+ bool isMem() const override {
+ return (Kind & (k_IndirectReg | k_IndirectRegInc | k_IndirectRegDec |
+ k_IndirectIndex)) != 0;
+ }
bool isIReg() const { return Kind == k_IndirectReg; }
bool isIRegInc() const { return Kind == k_IndirectRegInc; }
bool isIRegDec() const { return Kind == k_IndirectRegDec; }
- bool isAnyReg() const { return isReg() || isIReg() || isIRegInc() || isIRegDec(); }
+ bool isAnyReg() const {
+ return isReg() || isIReg() || isIRegInc() || isIRegDec();
+ }
bool isPCRel() const { return Kind == k_Displacement && Mem.Base == SH::PC; }
SMLoc getStartLoc() const override { return StartLoc; }
@@ -232,7 +240,7 @@ public:
Inst.addOperand(MCOperand::createReg(getReg()));
}
- void addExpr(MCInst &Inst, const MCExpr *Expr) const{
+ void addExpr(MCInst &Inst, const MCExpr *Expr) const {
// Add as immediate when possible. Null MCExpr = 0.
if (!Expr)
Inst.addOperand(MCOperand::createImm(0));
@@ -286,7 +294,8 @@ public:
return Op;
}
- static std::unique_ptr<SuperHOperand> CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
+ static std::unique_ptr<SuperHOperand> CreateImm(const MCExpr *Val, SMLoc S,
+ SMLoc E) {
auto Op = std::make_unique<SuperHOperand>(k_Immediate);
Op->Imm.Val = Val;
Op->StartLoc = S;
@@ -294,7 +303,8 @@ public:
return Op;
}
- static std::unique_ptr<SuperHOperand> CreateDisp(MCRegister Reg, const MCExpr *Val, SMLoc S, SMLoc E) {
+ static std::unique_ptr<SuperHOperand>
+ CreateDisp(MCRegister Reg, const MCExpr *Val, SMLoc S, SMLoc E) {
auto Op = std::make_unique<SuperHOperand>(k_Displacement);
Op->Mem.Base = Reg;
Op->Mem.Offset = Val;
@@ -303,7 +313,8 @@ public:
return Op;
}
- static std::unique_ptr<SuperHOperand> CreateSymRef(const MCExpr *Val, SMLoc S, SMLoc E) {
+ static std::unique_ptr<SuperHOperand> CreateSymRef(const MCExpr *Val, SMLoc S,
+ SMLoc E) {
auto Op = std::make_unique<SuperHOperand>(k_Displacement);
Op->Mem.Base = SH::PC;
Op->Mem.Offset = Val;
@@ -312,7 +323,8 @@ public:
return Op;
}
- static std::unique_ptr<SuperHOperand> CreateIReg(MCRegister Reg, SMLoc S, SMLoc E) {
+ static std::unique_ptr<SuperHOperand> CreateIReg(MCRegister Reg, SMLoc S,
+ SMLoc E) {
auto Op = std::make_unique<SuperHOperand>(k_IndirectReg);
Op->Mem.Base = Reg;
Op->StartLoc = S;
@@ -320,7 +332,8 @@ public:
return Op;
}
- static std::unique_ptr<SuperHOperand> CreateIRegInc(MCRegister Reg, SMLoc S, SMLoc E) {
+ static std::unique_ptr<SuperHOperand> CreateIRegInc(MCRegister Reg, SMLoc S,
+ SMLoc E) {
auto Op = std::make_unique<SuperHOperand>(k_IndirectRegInc);
Op->Mem.Base = Reg;
Op->StartLoc = S;
@@ -328,7 +341,8 @@ public:
return Op;
}
- static std::unique_ptr<SuperHOperand> CreateIRegDec(MCRegister Reg, SMLoc S, SMLoc E) {
+ static std::unique_ptr<SuperHOperand> CreateIRegDec(MCRegister Reg, SMLoc S,
+ SMLoc E) {
auto Op = std::make_unique<SuperHOperand>(k_IndirectRegDec);
Op->Mem.Base = Reg;
Op->StartLoc = S;
@@ -336,8 +350,9 @@ public:
return Op;
}
- static std::unique_ptr<SuperHOperand> CreateIIndex(MCRegister Base, MCRegister OffsetReg,
- const MCExpr *Offset,
+ static std::unique_ptr<SuperHOperand> CreateIIndex(MCRegister Base,
+ MCRegister OffsetReg,
+ const MCExpr *Offset,
SMLoc S, SMLoc E) {
auto Op = std::make_unique<SuperHOperand>(k_IndirectIndex);
Op->Mem.Base = Base;
@@ -348,8 +363,8 @@ public:
return Op;
}
- static std::unique_ptr<SuperHOperand> CreateExpr(const MCExpr *Expr,
- SMLoc S, SMLoc E) {
+ static std::unique_ptr<SuperHOperand> CreateExpr(const MCExpr *Expr, SMLoc S,
+ SMLoc E) {
auto Op = std::make_unique<SuperHOperand>(k_Expression);
Op->Expr.Val = Expr;
Op->StartLoc = S;
@@ -357,8 +372,8 @@ public:
return Op;
}
- static std::unique_ptr<SuperHOperand> CreateFromExpr(const MCExpr *Expr,
- SMLoc S, SMLoc E) {
+ static std::unique_ptr<SuperHOperand> CreateFromExpr(const MCExpr *Expr,
+ SMLoc S, SMLoc E) {
if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
return CreateDisp(SH::PC, CE, S, E);
@@ -380,7 +395,7 @@ public:
// Indirect register has @ prefix.
if (isIReg())
OS << "@";
-
+
// Pre-decrement.
if (isIRegDec())
OS << "-";
@@ -402,39 +417,40 @@ public:
#define GET_MNEMONIC_CHECKER
#include "SuperHGenAsmMatcher.inc"
-MCRegister SuperHAsmParser::matchRegisterName(const AsmToken &Tok, unsigned &RegKind) {
+MCRegister SuperHAsmParser::matchRegisterName(const AsmToken &Tok,
+ unsigned &RegKind) {
RegKind = SuperHOperand::rk_None;
- if(Tok.isNot(AsmToken::Identifier))
+ if (Tok.isNot(AsmToken::Identifier))
return SH::NoRegister;
std::string Name = Tok.getString().lower();
MCRegister Reg = MatchRegisterName(Name);
if (MRI.getRegClass(SH::GPRRegClassID).contains(Reg)) {
-
+
// General purpose register class.
RegKind = SuperHOperand::rk_GPR;
} else if (Reg == SH::XMTRX) {
-
+
// XMTRX register.
RegKind = SuperHOperand::rk_XMTRX;
} else if (MRI.getRegClass(SH::SYSRegClassID).contains(Reg)) {
-
+
// System register class.
RegKind = SuperHOperand::rk_SYS;
} else if (MRI.getRegClass(SH::CTRLRegClassID).contains(Reg)) {
-
+
// Control register class.
RegKind = SuperHOperand::rk_CTRL;
} else if (MRI.getRegClass(SH::FR32RegClassID).contains(Reg)) {
-
+
// 32-bit float registers.
RegKind = SuperHOperand::rk_FR32;
} else if (MRI.getRegClass(SH::FR64RegClassID).contains(Reg)) {
-
+
// 64-bit float registers.
RegKind = SuperHOperand::rk_FR64;
} else if (MRI.getRegClass(SH::VEC128RegClassID).contains(Reg)) {
-
+
// 128-bit vector registers.
RegKind = SuperHOperand::rk_VEC128;
}
@@ -442,13 +458,15 @@ MCRegister SuperHAsmParser::matchRegisterName(const AsmToken &Tok, unsigned &Reg
return Reg;
}
-bool SuperHAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) {
+bool SuperHAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
+ SMLoc &EndLoc) {
if (!tryParseRegister(Reg, StartLoc, EndLoc).isSuccess())
- return Error(StartLoc, "invalid register name");
+ return Error(StartLoc, "invalid register name");
return false;
}
-ParseStatus SuperHAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) {
+ParseStatus SuperHAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
+ SMLoc &EndLoc) {
unsigned RegKind;
const AsmToken Tok = Parser.getTok();
StartLoc = Tok.getLoc();
@@ -464,15 +482,14 @@ ParseStatus SuperHAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
return ParseStatus::Success;
}
-
-
-
//===----------------------------------------------------------------------===//
// Parser Helpers
//===----------------------------------------------------------------------===//
// Try parsing a register by its name.
-ParseStatus SuperHAsmParser::tryParseRegister(MCRegister &Reg, unsigned &RegKind, SMLoc &StartLoc, SMLoc &EndLoc) {
+ParseStatus SuperHAsmParser::tryParseRegister(MCRegister &Reg,
+ unsigned &RegKind,
+ SMLoc &StartLoc, SMLoc &EndLoc) {
const AsmToken Tok = Parser.getTok();
StartLoc = Tok.getLoc();
EndLoc = Tok.getEndLoc();
@@ -488,8 +505,10 @@ ParseStatus SuperHAsmParser::tryParseRegister(MCRegister &Reg, unsigned &RegKind
}
// Parses register relative addressing modes.
-ParseStatus SuperHAsmParser::tryParseRegRelative(MCRegister &BaseReg, MCRegister &OffReg,
- const MCExpr *&Offset, SMLoc &StartLoc,
+ParseStatus SuperHAsmParser::tryParseRegRelative(MCRegister &BaseReg,
+ MCRegister &OffReg,
+ const MCExpr *&Offset,
+ SMLoc &StartLoc,
SMLoc &EndLoc) {
const AsmToken Tok = getTok();
unsigned RegKind;
@@ -497,11 +516,12 @@ ParseStatus SuperHAsmParser::tryParseRegRelative(MCRegister &BaseReg, MCRegister
// NOTE: SuperH Assemblers support subtituting the normal PC-relative form
// with a symbol reference.
//
- // The following instruction sequences are equivalent:
- // mova .ABC, r0
+ // The following instruction sequences are equivalent:
+ // mova .ABC, r0
// mova @(.ABC,pc), r0
// mova @(8,pc), r0 (Where 8 is an offset from PC that refers
- // to the same address as the identifier would)
+ // to the same address as the identifier
+ // would)
if (getTok().is(AsmToken::Identifier)) {
// Registers are *not* identifiers.
@@ -517,7 +537,8 @@ ParseStatus SuperHAsmParser::tryParseRegRelative(MCRegister &BaseReg, MCRegister
}
// Parse "@(" sequence
- if (getTok().isNot(AsmToken::At) || getLexer().peekTok().isNot(AsmToken::LParen)) {
+ if (getTok().isNot(AsmToken::At) ||
+ getLexer().peekTok().isNot(AsmToken::LParen)) {
return ParseStatus::NoMatch;
}
Parser.Lex();
@@ -544,7 +565,8 @@ ParseStatus SuperHAsmParser::tryParseRegRelative(MCRegister &BaseReg, MCRegister
Offset = MCConstantExpr::create(Disp, getContext());
} else {
- return Error(getTok().getLoc(), "expected identifier, register or displacement");
+ return Error(getTok().getLoc(),
+ "expected identifier, register or displacement");
}
// Parse seperator
@@ -564,12 +586,13 @@ ParseStatus SuperHAsmParser::tryParseRegRelative(MCRegister &BaseReg, MCRegister
}
// Parses register-indirect addressing in the following forms:
-//
+//
// @Rn - Register Indirect
// @-Rn - Register Indirect with Pre-decrement
// @Rn+ - Register Indirect with Post-increment
-ParseStatus SuperHAsmParser::tryParseRegIndirect(MCRegister &Reg, bool &IsInc, bool &IsDec,
- SMLoc &StartLoc, SMLoc &EndLoc) {
+ParseStatus SuperHAsmParser::tryParseRegIndirect(MCRegister &Reg, bool &IsInc,
+ bool &IsDec, SMLoc &StartLoc,
+ SMLoc &EndLoc) {
const AsmToken Tok = Parser.getTok();
SMLoc S = StartLoc;
SMLoc E = EndLoc;
@@ -601,7 +624,8 @@ ParseStatus SuperHAsmParser::tryParseRegIndirect(MCRegister &Reg, bool &IsInc, b
return ParseStatus::Success;
}
-ParseStatus SuperHAsmParser::tryParseImm(int64_t &Imm, SMLoc &StartLoc, SMLoc &EndLoc) {
+ParseStatus SuperHAsmParser::tryParseImm(int64_t &Imm, SMLoc &StartLoc,
+ SMLoc &EndLoc) {
const AsmToken Tok = Parser.getTok();
// Eat % and $ which are used in SuperH asm.
@@ -617,8 +641,6 @@ ParseStatus SuperHAsmParser::tryParseImm(int64_t &Imm, SMLoc &StartLoc, SMLoc &E
return ParseStatus::Success;
}
-
-
//===----------------------------------------------------------------------===//
// Parser Entrypoints
//===----------------------------------------------------------------------===//
@@ -632,14 +654,11 @@ ParseStatus SuperHAsmParser::parseImm(OperandVector &Operands) {
// Immediates start with a '#'
if (!Parser.parseOptionalToken(AsmToken::Hash))
return ParseStatus::NoMatch;
-
+
int64_t Imm;
if (tryParseImm(Imm, StartLoc, EndLoc).isSuccess()) {
Operands.push_back(SuperHOperand::CreateImm(
- MCConstantExpr::create(Imm, getContext()),
- StartLoc,
- EndLoc
- ));
+ MCConstantExpr::create(Imm, getContext()), StartLoc, EndLoc));
return ParseStatus::Success;
}
@@ -657,12 +676,13 @@ ParseStatus SuperHAsmParser::parsePCRel(OperandVector &Operands) {
const AsmToken Tok = Parser.getTok();
SMLoc StartLoc = getLexer().getLoc();
SMLoc EndLoc = getLexer().getLoc();
-
+
// Parse register relative.
MCRegister BaseReg;
MCRegister OffReg;
const MCExpr *Offset;
- ParseStatus Result = tryParseRegRelative(BaseReg, OffReg, Offset, StartLoc, EndLoc);
+ ParseStatus Result =
+ tryParseRegRelative(BaseReg, OffReg, Offset, StartLoc, EndLoc);
if (!Result.isSuccess())
return Result;
@@ -685,7 +705,8 @@ ParseStatus SuperHAsmParser::parseRegister(OperandVector &Operands) {
MCRegister Reg;
unsigned RegKind;
if (tryParseRegister(Reg, RegKind, StartLoc, EndLoc).isSuccess()) {
- Operands.push_back(SuperHOperand::CreateReg(Reg, RegKind, StartLoc, EndLoc));
+ Operands.push_back(
+ SuperHOperand::CreateReg(Reg, RegKind, StartLoc, EndLoc));
return ParseStatus::Success;
}
return ParseStatus::NoMatch;
@@ -739,10 +760,10 @@ ParseStatus SuperHAsmParser::parseDirective(AsmToken DirectiveID) {
return ParseStatus::Success;
}
if (IDVal.equals_insensitive(".little")) {
- return ParseStatus::Success;
+ return ParseStatus::Success;
}
if (IDVal.equals_insensitive(".big")) {
- return ParseStatus::Success;
+ return ParseStatus::Success;
}
return ParseStatus::NoMatch;
}
@@ -757,14 +778,16 @@ ParseStatus SuperHAsmParser::parseOperand(OperandVector &Operands) {
}
}
-bool SuperHAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Mnemonic,
- SMLoc NameLoc, OperandVector &Operands) {
+bool SuperHAsmParser::parseInstruction(ParseInstructionInfo &Info,
+ StringRef Mnemonic, SMLoc NameLoc,
+ OperandVector &Operands) {
// Match mnemonic.
bool MS = SuperHCheckMnemonic(Mnemonic, this->getAvailableFeatures(), 0);
if (!MS) {
- return Error(NameLoc, "invalid instruction mnemonic" +
- SuperHMnemonicSpellCheck(Mnemonic, getAvailableFeatures(), 0));
+ return Error(NameLoc, "invalid instruction mnemonic" +
+ SuperHMnemonicSpellCheck(
+ Mnemonic, getAvailableFeatures(), 0));
}
// Chomp name and add it to the operands.
@@ -789,7 +812,7 @@ bool SuperHAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Mne
Parser.eatToEndOfStatement();
return true;
}
-
+
// Initial operand
if (!parseOperand(Operands).isSuccess()) {
SMLoc Loc = getLexer().getLoc();
@@ -815,20 +838,23 @@ bool SuperHAsmParser::parseGNUAttribute(SMLoc L) {
}
bool SuperHAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
- OperandVector &Operands, MCStreamer &Out,
- uint64_t &ErrorInfo,
- bool MatchingInlineAsm) {
-
+ OperandVector &Operands,
+ MCStreamer &Out,
+ uint64_t &ErrorInfo,
+ bool MatchingInlineAsm) {
+
LLVM_DEBUG(dbgs() << "matchAndEmitInstruction\n");
MCInst Inst;
- unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
- switch(MatchResult) {
+ unsigned MatchResult =
+ MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
+ switch (MatchResult) {
case Match_Success:
Inst.setLoc(IDLoc);
Out.emitInstruction(Inst, getSTI());
return false;
case Match_MissingFeature:
- return Error(IDLoc, "instruction requires a CPU feature not currently enabled.");
+ return Error(IDLoc,
+ "instruction requires a CPU feature not currently enabled.");
case Match_InvalidOperand: {
SMLoc ErrorLoc = IDLoc;
if (ErrorInfo != ~0ULL) {
@@ -848,7 +874,6 @@ bool SuperHAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return false;
}
-
extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
LLVMInitializeSuperHAsmParser() {
RegisterMCAsmParser<SuperHAsmParser> A(getTheSuperHTarget());
diff --git a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHAsmBackend.cpp b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHAsmBackend.cpp
index 5adcf90b2..78387151b 100644
--- a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHAsmBackend.cpp
+++ b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHAsmBackend.cpp
@@ -1,4 +1,5 @@
-//===-- SuperHAsmBackend.cpp - SuperH Assembler Backend ---------------------===//
+//===-- SuperHAsmBackend.cpp - SuperH Assembler Backend
+//---------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -34,15 +35,14 @@
using namespace llvm;
-SuperHAsmBackend::SuperHAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI) :
- MCAsmBackend(STI.getTargetTriple().isLittleEndian()
- ? llvm::endianness::little
- : llvm::endianness::big),
- STI(STI), OSABI(OSABI) {
-}
+SuperHAsmBackend::SuperHAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI)
+ : MCAsmBackend(STI.getTargetTriple().isLittleEndian()
+ ? llvm::endianness::little
+ : llvm::endianness::big),
+ STI(STI), OSABI(OSABI) {}
bool SuperHAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
- const MCSubtargetInfo *STI) const {
+ const MCSubtargetInfo *STI) const {
const uint16_t SHNopEnc = 0b0000000000001001;
// If the count is not 4-byte aligned, we must be writing data into the
@@ -56,7 +56,8 @@ bool SuperHAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
OS.write_zeros(Count & 1);
return true;
}
-std::optional<MCFixupKind> SuperHAsmBackend::getFixupKind(StringRef Name) const {
+std::optional<MCFixupKind>
+SuperHAsmBackend::getFixupKind(StringRef Name) const {
if (STI.getTargetTriple().isOSBinFormatELF()) {
unsigned Type;
Type = llvm::StringSwitch<unsigned>(Name)
@@ -99,9 +100,11 @@ MCFixupKindInfo SuperHAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
return Infos[Kind - FirstTargetFixupKind];
}
-unsigned SuperHAsmBackend::adjustFixupValue(const MCAssembler &Asm, const MCFixup &Fixup,
- const MCValue &Target, uint64_t Value,
- bool IsResolved, MCContext &Ctx,
+unsigned SuperHAsmBackend::adjustFixupValue(const MCAssembler &Asm,
+ const MCFixup &Fixup,
+ const MCValue &Target,
+ uint64_t Value, bool IsResolved,
+ MCContext &Ctx,
const MCSubtargetInfo *STI) const {
unsigned Kind = Fixup.getKind();
int64_t Addend = Target.getConstant();
@@ -111,31 +114,31 @@ unsigned SuperHAsmBackend::adjustFixupValue(const MCAssembler &Asm, const MCFixu
return Value;
case SH::fixup_32:
- return (Value+Addend) & 0xFFFFFFFF;
+ return (Value + Addend) & 0xFFFFFFFF;
case SH::fixup_pcrel4_by2:
- return ((Value+Addend) / 2) & 0xF;
+ return ((Value + Addend) / 2) & 0xF;
case SH::fixup_pcrel4_by4:
- return ((Value+Addend) / 4) & 0xF;
-
+ return ((Value + Addend) / 4) & 0xF;
+
case SH::fixup_pcrel8_by4:
- return ((Value+Addend) / 4) & 0xFF;
-
+ return ((Value + Addend) / 4) & 0xFF;
+
case SH::fixup_pcrel8_4by2:
return ((alignTo(Value, 2) + Addend - 4) / 2) & 0xFF;
-
+
case SH::fixup_pcrel8_4by4:
return ((alignTo(Value, 4) + Addend - 4) / 4) & 0xFF;
-
+
case SH::fixup_pcrel12_4by2:
return ((alignTo(Value, 2) + Addend - 4) / 2) & 0xFFF;
}
}
bool SuperHAsmBackend::tryAddReloc(const MCFragment &F, const MCFixup &Fixup,
- const MCValue &Target, uint64_t &FixedValue,
- bool IsResolved) {
+ const MCValue &Target, uint64_t &FixedValue,
+ bool IsResolved) {
if (!IsResolved) {
Asm->getWriter().recordRelocation(F, Fixup, Target, FixedValue);
return false;
@@ -143,19 +146,21 @@ bool SuperHAsmBackend::tryAddReloc(const MCFragment &F, const MCFixup &Fixup,
return true;
}
-std::optional<bool> SuperHAsmBackend::evaluateFixup(const MCFragment &F, MCFixup &Fixup,
- MCValue &Target, uint64_t &FixedValue) {
+std::optional<bool> SuperHAsmBackend::evaluateFixup(const MCFragment &F,
+ MCFixup &Fixup,
+ MCValue &Target,
+ uint64_t &FixedValue) {
MCValue PCITarget; // PC-Indirect Target
// Get indirect target location.
- switch(Fixup.getKind()) {
- default:
+ switch (Fixup.getKind()) {
+ default:
return {};
case FK_Data_1:
case FK_Data_2:
case FK_Data_4:
- case FK_Data_8:
+ case FK_Data_8:
case SH::fixup_pcrel4_by2:
case SH::fixup_pcrel4_by4:
case SH::fixup_pcrel8_by4:
@@ -180,8 +185,8 @@ std::optional<bool> SuperHAsmBackend::evaluateFixup(const MCFragment &F, MCFixup
// Check if resolvable.
bool IsResolved = &SA.getSection() == F.getParent() &&
- SA.getBinding() == ELF::STB_LOCAL &&
- SA.getType() != ELF::STT_GNU_IFUNC;
+ SA.getBinding() == ELF::STB_LOCAL &&
+ SA.getType() != ELF::STT_GNU_IFUNC;
if (!IsResolved)
return false;
@@ -194,20 +199,20 @@ std::optional<bool> SuperHAsmBackend::evaluateFixup(const MCFragment &F, MCFixup
}
void SuperHAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
- const MCValue &Target, uint8_t *Data,
- uint64_t Value, bool IsResolved) {
-
+ const MCValue &Target, uint8_t *Data,
+ uint64_t Value, bool IsResolved) {
+
// Handle Relocations
IsResolved = tryAddReloc(F, Fixup, Target, Value, IsResolved);
MCFixupKind Kind = Fixup.getKind();
- if (mc::isRelocation(Kind))
+ if (mc::isRelocation(Kind))
return;
// Handle non-relocations
MCContext &Ctx = getContext();
MCFixupKindInfo Info = getFixupKindInfo(Kind);
- Value = adjustFixupValue(*Asm, Fixup, Target, Value, IsResolved,
- Ctx, getSubtargetInfo(F));
+ Value = adjustFixupValue(*Asm, Fixup, Target, Value, IsResolved, Ctx,
+ getSubtargetInfo(F));
if (!Value)
return; // No encoding change.
@@ -226,15 +231,16 @@ void SuperHAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
}
}
-std::unique_ptr<MCObjectTargetWriter>
+std::unique_ptr<MCObjectTargetWriter>
SuperHAsmBackend::createObjectTargetWriter() const {
return createSuperHELFObjectWriter(OSABI);
}
MCAsmBackend *llvm::createSuperHAsmBackend(const Target &T,
- const MCSubtargetInfo &STI,
- const MCRegisterInfo &MRI,
- const MCTargetOptions &Options) {
- uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(STI.getTargetTriple().getOS());
+ const MCSubtargetInfo &STI,
+ const MCRegisterInfo &MRI,
+ const MCTargetOptions &Options) {
+ uint8_t OSABI =
+ MCELFObjectTargetWriter::getOSABI(STI.getTargetTriple().getOS());
return new SuperHAsmBackend(STI, OSABI);
}
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHAsmBackend.h b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHAsmBackend.h
index 833e1247b..27e425934 100644
--- a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHAsmBackend.h
+++ b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHAsmBackend.h
@@ -9,13 +9,12 @@
#ifndef LLVM_LIB_TARGET_SUPERH_MCTARGETDESC_SUPERHASMBACKEND_H
#define LLVM_LIB_TARGET_SUPERH_MCTARGETDESC_SUPERHASMBACKEND_H
-#include "MCTargetDesc/SuperHMCTargetDesc.h"
#include "MCTargetDesc/SuperHMCAsmInfo.h"
+#include "MCTargetDesc/SuperHMCTargetDesc.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/MC/MCAsmBackend.h"
#include "llvm/MC/MCSubtargetInfo.h"
-
namespace llvm {
class MCAssembler;
class MCObjectTargetWriter;
@@ -25,6 +24,7 @@ class SuperHAsmBackend : public MCAsmBackend {
protected:
const MCSubtargetInfo &STI;
uint8_t OSABI;
+
public:
SuperHAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI);
~SuperHAsmBackend() override = default;
@@ -36,17 +36,16 @@ public:
uint8_t *Data, uint64_t Value, bool IsResolved) override;
std::optional<bool> evaluateFixup(const MCFragment &, MCFixup &, MCValue &,
uint64_t &) override;
-
- std::unique_ptr<MCObjectTargetWriter>
+
+ std::unique_ptr<MCObjectTargetWriter>
createObjectTargetWriter() const override;
-
+
bool writeNopData(raw_ostream &OS, uint64_t Count,
const MCSubtargetInfo *STI) const override;
-
bool tryAddReloc(const MCFragment &F, const MCFixup &Fixup,
- const MCValue &Target, uint64_t &FixedValue,
- bool IsResolved);
+ const MCValue &Target, uint64_t &FixedValue,
+ bool IsResolved);
unsigned adjustFixupValue(const MCAssembler &Asm, const MCFixup &Fixup,
const MCValue &Target, uint64_t Value,
diff --git a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHBaseInfo.h b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHBaseInfo.h
index f0f7b7e51..ebc289919 100644
--- a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHBaseInfo.h
+++ b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHBaseInfo.h
@@ -1,4 +1,5 @@
-//===-- SuperHBaseInfo.h - Top level definitions for SH MC --------*- C++ -*-===//
+//===-- SuperHBaseInfo.h - Top level definitions for SH MC --------*- C++
+//-*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
diff --git a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHELFObjectWriter.cpp b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHELFObjectWriter.cpp
index b7910e8bb..1120c2af8 100644
--- a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHELFObjectWriter.cpp
+++ b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHELFObjectWriter.cpp
@@ -6,9 +6,9 @@
//
//===----------------------------------------------------------------------===//
-#include "MCTargetDesc/SuperHMCTargetDesc.h"
#include "MCTargetDesc/SuperHBaseInfo.h"
#include "MCTargetDesc/SuperHFixupKinds.h"
+#include "MCTargetDesc/SuperHMCTargetDesc.h"
#include "SuperHMCAsmInfo.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/MC/MCContext.h"
@@ -25,29 +25,28 @@ using namespace llvm;
#define DEBUG_TYPE "sh-elf-objwriter"
namespace llvm {
- class SuperHELFObjectWriter : public MCELFObjectTargetWriter {
- public:
- SuperHELFObjectWriter(uint8_t OSABI)
- : MCELFObjectTargetWriter(
- false, OSABI,
- ELF::EM_SH,
- /*HasRelocationAddend*/ true) {}
+class SuperHELFObjectWriter : public MCELFObjectTargetWriter {
+public:
+ SuperHELFObjectWriter(uint8_t OSABI)
+ : MCELFObjectTargetWriter(false, OSABI, ELF::EM_SH,
+ /*HasRelocationAddend*/ true) {}
- ~SuperHELFObjectWriter() override = default;
+ ~SuperHELFObjectWriter() override = default;
- protected:
- unsigned getRelocType(const MCFixup &Fixup, const MCValue &Target,
- bool IsPCRel) const override;
+protected:
+ unsigned getRelocType(const MCFixup &Fixup, const MCValue &Target,
+ bool IsPCRel) const override;
- bool needsRelocateWithSymbol(const MCValue &Val, unsigned Type) const override;
- };
-}
+ bool needsRelocateWithSymbol(const MCValue &Val,
+ unsigned Type) const override;
+};
+} // namespace llvm
unsigned SuperHELFObjectWriter::getRelocType(const MCFixup &Fixup,
- const MCValue &Target,
- bool IsPCRel) const {
+ const MCValue &Target,
+ bool IsPCRel) const {
auto Spec = Target.getSpecifier();
- switch ((unsigned)Fixup.getKind()) {
+ switch ((unsigned)Fixup.getKind()) {
case FK_Data_1:
case FK_Data_2:
case FK_Data_8:
@@ -63,7 +62,7 @@ unsigned SuperHELFObjectWriter::getRelocType(const MCFixup &Fixup,
return ELF::R_SH_NONE;
}
}
-
+
case SH::fixup_pcrel4_by2:
case SH::fixup_pcrel4_by4:
case SH::fixup_pcrel8_by4:
@@ -88,7 +87,7 @@ unsigned SuperHELFObjectWriter::getRelocType(const MCFixup &Fixup,
}
bool SuperHELFObjectWriter::needsRelocateWithSymbol(const MCValue &Val,
- unsigned Type) const {
+ unsigned Type) const {
return false;
}
diff --git a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHInstPrinter.cpp b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHInstPrinter.cpp
index 22b993ca7..00e437133 100644
--- a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHInstPrinter.cpp
+++ b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHInstPrinter.cpp
@@ -26,17 +26,19 @@ using namespace llvm;
// The generated AsmMatcher SparcGenAsmWriter uses "SuperH" as the target
// namespace. But SuperH backend uses "SH" as its namespace.
namespace llvm {
- namespace SuperH {
- using namespace SH;
- }
+namespace SuperH {
+using namespace SH;
}
+} // namespace llvm
#define GET_INSTRUCTION_NAME
#define PRINT_ALIAS_INSTR
#include "SuperHGenAsmWriter.inc"
-SuperHInstPrinter::SuperHInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
- const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {}
+SuperHInstPrinter::SuperHInstPrinter(const MCAsmInfo &MAI,
+ const MCInstrInfo &MII,
+ const MCRegisterInfo &MRI)
+ : MCInstPrinter(MAI, MII, MRI) {}
const std::string SuperHInstPrinter::getRegName(MCRegister Reg) {
return StringRef(getRegisterName(Reg)).lower();
@@ -46,40 +48,46 @@ void SuperHInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) {
OS << getRegName(Reg);
}
-void SuperHInstPrinter::printImm(const MCInst *MI, unsigned OpNo, raw_ostream &OS) {
+void SuperHInstPrinter::printImm(const MCInst *MI, unsigned OpNo,
+ raw_ostream &OS) {
const MCOperand &Op = MI->getOperand(OpNo);
OS << "#" << Op.getImm();
}
-void SuperHInstPrinter::printIReg(const MCInst *MI, unsigned OpNo, raw_ostream &OS) {
+void SuperHInstPrinter::printIReg(const MCInst *MI, unsigned OpNo,
+ raw_ostream &OS) {
const MCOperand &Op = MI->getOperand(OpNo);
OS << "@" << getRegName(Op.getReg());
}
-void SuperHInstPrinter::printIRegInc(const MCInst *MI, unsigned OpNo, raw_ostream &OS) {
+void SuperHInstPrinter::printIRegInc(const MCInst *MI, unsigned OpNo,
+ raw_ostream &OS) {
const MCOperand &Op = MI->getOperand(OpNo);
OS << "@" << getRegName(Op.getReg()) << "+";
}
-void SuperHInstPrinter::printIRegDec(const MCInst *MI, unsigned OpNo, raw_ostream &OS) {
+void SuperHInstPrinter::printIRegDec(const MCInst *MI, unsigned OpNo,
+ raw_ostream &OS) {
const MCOperand &Op = MI->getOperand(OpNo);
OS << "@-" << getRegName(Op.getReg());
}
-template<int Scale>
-void SuperHInstPrinter::printDisp(const MCInst *MI, unsigned OpNo, raw_ostream &OS) {
+template <int Scale>
+void SuperHInstPrinter::printDisp(const MCInst *MI, unsigned OpNo,
+ raw_ostream &OS) {
const MCOperand &Op = MI->getOperand(OpNo);
OS << Op.getImm();
}
-template<int Scale>
-void SuperHInstPrinter::printPCRel(const MCInst *MI, uint64_t Address,
- unsigned OpNo, raw_ostream &O) {
+template <int Scale>
+void SuperHInstPrinter::printPCRel(const MCInst *MI, uint64_t Address,
+ unsigned OpNo, raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
// Print standalone symbol.
if (Op.isExpr()) {
- if (const MCSymbolRefExpr *SymOp = dyn_cast<MCSymbolRefExpr>(Op.getExpr())) {
+ if (const MCSymbolRefExpr *SymOp =
+ dyn_cast<MCSymbolRefExpr>(Op.getExpr())) {
O << SymOp->getSymbol().getName();
return;
}
@@ -91,20 +99,22 @@ void SuperHInstPrinter::printPCRel(const MCInst *MI, uint64_t Address,
}
}
-template<int Scale>
-void SuperHInstPrinter::printMemri(const MCInst *MI, unsigned OpNo, raw_ostream &OS) {
+template <int Scale>
+void SuperHInstPrinter::printMemri(const MCInst *MI, unsigned OpNo,
+ raw_ostream &OS) {
// Skip "Uses" operands, as some Memri operations are destinations.
- if (MI->getOperand(OpNo+1).isReg())
+ if (MI->getOperand(OpNo + 1).isReg())
OpNo++;
const MCOperand &Op0 = MI->getOperand(OpNo);
- const MCOperand &Op1 = MI->getOperand(OpNo+1);
+ const MCOperand &Op1 = MI->getOperand(OpNo + 1);
// For globals, we want to render a symbol.
// even if they get lowered beforehand.
if (Op0.isExpr()) {
- if (const MCSymbolRefExpr *SymOp = dyn_cast<MCSymbolRefExpr>(Op0.getExpr())) {
+ if (const MCSymbolRefExpr *SymOp =
+ dyn_cast<MCSymbolRefExpr>(Op0.getExpr())) {
OS << SymOp->getSymbol().getName();
return;
}
@@ -114,11 +124,13 @@ void SuperHInstPrinter::printMemri(const MCInst *MI, unsigned OpNo, raw_ostream
OS << "@(" << Op1.getImm() << "," << getRegName(Op0.getReg()) << ")";
}
-void SuperHInstPrinter::printMemrii(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
+void SuperHInstPrinter::printMemrii(const MCInst *MI, unsigned OpNo,
+ raw_ostream &O) {
printOperand(MI, OpNo, O);
}
-void SuperHInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
+void SuperHInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
+ raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
// Print Register
@@ -134,13 +146,15 @@ void SuperHInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, raw_ostrea
}
// Print symbol references
- if (const MCSymbolRefExpr *SymOp = dyn_cast_or_null<MCSymbolRefExpr>(Op.getExpr())) {
+ if (const MCSymbolRefExpr *SymOp =
+ dyn_cast_or_null<MCSymbolRefExpr>(Op.getExpr())) {
O << SymOp->getSymbol().getName();
return;
}
}
-void SuperHInstPrinter::printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
- const MCSubtargetInfo &STI, raw_ostream &OS) {
+void SuperHInstPrinter::printInst(const MCInst *MI, uint64_t Address,
+ StringRef Annot, const MCSubtargetInfo &STI,
+ raw_ostream &OS) {
printInstruction(MI, Address, OS);
}
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHInstPrinter.h b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHInstPrinter.h
index 2a95c92f0..a4a27395e 100644
--- a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHInstPrinter.h
+++ b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHInstPrinter.h
@@ -50,13 +50,14 @@ private:
static const char *getRegisterName(MCRegister Reg);
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
- template<int Scale>
- void printPCRel(const MCInst *MI, uint64_t Address, unsigned OpNo, raw_ostream &O);
+ template <int Scale>
+ void printPCRel(const MCInst *MI, uint64_t Address, unsigned OpNo,
+ raw_ostream &O);
- template<int Scale>
+ template <int Scale>
void printDisp(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-
- template<int Scale>
+
+ template <int Scale>
void printMemri(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printMemrii(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
diff --git a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCAsmInfo.h b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCAsmInfo.h
index 232d952eb..26a05673b 100644
--- a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCAsmInfo.h
+++ b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCAsmInfo.h
@@ -11,7 +11,6 @@
///
//===----------------------------------------------------------------------===//
-
#ifndef LLVM_LIB_TARGET_SUPERH_MCTARGETDESC_SUPERHMCASMINFO_H
#define LLVM_LIB_TARGET_SUPERH_MCTARGETDESC_SUPERHMCASMINFO_H
@@ -28,10 +27,10 @@ class Triple;
//===----------------------------------------------------------------------===//
class SuperHMCAsmInfo : public MCAsmInfoELF {
private:
- void anchor() override;
+ void anchor() override;
public:
- explicit SuperHMCAsmInfo(const Triple &TheTriple,
+ explicit SuperHMCAsmInfo(const Triple &TheTriple,
const MCTargetOptions &Options);
};
diff --git a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCCodeEmitter.cpp b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCCodeEmitter.cpp
index 848cff47c..a1ac957bf 100644
--- a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCCodeEmitter.cpp
+++ b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCCodeEmitter.cpp
@@ -10,7 +10,6 @@
//
//===----------------------------------------------------------------------===//
-
#include "SuperHFixupKinds.h"
#include "SuperHMCTargetDesc.h"
#include "llvm/ADT/Statistic.h"
@@ -19,23 +18,22 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCCodeEmitter.h"
-#include "llvm/MC/MCInstPrinter.h"
-#include "llvm/MC/TargetRegistry.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCFixup.h"
#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstPrinter.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCObjectFileInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
+#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/EndianStream.h"
#include "llvm/Support/ErrorHandling.h"
#include <cstdint>
#include <optional>
-
using namespace llvm;
#define DEBUG_TYPE "sh-mccodeemitter"
@@ -48,8 +46,7 @@ class SuperHMCCodeEmitter : public MCCodeEmitter {
MCContext &Ctx;
public:
- SuperHMCCodeEmitter(const MCInstrInfo &, MCContext &ctx)
- : Ctx(ctx) {}
+ SuperHMCCodeEmitter(const MCInstrInfo &, MCContext &ctx) : Ctx(ctx) {}
SuperHMCCodeEmitter(const SuperHMCCodeEmitter &) = delete;
SuperHMCCodeEmitter &operator=(const SuperHMCCodeEmitter &) = delete;
~SuperHMCCodeEmitter() override = default;
@@ -72,27 +69,25 @@ public:
unsigned getExprOpValue(const MCInst &MI, const MCExpr *Expr,
SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI,
- int64_t Shift) const;
+ const MCSubtargetInfo &STI, int64_t Shift) const;
unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+
// Displacement
- template<int Scale>
+ template <int Scale>
unsigned getDispOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// PC-relative displacement.
- template<int Scale>
+ template <int Scale>
unsigned getPCRelOpValue(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
- unsigned getOpBits(const MCInst &MI,
- SmallVectorImpl<MCFixup> &Fixups,
+ unsigned getOpBits(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
};
@@ -105,17 +100,17 @@ public:
// Checks the passed opcode for any bit patterns
// that must be encoded as 32-bits.
static bool isOpcode32(uint32_t Opcode) {
-
+
// movi20 & movi20s
if ((Opcode & 0xF00F) <= 0x0001)
return true;
-
+
// Other SH2A 32-bit instructions
if ((Opcode & 0xF00F) == 0x3001)
return true;
// Opcodes bigger than 0xFFFF are always 32-bits.
- return Opcode > 0xFFFF;
+ return Opcode > 0xFFFF;
}
// Helper that gets the bits for the given instruction.
@@ -124,25 +119,27 @@ unsigned SuperHMCCodeEmitter::getOpBits(const MCInst &MI,
const MCSubtargetInfo &STI) const {
MCInst Inst = MCInst();
Inst.setOpcode(MI.getOpcode());
- for(unsigned i = 0; i < MI.getNumOperands(); i++) {
+ for (unsigned i = 0; i < MI.getNumOperands(); i++) {
Inst.addOperand(MCOperand::createImm(0));
}
return getBinaryCodeForInstr(Inst, Fixups, STI);
}
-// @getFixupForOpcode - Helper that gets the neccesary fixup for
+// @getFixupForOpcode - Helper that gets the neccesary fixup for
// the given opcode.
// This is neccesary due to the various opcodes that access memory
// have different scaling factors applied.
-static MCFixup getFixupForOpcode(unsigned Opcode, const MCExpr *Expr, MCContext &Ctx) {
+static MCFixup getFixupForOpcode(unsigned Opcode, const MCExpr *Expr,
+ MCContext &Ctx) {
// NOTE: A few (DSP and SH2A) instructions are 32-bits wide.
// We handle those quite crudely.
MCFixupKind Kind = isOpcode32(Opcode) ? FK_Data_4 : FK_Data_2;
- switch(Opcode) {
- default: break;
+ switch (Opcode) {
+ default:
+ break;
// disp4 * 2
case SH::MOVWL4:
@@ -190,51 +187,47 @@ static MCFixup getFixupForOpcode(unsigned Opcode, const MCExpr *Expr, MCContext
}
void SuperHMCCodeEmitter::encodeInstruction(const MCInst &MI,
- SmallVectorImpl<char> &CB,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
+ SmallVectorImpl<char> &CB,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
uint64_t OpCode = getBinaryCodeForInstr(MI, Fixups, STI);
// NOTE: All base instructions are 16-bit in SH ASM
- // But some instructions may be 32-bit for eg. SH2A or the DSP extensions.
- // This is ugly, but it'll work.
+ // But some instructions may be 32-bit for eg. SH2A or the DSP
+ // extensions. This is ugly, but it'll work.
if (isOpcode32(OpCode)) {
- support::endian::write(CB, (uint32_t)OpCode, Ctx.getAsmInfo().isLittleEndian()
- ? llvm::endianness::little
- : llvm::endianness::big);
+ support::endian::write(CB, (uint32_t)OpCode,
+ Ctx.getAsmInfo().isLittleEndian()
+ ? llvm::endianness::little
+ : llvm::endianness::big);
} else {
- support::endian::write(CB, (uint16_t)OpCode, Ctx.getAsmInfo().isLittleEndian()
- ? llvm::endianness::little
- : llvm::endianness::big);
-
+ support::endian::write(CB, (uint16_t)OpCode,
+ Ctx.getAsmInfo().isLittleEndian()
+ ? llvm::endianness::little
+ : llvm::endianness::big);
}
++MCNumEmitted;
}
-
-
-
//===----------------------------------------------------------------------===//
// Branch Target
//===----------------------------------------------------------------------===//
-unsigned SuperHMCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
+unsigned
+SuperHMCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
}
-
-
-
//===----------------------------------------------------------------------===//
// Displacement
//===----------------------------------------------------------------------===//
-template<int Scale>
+template <int Scale>
unsigned SuperHMCCodeEmitter::getDispOpValue(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
// Skip base register if found.
if (MI.getOperand(OpNo).isReg())
OpNo++;
@@ -247,18 +240,15 @@ unsigned SuperHMCCodeEmitter::getDispOpValue(const MCInst &MI, unsigned OpNo,
return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
}
-
-
-
-
//===----------------------------------------------------------------------===//
// PC-Relative Displacement
//===----------------------------------------------------------------------===//
-template<int Scale>
-unsigned SuperHMCCodeEmitter::getPCRelOpValue(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
+template <int Scale>
+unsigned
+SuperHMCCodeEmitter::getPCRelOpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
auto MO = MI.getOperand(OpNo);
if (MO.isImm())
return MO.getImm() / Scale;
@@ -267,21 +257,25 @@ unsigned SuperHMCCodeEmitter::getPCRelOpValue(const MCInst &MI, unsigned OpNo,
return getExprOpValue(MI, MO.getExpr(), Fixups, STI, Scale);
}
-unsigned
-SuperHMCCodeEmitter::getExprOpValue(const MCInst &MI, const MCExpr *Expr,
- SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI,
- int64_t Shift) const {
+unsigned SuperHMCCodeEmitter::getExprOpValue(const MCInst &MI,
+ const MCExpr *Expr,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI,
+ int64_t Shift) const {
if (!Expr)
return 0;
- switch(Expr->getKind()) {
+ switch (Expr->getKind()) {
case MCExpr::ExprKind::Binary: {
- unsigned Res = getExprOpValue(MI, static_cast<const MCBinaryExpr *>(Expr)->getLHS(), Fixups, STI, Shift);
- Res += getExprOpValue(MI, static_cast<const MCBinaryExpr *>(Expr)->getRHS(), Fixups, STI, Shift);
+ unsigned Res =
+ getExprOpValue(MI, static_cast<const MCBinaryExpr *>(Expr)->getLHS(),
+ Fixups, STI, Shift);
+ Res += getExprOpValue(MI, static_cast<const MCBinaryExpr *>(Expr)->getRHS(),
+ Fixups, STI, Shift);
return Res;
}
case MCExpr::ExprKind::Target: {
- llvm_unreachable("TODO");
+ llvm_unreachable("TODO");
}
case MCExpr::ExprKind::Specifier: {
const MCSpecifierExpr *Spec = static_cast<const MCSpecifierExpr *>(Expr);
@@ -303,10 +297,10 @@ SuperHMCCodeEmitter::getExprOpValue(const MCInst &MI, const MCExpr *Expr,
/// getMachineOpValue - Return binary encoding of operand. If the machine
/// operand requires relocation, record the relocation and return zero.
-unsigned SuperHMCCodeEmitter::getMachineOpValue(const MCInst &MI,
- const MCOperand &MO,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
+unsigned
+SuperHMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
if (MO.isReg())
return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
@@ -318,6 +312,6 @@ unsigned SuperHMCCodeEmitter::getMachineOpValue(const MCInst &MI,
}
MCCodeEmitter *llvm::createSuperHMCCodeEmitter(const MCInstrInfo &MCII,
- MCContext &Ctx) {
+ MCContext &Ctx) {
return new SuperHMCCodeEmitter(MCII, Ctx);
}
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCTargetDesc.cpp b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCTargetDesc.cpp
index 8aaa8a304..1e6d469e7 100644
--- a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCTargetDesc.cpp
+++ b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCTargetDesc.cpp
@@ -107,12 +107,13 @@ LLVMInitializeSuperHTargetMC() {
// Register the AsmBackend
TargetRegistry::RegisterMCAsmBackend(*T, createSuperHAsmBackend);
-
+
// Register the MC asm info.
TargetRegistry::RegisterMCAsmInfo(*T, createSuperHMCAsmInfo);
// Register the object target streamer.
- TargetRegistry::RegisterObjectTargetStreamer(*T, createTargetObjectStreamer);
+ TargetRegistry::RegisterObjectTargetStreamer(*T,
+ createTargetObjectStreamer);
// Register the asm streamer.
TargetRegistry::RegisterAsmTargetStreamer(*T, createTargetAsmStreamer);
diff --git a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCTargetDesc.h b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCTargetDesc.h
index 5d060e597..a34417651 100644
--- a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCTargetDesc.h
+++ b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHMCTargetDesc.h
@@ -1,4 +1,5 @@
-//===-- SuperHMCTargetDesc.h - SuperH Target Descriptions -----------*- C++ -*-===//
+//===-- SuperHMCTargetDesc.h - SuperH Target Descriptions -----------*- C++
+//-*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -34,14 +35,16 @@ class raw_ostream;
class raw_pwrite_stream;
MCCodeEmitter *createSuperHMCCodeEmitter(const MCInstrInfo &MCII,
- MCContext &Ctx);
+ MCContext &Ctx);
-MCAsmBackend *createSuperHAsmBackend(const Target &T, const MCSubtargetInfo &STI,
- const MCRegisterInfo &MRI,
- const MCTargetOptions &Options);
+MCAsmBackend *createSuperHAsmBackend(const Target &T,
+ const MCSubtargetInfo &STI,
+ const MCRegisterInfo &MRI,
+ const MCTargetOptions &Options);
-std::unique_ptr<MCObjectTargetWriter> createSuperHELFObjectWriter(uint8_t OSABI);
-}
+std::unique_ptr<MCObjectTargetWriter>
+createSuperHELFObjectWriter(uint8_t OSABI);
+} // namespace llvm
#define GET_REGINFO_ENUM
#include "SuperHGenRegisterInfo.inc"
diff --git a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHTargetStreamer.cpp b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHTargetStreamer.cpp
index 86e98b93b..3e9aff783 100644
--- a/llvm/lib/Target/SuperH/MCTargetDesc/SuperHTargetStreamer.cpp
+++ b/llvm/lib/Target/SuperH/MCTargetDesc/SuperHTargetStreamer.cpp
@@ -17,14 +17,15 @@
using namespace llvm;
-SuperHTargetStreamer::SuperHTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
+SuperHTargetStreamer::SuperHTargetStreamer(MCStreamer &S)
+ : MCTargetStreamer(S) {}
SuperHTargetAsmStreamer::SuperHTargetAsmStreamer(MCStreamer &S,
formatted_raw_ostream &OS)
: SuperHTargetStreamer(S), OS(OS) {}
SuperHTargetELFStreamer::SuperHTargetELFStreamer(MCStreamer &S,
- const MCSubtargetInfo &STI)
+ const MCSubtargetInfo &STI)
: SuperHTargetStreamer(S) {
ELFObjectWriter &W = getStreamer().getWriter();
unsigned EFlags = W.getELFHeaderEFlags();
diff --git a/llvm/lib/Target/SuperH/SuperH.h b/llvm/lib/Target/SuperH/SuperH.h
index efd8275d9..a779b5856 100644
--- a/llvm/lib/Target/SuperH/SuperH.h
+++ b/llvm/lib/Target/SuperH/SuperH.h
@@ -25,7 +25,8 @@ class MachineInstr;
class PassRegistry;
class SuperHTargetMachine;
-FunctionPass *createSuperHISelDag(SuperHTargetMachine &TM, CodeGenOptLevel OptLevel);
+FunctionPass *createSuperHISelDag(SuperHTargetMachine &TM,
+ CodeGenOptLevel OptLevel);
FunctionPass *createSuperHFillDelaySlotsPass();
FunctionPass *createSuperHConstantIslandPass();
FunctionPass *createSuperHExpandPseudoPass();
@@ -39,5 +40,4 @@ void initializeSuperHConstantIslandsPass(PassRegistry &);
void initializeSuperHExpandPseudoPass(PassRegistry &);
} // namespace llvm
-
#endif
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/SuperHAsmPrinter.cpp b/llvm/lib/Target/SuperH/SuperHAsmPrinter.cpp
index 7ae610276..a95de5650 100644
--- a/llvm/lib/Target/SuperH/SuperHAsmPrinter.cpp
+++ b/llvm/lib/Target/SuperH/SuperHAsmPrinter.cpp
@@ -38,7 +38,6 @@ public:
static char ID;
private:
-
/// MCP - Keep a pointer to constantpool entries of the current
/// MachineFunction.
const MachineConstantPool *MCP;
@@ -50,16 +49,16 @@ private:
/// Set of globals in PromotedGlobals that we've emitted labels for.
/// We need to emit labels even for promoted globals so that DWARF
/// debug info can link properly.
- SmallPtrSet<const GlobalVariable*,2> EmittedPromotedGlobalLabels;
+ SmallPtrSet<const GlobalVariable *, 2> EmittedPromotedGlobalLabels;
- SuperHTargetStreamer &getTargetStreamer() {
- return static_cast<SuperHTargetStreamer &>(
- *OutStreamer->getTargetStreamer());
- }
+ SuperHTargetStreamer &getTargetStreamer() {
+ return static_cast<SuperHTargetStreamer &>(
+ *OutStreamer->getTargetStreamer());
+ }
public:
explicit SuperHAsmPrinter(TargetMachine &TM,
- std::unique_ptr<MCStreamer> Streamer)
+ std::unique_ptr<MCStreamer> Streamer)
: AsmPrinter(TM, std::move(Streamer), ID), MCP(nullptr) {}
StringRef getPassName() const override { return "SuperH Assembly Printer"; }
@@ -73,7 +72,7 @@ public:
void emitInstruction(const MachineInstr *MI) override;
// We emit them ourselves.
- void emitConstantPool() override { }
+ void emitConstantPool() override {}
void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override;
static std::string getRegisterName(MCRegister Reg) {
@@ -94,9 +93,6 @@ bool SuperHAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
return AsmPrinter::runOnMachineFunction(MF);
}
-
-
-
//===----------------------------------------------------------------------===//
// Utilities
//===----------------------------------------------------------------------===//
@@ -115,14 +111,12 @@ static uint8_t getModifierSpecifier(SHCP::SHCPModifier Modifier) {
llvm_unreachable("Invalid SHCPModifier!");
}
-
-
-
//===----------------------------------------------------------------------===//
// Operands
//===----------------------------------------------------------------------===//
-void SuperHAsmPrinter::printOperand(const MachineInstr *MI, int OpNo, raw_ostream &O) {
+void SuperHAsmPrinter::printOperand(const MachineInstr *MI, int OpNo,
+ raw_ostream &O) {
const MachineOperand &MO = MI->getOperand(OpNo);
switch (MO.getType()) {
@@ -147,7 +141,7 @@ void SuperHAsmPrinter::printOperand(const MachineInstr *MI, int OpNo, raw_ostrea
}
bool SuperHAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
- const char *ExtraCode, raw_ostream &O) {
+ const char *ExtraCode, raw_ostream &O) {
if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O))
return false;
@@ -160,8 +154,10 @@ bool SuperHAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
return false;
}
-bool SuperHAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
- const char *ExtraCode, raw_ostream &O) {
+bool SuperHAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
+ unsigned OpNo,
+ const char *ExtraCode,
+ raw_ostream &O) {
if (ExtraCode && ExtraCode[0])
return true; // Unknown modifier
@@ -175,21 +171,19 @@ bool SuperHAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned Op
return false;
}
-
-
-
//===----------------------------------------------------------------------===//
// Constant Pool
//===----------------------------------------------------------------------===//
-void SuperHAsmPrinter::emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
+void SuperHAsmPrinter::emitMachineConstantPoolValue(
+ MachineConstantPoolValue *MCPV) {
const DataLayout &DL = getDataLayout();
int Size = DL.getTypeAllocSize(MCPV->getType());
if (Size < 4)
Size = 4;
// Handle promoted constants (eg. immediates that don't fit in 8 bits).
- SuperHConstantPoolValue *SCPV = static_cast<SuperHConstantPoolValue*>(MCPV);
+ SuperHConstantPoolValue *SCPV = static_cast<SuperHConstantPoolValue *>(MCPV);
if (SCPV->isPromotedGlobal()) {
auto *SCPC = cast<SuperHConstantPoolConstant>(SCPV);
for (const auto *GV : SCPC->promotedGlobals()) {
@@ -200,38 +194,35 @@ void SuperHAsmPrinter::emitMachineConstantPoolValue(MachineConstantPoolValue *MC
}
}
return emitGlobalConstant(DL, SCPC->getPromotedGlobalInit());
- }
+ }
MCSymbol *MCSym;
if (SCPV->isBlockAddress()) {
const BlockAddress *BA =
- cast<SuperHConstantPoolConstant>(SCPV)->getBlockAddress();
+ cast<SuperHConstantPoolConstant>(SCPV)->getBlockAddress();
MCSym = GetBlockAddressSymbol(BA);
- LLVM_DEBUG(dbgs() << "Emit CPV BlockAddress " << SCPV->getLabelId()
- << " \"" << MCSym->getName() << "\"...\n");
+ LLVM_DEBUG(dbgs() << "Emit CPV BlockAddress " << SCPV->getLabelId() << " \""
+ << MCSym->getName() << "\"...\n");
} else if (SCPV->isGlobalValue()) {
const GlobalValue *GV = cast<SuperHConstantPoolConstant>(SCPV)->getGV();
MCSym = getSymbolPreferLocal(*GV);
- LLVM_DEBUG(dbgs() << "Emit CPV GlobalValue " << SCPV->getLabelId()
- << " \"" << MCSym->getName() << "\"...\n");
-
+ LLVM_DEBUG(dbgs() << "Emit CPV GlobalValue " << SCPV->getLabelId() << " \""
+ << MCSym->getName() << "\"...\n");
+
} else {
assert(SCPV->isExtSymbol() && "unrecognized constant pool value");
auto Sym = cast<SuperHConstantPoolSymbol>(SCPV)->getSymbol();
MCSym = GetExternalSymbolSymbol(Sym);
- LLVM_DEBUG(dbgs() << "Emit CPV GlobalValue " << SCPV->getLabelId()
- << " \"" << MCSym->getName() << "\"...\n");
+ LLVM_DEBUG(dbgs() << "Emit CPV GlobalValue " << SCPV->getLabelId() << " \""
+ << MCSym->getName() << "\"...\n");
}
// Create an MCSymbol for the reference.
- const MCExpr *Expr = MCSymbolRefExpr::create(
- MCSym,
- OutContext
- );
+ const MCExpr *Expr = MCSymbolRefExpr::create(MCSym, OutContext);
OutStreamer->emitValue(Expr, Size);
}
@@ -250,7 +241,6 @@ void SuperHAsmPrinter::emitFunctionBodyEnd() {
OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
}
-
void SuperHAsmPrinter::emitInstruction(const MachineInstr *MI) {
const SuperHSubtarget &STI = MF->getSubtarget<SuperHSubtarget>();
const DataLayout &DL = getDataLayout();
@@ -276,7 +266,7 @@ void SuperHAsmPrinter::emitInstruction(const MachineInstr *MI) {
case SH::CONSTPOOL_ENTRY: {
unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
- unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
+ unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
// If this is the first entry of the pool, mark it.
if (!InConstantPool) {
@@ -297,7 +287,8 @@ void SuperHAsmPrinter::emitInstruction(const MachineInstr *MI) {
}
char SuperHAsmPrinter::ID = 0;
-INITIALIZE_PASS(SuperHAsmPrinter, "sh-asm-printer", "SuperH Assembly Printer", false, false)
+INITIALIZE_PASS(SuperHAsmPrinter, "sh-asm-printer", "SuperH Assembly Printer",
+ false, false)
// Force static initialization.
extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
diff --git a/llvm/lib/Target/SuperH/SuperHBasicBlockInfo.cpp b/llvm/lib/Target/SuperH/SuperHBasicBlockInfo.cpp
index 3a139ba14..1e97ac772 100644
--- a/llvm/lib/Target/SuperH/SuperHBasicBlockInfo.cpp
+++ b/llvm/lib/Target/SuperH/SuperHBasicBlockInfo.cpp
@@ -52,10 +52,10 @@ unsigned SuperHBasicBlockUtils::getOffsetOf(MachineInstr *MI) const {
/// isBBInRange - Returns true if the distance between specific MI and
/// specific BB can fit in MI's displacement field.
bool SuperHBasicBlockUtils::isBBInRange(MachineInstr *MI,
- MachineBasicBlock *DestBB,
- unsigned MaxDisp) const {
- unsigned PCAdj = 4;
- unsigned BrOffset = getOffsetOf(MI) + PCAdj;
+ MachineBasicBlock *DestBB,
+ unsigned MaxDisp) const {
+ unsigned PCAdj = 4;
+ unsigned BrOffset = getOffsetOf(MI) + PCAdj;
unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset;
LLVM_DEBUG(dbgs() << "Branch of destination " << printMBBReference(*DestBB)
@@ -66,10 +66,10 @@ bool SuperHBasicBlockUtils::isBBInRange(MachineInstr *MI,
if (BrOffset <= DestOffset) {
// Branch before the Dest.
- if (DestOffset-BrOffset <= MaxDisp)
+ if (DestOffset - BrOffset <= MaxDisp)
return true;
} else {
- if (BrOffset-DestOffset <= MaxDisp)
+ if (BrOffset - DestOffset <= MaxDisp)
return true;
}
return false;
@@ -81,12 +81,12 @@ void SuperHBasicBlockUtils::adjustBBOffsetsAfter(MachineBasicBlock *BB) {
unsigned BBNum = BB->getNumber();
LLVM_DEBUG(dbgs() << "Adjust block:\n"
- << " - name: " << BB->getName() << "\n"
- << " - number: " << BB->getNumber() << "\n"
- << " - function: " << MF.getName() << "\n"
- << " - blocks: " << MF.getNumBlockIDs() << "\n");
+ << " - name: " << BB->getName() << "\n"
+ << " - number: " << BB->getNumber() << "\n"
+ << " - function: " << MF.getName() << "\n"
+ << " - blocks: " << MF.getNumBlockIDs() << "\n");
- for(unsigned i = BBNum + 1, e = MF.getNumBlockIDs(); i < e; ++i) {
+ for (unsigned i = BBNum + 1, e = MF.getNumBlockIDs(); i < e; ++i) {
// Get the offset and known bits at the end of the layout predecessor.
// Include the alignment of the current block.
const Align Align = MF.getBlockNumbered(i)->getAlignment();
@@ -96,8 +96,7 @@ void SuperHBasicBlockUtils::adjustBBOffsetsAfter(MachineBasicBlock *BB) {
// This is where block i begins. Stop if the offset is already correct,
// and we have updated 2 blocks. This is the maximum number of blocks
// changed before calling this function.
- if (i > BBNum + 2 &&
- BBInfo[i].Offset == Offset &&
+ if (i > BBNum + 2 && BBInfo[i].Offset == Offset &&
BBInfo[i].KnownBits == KnownBits)
break;
@@ -106,5 +105,4 @@ void SuperHBasicBlockUtils::adjustBBOffsetsAfter(MachineBasicBlock *BB) {
}
}
-
} // namespace llvm
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/SuperHBasicBlockInfo.h b/llvm/lib/Target/SuperH/SuperHBasicBlockInfo.h
index f0039cbc5..ce31e86cd 100644
--- a/llvm/lib/Target/SuperH/SuperHBasicBlockInfo.h
+++ b/llvm/lib/Target/SuperH/SuperHBasicBlockInfo.h
@@ -116,7 +116,7 @@ private:
public:
SuperHBasicBlockUtils(MachineFunction &MF) : MF(MF) {
TII =
- static_cast<const SuperHInstrInfo*>(MF.getSubtarget().getInstrInfo());
+ static_cast<const SuperHInstrInfo *>(MF.getSubtarget().getInstrInfo());
}
void computeAllBlockSizes() {
@@ -149,7 +149,6 @@ public:
void clear() { BBInfo.clear(); }
BBInfoVector &getBBInfo() { return BBInfo; }
-
};
} // end namespace llvm
diff --git a/llvm/lib/Target/SuperH/SuperHConstantIslandPass.cpp b/llvm/lib/Target/SuperH/SuperHConstantIslandPass.cpp
index 8703f20fd..eadc9243c 100644
--- a/llvm/lib/Target/SuperH/SuperHConstantIslandPass.cpp
+++ b/llvm/lib/Target/SuperH/SuperHConstantIslandPass.cpp
@@ -16,199 +16,191 @@
#include "SuperHBasicBlockInfo.h"
#include "SuperHMachineFunctionInfo.h"
#include "SuperHSubtarget.h"
-#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/LivePhysRegs.h"
+#include "llvm/CodeGen/MachineDominators.h"
#include <memory>
using namespace llvm;
#define DEBUG_TYPE "sh-cp-islands"
-#define SH_CP_ISLANDS_OPT_NAME \
+#define SH_CP_ISLANDS_OPT_NAME \
"SH constant island placement and branch shortening pass"
static cl::opt<unsigned>
-CPMaxIteration("sh-constant-island-max-iteration", cl::Hidden, cl::init(30),
- cl::desc("The max number of iteration for converge"));
+ CPMaxIteration("sh-constant-island-max-iteration", cl::Hidden, cl::init(30),
+ cl::desc("The max number of iteration for converge"));
namespace {
- /// SuperHConstantIslands - Due to limited PC-relative displacements, SH
- /// requires constant pool entries to be scattered among the instructions
- /// inside a function. To do this, it completely ignores the normal LLVM
- /// constant pool; instead, it places constants wherever it feels like with
- /// special instructions.
- ///
- /// The terminology used in this pass includes:
- /// Islands - Clumps of constants placed in the function.
- /// Water - Potential places where an island could be formed.
- /// CPE - A constant pool entry that has been placed somewhere, which
- /// tracks a list of users.
- class SuperHConstantIslands : public MachineFunctionPass {
- public:
- static char ID;
-
- private:
- std::unique_ptr<SuperHBasicBlockUtils> BBUtils = nullptr;
-
- /// WaterList - A sorted list of basic blocks where islands could be placed
- /// (i.e. blocks that don't fall through to the following block, due
- /// to a return, unreachable, or unconditional branch).
- std::vector<MachineBasicBlock*> WaterList;
-
- /// NewWaterList - The subset of WaterList that was created since the
- /// previous iteration by inserting unconditional branches.
- SmallPtrSet<MachineBasicBlock *, 4> NewWaterList;
-
- using water_iterator = std::vector<MachineBasicBlock *>::iterator;
-
- /// CPUser - One user of a constant pool, keeping the machine instruction
- /// pointer, the constant pool being referenced, and the max displacement
- /// allowed from the instruction to the CP. The HighWaterMark records the
- /// highest basic block where a new CPEntry can be placed. To ensure this
- /// pass terminates, the CP entries are initially placed at the end of the
- /// function and then move monotonically to lower addresses. The
- /// exception to this rule is when the current CP entry for a particular
- /// CPUser is out of range, but there is another CP entry for the same
- /// constant value in range. We want to use the existing in-range CP
- /// entry, but if it later moves out of range, the search for new water
- /// should resume where it left off. The HighWaterMark is used to record
- /// that point.
- struct CPUser {
- MachineInstr *MI;
- MachineInstr *CPEMI;
- MachineBasicBlock *HighWaterMark;
- unsigned MaxDisp;
- bool NegOk;
- bool IsSoImm;
- bool KnownAlignment = false;
-
- CPUser(MachineInstr *mi, MachineInstr *cpemi, unsigned maxdisp,
- bool neg, bool soimm)
+/// SuperHConstantIslands - Due to limited PC-relative displacements, SH
+/// requires constant pool entries to be scattered among the instructions
+/// inside a function. To do this, it completely ignores the normal LLVM
+/// constant pool; instead, it places constants wherever it feels like with
+/// special instructions.
+///
+/// The terminology used in this pass includes:
+/// Islands - Clumps of constants placed in the function.
+/// Water - Potential places where an island could be formed.
+/// CPE - A constant pool entry that has been placed somewhere, which
+/// tracks a list of users.
+class SuperHConstantIslands : public MachineFunctionPass {
+public:
+ static char ID;
+
+private:
+ std::unique_ptr<SuperHBasicBlockUtils> BBUtils = nullptr;
+
+ /// WaterList - A sorted list of basic blocks where islands could be placed
+ /// (i.e. blocks that don't fall through to the following block, due
+ /// to a return, unreachable, or unconditional branch).
+ std::vector<MachineBasicBlock *> WaterList;
+
+ /// NewWaterList - The subset of WaterList that was created since the
+ /// previous iteration by inserting unconditional branches.
+ SmallPtrSet<MachineBasicBlock *, 4> NewWaterList;
+
+ using water_iterator = std::vector<MachineBasicBlock *>::iterator;
+
+ /// CPUser - One user of a constant pool, keeping the machine instruction
+ /// pointer, the constant pool being referenced, and the max displacement
+ /// allowed from the instruction to the CP. The HighWaterMark records the
+ /// highest basic block where a new CPEntry can be placed. To ensure this
+ /// pass terminates, the CP entries are initially placed at the end of the
+ /// function and then move monotonically to lower addresses. The
+ /// exception to this rule is when the current CP entry for a particular
+ /// CPUser is out of range, but there is another CP entry for the same
+ /// constant value in range. We want to use the existing in-range CP
+ /// entry, but if it later moves out of range, the search for new water
+ /// should resume where it left off. The HighWaterMark is used to record
+ /// that point.
+ struct CPUser {
+ MachineInstr *MI;
+ MachineInstr *CPEMI;
+ MachineBasicBlock *HighWaterMark;
+ unsigned MaxDisp;
+ bool NegOk;
+ bool IsSoImm;
+ bool KnownAlignment = false;
+
+ CPUser(MachineInstr *mi, MachineInstr *cpemi, unsigned maxdisp, bool neg,
+ bool soimm)
: MI(mi), CPEMI(cpemi), MaxDisp(maxdisp), NegOk(neg), IsSoImm(soimm) {
- HighWaterMark = CPEMI->getParent();
- }
+ HighWaterMark = CPEMI->getParent();
+ }
- /// getMaxDisp - Returns the maximum displacement supported by MI.
- /// Correct for unknown alignment.
- /// Conservatively subtract 2 bytes to handle weird alignment effects.
- unsigned getMaxDisp() const {
- return (KnownAlignment ? MaxDisp : MaxDisp - 2) - 2;
- }
- };
+ /// getMaxDisp - Returns the maximum displacement supported by MI.
+ /// Correct for unknown alignment.
+ /// Conservatively subtract 2 bytes to handle weird alignment effects.
+ unsigned getMaxDisp() const {
+ return (KnownAlignment ? MaxDisp : MaxDisp - 2) - 2;
+ }
+ };
- /// CPUsers - Keep track of all of the machine instructions that use various
- /// constant pools and their max displacement.
- std::vector<CPUser> CPUsers;
+ /// CPUsers - Keep track of all of the machine instructions that use various
+ /// constant pools and their max displacement.
+ std::vector<CPUser> CPUsers;
- /// CPEntry - One per constant pool entry, keeping the machine instruction
- /// pointer, the constpool index, and the number of CPUser's which
- /// reference this entry.
- struct CPEntry {
- MachineInstr *CPEMI;
- unsigned CPI;
- unsigned RefCount;
+ /// CPEntry - One per constant pool entry, keeping the machine instruction
+ /// pointer, the constpool index, and the number of CPUser's which
+ /// reference this entry.
+ struct CPEntry {
+ MachineInstr *CPEMI;
+ unsigned CPI;
+ unsigned RefCount;
- CPEntry(MachineInstr *cpemi, unsigned cpi, unsigned rc = 0)
+ CPEntry(MachineInstr *cpemi, unsigned cpi, unsigned rc = 0)
: CPEMI(cpemi), CPI(cpi), RefCount(rc) {}
- };
-
- /// CPEntries - Keep track of all of the constant pool entry machine
- /// instructions. For each original constpool index (i.e. those that existed
- /// upon entry to this pass), it keeps a vector of entries. Original
- /// elements are cloned as we go along; the clones are put in the vector of
- /// the original element, but have distinct CPIs.
- ///
- /// The first half of CPEntries contains generic constants, the second half
- /// contains jump tables. Use getCombinedIndex on a generic CPEMI to look up
- /// which vector it will be in here.
- std::vector<std::vector<CPEntry>> CPEntries;
-
- /// ImmBranch - One per immediate branch, keeping the machine instruction
- /// pointer, conditional or unconditional, the max displacement,
- /// and (if isCond is true) the corresponding unconditional branch
- /// opcode.
- struct ImmBranch {
- MachineInstr *MI;
- unsigned MaxDisp : 12;
-
- ImmBranch(MachineInstr *mi, unsigned maxdisp)
- : MI(mi), MaxDisp(maxdisp) {}
- };
-
- /// ImmBranches - Keep track of all the immediate branch instructions.
- std::vector<ImmBranch> ImmBranches;
-
- MachineFunction *MF;
- MachineConstantPool *MCP;
- const SuperHInstrInfo *TII;
- const SuperHSubtarget *STI;
- SuperHMachineFunctionInfo *SFI;
- MachineDominatorTree *DT = nullptr;
- bool isPIC;
-
- public:
-
- SuperHConstantIslands() : MachineFunctionPass(ID) {}
-
- bool runOnMachineFunction(MachineFunction &MF) override;
-
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.addRequired<MachineDominatorTreeWrapperPass>();
- MachineFunctionPass::getAnalysisUsage(AU);
- }
+ };
- MachineFunctionProperties getRequiredProperties() const override {
- return MachineFunctionProperties().setNoVRegs();
- }
+ /// CPEntries - Keep track of all of the constant pool entry machine
+ /// instructions. For each original constpool index (i.e. those that existed
+ /// upon entry to this pass), it keeps a vector of entries. Original
+ /// elements are cloned as we go along; the clones are put in the vector of
+ /// the original element, but have distinct CPIs.
+ ///
+ /// The first half of CPEntries contains generic constants, the second half
+ /// contains jump tables. Use getCombinedIndex on a generic CPEMI to look up
+ /// which vector it will be in here.
+ std::vector<std::vector<CPEntry>> CPEntries;
+
+ /// ImmBranch - One per immediate branch, keeping the machine instruction
+ /// pointer, conditional or unconditional, the max displacement,
+ /// and (if isCond is true) the corresponding unconditional branch
+ /// opcode.
+ struct ImmBranch {
+ MachineInstr *MI;
+ unsigned MaxDisp : 12;
+
+ ImmBranch(MachineInstr *mi, unsigned maxdisp) : MI(mi), MaxDisp(maxdisp) {}
+ };
- StringRef getPassName() const override {
- return SH_CP_ISLANDS_OPT_NAME;
- }
+ /// ImmBranches - Keep track of all the immediate branch instructions.
+ std::vector<ImmBranch> ImmBranches;
- private:
- bool BBHasFallthrough(MachineBasicBlock *MBB);
- void doInitialConstPlacement(std::vector<MachineInstr *> &CPEMIs);
- CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);
- Align getCPEAlign(const MachineInstr *CPEMI);
- void initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs);
- MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI);
- void updateForInsertedWaterBlock(MachineBasicBlock *NewBB);
- bool decrementCPEReferenceCount(unsigned CPI, MachineInstr* CPEMI);
- unsigned getCombinedIndex(const MachineInstr *CPEMI);
- int findInRangeCPEntry(CPUser& U, unsigned UserOffset);
- bool findAvailableWater(CPUser&U, unsigned UserOffset,
- water_iterator &WaterIter, bool CloserWater);
- void createNewWater(unsigned CPUserIndex, unsigned UserOffset,
- MachineBasicBlock *&NewMBB);
- bool handleConstantPoolUser(unsigned CPUserIndex, bool CloserWater);
- void removeDeadCPEMI(MachineInstr *CPEMI);
- bool removeUnusedCPEntries();
- bool isCPEntryInRange(MachineInstr *MI, unsigned UserOffset,
- MachineInstr *CPEMI, unsigned Disp, bool NegOk,
- bool DoDump = false);
- bool isWaterInRange(unsigned UserOffset, MachineBasicBlock *Water,
- CPUser &U, unsigned &Growth);
- bool fixupImmediateBr(ImmBranch &Br);
-
- unsigned getUserOffset(CPUser&) const;
- void verify();
-
- bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
- unsigned Disp, bool NegativeOK, bool IsSoImm = false);
- bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
- const CPUser &U) {
- return isOffsetInRange(UserOffset, TrialOffset,
- U.getMaxDisp(), U.NegOk, U.IsSoImm);
- }
+ MachineFunction *MF;
+ MachineConstantPool *MCP;
+ const SuperHInstrInfo *TII;
+ const SuperHSubtarget *STI;
+ SuperHMachineFunctionInfo *SFI;
+ MachineDominatorTree *DT = nullptr;
+ bool isPIC;
- };
+public:
+ SuperHConstantIslands() : MachineFunctionPass(ID) {}
-} // end anonymous namespace
+ bool runOnMachineFunction(MachineFunction &MF) override;
-char SuperHConstantIslands::ID = 0;
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.addRequired<MachineDominatorTreeWrapperPass>();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+ MachineFunctionProperties getRequiredProperties() const override {
+ return MachineFunctionProperties().setNoVRegs();
+ }
+
+ StringRef getPassName() const override { return SH_CP_ISLANDS_OPT_NAME; }
+
+private:
+ bool BBHasFallthrough(MachineBasicBlock *MBB);
+ void doInitialConstPlacement(std::vector<MachineInstr *> &CPEMIs);
+ CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);
+ Align getCPEAlign(const MachineInstr *CPEMI);
+ void initializeFunctionInfo(const std::vector<MachineInstr *> &CPEMIs);
+ MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI);
+ void updateForInsertedWaterBlock(MachineBasicBlock *NewBB);
+ bool decrementCPEReferenceCount(unsigned CPI, MachineInstr *CPEMI);
+ unsigned getCombinedIndex(const MachineInstr *CPEMI);
+ int findInRangeCPEntry(CPUser &U, unsigned UserOffset);
+ bool findAvailableWater(CPUser &U, unsigned UserOffset,
+ water_iterator &WaterIter, bool CloserWater);
+ void createNewWater(unsigned CPUserIndex, unsigned UserOffset,
+ MachineBasicBlock *&NewMBB);
+ bool handleConstantPoolUser(unsigned CPUserIndex, bool CloserWater);
+ void removeDeadCPEMI(MachineInstr *CPEMI);
+ bool removeUnusedCPEntries();
+ bool isCPEntryInRange(MachineInstr *MI, unsigned UserOffset,
+ MachineInstr *CPEMI, unsigned Disp, bool NegOk,
+ bool DoDump = false);
+ bool isWaterInRange(unsigned UserOffset, MachineBasicBlock *Water, CPUser &U,
+ unsigned &Growth);
+ bool fixupImmediateBr(ImmBranch &Br);
+
+ unsigned getUserOffset(CPUser &) const;
+ void verify();
+
+ bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset, unsigned Disp,
+ bool NegativeOK, bool IsSoImm = false);
+ bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
+ const CPUser &U) {
+ return isOffsetInRange(UserOffset, TrialOffset, U.getMaxDisp(), U.NegOk,
+ U.IsSoImm);
+ }
+};
+} // end anonymous namespace
+char SuperHConstantIslands::ID = 0;
//===----------------------------------------------------------------------===//
// HELPERS
@@ -248,9 +240,7 @@ static bool CompareMBBNumbers(const MachineBasicBlock *LHS,
/// getDispRange - Returns the maximum displacement that can fit in
/// the specific unconditional branch instruction.
-static inline unsigned getDispRange(int Opc) {
- return ((1<<8)-1)*4;
-}
+static inline unsigned getDispRange(int Opc) { return ((1 << 8) - 1) * 4; }
/// isOffsetInRange - Checks whether UserOffset (the location of a constant pool
/// reference) is within MaxDisp of TrialOffset (a proposed location of a
@@ -259,8 +249,9 @@ static inline unsigned getDispRange(int Opc) {
/// the mod 4 alignment of UserOffset is not known, the uncertainty must be
/// subtracted from MaxDisp instead. CPUser::getMaxDisp() does that.
bool SuperHConstantIslands::isOffsetInRange(unsigned UserOffset,
- unsigned TrialOffset, unsigned MaxDisp,
- bool NegativeOK, bool IsSoImm) {
+ unsigned TrialOffset,
+ unsigned MaxDisp, bool NegativeOK,
+ bool IsSoImm) {
if (UserOffset <= TrialOffset) {
// User before the Trial.
if (TrialOffset - UserOffset <= MaxDisp)
@@ -308,8 +299,8 @@ Align SuperHConstantIslands::getCPEAlign(const MachineInstr *CPEMI) {
///
/// Compute how much the function will grow by inserting a CPE after Water.
bool SuperHConstantIslands::isWaterInRange(unsigned UserOffset,
- MachineBasicBlock* Water, CPUser &U,
- unsigned &Growth) {
+ MachineBasicBlock *Water, CPUser &U,
+ unsigned &Growth) {
BBInfoVector &BBInfo = BBUtils->getBBInfo();
const Align CPEAlign = getCPEAlign(U.CPEMI);
const unsigned CPEOffset = BBInfo[Water->getNumber()].postOffset(CPEAlign);
@@ -348,14 +339,16 @@ bool SuperHConstantIslands::isWaterInRange(unsigned UserOffset,
/// isCPEntryInRange - Returns true if the distance between specific MI and
/// specific ConstPool entry instruction can fit in MI's displacement field.
-bool SuperHConstantIslands::isCPEntryInRange(MachineInstr *MI, unsigned UserOffset,
- MachineInstr *CPEMI, unsigned MaxDisp,
- bool NegOk, bool DoDump) {
+bool SuperHConstantIslands::isCPEntryInRange(MachineInstr *MI,
+ unsigned UserOffset,
+ MachineInstr *CPEMI,
+ unsigned MaxDisp, bool NegOk,
+ bool DoDump) {
unsigned CPEOffset = BBUtils->getOffsetOf(CPEMI);
if (DoDump) {
LLVM_DEBUG({
- BBInfoVector &BBInfo = BBUtils->getBBInfo();
+ BBInfoVector &BBInfo = BBUtils->getBBInfo();
unsigned Block = MI->getParent()->getNumber();
const BasicBlockInfo &BBI = BBInfo[Block];
dbgs() << "User of CPE#" << CPEMI->getOperand(0).getImm()
@@ -390,9 +383,6 @@ unsigned SuperHConstantIslands::getUserOffset(CPUser &U) const {
return UserOffset;
}
-
-
-
//===----------------------------------------------------------------------===//
// BASE IMPLEMENTATION
//===----------------------------------------------------------------------===//
@@ -423,17 +413,16 @@ bool SuperHConstantIslands::runOnMachineFunction(MachineFunction &mf) {
// Perform the initial placement of the constant pool entries. To start with,
// we put them all at the end of the function.
- std::vector<MachineInstr*> CPEMIs;
+ std::vector<MachineInstr *> CPEMIs;
if (!MCP->isEmpty())
doInitialConstPlacement(CPEMIs);
-
// Iteratively place constant pool entries and fix up branches until there
// is no change.
unsigned NoCPIters = 0, NoBRIters = 0;
while (true) {
- LLVM_DEBUG(dbgs() << "Beginning CP iteration #" << NoCPIters << " with " <<
- CPUsers.size() << " entries..." << '\n');
+ LLVM_DEBUG(dbgs() << "Beginning CP iteration #" << NoCPIters << " with "
+ << CPUsers.size() << " entries..." << '\n');
bool CPChange = false;
for (unsigned i = 0, e = CPUsers.size(); i != e; ++i)
// For most inputs, it converges in no more than 5 iterations.
@@ -447,8 +436,8 @@ bool SuperHConstantIslands::runOnMachineFunction(MachineFunction &mf) {
// appear as "new water" for the next iteration of constant pool placement.
NewWaterList.clear();
- LLVM_DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << " with " <<
- ImmBranches.size() << " entries..." << '\n');
+ LLVM_DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << " with "
+ << ImmBranches.size() << " entries..." << '\n');
bool BRChange = false;
for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i) {
// Note: fixupImmediateBr can append to ImmBranches.
@@ -473,8 +462,8 @@ bool SuperHConstantIslands::runOnMachineFunction(MachineFunction &mf) {
/// initializeFunctionInfo - Do the initial scan of the function, building up
/// information about the sizes of each block, the location of all the water,
/// and finding all of the constant pool users.
-void SuperHConstantIslands::
-initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
+void SuperHConstantIslands::initializeFunctionInfo(
+ const std::vector<MachineInstr *> &CPEMIs) {
BBUtils->computeAllBlockSizes();
BBInfoVector &BBInfo = BBUtils->getBBInfo();
@@ -520,9 +509,8 @@ initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
break;
}
-
// Record this immediate branch.
- unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
+ unsigned MaxOffs = ((1 << (Bits - 1)) - 1) * Scale;
ImmBranches.push_back(ImmBranch(&I, MaxOffs));
}
@@ -537,7 +525,7 @@ initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
unsigned CPI = I.getOperand(op).getIndex();
MachineInstr *CPEMI = CPEMIs[CPI];
- unsigned MaxOffs = ((1 << 8)-1) * 4;
+ unsigned MaxOffs = ((1 << 8) - 1) * 4;
CPUsers.push_back(CPUser(&I, CPEMI, MaxOffs, NegOk, IsSoImm));
// Increment corresponding CPEntry reference count.
@@ -548,16 +536,12 @@ initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
// Instructions can only use one CP entry, don't bother scanning the
// rest of the operands.
break;
-
}
}
}
}
}
-
-
-
//===----------------------------------------------------------------------===//
// CONSTPOOL MANAGMENT
//===----------------------------------------------------------------------===//
@@ -605,7 +589,7 @@ bool SuperHConstantIslands::removeUnusedCPEntries() {
/// becomes 0 remove the entry and instruction. Returns true if we removed
/// the entry, false if we didn't.
bool SuperHConstantIslands::decrementCPEReferenceCount(unsigned CPI,
- MachineInstr *CPEMI) {
+ MachineInstr *CPEMI) {
// Find the old entry. Eliminate it if it is no longer used.
CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
assert(CPE && "Unexpected!");
@@ -629,9 +613,9 @@ unsigned SuperHConstantIslands::getCombinedIndex(const MachineInstr *CPEMI) {
/// 0 = no existing entry found
/// 1 = entry found, and there were no code insertions or deletions
/// 2 = entry found, and there were code insertions or deletions
-int SuperHConstantIslands::findInRangeCPEntry(CPUser& U, unsigned UserOffset) {
+int SuperHConstantIslands::findInRangeCPEntry(CPUser &U, unsigned UserOffset) {
MachineInstr *UserMI = U.MI;
- MachineInstr *CPEMI = U.CPEMI;
+ MachineInstr *CPEMI = U.CPEMI;
// Check to see if the CPE is already in-range.
if (isCPEntryInRange(UserMI, UserOffset, CPEMI, U.getMaxDisp(), U.NegOk,
@@ -677,10 +661,10 @@ int SuperHConstantIslands::findInRangeCPEntry(CPUser& U, unsigned UserOffset) {
/// place in-range. Return true if we changed any addresses (thus must run
/// another pass of branch lengthening), false otherwise.
bool SuperHConstantIslands::handleConstantPoolUser(unsigned CPUserIndex,
- bool CloserWater) {
+ bool CloserWater) {
CPUser &U = CPUsers[CPUserIndex];
MachineInstr *UserMI = U.MI;
- MachineInstr *CPEMI = U.CPEMI;
+ MachineInstr *CPEMI = U.CPEMI;
unsigned CPI = getCombinedIndex(CPEMI);
unsigned Size = CPEMI->getOperand(2).getImm();
// Compute this only once, it's expensive.
@@ -689,8 +673,10 @@ bool SuperHConstantIslands::handleConstantPoolUser(unsigned CPUserIndex,
// See if the current entry is within range, or there is a clone of it
// in range.
int result = findInRangeCPEntry(U, UserOffset);
- if (result==1) return false;
- else if (result==2) return true;
+ if (result == 1)
+ return false;
+ else if (result == 2)
+ return true;
// No existing clone of this CPE is within range.
// We will be generating a new clone. Get a UID for it.
@@ -789,7 +775,7 @@ bool SuperHConstantIslands::handleConstantPoolUser(unsigned CPUserIndex,
/// look up the corresponding CPEntry.
SuperHConstantIslands::CPEntry *
SuperHConstantIslands::findConstPoolEntry(unsigned CPI,
- const MachineInstr *CPEMI) {
+ const MachineInstr *CPEMI) {
std::vector<CPEntry> &CPEs = CPEntries[CPI];
// Number of entries per constpool index should be small, just do a
// linear search.
@@ -808,8 +794,8 @@ SuperHConstantIslands::findConstPoolEntry(unsigned CPI,
/// move to a lower address, so search backward from the end of the list and
/// prefer the first water that is in range.
bool SuperHConstantIslands::findAvailableWater(CPUser &U, unsigned UserOffset,
- water_iterator &WaterIter,
- bool CloserWater) {
+ water_iterator &WaterIter,
+ bool CloserWater) {
if (WaterList.empty())
return false;
@@ -832,7 +818,7 @@ bool SuperHConstantIslands::findAvailableWater(CPUser &U, unsigned UserOffset,
return false;
for (water_iterator IP = std::prev(WaterList.end()), B = WaterList.begin();;
--IP) {
- MachineBasicBlock* WaterBB = *IP;
+ MachineBasicBlock *WaterBB = *IP;
// Check if water is in range and is either at a lower address than the
// current "high water mark" or a new water block that was created since
// the previous iteration by inserting an unconditional branch. In the
@@ -875,11 +861,11 @@ bool SuperHConstantIslands::findAvailableWater(CPUser &U, unsigned UserOffset,
/// block following which the new island can be inserted (the WaterList
/// is not adjusted).
void SuperHConstantIslands::createNewWater(unsigned CPUserIndex,
- unsigned UserOffset,
- MachineBasicBlock *&NewMBB) {
+ unsigned UserOffset,
+ MachineBasicBlock *&NewMBB) {
CPUser &U = CPUsers[CPUserIndex];
MachineInstr *UserMI = U.MI;
- MachineInstr *CPEMI = U.CPEMI;
+ MachineInstr *CPEMI = U.CPEMI;
const Align CPEAlign = getCPEAlign(CPEMI);
MachineBasicBlock *UserMBB = UserMI->getParent();
BBInfoVector &BBInfo = BBUtils->getBBInfo();
@@ -905,8 +891,7 @@ void SuperHConstantIslands::createNewWater(unsigned CPUserIndex,
// but if the preceding conditional branch is out of range, the targets
// will be exchanged, and the altered branch may be out of range, so the
// machinery has to know about it.
- BuildMI(UserMBB, DebugLoc(), TII->get(SH::BRA))
- .addMBB(NewMBB);
+ BuildMI(UserMBB, DebugLoc(), TII->get(SH::BRA)).addMBB(NewMBB);
unsigned MaxDisp = getDispRange(SH::BRA);
ImmBranches.push_back(ImmBranch(&UserMBB->back(), MaxDisp));
@@ -948,11 +933,11 @@ void SuperHConstantIslands::createNewWater(unsigned CPUserIndex,
<< " la=" << Log2(Align) << " kb=" << KnownBits
<< " up=" << UPad << '\n');
- unsigned EndInsertOffset = BaseInsertOffset + 4 + UPad +
- CPEMI->getOperand(2).getImm();
+ unsigned EndInsertOffset =
+ BaseInsertOffset + 4 + UPad + CPEMI->getOperand(2).getImm();
MachineBasicBlock::iterator MI = UserMI;
++MI;
- unsigned CPUIndex = CPUserIndex+1;
+ unsigned CPUIndex = CPUserIndex + 1;
unsigned NumCPUsers = CPUsers.size();
for (unsigned Offset = UserOffset + TII->getInstSizeInBytes(*UserMI);
Offset < BaseInsertOffset;
@@ -983,7 +968,8 @@ void SuperHConstantIslands::createNewWater(unsigned CPUserIndex,
/// updateForInsertedWaterBlock - When a block is newly inserted into the
/// machine function, it upsets all of the block numbers. Renumber the blocks
/// and update the arrays that parallel this numbering.
-void SuperHConstantIslands::updateForInsertedWaterBlock(MachineBasicBlock *NewBB) {
+void SuperHConstantIslands::updateForInsertedWaterBlock(
+ MachineBasicBlock *NewBB) {
// Renumber the MBB's to keep them consecutive.
NewBB->getParent()->RenumberBlocks(NewBB);
@@ -1000,7 +986,8 @@ void SuperHConstantIslands::updateForInsertedWaterBlock(MachineBasicBlock *NewBB
/// Split the basic block containing MI into two blocks, which are joined by
/// an unconditional branch. Update data structures and renumber blocks to
/// account for this change and returns the newly created block.
-MachineBasicBlock *SuperHConstantIslands::splitBlockBeforeInstr(MachineInstr *MI) {
+MachineBasicBlock *
+SuperHConstantIslands::splitBlockBeforeInstr(MachineInstr *MI) {
MachineBasicBlock *OrigBB = MI->getParent();
// Collect liveness information at MI.
@@ -1012,7 +999,7 @@ MachineBasicBlock *SuperHConstantIslands::splitBlockBeforeInstr(MachineInstr *MI
// Create a new MBB for the code after the OrigBB.
MachineBasicBlock *NewBB =
- MF->CreateMachineBasicBlock(OrigBB->getBasicBlock());
+ MF->CreateMachineBasicBlock(OrigBB->getBasicBlock());
MachineFunction::iterator MBBI = ++OrigBB->getIterator();
MF->insert(MBBI, NewBB);
@@ -1051,7 +1038,7 @@ MachineBasicBlock *SuperHConstantIslands::splitBlockBeforeInstr(MachineInstr *MI
// when splitting before a conditional branch that is followed by an
// unconditional branch - in that case we want to insert NewBB).
water_iterator IP = llvm::lower_bound(WaterList, OrigBB, CompareMBBNumbers);
- MachineBasicBlock* WaterBB = *IP;
+ MachineBasicBlock *WaterBB = *IP;
if (WaterBB == OrigBB)
WaterList.insert(std::next(IP), NewBB);
else
@@ -1075,18 +1062,15 @@ MachineBasicBlock *SuperHConstantIslands::splitBlockBeforeInstr(MachineInstr *MI
return NewBB;
}
-
-
-
//===----------------------------------------------------------------------===//
// CONST PLACEMENT
//===----------------------------------------------------------------------===//
/// Perform the initial placement of the regular constant pool entries.
/// To start with, we put them all at the end of the function.
-void
-SuperHConstantIslands::doInitialConstPlacement(std::vector<MachineInstr *> &CPEMIs) {
-
+void SuperHConstantIslands::doInitialConstPlacement(
+ std::vector<MachineInstr *> &CPEMIs) {
+
// Create the basic block to hold the CPE's.
MachineBasicBlock *BB = MF->CreateMachineBasicBlock();
MF->push_back(BB);
@@ -1129,8 +1113,10 @@ SuperHConstantIslands::doInitialConstPlacement(std::vector<MachineInstr *> &CPEM
unsigned LogAlign = Log2(Alignment);
MachineBasicBlock::iterator InsAt = InsPoint[LogAlign];
MachineInstr *CPEMI =
- BuildMI(*BB, InsAt, DebugLoc(), TII->get(SH::CONSTPOOL_ENTRY))
- .addImm(i).addConstantPoolIndex(i).addImm(Size);
+ BuildMI(*BB, InsAt, DebugLoc(), TII->get(SH::CONSTPOOL_ENTRY))
+ .addImm(i)
+ .addConstantPoolIndex(i)
+ .addImm(Size);
CPEMIs.push_back(CPEMI);
// Ensure that future entries with higher alignment get inserted before
@@ -1167,9 +1153,6 @@ bool SuperHConstantIslands::fixupImmediateBr(ImmBranch &Br) {
return true;
}
-
-
-
//===----------------------------------------------------------------------===//
// INITIALIZATION
//===----------------------------------------------------------------------===//
@@ -1180,6 +1163,5 @@ FunctionPass *llvm::createSuperHConstantIslandPass() {
return new SuperHConstantIslands();
}
-
INITIALIZE_PASS(SuperHConstantIslands, "sh-cp-islands", SH_CP_ISLANDS_OPT_NAME,
false, false)
diff --git a/llvm/lib/Target/SuperH/SuperHConstantPoolValue.cpp b/llvm/lib/Target/SuperH/SuperHConstantPoolValue.cpp
index e102c2438..fe8700ae4 100644
--- a/llvm/lib/Target/SuperH/SuperHConstantPoolValue.cpp
+++ b/llvm/lib/Target/SuperH/SuperHConstantPoolValue.cpp
@@ -14,22 +14,21 @@
using namespace llvm;
-
-
//===----------------------------------------------------------------------===//
// SuperHConstantPoolValue
//===----------------------------------------------------------------------===//
SuperHConstantPoolValue::SuperHConstantPoolValue(Type *Ty, unsigned id,
- SHCP::SHCPKind kind,
- SHCP::SHCPModifier modifier)
- : MachineConstantPoolValue(Ty), LabelId(id), Kind(kind), Modifier(modifier) {}
+ SHCP::SHCPKind kind,
+ SHCP::SHCPModifier modifier)
+ : MachineConstantPoolValue(Ty), LabelId(id), Kind(kind),
+ Modifier(modifier) {}
SuperHConstantPoolValue::SuperHConstantPoolValue(LLVMContext &C, unsigned id,
- SHCP::SHCPKind kind,
- SHCP::SHCPModifier modifier)
- : MachineConstantPoolValue((Type*)Type::getInt32Ty(C)),
- LabelId(id), Kind(kind), Modifier(modifier) {}
+ SHCP::SHCPKind kind,
+ SHCP::SHCPModifier modifier)
+ : MachineConstantPoolValue((Type *)Type::getInt32Ty(C)), LabelId(id),
+ Kind(kind), Modifier(modifier) {}
SuperHConstantPoolValue::~SuperHConstantPoolValue() = default;
@@ -48,19 +47,16 @@ StringRef SuperHConstantPoolValue::getModifierText() const {
}
int SuperHConstantPoolValue::getExistingMachineCPValue(MachineConstantPool *CP,
- Align Alignment) {
+ Align Alignment) {
llvm_unreachable("Shouldn't be calling this directly!");
}
-void
-SuperHConstantPoolValue::addSelectionDAGCSEId(FoldingSetNodeID &ID) {
+void SuperHConstantPoolValue::addSelectionDAGCSEId(FoldingSetNodeID &ID) {
ID.AddInteger(LabelId);
}
-bool
-SuperHConstantPoolValue::hasSameValue(SuperHConstantPoolValue *ACPV) {
- if (ACPV->Kind == Kind &&
- ACPV->Modifier == Modifier &&
+bool SuperHConstantPoolValue::hasSameValue(SuperHConstantPoolValue *ACPV) {
+ if (ACPV->Kind == Kind && ACPV->Modifier == Modifier &&
ACPV->LabelId == LabelId) {
// Two PC relative constpool entries containing the same GV address or
@@ -78,69 +74,63 @@ LLVM_DUMP_METHOD void SuperHConstantPoolValue::dump() const {
#endif
void SuperHConstantPoolValue::print(raw_ostream &O) const {
- if (Modifier) O << "(" << getModifierText() << ")";
+ if (Modifier)
+ O << "(" << getModifierText() << ")";
}
-
-
-
//===----------------------------------------------------------------------===//
// SuperHConstantPoolConstant
//===----------------------------------------------------------------------===//
-SuperHConstantPoolConstant::SuperHConstantPoolConstant(Type *Ty,
- const Constant *C,
- unsigned ID,
- SHCP::SHCPKind Kind,
- SHCP::SHCPModifier Modifier)
- : SuperHConstantPoolValue(Ty, ID, Kind, Modifier),
- CVal(C) {}
-
-SuperHConstantPoolConstant::SuperHConstantPoolConstant(const Constant *C,
- unsigned ID,
- SHCP::SHCPKind Kind,
- SHCP::SHCPModifier Modifier)
- : SuperHConstantPoolValue((Type*)C->getType(), ID, Kind, Modifier),
- CVal(C) {}
+SuperHConstantPoolConstant::SuperHConstantPoolConstant(
+ Type *Ty, const Constant *C, unsigned ID, SHCP::SHCPKind Kind,
+ SHCP::SHCPModifier Modifier)
+ : SuperHConstantPoolValue(Ty, ID, Kind, Modifier), CVal(C) {}
+
+SuperHConstantPoolConstant::SuperHConstantPoolConstant(
+ const Constant *C, unsigned ID, SHCP::SHCPKind Kind,
+ SHCP::SHCPModifier Modifier)
+ : SuperHConstantPoolValue((Type *)C->getType(), ID, Kind, Modifier),
+ CVal(C) {}
SuperHConstantPoolConstant::SuperHConstantPoolConstant(const GlobalVariable *GV,
- const Constant *C)
+ const Constant *C)
: SuperHConstantPoolValue((Type *)C->getType(), 0, SHCP::CPPromotedGlobal,
- SHCP::no_modifier), CVal(C) {
+ SHCP::no_modifier),
+ CVal(C) {
GVars.insert(GV);
}
SuperHConstantPoolConstant *
SuperHConstantPoolConstant::Create(const Constant *C, unsigned ID) {
return new SuperHConstantPoolConstant(C, ID, SHCP::CPValue,
- SHCP::no_modifier);
+ SHCP::no_modifier);
}
SuperHConstantPoolConstant *
SuperHConstantPoolConstant::Create(const GlobalVariable *GVar,
- const Constant *Initializer) {
+ const Constant *Initializer) {
return new SuperHConstantPoolConstant(GVar, Initializer);
}
SuperHConstantPoolConstant *
SuperHConstantPoolConstant::Create(const GlobalValue *GV,
- SHCP::SHCPModifier Modifier) {
- return new SuperHConstantPoolConstant((Type*)Type::getInt32Ty(GV->getContext()),
- GV, 0, SHCP::CPValue,
- Modifier);
+ SHCP::SHCPModifier Modifier) {
+ return new SuperHConstantPoolConstant(
+ (Type *)Type::getInt32Ty(GV->getContext()), GV, 0, SHCP::CPValue,
+ Modifier);
}
SuperHConstantPoolConstant *
SuperHConstantPoolConstant::Create(const Constant *C, unsigned ID,
- SHCP::SHCPKind Kind) {
- return new SuperHConstantPoolConstant(C, ID, Kind,
- SHCP::no_modifier);
+ SHCP::SHCPKind Kind) {
+ return new SuperHConstantPoolConstant(C, ID, Kind, SHCP::no_modifier);
}
SuperHConstantPoolConstant *
SuperHConstantPoolConstant::Create(const Constant *C, unsigned ID,
- SHCP::SHCPKind Kind,
- SHCP::SHCPModifier Modifier) {
+ SHCP::SHCPKind Kind,
+ SHCP::SHCPModifier Modifier) {
return new SuperHConstantPoolConstant(C, ID, Kind, Modifier);
}
@@ -152,12 +142,12 @@ const BlockAddress *SuperHConstantPoolConstant::getBlockAddress() const {
return dyn_cast_or_null<BlockAddress>(CVal);
}
-int SuperHConstantPoolConstant::getExistingMachineCPValue(MachineConstantPool *CP,
- Align Alignment) {
+int SuperHConstantPoolConstant::getExistingMachineCPValue(
+ MachineConstantPool *CP, Align Alignment) {
int index =
- getExistingMachineCPValueImpl<SuperHConstantPoolConstant>(CP, Alignment);
+ getExistingMachineCPValueImpl<SuperHConstantPoolConstant>(CP, Alignment);
if (index != -1) {
- auto *CPV = static_cast<SuperHConstantPoolValue*>(
+ auto *CPV = static_cast<SuperHConstantPoolValue *>(
CP->getConstants()[index].Val.MachineCPVal);
auto *Constant = cast<SuperHConstantPoolConstant>(CPV);
Constant->GVars.insert_range(GVars);
@@ -166,8 +156,10 @@ int SuperHConstantPoolConstant::getExistingMachineCPValue(MachineConstantPool *C
}
bool SuperHConstantPoolConstant::hasSameValue(SuperHConstantPoolValue *ACPV) {
- const SuperHConstantPoolConstant *ACPC = dyn_cast<SuperHConstantPoolConstant>(ACPV);
- return ACPC && ACPC->CVal == CVal && SuperHConstantPoolValue::hasSameValue(ACPV);
+ const SuperHConstantPoolConstant *ACPC =
+ dyn_cast<SuperHConstantPoolConstant>(ACPV);
+ return ACPC && ACPC->CVal == CVal &&
+ SuperHConstantPoolValue::hasSameValue(ACPV);
}
void SuperHConstantPoolConstant::addSelectionDAGCSEId(FoldingSetNodeID &ID) {
@@ -182,31 +174,29 @@ void SuperHConstantPoolConstant::print(raw_ostream &O) const {
SuperHConstantPoolValue::print(O);
}
-
-
-
//===----------------------------------------------------------------------===//
// SuperHConstantPoolSymbol
//===----------------------------------------------------------------------===//
SuperHConstantPoolSymbol::SuperHConstantPoolSymbol(LLVMContext &C, StringRef s,
- unsigned id,
- SHCP::SHCPModifier Modifier)
+ unsigned id,
+ SHCP::SHCPModifier Modifier)
: SuperHConstantPoolValue(C, id, SHCP::CPExtSymbol, Modifier),
S(std::string(s)) {}
-SuperHConstantPoolSymbol *SuperHConstantPoolSymbol::Create(LLVMContext &C,
- StringRef s, unsigned ID) {
+SuperHConstantPoolSymbol *
+SuperHConstantPoolSymbol::Create(LLVMContext &C, StringRef s, unsigned ID) {
return new SuperHConstantPoolSymbol(C, s, ID, SHCP::DIR);
}
int SuperHConstantPoolSymbol::getExistingMachineCPValue(MachineConstantPool *CP,
- Align Alignment) {
+ Align Alignment) {
return getExistingMachineCPValueImpl<SuperHConstantPoolSymbol>(CP, Alignment);
}
bool SuperHConstantPoolSymbol::hasSameValue(SuperHConstantPoolValue *SCPV) {
- const SuperHConstantPoolSymbol *ACPS = dyn_cast<SuperHConstantPoolSymbol>(SCPV);
+ const SuperHConstantPoolSymbol *ACPS =
+ dyn_cast<SuperHConstantPoolSymbol>(SCPV);
return ACPS && ACPS->S == S && SuperHConstantPoolValue::hasSameValue(SCPV);
}
diff --git a/llvm/lib/Target/SuperH/SuperHConstantPoolValue.h b/llvm/lib/Target/SuperH/SuperHConstantPoolValue.h
index 86f718ca3..d5d86e4cf 100644
--- a/llvm/lib/Target/SuperH/SuperHConstantPoolValue.h
+++ b/llvm/lib/Target/SuperH/SuperHConstantPoolValue.h
@@ -29,28 +29,28 @@ class Type;
namespace SHCP {
- enum SHCPKind {
- CPValue,
- CPExtSymbol,
- CPBlockAddress,
- CPMachineBasicBlock,
- CPPromotedGlobal
- };
-
- enum SHCPModifier {
- no_modifier, /// None
- DIR, /// Direct
- GOT_PCREL, /// Global Offset Table, PC Relative
- };
+enum SHCPKind {
+ CPValue,
+ CPExtSymbol,
+ CPBlockAddress,
+ CPMachineBasicBlock,
+ CPPromotedGlobal
+};
+
+enum SHCPModifier {
+ no_modifier, /// None
+ DIR, /// Direct
+ GOT_PCREL, /// Global Offset Table, PC Relative
+};
} // end namespace SHCP
class SuperHConstantPoolValue : public MachineConstantPoolValue {
- unsigned LabelId; // Label id of the load.
- SHCP::SHCPKind Kind; // Kind of constant.
- SHCP::SHCPModifier Modifier; // GV modifier i.e. (&GV(modifier)-(LPIC+8))
+ unsigned LabelId; // Label id of the load.
+ SHCP::SHCPKind Kind; // Kind of constant.
+ SHCP::SHCPModifier Modifier; // GV modifier i.e. (&GV(modifier)-(LPIC+8))
protected:
- SuperHConstantPoolValue(Type *Ty, unsigned id, SHCP::SHCPKind Kind,
+ SuperHConstantPoolValue(Type *Ty, unsigned id, SHCP::SHCPKind Kind,
SHCP::SHCPModifier Modifier);
SuperHConstantPoolValue(LLVMContext &C, unsigned id, SHCP::SHCPKind Kind,
@@ -62,8 +62,8 @@ protected:
for (unsigned i = 0, e = Constants.size(); i != e; ++i) {
if (Constants[i].isMachineConstantPoolEntry() &&
Constants[i].getAlign() >= Alignment) {
- auto *CPV =
- static_cast<SuperHConstantPoolValue*>(Constants[i].Val.MachineCPVal);
+ auto *CPV = static_cast<SuperHConstantPoolValue *>(
+ Constants[i].Val.MachineCPVal);
if (Derived *APC = dyn_cast<Derived>(CPV))
if (cast<Derived>(this)->equals(APC))
return i;
@@ -86,8 +86,8 @@ public:
bool isGlobalValue() const { return Kind == SHCP::CPValue; }
bool isExtSymbol() const { return Kind == SHCP::CPExtSymbol; }
bool isBlockAddress() const { return Kind == SHCP::CPBlockAddress; }
- bool isMachineBasicBlock() const{ return Kind == SHCP::CPMachineBasicBlock; }
- bool isPromotedGlobal() const{ return Kind == SHCP::CPPromotedGlobal; }
+ bool isMachineBasicBlock() const { return Kind == SHCP::CPMachineBasicBlock; }
+ bool isPromotedGlobal() const { return Kind == SHCP::CPPromotedGlobal; }
int getExistingMachineCPValue(MachineConstantPool *CP,
Align Alignment) override;
@@ -99,48 +99,46 @@ public:
virtual bool hasSameValue(SuperHConstantPoolValue *ACPV);
bool equals(const SuperHConstantPoolValue *A) const {
- return this->LabelId == A->LabelId &&
- this->Modifier == A->Modifier;
+ return this->LabelId == A->LabelId && this->Modifier == A->Modifier;
}
void print(raw_ostream &O) const override;
- void print(raw_ostream *O) const { if (O) print(*O); }
+ void print(raw_ostream *O) const {
+ if (O)
+ print(*O);
+ }
void dump() const;
};
-inline raw_ostream &operator<<(raw_ostream &O, const SuperHConstantPoolValue &V) {
+inline raw_ostream &operator<<(raw_ostream &O,
+ const SuperHConstantPoolValue &V) {
V.print(O);
return O;
}
-
-/// SuperHConstantPoolConstant - SuperH-specific constant pool values for Constants,
-/// Functions, and BlockAddresses.
+/// SuperHConstantPoolConstant - SuperH-specific constant pool values for
+/// Constants, Functions, and BlockAddresses.
class SuperHConstantPoolConstant : public SuperHConstantPoolValue {
- const Constant *CVal; // Constant being loaded.
- SmallPtrSet<const GlobalVariable*, 1> GVars;
-
- SuperHConstantPoolConstant(const Constant *C,
- unsigned ID,
- SHCP::SHCPKind Kind,
- SHCP::SHCPModifier Modifier);
- SuperHConstantPoolConstant(Type *Ty, const Constant *C,
- unsigned ID,
- SHCP::SHCPKind Kind,
- SHCP::SHCPModifier Modifier);
+ const Constant *CVal; // Constant being loaded.
+ SmallPtrSet<const GlobalVariable *, 1> GVars;
+
+ SuperHConstantPoolConstant(const Constant *C, unsigned ID,
+ SHCP::SHCPKind Kind, SHCP::SHCPModifier Modifier);
+ SuperHConstantPoolConstant(Type *Ty, const Constant *C, unsigned ID,
+ SHCP::SHCPKind Kind, SHCP::SHCPModifier Modifier);
SuperHConstantPoolConstant(const GlobalVariable *GV, const Constant *Init);
public:
static SuperHConstantPoolConstant *Create(const Constant *C, unsigned ID);
static SuperHConstantPoolConstant *Create(const GlobalValue *GV,
- SHCP::SHCPModifier Modifier);
+ SHCP::SHCPModifier Modifier);
static SuperHConstantPoolConstant *Create(const GlobalVariable *GV,
- const Constant *Initializer);
+ const Constant *Initializer);
static SuperHConstantPoolConstant *Create(const Constant *C, unsigned ID,
- SHCP::SHCPKind Kind);
+ SHCP::SHCPKind Kind);
static SuperHConstantPoolConstant *Create(const Constant *C, unsigned ID,
- SHCP::SHCPKind Kind,
- SHCP::SHCPModifier Modifier);
+ SHCP::SHCPKind Kind,
+ SHCP::SHCPModifier Modifier);
const GlobalValue *getGV() const;
const BlockAddress *getBlockAddress() const;
@@ -149,9 +147,7 @@ public:
iterator_range<promoted_iterator> promotedGlobals() { return GVars; }
- const Constant *getPromotedGlobalInit() const {
- return CVal;
- }
+ const Constant *getPromotedGlobalInit() const { return CVal; }
int getExistingMachineCPValue(MachineConstantPool *CP,
Align Alignment) override;
@@ -174,15 +170,17 @@ public:
}
};
-/// SuperHConstantPoolSymbol - SH-specific constantpool
+/// SuperHConstantPoolSymbol - SH-specific constantpool
/// values for external symbols.
class SuperHConstantPoolSymbol : public SuperHConstantPoolValue {
- const std::string S; // ExtSymbol being loaded.
+ const std::string S; // ExtSymbol being loaded.
- SuperHConstantPoolSymbol(LLVMContext &C, StringRef s, unsigned id, SHCP::SHCPModifier Modifier);
+ SuperHConstantPoolSymbol(LLVMContext &C, StringRef s, unsigned id,
+ SHCP::SHCPModifier Modifier);
public:
- static SuperHConstantPoolSymbol *Create(LLVMContext &C, StringRef s, unsigned ID);
+ static SuperHConstantPoolSymbol *Create(LLVMContext &C, StringRef s,
+ unsigned ID);
StringRef getSymbol() const { return S; }
diff --git a/llvm/lib/Target/SuperH/SuperHExpandPseudoInsts.cpp b/llvm/lib/Target/SuperH/SuperHExpandPseudoInsts.cpp
index 87d2f1453..f83e0f251 100644
--- a/llvm/lib/Target/SuperH/SuperHExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/SuperH/SuperHExpandPseudoInsts.cpp
@@ -12,12 +12,12 @@
//
//===----------------------------------------------------------------------===//
+#include "MCTargetDesc/SuperHMCTargetDesc.h"
#include "SuperH.h"
#include "SuperHInstrInfo.h"
#include "SuperHMachineFunctionInfo.h"
#include "SuperHSubtarget.h"
#include "SuperHTargetMachine.h"
-#include "MCTargetDesc/SuperHMCTargetDesc.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -32,11 +32,11 @@ using namespace llvm;
#ifndef NDEBUG
static cl::opt<bool>
-CNoExpand("sh-no-expand", cl::Hidden, cl::init(false),
- cl::desc("Force the backend to not expand instructions."));
+ CNoExpand("sh-no-expand", cl::Hidden, cl::init(false),
+ cl::desc("Force the backend to not expand instructions."));
static cl::opt<bool>
-CKeepPseudo("sh-keep-pseudo", cl::Hidden, cl::init(false),
- cl::desc("Force the backend to keep pseudos around."));
+ CKeepPseudo("sh-keep-pseudo", cl::Hidden, cl::init(false),
+ cl::desc("Force the backend to keep pseudos around."));
#endif
namespace {
@@ -67,24 +67,21 @@ private:
bool loadFromGlobal(Block &MBB, BlockIt MBBI);
};
-
-
-
//===----------------------------------------------------------------------===//
// Helpers
//===----------------------------------------------------------------------===//
// getOffsetForStackOffset - Calculates how much to offset the stack pointer for
// the indirect load/store to be in range.
-static int64_t getOffsetForStackOffset(const MachineFunction &MF,
- uint8_t Bits, uint8_t Scale = 1) {
+static int64_t getOffsetForStackOffset(const MachineFunction &MF, uint8_t Bits,
+ uint8_t Scale = 1) {
const MachineFrameInfo &MFI = MF.getFrameInfo();
-
+
// The base value range for the instruction.
- int64_t BM = ((1<<Bits)-1)*Scale;
+ int64_t BM = ((1 << Bits) - 1) * Scale;
int64_t StackSize = MFI.getStackSize();
- int64_t Slot = StackSize/BM;
- return alignTo((BM*Slot)+(StackSize%BM), Scale);
+ int64_t Slot = StackSize / BM;
+ return alignTo((BM * Slot) + (StackSize % BM), Scale);
}
// eraseMI - Helper that erases a machine instruction while respecting
@@ -95,14 +92,11 @@ static bool eraseMI(MachineInstr &MI) {
if (CKeepPseudo)
return false;
#endif
-
+
MI.eraseFromParent();
return true;
}
-
-
-
//===----------------------------------------------------------------------===//
// Frame Stores
//===----------------------------------------------------------------------===//
@@ -121,23 +115,23 @@ bool SuperHExpandPseudo::storeToFrame(Block &MBB, BlockIt MBBI, int Scale) {
// Expand sequence to
// mov <frame reg>, r1
// add #-SpOffset, r1
- BuildMI(MBB, MBBI, DL, TII->get(SH::MOV), SH::R1)
- .addReg(FrameReg);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::MOV), SH::R1).addReg(FrameReg);
BuildMI(MBB, MBBI, DL, TII->get(SH::ADDI), SH::R1)
- .addReg(SH::R1)
- .addImm(-SpOffset);
+ .addReg(SH::R1)
+ .addImm(-SpOffset);
- switch(MI.getOpcode()) {
- default: llvm_unreachable("Expected valid MOV*SPtr opcode.");
+ switch (MI.getOpcode()) {
+ default:
+ llvm_unreachable("Expected valid MOV*SPtr opcode.");
case SH::MOVBSPtr: {
// mov <src reg>, r0
// mov.b r0, @(offset,r1)
BuildMI(MBB, MBBI, DL, TII->get(SH::MOV), SH::R0)
- .addReg(SrcReg, getKillRegState(SrcIsKill));
+ .addReg(SrcReg, getKillRegState(SrcIsKill));
BuildMI(MBB, MBBI, DL, TII->get(SH::MOVBS4))
- .addReg(SH::R1, RegState::Kill)
- .addImm(Offset);
+ .addReg(SH::R1, RegState::Kill)
+ .addImm(Offset);
break;
}
case SH::MOVWSPtr: {
@@ -145,19 +139,19 @@ bool SuperHExpandPseudo::storeToFrame(Block &MBB, BlockIt MBBI, int Scale) {
// mov <src reg>, r0
// mov.w r0, @(offset,r1)
BuildMI(MBB, MBBI, DL, TII->get(SH::MOV), SH::R0)
- .addReg(SrcReg, getKillRegState(SrcIsKill));
+ .addReg(SrcReg, getKillRegState(SrcIsKill));
BuildMI(MBB, MBBI, DL, TII->get(SH::MOVWS4))
- .addReg(SH::R1, RegState::Kill)
- .addImm(Offset);
+ .addReg(SH::R1, RegState::Kill)
+ .addImm(Offset);
break;
}
case SH::MOVLSPtr: {
// mov.b <src reg>, @(offset,r1)
BuildMI(MBB, MBBI, DL, TII->get(SH::MOVLS4))
- .addReg(SrcReg, getKillRegState(SrcIsKill))
- .addReg(SH::R1, RegState::Kill)
- .addImm(Offset);
+ .addReg(SrcReg, getKillRegState(SrcIsKill))
+ .addReg(SH::R1, RegState::Kill)
+ .addImm(Offset);
break;
}
}
@@ -177,30 +171,25 @@ bool SuperHExpandPseudo::storeToGlobal(Block &MBB, BlockIt MBBI) {
return false;
BuildMI(MBB, MBBI, DL, TII->get(SH::MOVLI), SH::R1)
- .addConstantPoolIndex(G->getLabelId());
+ .addConstantPoolIndex(G->getLabelId());
- switch(MI.getOpcode()) {
- default: llvm_unreachable("Expected valid MOV*SPtr opcode.");
+ switch (MI.getOpcode()) {
+ default:
+ llvm_unreachable("Expected valid MOV*SPtr opcode.");
case SH::MOVBSPtr: {
- BuildMI(MBB, MBBI, DL, TII->get(SH::MOVBS))
- .addReg(SrcReg)
- .addReg(SH::R1);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::MOVBS)).addReg(SrcReg).addReg(SH::R1);
break;
}
case SH::MOVWSPtr: {
- BuildMI(MBB, MBBI, DL, TII->get(SH::MOVWS))
- .addReg(SrcReg)
- .addReg(SH::R1);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::MOVWS)).addReg(SrcReg).addReg(SH::R1);
break;
}
case SH::MOVLSPtr: {
- BuildMI(MBB, MBBI, DL, TII->get(SH::MOVLS))
- .addReg(SrcReg)
- .addReg(SH::R1);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::MOVLS)).addReg(SrcReg).addReg(SH::R1);
break;
}
}
-
+
return eraseMI(MI);
}
@@ -240,9 +229,6 @@ bool SuperHExpandPseudo::expand<SH::MOVLSPtr>(Block &MBB, BlockIt MBBI) {
return storeToFrame(MBB, MBBI, 4);
}
-
-
-
//===----------------------------------------------------------------------===//
// Frame Loads
//===----------------------------------------------------------------------===//
@@ -261,50 +247,48 @@ bool SuperHExpandPseudo::loadFromFrame(Block &MBB, BlockIt MBBI, int Scale) {
// Expand sequence to
// mov <frame reg>, r1
// add #-SpOffset, r1
- BuildMI(MBB, MBBI, DL, TII->get(SH::MOV), SH::R1)
- .addReg(FrameReg);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::MOV), SH::R1).addReg(FrameReg);
BuildMI(MBB, MBBI, DL, TII->get(SH::ADDI), SH::R1)
- .addReg(SH::R1)
- .addImm(-SpOffset);
+ .addReg(SH::R1)
+ .addImm(-SpOffset);
- switch(MI.getOpcode()) {
- default: llvm_unreachable("Expected valid MOV*LPtr opcode.");
+ switch (MI.getOpcode()) {
+ default:
+ llvm_unreachable("Expected valid MOV*LPtr opcode.");
case SH::MOVBLPtr: {
// mov.w @(offset,r1), r0
// mov r0, <dst reg>
BuildMI(MBB, MBBI, DL, TII->get(SH::MOVBL4))
- .addReg(SH::R1)
- .addImm(Offset)
- .addReg(SH::R0, RegState::Define);
+ .addReg(SH::R1)
+ .addImm(Offset)
+ .addReg(SH::R0, RegState::Define);
BuildMI(MBB, MBBI, DL, TII->get(SH::MOV))
- .addReg(DstReg, getKillRegState(DstIsKill))
- .addReg(SH::R0, RegState::Kill);
+ .addReg(DstReg, getKillRegState(DstIsKill))
+ .addReg(SH::R0, RegState::Kill);
break;
}
case SH::MOVWLPtr: {
// mov.b @(offset,r1), r0
// mov r0, <dst reg>
- BuildMI(MBB, MBBI, DL, TII->get(SH::MOVWL4))
- .addReg(SH::R1)
- .addImm(Offset);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::MOVWL4)).addReg(SH::R1).addImm(Offset);
BuildMI(MBB, MBBI, DL, TII->get(SH::MOV))
- .addReg(DstReg, getKillRegState(DstIsKill))
- .addReg(SH::R0, RegState::Define);
+ .addReg(DstReg, getKillRegState(DstIsKill))
+ .addReg(SH::R0, RegState::Define);
break;
}
case SH::MOVLLPtr: {
// mov.l @(offset,r1), <dst reg>
BuildMI(MBB, MBBI, DL, TII->get(SH::MOVLL4))
- .addReg(DstReg, getKillRegState(DstIsKill))
- .addReg(SH::R1)
- .addImm(Offset);
+ .addReg(DstReg, getKillRegState(DstIsKill))
+ .addReg(SH::R1)
+ .addImm(Offset);
break;
}
}
-
+
return eraseMI(MI);
}
@@ -321,27 +305,25 @@ bool SuperHExpandPseudo::loadFromGlobal(Block &MBB, BlockIt MBBI) {
return false;
BuildMI(MBB, MBBI, DL, TII->get(SH::MOVLI), SH::R1)
- .addConstantPoolIndex(G->getLabelId());
+ .addConstantPoolIndex(G->getLabelId());
- switch(MI.getOpcode()) {
- default: llvm_unreachable("Expected valid MOV*LPtr opcode.");
+ switch (MI.getOpcode()) {
+ default:
+ llvm_unreachable("Expected valid MOV*LPtr opcode.");
case SH::MOVBLPtr: {
- BuildMI(MBB, MBBI, DL, TII->get(SH::MOVBL), DstReg)
- .addReg(SH::R1);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::MOVBL), DstReg).addReg(SH::R1);
break;
}
case SH::MOVWLPtr: {
- BuildMI(MBB, MBBI, DL, TII->get(SH::MOVWL), DstReg)
- .addReg(SH::R1);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::MOVWL), DstReg).addReg(SH::R1);
break;
}
case SH::MOVLLPtr: {
- BuildMI(MBB, MBBI, DL, TII->get(SH::MOVLL), DstReg)
- .addReg(SH::R1);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::MOVLL), DstReg).addReg(SH::R1);
break;
}
}
-
+
return eraseMI(MI);
}
@@ -378,9 +360,6 @@ bool SuperHExpandPseudo::expand<SH::MOVLLPtr>(Block &MBB, BlockIt MBBI) {
return loadFromFrame(MBB, MBBI, 4);
}
-
-
-
//===----------------------------------------------------------------------===//
// Bit Shifting
//===----------------------------------------------------------------------===//
@@ -396,38 +375,34 @@ bool SuperHExpandPseudo::expand<SH::SHLri>(Block &MBB, BlockIt MBBI) {
auto SrcReg = MI.getOperand(1).getReg();
int64_t Offset = MI.getOperand(2).getImm();
- while(Offset > 0) {
+ while (Offset > 0) {
if (Offset > 16) {
- BuildMI(MBB, MBBI, DL, TII->get(SH::SHLL16), DstReg)
- .addReg(SrcReg);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::SHLL16), DstReg).addReg(SrcReg);
Offset -= 16;
continue;
}
if (Offset > 8) {
- BuildMI(MBB, MBBI, DL, TII->get(SH::SHLL8), DstReg)
- .addReg(SrcReg);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::SHLL8), DstReg).addReg(SrcReg);
Offset -= 8;
continue;
}
if (Offset > 2) {
- BuildMI(MBB, MBBI, DL, TII->get(SH::SHLL2), DstReg)
- .addReg(SrcReg);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::SHLL2), DstReg).addReg(SrcReg);
Offset -= 2;
continue;
}
- BuildMI(MBB, MBBI, DL, TII->get(SH::SHLL), DstReg)
- .addReg(SrcReg);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::SHLL), DstReg).addReg(SrcReg);
Offset -= 1;
continue;
}
-
+
return eraseMI(MI);
}
@@ -442,38 +417,34 @@ bool SuperHExpandPseudo::expand<SH::SHRri>(Block &MBB, BlockIt MBBI) {
auto SrcReg = MI.getOperand(1).getReg();
int64_t Offset = MI.getOperand(2).getImm();
- while(Offset > 0) {
-
+ while (Offset > 0) {
+
if (Offset > 16) {
- BuildMI(MBB, MBBI, DL, TII->get(SH::SHLR16), DstReg)
- .addReg(SrcReg);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::SHLR16), DstReg).addReg(SrcReg);
Offset -= 16;
continue;
}
if (Offset > 8) {
- BuildMI(MBB, MBBI, DL, TII->get(SH::SHLR8), DstReg)
- .addReg(SrcReg);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::SHLR8), DstReg).addReg(SrcReg);
Offset -= 8;
continue;
}
if (Offset > 2) {
- BuildMI(MBB, MBBI, DL, TII->get(SH::SHLR2), DstReg)
- .addReg(SrcReg);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::SHLR2), DstReg).addReg(SrcReg);
Offset -= 2;
continue;
}
- BuildMI(MBB, MBBI, DL, TII->get(SH::SHLR), DstReg)
- .addReg(SrcReg);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::SHLR), DstReg).addReg(SrcReg);
Offset -= 1;
continue;
}
-
+
return eraseMI(MI);
}
@@ -488,12 +459,11 @@ bool SuperHExpandPseudo::expand<SH::SRAri>(Block &MBB, BlockIt MBBI) {
auto SrcReg = MI.getOperand(1).getReg();
int64_t Offset = MI.getOperand(2).getImm();
- while(Offset > 0) {
- BuildMI(MBB, MBBI, DL, TII->get(SH::SHAR), DstReg)
- .addReg(SrcReg);
+ while (Offset > 0) {
+ BuildMI(MBB, MBBI, DL, TII->get(SH::SHAR), DstReg).addReg(SrcReg);
Offset -= 1;
}
-
+
return eraseMI(MI);
}
@@ -505,12 +475,9 @@ bool SuperHExpandPseudo::expand<SH::SHLrr>(Block &MBB, BlockIt MBBI) {
auto Src1Reg = MI.getOperand(1).getReg();
auto Src2Reg = MI.getOperand(2).getReg();
- BuildMI(MBB, MBBI, DL, TII->get(SH::SHLL))
- .addReg(Src1Reg);
- BuildMI(MBB, MBBI, DL, TII->get(SH::DT))
- .addReg(Src2Reg);
- BuildMI(MBB, MBBI, DL, TII->get(SH::BF))
- .addImm(-4);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::SHLL)).addReg(Src1Reg);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::DT)).addReg(Src2Reg);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::BF)).addImm(-4);
return eraseMI(MI);
}
@@ -523,12 +490,9 @@ bool SuperHExpandPseudo::expand<SH::SHRrr>(Block &MBB, BlockIt MBBI) {
auto Src1Reg = MI.getOperand(1).getReg();
auto Src2Reg = MI.getOperand(2).getReg();
- BuildMI(MBB, MBBI, DL, TII->get(SH::SHLR))
- .addReg(Src1Reg);
- BuildMI(MBB, MBBI, DL, TII->get(SH::DT))
- .addReg(Src2Reg);
- BuildMI(MBB, MBBI, DL, TII->get(SH::BF))
- .addImm(-4);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::SHLR)).addReg(Src1Reg);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::DT)).addReg(Src2Reg);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::BF)).addImm(-4);
return eraseMI(MI);
}
@@ -541,19 +505,13 @@ bool SuperHExpandPseudo::expand<SH::SRArr>(Block &MBB, BlockIt MBBI) {
auto Src1Reg = MI.getOperand(1).getReg();
auto Src2Reg = MI.getOperand(2).getReg();
- BuildMI(MBB, MBBI, DL, TII->get(SH::SHAR))
- .addReg(Src1Reg);
- BuildMI(MBB, MBBI, DL, TII->get(SH::DT))
- .addReg(Src2Reg);
- BuildMI(MBB, MBBI, DL, TII->get(SH::BF))
- .addImm(-4);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::SHAR)).addReg(Src1Reg);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::DT)).addReg(Src2Reg);
+ BuildMI(MBB, MBBI, DL, TII->get(SH::BF)).addImm(-4);
return eraseMI(MI);
}
-
-
-
//===----------------------------------------------------------------------===//
// Conditional Branching
//===----------------------------------------------------------------------===//
@@ -566,9 +524,6 @@ bool SuperHExpandPseudo::expand<SH::BRCC>(Block &MBB, BlockIt MBBI) {
return eraseMI(MI);
}
-
-
-
//===----------------------------------------------------------------------===//
// General Interface
//===----------------------------------------------------------------------===//
@@ -590,10 +545,10 @@ bool SuperHExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
LLVM_DEBUG(dbgs() << "\n********** SuperHExpandPseudo **********\n");
bool Modified = false;
- #ifndef NDEBUG
+#ifndef NDEBUG
if (CNoExpand)
return false;
- #endif
+#endif
const SuperHSubtarget &STI = MF.getSubtarget<SuperHSubtarget>();
TRI = STI.getRegisterInfo();
@@ -627,20 +582,21 @@ bool SuperHExpandPseudo::expandMI(Block &MBB, BlockIt MBBI) {
case Op: \
return expand<Op>(MBB, MI)
- switch(Opcode) {
- default: break;
- EXPAND(SH::MOVBSPtr);
- EXPAND(SH::MOVWSPtr);
- EXPAND(SH::MOVLSPtr);
- EXPAND(SH::MOVBLPtr);
- EXPAND(SH::MOVWLPtr);
- EXPAND(SH::MOVLLPtr);
- EXPAND(SH::SHLri);
- EXPAND(SH::SHRri);
- EXPAND(SH::SRAri);
- EXPAND(SH::SHLrr);
- EXPAND(SH::SHRrr);
- EXPAND(SH::SRArr);
+ switch (Opcode) {
+ default:
+ break;
+ EXPAND(SH::MOVBSPtr);
+ EXPAND(SH::MOVWSPtr);
+ EXPAND(SH::MOVLSPtr);
+ EXPAND(SH::MOVBLPtr);
+ EXPAND(SH::MOVWLPtr);
+ EXPAND(SH::MOVLLPtr);
+ EXPAND(SH::SHLri);
+ EXPAND(SH::SHRri);
+ EXPAND(SH::SRAri);
+ EXPAND(SH::SHLrr);
+ EXPAND(SH::SHRrr);
+ EXPAND(SH::SRArr);
}
#undef EXPAND
return false;
@@ -650,7 +606,6 @@ char SuperHExpandPseudo::ID = 0;
} // namespace
-
INITIALIZE_PASS(SuperHExpandPseudo, "sh-expand-pseudo", SH_EXPAND_PSEUDO_NAME,
false, false)
diff --git a/llvm/lib/Target/SuperH/SuperHFillDelaySlots.cpp b/llvm/lib/Target/SuperH/SuperHFillDelaySlots.cpp
index a35a0a82e..ab0e98f2c 100644
--- a/llvm/lib/Target/SuperH/SuperHFillDelaySlots.cpp
+++ b/llvm/lib/Target/SuperH/SuperHFillDelaySlots.cpp
@@ -10,10 +10,10 @@
//
//===----------------------------------------------------------------------===//
+#include "MCTargetDesc/SuperHMCTargetDesc.h"
#include "SuperH.h"
#include "SuperHInstrInfo.h"
#include "SuperHTargetMachine.h"
-#include "MCTargetDesc/SuperHMCTargetDesc.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
@@ -37,7 +37,9 @@ public:
bool runOnMachineFunction(MachineFunction &MF) override;
- StringRef getPassName() const override { return SUPERH_FILL_DELAY_SLOTS_NAME; }
+ StringRef getPassName() const override {
+ return SUPERH_FILL_DELAY_SLOTS_NAME;
+ }
private:
typedef MachineBasicBlock Block;
@@ -57,16 +59,14 @@ private:
} // end namespace
-
-
-
//===----------------------------------------------------------------------===//
// Expansions
//===----------------------------------------------------------------------===//
// Walks backwards through the basic block to find a candidate that is eligible
// for filling delay slots.
-MachineInstr *SuperHFillDelaySlots::findSlotCandidate(Block &MBB, BlockIt MBBI) {
+MachineInstr *SuperHFillDelaySlots::findSlotCandidate(Block &MBB,
+ BlockIt MBBI) {
MachineInstr &MI = *MBBI;
auto *Prev = MBBI->getPrevNode();
@@ -77,7 +77,8 @@ MachineInstr *SuperHFillDelaySlots::findSlotCandidate(Block &MBB, BlockIt MBBI)
// // We might have a useful instruction above the instruction that
// // loads our destination address.
// if (MI.isCall() && Prev) {
- // if (!Prev->getPrevNode()->definesRegister(MI.getOperand(0).getReg(), TRI))
+ // if (!Prev->getPrevNode()->definesRegister(MI.getOperand(0).getReg(),
+ // TRI))
// Prev = Prev->getPrevNode();
// }
@@ -88,13 +89,13 @@ MachineInstr *SuperHFillDelaySlots::findSlotCandidate(Block &MBB, BlockIt MBBI)
// If we encounter a branch instruction, then it's no longer safe to
// move the instruction down.
- if (Prev->isBranch() || Prev->isCall() || Prev->isReturn())
+ if (Prev->isBranch() || Prev->isCall() || Prev->isReturn())
return nullptr;
// NOTE: RTS has an extra constraint that it cannot have
// lds @r15+,PR or equivalent in its delay slot.
if (MI.isReturn()) {
-
+
// Skip the LDS instruction.
if (Opcode == SH::LDSPR || Opcode == SH::LDSMPR)
return nullptr;
@@ -102,7 +103,7 @@ MachineInstr *SuperHFillDelaySlots::findSlotCandidate(Block &MBB, BlockIt MBBI)
// NOTE: Conditional branches can't have their condition code set
// in the delay slot. As such, if the previous instruction
- // implicitly defines the status register, assume that the
+ // implicitly defines the status register, assume that the
// T bit was set.
if (MI.isConditionalBranch()) {
if (Prev->definesRegister(SH::SR, TRI))
@@ -126,25 +127,23 @@ bool SuperHFillDelaySlots::fillDelaySlot(Block &MBB, BlockIt MBBI) {
MachineInstr &MI = *MBBI;
if (auto *Candidate = findSlotCandidate(MBB, MBBI)) {
- LLVM_DEBUG(dbgs() << "Swapping " << TII->getName(MI.getOpcode())
- << " and " << TII->getName(Candidate->getOpcode())
- << " @ " << MBB.getParent()->getName() << "\n");
+ LLVM_DEBUG(dbgs() << "Swapping " << TII->getName(MI.getOpcode()) << " and "
+ << TII->getName(Candidate->getOpcode()) << " @ "
+ << MBB.getParent()->getName() << "\n");
- MBB.insertAfter(MBBI, Candidate->removeFromParent());
- return true;
+ MBB.insertAfter(MBBI, Candidate->removeFromParent());
+ return true;
}
LLVM_DEBUG(dbgs() << "Inserting NOP after " << TII->getName(MI.getOpcode())
<< " @ " << MBB.getParent()->getName() << "\n");
// Otherwise just insert a NOP.
- MBB.insertAfter(MBBI, MF.CreateMachineInstr(TII->get(SH::NOP), MI.getDebugLoc()));
+ MBB.insertAfter(MBBI,
+ MF.CreateMachineInstr(TII->get(SH::NOP), MI.getDebugLoc()));
return true;
}
-
-
-
//===----------------------------------------------------------------------===//
// Helpers
//===----------------------------------------------------------------------===//
@@ -188,11 +187,10 @@ bool SuperHFillDelaySlots::runOnMachineFunction(MachineFunction &MF) {
return Modified;
}
-
char SuperHFillDelaySlots::ID = 0;
-INITIALIZE_PASS(SuperHFillDelaySlots, "sh-fill-delay-slots", SUPERH_FILL_DELAY_SLOTS_NAME,
- false, false)
+INITIALIZE_PASS(SuperHFillDelaySlots, "sh-fill-delay-slots",
+ SUPERH_FILL_DELAY_SLOTS_NAME, false, false)
FunctionPass *llvm::createSuperHFillDelaySlotsPass() {
return new SuperHFillDelaySlots();
diff --git a/llvm/lib/Target/SuperH/SuperHFrameLowering.cpp b/llvm/lib/Target/SuperH/SuperHFrameLowering.cpp
index d275c4005..0e7c2c424 100644
--- a/llvm/lib/Target/SuperH/SuperHFrameLowering.cpp
+++ b/llvm/lib/Target/SuperH/SuperHFrameLowering.cpp
@@ -11,7 +11,6 @@
//
//===----------------------------------------------------------------------===//
-
#include "SuperHFrameLowering.h"
#include "MCTargetDesc/SuperHMCTargetDesc.h"
#include "SuperHInstrInfo.h"
@@ -39,15 +38,12 @@
#define DEBUG_TYPE "sh-framelowering"
-static cl::opt<bool>
-AccumOutgoingArgs("sh-accumulate-outgoing-args", cl::Hidden, cl::init(false),
- cl::desc("Reserve space for outgoing arguments in the function prologue."));
+static cl::opt<bool> AccumOutgoingArgs(
+ "sh-accumulate-outgoing-args", cl::Hidden, cl::init(false),
+ cl::desc("Reserve space for outgoing arguments in the function prologue."));
using namespace llvm;
-
-
-
//===--------------------------------------------------------------------------===//
// Helpers
//===--------------------------------------------------------------------------===//
@@ -56,20 +52,24 @@ using namespace llvm;
// for it to fit.
static unsigned getShiftAmt(uint32_t Val) {
unsigned R = 0;
- for(unsigned i = 0; i < 4; i++) {
- if (((Val >> (i*8)) & 0xFF))
+ for (unsigned i = 0; i < 4; i++) {
+ if (((Val >> (i * 8)) & 0xFF))
R = i;
}
return R;
}
// Helper to emit stack pointer adjustment.
-void SuperHFrameLowering::emitFrameAdjust(Register Base, MachineFunction &MF, MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, int32_t AdjValue) const {
- const SuperHInstrInfo &TII = *static_cast<const SuperHInstrInfo *>(MF.getSubtarget().getInstrInfo());
- MachineInstr::MIFlag MFlag = AdjValue < 0 ? MachineInstr::FrameSetup : MachineInstr::FrameDestroy;
+void SuperHFrameLowering::emitFrameAdjust(Register Base, MachineFunction &MF,
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ int32_t AdjValue) const {
+ const SuperHInstrInfo &TII =
+ *static_cast<const SuperHInstrInfo *>(MF.getSubtarget().getInstrInfo());
+ MachineInstr::MIFlag MFlag =
+ AdjValue < 0 ? MachineInstr::FrameSetup : MachineInstr::FrameDestroy;
DebugLoc DL = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
-
+
// No stack frame allocation neccesary.
if (AdjValue == 0)
return;
@@ -79,8 +79,8 @@ void SuperHFrameLowering::emitFrameAdjust(Register Base, MachineFunction &MF, Ma
// Fast path, emit a single immediate add.
BuildMI(MBB, MBBI, DL, TII.get(SH::ADDI), Base)
- .addReg(Base)
- .addImm(AdjValue);
+ .addReg(Base)
+ .addImm(AdjValue);
return;
}
@@ -91,19 +91,19 @@ void SuperHFrameLowering::emitFrameAdjust(Register Base, MachineFunction &MF, Ma
// Empty R0 in case it had something.
BuildMI(MBB, MBBI, DL, TII.get(SH::XOR), SH::R0)
- .addReg(SH::R0)
- .setMIFlag(MFlag);
+ .addReg(SH::R0)
+ .setMIFlag(MFlag);
// Shift value in with the following pattern:
// or #(byte), r0
// shll8 r0
- for(unsigned i = 0; i < ToShift; i++) {
+ for (unsigned i = 0; i < ToShift; i++) {
BuildMI(MBB, MBBI, DL, TII.get(SH::ORI))
- .addImm((AdjValue >> (i*8)) & 0xFF)
- .setMIFlag(MFlag);
+ .addImm((AdjValue >> (i * 8)) & 0xFF)
+ .setMIFlag(MFlag);
BuildMI(MBB, MBBI, DL, TII.get(SH::SHLL8), SH::R0)
- .addReg(SH::R0)
- .setMIFlag(MFlag);
+ .addReg(SH::R0)
+ .setMIFlag(MFlag);
}
// Finally negate and add to r15.
@@ -111,26 +111,23 @@ void SuperHFrameLowering::emitFrameAdjust(Register Base, MachineFunction &MF, Ma
// add r0, <base>
if (AdjValue < 0)
BuildMI(MBB, MBBI, DL, TII.get(SH::NEG), SH::R0)
- .addReg(SH::R0)
- .addReg(SH::R0)
- .setMIFlag(MFlag);
+ .addReg(SH::R0)
+ .addReg(SH::R0)
+ .setMIFlag(MFlag);
BuildMI(MBB, MBBI, DL, TII.get(SH::SUB), Base)
- .addReg(SH::R0, RegState::Kill)
- .addReg(Base)
- .setMIFlag(MFlag);
+ .addReg(SH::R0, RegState::Kill)
+ .addReg(Base)
+ .setMIFlag(MFlag);
}
-
-
-
//===--------------------------------------------------------------------------===//
// Call-Frame Objects
//===--------------------------------------------------------------------------===//
StackOffset
SuperHFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
- Register &FrameReg) const {
+ Register &FrameReg) const {
const SuperHSubtarget &Subtarget = MF.getSubtarget<SuperHSubtarget>();
const SuperHRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
const MachineFrameInfo &MFI = MF.getFrameInfo();
@@ -153,14 +150,12 @@ SuperHFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
return StackOffset::getFixed(-FrameOffset);
}
-
-
-
//===--------------------------------------------------------------------------===//
// Prologue/Epilogue Emission
//===--------------------------------------------------------------------------===//
-void SuperHFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const {
+void SuperHFrameLowering::emitPrologue(MachineFunction &MF,
+ MachineBasicBlock &MBB) const {
LLVM_DEBUG(dbgs() << "Emitting prologue for " << MF.getName() << "...\n");
MachineBasicBlock::iterator MBBI = MBB.begin();
@@ -185,23 +180,23 @@ void SuperHFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &M
// Store previous frame pointer.
if (HasFP) {
BuildMI(MBB, MBBI, DL, TII.get(SH::MOVLM), FP)
- .addReg(SP)
- .setMIFlag(MachineInstr::FrameSetup);
+ .addReg(SP)
+ .setMIFlag(MachineInstr::FrameSetup);
}
// Store Return address on stack (if needed)
if (MFI.hasCalls()) {
BuildMI(MBB, MBBI, DL, TII.get(SH::STSMPR))
- .addReg(SP)
- .setMIFlag(MachineInstr::FrameSetup);
+ .addReg(SP)
+ .setMIFlag(MachineInstr::FrameSetup);
}
// Create new stack frame.
emitFrameAdjust(SP, MF, MBB, MBBI, -StackSize);
if (HasFP) {
BuildMI(MBB, MBBI, DL, TII.get(SH::MOV), FP)
- .addReg(SP)
- .setMIFlag(MachineInstr::FrameSetup);
+ .addReg(SP)
+ .setMIFlag(MachineInstr::FrameSetup);
}
// // Store GOT
@@ -214,7 +209,8 @@ void SuperHFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &M
// }
}
-void SuperHFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
+void SuperHFrameLowering::emitEpilogue(MachineFunction &MF,
+ MachineBasicBlock &MBB) const {
LLVM_DEBUG(dbgs() << "Emitting epilogue for " << MF.getName() << "...\n");
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
@@ -227,7 +223,6 @@ void SuperHFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &M
DebugLoc DL = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
bool HasFP = hasFP(MF);
-
// Get stack frame size.
int64_t StackSize = MFI.getStackSize();
@@ -235,44 +230,43 @@ void SuperHFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &M
if (HasFP) {
emitFrameAdjust(FP, MF, MBB, MBBI, StackSize);
BuildMI(MBB, MBBI, DL, TII.get(SH::MOV), SP)
- .addReg(FP)
- .setMIFlag(MachineInstr::FrameSetup);
+ .addReg(FP)
+ .setMIFlag(MachineInstr::FrameSetup);
} else {
emitFrameAdjust(SP, MF, MBB, MBBI, StackSize);
}
// Restore return address from stack (if needed.)
- if (MFI.hasCalls()) {
+ if (MFI.hasCalls()) {
BuildMI(MBB, MBBI, DL, TII.get(SH::LDSMPR))
- .addReg(SP)
- .setMIFlag(MachineInstr::FrameDestroy);
+ .addReg(SP)
+ .setMIFlag(MachineInstr::FrameDestroy);
}
// Restore stack pointer
if (HasFP) {
BuildMI(MBB, MBBI, DL, TII.get(SH::MOVLP), FP)
- .addReg(SP)
- .setMIFlag(MachineInstr::FrameDestroy);
+ .addReg(SP)
+ .setMIFlag(MachineInstr::FrameDestroy);
}
// TODO: Handle GOT
}
-
-
-
//===--------------------------------------------------------------------------===//
// Callee-Saves
//===--------------------------------------------------------------------------===//
-void SuperHFrameLowering::determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
- RegScavenger *RS) const {
+void SuperHFrameLowering::determineCalleeSaves(MachineFunction &MF,
+ BitVector &SavedRegs,
+ RegScavenger *RS) const {
TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
}
-bool SuperHFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
- ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
-
+bool SuperHFrameLowering::spillCalleeSavedRegisters(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+ ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
+
LLVM_DEBUG(dbgs() << "Spilling " << CSI.size() << " registers...\n");
if (CSI.empty()) {
return false;
@@ -283,17 +277,19 @@ bool SuperHFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, Mach
const SuperHSubtarget &STI = MF.getSubtarget<SuperHSubtarget>();
const TargetInstrInfo &TII = *STI.getInstrInfo();
for (const CalleeSavedInfo &I : reverse(CSI)) {
- TII.storeRegToStackSlot(MBB, MI, I.getReg(), true, I.getFrameIdx(), &SH::GPRRegClass, 0);
+ TII.storeRegToStackSlot(MBB, MI, I.getReg(), true, I.getFrameIdx(),
+ &SH::GPRRegClass, 0);
}
return true;
}
-bool SuperHFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator II,
- MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
-
+bool SuperHFrameLowering::restoreCalleeSavedRegisters(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator II,
+ MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
+
LLVM_DEBUG(dbgs() << "Restoring " << CSI.size() << " registers...\n");
if (CSI.empty()) {
- return false;
+ return false;
}
DebugLoc DL = MBB.findDebugLoc(II);
@@ -301,23 +297,20 @@ bool SuperHFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, Ma
const SuperHSubtarget &STI = MF.getSubtarget<SuperHSubtarget>();
const TargetInstrInfo &TII = *STI.getInstrInfo();
for (const CalleeSavedInfo &I : CSI) {
- TII.loadRegFromStackSlot(MBB, II, I.getReg(), I.getFrameIdx(), &SH::GPRRegClass, 0);
+ TII.loadRegFromStackSlot(MBB, II, I.getReg(), I.getFrameIdx(),
+ &SH::GPRRegClass, 0);
}
return true;
}
-
-
-
//===--------------------------------------------------------------------------===//
// Call-Frame Meta
//===--------------------------------------------------------------------------===//
-MachineBasicBlock::iterator
-SuperHFrameLowering::eliminateCallFramePseudoInstr(MachineFunction &MF,
- MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI) const {
+MachineBasicBlock::iterator SuperHFrameLowering::eliminateCallFramePseudoInstr(
+ MachineFunction &MF, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI) const {
const SuperHSubtarget &STI = MF.getSubtarget<SuperHSubtarget>();
const SuperHInstrInfo &TII = *STI.getInstrInfo();
@@ -344,17 +337,16 @@ bool SuperHFrameLowering::canSimplifyCallFramePseudos(
bool SuperHFrameLowering::hasFPImpl(const MachineFunction &MF) const {
const MachineFrameInfo &MFI = MF.getFrameInfo();
- return MF.disableFramePointerElim() ||
- MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();
+ return MF.disableFramePointerElim() || MFI.hasVarSizedObjects() ||
+ MFI.isFrameAddressTaken();
}
-bool SuperHFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
+bool SuperHFrameLowering::hasReservedCallFrame(
+ const MachineFunction &MF) const {
const MachineFrameInfo &MFI = MF.getFrameInfo();
return hasFP(MF) && !MFI.hasVarSizedObjects();
}
-
-
//===--------------------------------------------------------------------------===//
//===--------------------------------------------------------------------------===//
// Frame Load-Store Fixup Pass
@@ -379,8 +371,8 @@ public:
SuperHFrameFixupPass() : MachineFunctionPass(ID) {}
- // Fixes up JSR instructions so that their return values don't
- // get clobbered by the implicit uses of R0 and R1 done by stack
+ // Fixes up JSR instructions so that their return values don't
+ // get clobbered by the implicit uses of R0 and R1 done by stack
// loads.
bool fixupJSR(Block MBB, BlockIt MBII) {
LLVM_DEBUG(dbgs() << " - Fixing up JSR instruction...\n");
@@ -391,7 +383,7 @@ public:
while (II != E) {
BlockIt NII = std::next(II);
- switch(II->getOpcode()) {
+ switch (II->getOpcode()) {
case SH::MOVBLPtr:
case SH::MOVWLPtr:
case SH::MOVLLPtr:
@@ -400,16 +392,17 @@ public:
break;
}
case SH::COPY: {
- if (II->readsRegister(SH::R0, nullptr) || II->readsRegister(SH::R1, nullptr)) {
+ if (II->readsRegister(SH::R0, nullptr) ||
+ II->readsRegister(SH::R1, nullptr)) {
II->moveBefore(MP);
Moved++;
}
break;
}
- default:
+ default:
- // We've reached a barrier where moving instructions up could be dangerous.
- // as such, end the MBB pass here.
+ // We've reached a barrier where moving instructions up could be
+ // dangerous. as such, end the MBB pass here.
NII = E;
break;
}
@@ -424,8 +417,9 @@ public:
bool runOnBasicBlock(Block &MBB) {
BlockIt II = MBB.begin(), E = MBB.end();
while (II != E) {
- switch(II->getOpcode()) {
- default: break;
+ switch (II->getOpcode()) {
+ default:
+ break;
case SH::JSR:
return fixupJSR(MBB, II);
}
@@ -444,17 +438,21 @@ public:
for (Block &BB : MF) {
Modified += runOnBasicBlock(BB);
}
- LLVM_DEBUG(dbgs() << "Modified " << Modified << " BBs in " << MF.getName() << "...\n\n");
+ LLVM_DEBUG(dbgs() << "Modified " << Modified << " BBs in " << MF.getName()
+ << "...\n\n");
return Modified > 0;
}
-
- StringRef getPassName() const override { return "SuperH frame load/store fixup pass"; }
+ StringRef getPassName() const override {
+ return "SuperH frame load/store fixup pass";
+ }
};
char SuperHFrameFixupPass::ID = 0;
/// Creates instance of the frame analyzer pass.
-FunctionPass *createSuperHFrameFixupPass() { return new SuperHFrameFixupPass(); }
+FunctionPass *createSuperHFrameFixupPass() {
+ return new SuperHFrameFixupPass();
+}
} // namespace llvm
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/SuperHFrameLowering.h b/llvm/lib/Target/SuperH/SuperHFrameLowering.h
index 10a8f8ac6..66f2b19d9 100644
--- a/llvm/lib/Target/SuperH/SuperHFrameLowering.h
+++ b/llvm/lib/Target/SuperH/SuperHFrameLowering.h
@@ -26,26 +26,33 @@ protected:
public:
explicit SuperHFrameLowering(const SuperHSubtarget &STI)
- : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
- /*StackAlignment*/Align(4),
- /*LocalAreaOffset*/0,
- /*TransAl*/Align(1),
- /*StackReal*/false),
- STI(STI) {}
+ : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
+ /*StackAlignment*/ Align(4),
+ /*LocalAreaOffset*/ 0,
+ /*TransAl*/ Align(1),
+ /*StackReal*/ false),
+ STI(STI) {}
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override;
bool hasReservedCallFrame(const MachineFunction &MF) const override;
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
- bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
- ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const override;
- bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
- MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const override;
+ bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ ArrayRef<CalleeSavedInfo> CSI,
+ const TargetRegisterInfo *TRI) const override;
+ bool
+ restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ MutableArrayRef<CalleeSavedInfo> CSI,
+ const TargetRegisterInfo *TRI) const override;
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
RegScavenger *RS) const override;
- void emitFrameAdjust(Register Base, MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int32_t AdjValue) const;
+ void emitFrameAdjust(Register Base, MachineFunction &MF,
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ int32_t AdjValue) const;
/// getFrameIndexReference - This method should return the base register
/// and offset used to reference a frame index location. The offset is
@@ -56,11 +63,11 @@ public:
MachineBasicBlock::iterator
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const override;
+
protected:
bool hasFPImpl(const MachineFunction &MF) const override;
};
} // end namespace llvm
-
#endif // end LLVM_LIB_TARGET_SUPERH_SUPERHFRAMELOWERING_H
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/SuperHISelDAGToDAG.cpp b/llvm/lib/Target/SuperH/SuperHISelDAGToDAG.cpp
index b3fff5b4d..9384c9d50 100644
--- a/llvm/lib/Target/SuperH/SuperHISelDAGToDAG.cpp
+++ b/llvm/lib/Target/SuperH/SuperHISelDAGToDAG.cpp
@@ -17,9 +17,9 @@
#include "SuperHConstantPoolValue.h"
#include "SuperHInstrInfo.h"
#include "SuperHMachineFunctionInfo.h"
+#include "SuperHSelectionDAGInfo.h"
#include "SuperHSubtarget.h"
#include "SuperHTargetMachine.h"
-#include "SuperHSelectionDAGInfo.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
@@ -31,9 +31,9 @@
#define DEBUG_TYPE "sh-isel"
#define PASS_NAME "SH DAG->DAG Instruction Selection"
-static cl::opt<bool>
-CBranchForceDelaySlot("sh-cbranch-force-delay-slot", cl::Hidden, cl::init(false),
- cl::desc("Force the usage of delay slots for conditional branches."));
+static cl::opt<bool> CBranchForceDelaySlot(
+ "sh-cbranch-force-delay-slot", cl::Hidden, cl::init(false),
+ cl::desc("Force the usage of delay slots for conditional branches."));
using namespace llvm;
@@ -51,22 +51,19 @@ public:
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
InlineAsm::ConstraintCode ConstraintCode,
std::vector<SDValue> &OutOps) override;
-
- bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base, SDValue &Disp);
+ bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base, SDValue &Disp);
/// Return a target constant with the specified value of type i4.
inline SDValue getI4Imm(int64_t Imm, const SDLoc &DL) {
return CurDAG->getSignedTargetConstant(Imm, DL, MVT::i4);
}
-
/// Return a target constant with the specified value of type i8.
inline SDValue getI8Imm(int64_t Imm, const SDLoc &DL) {
return CurDAG->getSignedTargetConstant(Imm, DL, MVT::i8);
}
-
/// Return a target constant with the specified value of type i16.
inline SDValue getI16Imm(int64_t Imm, const SDLoc &DL) {
return CurDAG->getSignedTargetConstant(Imm, DL, MVT::i16);
@@ -80,8 +77,7 @@ private:
bool trySelect(SDNode *N);
- template<unsigned Opcode>
- bool trySelect(SDNode *N);
+ template <unsigned Opcode> bool trySelect(SDNode *N);
const SuperHSubtarget *Subtarget;
};
@@ -89,8 +85,10 @@ private:
class SuperHDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
public:
static char ID;
- explicit SuperHDAGToDAGISelLegacy(SuperHTargetMachine &TM, CodeGenOptLevel OptLevel)
- : SelectionDAGISelLegacy(ID, std::make_unique<SuperHDAGToDAGISel>(TM, OptLevel)) {}
+ explicit SuperHDAGToDAGISelLegacy(SuperHTargetMachine &TM,
+ CodeGenOptLevel OptLevel)
+ : SelectionDAGISelLegacy(
+ ID, std::make_unique<SuperHDAGToDAGISel>(TM, OptLevel)) {}
};
} // end anonymous namespace
@@ -103,9 +101,9 @@ bool SuperHDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
return SelectionDAGISel::runOnMachineFunction(MF);
}
-bool SuperHDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
- InlineAsm::ConstraintCode ConstraintCode,
- std::vector<SDValue> &OutOps) {
+bool SuperHDAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, InlineAsm::ConstraintCode ConstraintCode,
+ std::vector<SDValue> &OutOps) {
return false;
}
@@ -136,7 +134,8 @@ bool SuperHDAGToDAGISel::SelectAddr(SDNode *Op, SDValue N, SDValue &Base,
// Handle reg + offset
if (N.getOpcode() == ISD::ADD) {
Base = N.getOperand(0);
- Disp = CurDAG->getTargetConstant(RHS->getZExtValue(), SDLoc(Op), MVT::i32);
+ Disp =
+ CurDAG->getTargetConstant(RHS->getZExtValue(), SDLoc(Op), MVT::i32);
return true;
}
}
@@ -150,15 +149,11 @@ bool SuperHDAGToDAGISel::SelectAddr(SDNode *Op, SDValue N, SDValue &Base,
return false;
}
-
-
-
//===----------------------------------------------------------------------===//
// Address Lowering
//===----------------------------------------------------------------------===//
-template<>
-bool SuperHDAGToDAGISel::trySelect<SHISD::WRAPPER>(SDNode *N) {
+template <> bool SuperHDAGToDAGISel::trySelect<SHISD::WRAPPER>(SDNode *N) {
auto PtrVT = getTargetLowering()->getPointerTy(CurDAG->getDataLayout());
auto DL = SDLoc(N);
@@ -167,7 +162,8 @@ bool SuperHDAGToDAGISel::trySelect<SHISD::WRAPPER>(SDNode *N) {
SDValue N0 = N->getOperand(0);
// External Symbols
- if (ExternalSymbolSDNode* Sym = dyn_cast<ExternalSymbolSDNode>(N0.getNode())) {
+ if (ExternalSymbolSDNode *Sym =
+ dyn_cast<ExternalSymbolSDNode>(N0.getNode())) {
if (auto *CPV = SFI->tryGetConstant(Sym, *CurDAG, SHCP::no_modifier)) {
SDValue TGA = CurDAG->getTargetConstantPool(CPV, PtrVT, Align(4), 0);
MachineSDNode *Res = CurDAG->getMachineNode(SH::MOVLI, DL, MVT::i32, TGA);
@@ -177,7 +173,7 @@ bool SuperHDAGToDAGISel::trySelect<SHISD::WRAPPER>(SDNode *N) {
}
// Block Addresses
- if (BlockAddressSDNode* BA = dyn_cast<BlockAddressSDNode>(N0.getNode())) {
+ if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0.getNode())) {
if (auto *CPV = SFI->tryGetConstant(BA, *CurDAG, SHCP::no_modifier)) {
SDValue TGA = CurDAG->getTargetConstantPool(CPV, PtrVT, Align(4), 0);
MachineSDNode *Res = CurDAG->getMachineNode(SH::MOVLI, DL, MVT::i32, TGA);
@@ -186,7 +182,7 @@ bool SuperHDAGToDAGISel::trySelect<SHISD::WRAPPER>(SDNode *N) {
}
}
- if (ConstantSDNode* Const = dyn_cast<ConstantSDNode>(N0.getNode())) {
+ if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N0.getNode())) {
if (auto *CPV = SFI->tryGetConstant(Const, *CurDAG, SHCP::no_modifier)) {
SDValue TGA = CurDAG->getTargetConstantPool(CPV, PtrVT, Align(4), 0);
MachineSDNode *Res = CurDAG->getMachineNode(SH::MOVLI, DL, MVT::i32, TGA);
@@ -196,7 +192,7 @@ bool SuperHDAGToDAGISel::trySelect<SHISD::WRAPPER>(SDNode *N) {
}
// Global Addresses
- if (GlobalAddressSDNode* GA = dyn_cast<GlobalAddressSDNode>(N0.getNode())) {
+ if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0.getNode())) {
if (auto *CPV = SFI->tryGetConstant(GA, *CurDAG, SHCP::no_modifier)) {
SDValue TGA = CurDAG->getTargetConstantPool(CPV, PtrVT, Align(4), 0);
MachineSDNode *Res = CurDAG->getMachineNode(SH::MOVLI, DL, MVT::i32, TGA);
@@ -207,25 +203,23 @@ bool SuperHDAGToDAGISel::trySelect<SHISD::WRAPPER>(SDNode *N) {
return false;
}
-
-
-
//===----------------------------------------------------------------------===//
// Conditionals Lowering
//===----------------------------------------------------------------------===//
-template<>
-bool SuperHDAGToDAGISel::trySelect<SHISD::CMP>(SDNode *N) {
+template <> bool SuperHDAGToDAGISel::trySelect<SHISD::CMP>(SDNode *N) {
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
- SHCC::CondCode CC = (SHCC::CondCode)dyn_cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
+ SHCC::CondCode CC = (SHCC::CondCode)dyn_cast<ConstantSDNode>(N->getOperand(2))
+ ->getZExtValue();
SDLoc DL(N);
// NOTE: The comparisons just set the T bit, it's up to later instructions
// to interpret the T bit as positive or negative.
SDNode *Res = nullptr;
- switch(CC) {
- default: break;
+ switch (CC) {
+ default:
+ break;
case SHCC::COND_EQ: {
// TST would be faster in this case.
@@ -273,26 +267,27 @@ bool SuperHDAGToDAGISel::trySelect<SHISD::CMP>(SDNode *N) {
return false;
}
-template<>
-bool SuperHDAGToDAGISel::trySelect<SHISD::BRCOND>(SDNode *N) {
+template <> bool SuperHDAGToDAGISel::trySelect<SHISD::BRCOND>(SDNode *N) {
SDValue Chain = N->getOperand(0);
SDValue Dest = N->getOperand(1);
- SHCC::CondCode CC = (SHCC::CondCode)dyn_cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
+ SHCC::CondCode CC = (SHCC::CondCode)dyn_cast<ConstantSDNode>(N->getOperand(2))
+ ->getZExtValue();
SDValue Cmp = N->getOperand(3);
SDLoc DL(N);
// NOTE: The comparisons just set the T bit, it's up to later instructions
// to interpret the T bit as positive or negative.
MachineSDNode *Res = nullptr;
- switch(CC) {
- default: break;
+ switch (CC) {
+ default:
+ break;
case SHCC::COND_T:
- Res = CurDAG->getMachineNode(CBranchForceDelaySlot ? SH::BTS : SH::BT,
- DL, MVT::Other, Dest, Chain, Cmp);
+ Res = CurDAG->getMachineNode(CBranchForceDelaySlot ? SH::BTS : SH::BT, DL,
+ MVT::Other, Dest, Chain, Cmp);
break;
case SHCC::COND_F:
- Res = CurDAG->getMachineNode(CBranchForceDelaySlot ? SH::BFS : SH::BF,
- DL, MVT::Other, Dest, Chain, Cmp);
+ Res = CurDAG->getMachineNode(CBranchForceDelaySlot ? SH::BFS : SH::BF, DL,
+ MVT::Other, Dest, Chain, Cmp);
break;
}
@@ -305,28 +300,22 @@ bool SuperHDAGToDAGISel::trySelect<SHISD::BRCOND>(SDNode *N) {
return false;
}
-
-
-
//===----------------------------------------------------------------------===//
// Branch Lowering
//===----------------------------------------------------------------------===//
-template<>
-bool SuperHDAGToDAGISel::trySelect<ISD::FrameIndex>(SDNode *N) {
+template <> bool SuperHDAGToDAGISel::trySelect<ISD::FrameIndex>(SDNode *N) {
auto DL = CurDAG->getDataLayout();
// Get the effective address of the stack slot.
int FI = cast<FrameIndexSDNode>(N)->getIndex();
- SDValue TFI = CurDAG->getTargetFrameIndex(FI, getTargetLowering()->getPointerTy(DL));
+ SDValue TFI =
+ CurDAG->getTargetFrameIndex(FI, getTargetLowering()->getPointerTy(DL));
CurDAG->SelectNodeTo(N, SH::SHFrmIdx, getTargetLowering()->getPointerTy(DL),
TFI, CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32));
return true;
}
-
-
-
//===----------------------------------------------------------------------===//
// Selection Code
//===----------------------------------------------------------------------===//
@@ -339,21 +328,21 @@ bool SuperHDAGToDAGISel::trySelect(SDNode *N) {
case Op: \
return trySelect<Op>(N)
- switch(Opcode) {
- default: break;
+ switch (Opcode) {
+ default:
+ break;
case ISD::GLOBAL_OFFSET_TABLE: {
- SDValue GOT = CurDAG->getTargetExternalSymbol(
- "_GLOBAL_OFFSET_TABLE_", MVT::i32, SHII::MO_GOTPC);
- MachineSDNode *Res =
- CurDAG->getMachineNode(SH::MOVA, DL, MVT::i32, GOT);
+ SDValue GOT = CurDAG->getTargetExternalSymbol("_GLOBAL_OFFSET_TABLE_",
+ MVT::i32, SHII::MO_GOTPC);
+ MachineSDNode *Res = CurDAG->getMachineNode(SH::MOVA, DL, MVT::i32, GOT);
ReplaceNode(N, Res);
return true;
}
- SELECT(ISD::FrameIndex);
- SELECT(SHISD::WRAPPER);
- SELECT(SHISD::BRCOND);
- SELECT(SHISD::CMP);
+ SELECT(ISD::FrameIndex);
+ SELECT(SHISD::WRAPPER);
+ SELECT(SHISD::BRCOND);
+ SELECT(SHISD::CMP);
}
#undef SELECT
@@ -363,7 +352,7 @@ bool SuperHDAGToDAGISel::trySelect(SDNode *N) {
void SuperHDAGToDAGISel::Select(SDNode *N) {
LLVM_DEBUG(dbgs() << "SH: Selecting "; N->dump(CurDAG); dbgs() << '\n');
-
+
// Node was already selected?
if (N->isMachineOpcode()) {
LLVM_DEBUG(dbgs() << "== "; N->dump(CurDAG); dbgs() << '\n');
@@ -380,6 +369,6 @@ void SuperHDAGToDAGISel::Select(SDNode *N) {
}
FunctionPass *llvm::createSuperHISelDag(SuperHTargetMachine &TM,
- CodeGenOptLevel OptLevel) {
+ CodeGenOptLevel OptLevel) {
return new SuperHDAGToDAGISelLegacy(TM, OptLevel);
}
diff --git a/llvm/lib/Target/SuperH/SuperHISelLowering.cpp b/llvm/lib/Target/SuperH/SuperHISelLowering.cpp
index 3035002d9..4215c819d 100644
--- a/llvm/lib/Target/SuperH/SuperHISelLowering.cpp
+++ b/llvm/lib/Target/SuperH/SuperHISelLowering.cpp
@@ -12,13 +12,13 @@
//===-----------------------------------------------------------------------===//
#include "SuperHISelLowering.h"
+#include "MCTargetDesc/SuperHBaseInfo.h"
+#include "MCTargetDesc/SuperHMCTargetDesc.h"
#include "SuperHConstantPoolValue.h"
#include "SuperHInstrInfo.h"
#include "SuperHMachineFunctionInfo.h"
-#include "SuperHSelectionDAGInfo.h"
-#include "MCTargetDesc/SuperHMCTargetDesc.h"
-#include "MCTargetDesc/SuperHBaseInfo.h"
#include "SuperHRegisterInfo.h"
+#include "SuperHSelectionDAGInfo.h"
#include "SuperHSubtarget.h"
#include "SuperHTargetMachine.h"
#include "llvm/ADT/ArrayRef.h"
@@ -41,8 +41,8 @@ using namespace llvm;
#define DEBUG_TYPE "sh-lower"
-#define DEBUG_FN_PRINT() LLVM_DEBUG(dbgs() << " - " << __PRETTY_FUNCTION__ << "\n");
-
+#define DEBUG_FN_PRINT() \
+ LLVM_DEBUG(dbgs() << " - " << __PRETTY_FUNCTION__ << "\n");
SuperHTargetLowering::SuperHTargetLowering(const TargetMachine &TM,
const SuperHSubtarget &STI)
@@ -89,7 +89,7 @@ SuperHTargetLowering::SuperHTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
setOperationAction(ISD::ExternalSymbol, MVT::i32, Custom);
setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
-
+
for (MVT VT : MVT::integer_valuetypes()) {
setOperationAction(ISD::Constant, VT, Custom);
}
@@ -116,9 +116,6 @@ SuperHTargetLowering::SuperHTargetLowering(const TargetMachine &TM,
setMinStackArgumentAlignment(Align(4));
}
-
-
-
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// CALLING CONVENTIONS
@@ -126,44 +123,37 @@ SuperHTargetLowering::SuperHTargetLowering(const TargetMachine &TM,
//===----------------------------------------------------------------------===//
static bool RetCC_SH_SRet(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
- CCValAssign::LocInfo &LocInfo,
- ISD::ArgFlagsTy &ArgFlags, CCState &State) {
- assert (ArgFlags.isSRet());
+ CCValAssign::LocInfo &LocInfo,
+ ISD::ArgFlagsTy &ArgFlags, CCState &State) {
+ assert(ArgFlags.isSRet());
// Assign SRet argument.
- State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
- 0,
- LocVT, LocInfo));
+ State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 0, LocVT, LocInfo));
return true;
}
#define GET_CALLING_CONV_IMPL
#include "SuperHGenCallingConv.inc"
-
-
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// LOWERING
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
-
-
-
-
//===----------------------------------------------------------------------===//
// CONDITIONAL BRANCH LOWERING
//===----------------------------------------------------------------------===//
-SDValue SuperHTargetLowering::getSHCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
- SDValue &OutCC, SelectionDAG &DAG,
- SDLoc DL) const {
+SDValue SuperHTargetLowering::getSHCmp(SDValue LHS, SDValue RHS,
+ ISD::CondCode CC, SDValue &OutCC,
+ SelectionDAG &DAG, SDLoc DL) const {
SDValue InCC;
SHCC::CondCode SHcc = SHCC::COND_INVALID;
SHCC::CondCode SHocc = SHCC::COND_T;
- switch(CC) {
- default: break;
+ switch (CC) {
+ default:
+ break;
case ISD::SETEQ: {
SHcc = SHCC::COND_EQ;
SHocc = SHCC::COND_T;
@@ -241,7 +231,8 @@ SDValue SuperHTargetLowering::getSHCmp(SDValue LHS, SDValue RHS, ISD::CondCode C
return DAG.getNode(SHISD::CMP, DL, MVT::Glue, LHS, RHS, InCC);
}
-SDValue SuperHTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
+SDValue SuperHTargetLowering::LowerSELECT_CC(SDValue Op,
+ SelectionDAG &DAG) const {
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);
SDValue TrueV = Op.getOperand(2);
@@ -289,16 +280,13 @@ SDValue SuperHTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
return DAG.getNode(SHISD::BRCOND, DL, MVT::Other, Ops);
}
-
-
-
//===----------------------------------------------------------------------===//
// TYPE LOWERING
//===----------------------------------------------------------------------===//
-void
-SuperHTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
- SelectionDAG &DAG) const {
+void SuperHTargetLowering::ReplaceNodeResults(SDNode *N,
+ SmallVectorImpl<SDValue> &Results,
+ SelectionDAG &DAG) const {
DEBUG_FN_PRINT()
SDLoc DL(N);
@@ -321,14 +309,12 @@ SuperHTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Re
}
}
-
-
-
//===----------------------------------------------------------------------===//
// CONSTANT LOWERING
//===----------------------------------------------------------------------===//
-SDValue SuperHTargetLowering::LowerConstant(SDValue Op, SelectionDAG &DAG) const {
+SDValue SuperHTargetLowering::LowerConstant(SDValue Op,
+ SelectionDAG &DAG) const {
DEBUG_FN_PRINT()
// Get the address of the target into a register
@@ -341,20 +327,19 @@ SDValue SuperHTargetLowering::LowerConstant(SDValue Op, SelectionDAG &DAG) const
}
// Constant would NOT fit in immediate, lower to constpool.
- SDValue Const = DAG.getSignedTargetConstant(C->getSExtValue(), DL, C->getValueType(0));
+ SDValue Const =
+ DAG.getSignedTargetConstant(C->getSExtValue(), DL, C->getValueType(0));
return DAG.getNode(SHISD::WRAPPER, DL, C->getValueType(0), Const);
}
return SDValue();
}
-
-
-
//===----------------------------------------------------------------------===//
// ADDRESS LOWERING
//===----------------------------------------------------------------------===//
-SDValue SuperHTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
+SDValue SuperHTargetLowering::LowerGlobalAddress(SDValue Op,
+ SelectionDAG &DAG) const {
DEBUG_FN_PRINT()
// Get the address of the target into a register
@@ -363,13 +348,15 @@ SDValue SuperHTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
auto DL = SDLoc(G);
SHRefClass OpFlags = Subtarget->classifyGlobalReference(G->getGlobal());
- SDValue Addr = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT, 0, OpFlags);
+ SDValue Addr =
+ DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT, 0, OpFlags);
return DAG.getNode(SHISD::WRAPPER, DL, MVT::i32, Addr);
}
return SDValue();
}
-SDValue SuperHTargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
+SDValue SuperHTargetLowering::LowerExternalSymbol(SDValue Op,
+ SelectionDAG &DAG) const {
DEBUG_FN_PRINT()
// Get the address of the target into a register
@@ -378,7 +365,8 @@ SDValue SuperHTargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG)
auto DL = SDLoc(S);
const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
- SHRefClass OpFlags = Subtarget->classifyGlobalFunctionReference(nullptr, *Mod);
+ SHRefClass OpFlags =
+ Subtarget->classifyGlobalFunctionReference(nullptr, *Mod);
SDValue Addr = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, OpFlags);
return DAG.getNode(SHISD::WRAPPER, DL, MVT::i32, Addr);
@@ -386,7 +374,8 @@ SDValue SuperHTargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG)
return SDValue();
}
-SDValue SuperHTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
+SDValue SuperHTargetLowering::LowerBlockAddress(SDValue Op,
+ SelectionDAG &DAG) const {
DEBUG_FN_PRINT()
// Get the address of the target into a register
@@ -395,34 +384,32 @@ SDValue SuperHTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) c
auto DL = SDLoc(BA);
const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
- SHRefClass OpFlags = Subtarget->classifyGlobalFunctionReference(nullptr, *Mod);
+ SHRefClass OpFlags =
+ Subtarget->classifyGlobalFunctionReference(nullptr, *Mod);
- SDValue Addr = DAG.getTargetBlockAddress(BA->getBlockAddress(), PtrVT, 0, OpFlags);
+ SDValue Addr =
+ DAG.getTargetBlockAddress(BA->getBlockAddress(), PtrVT, 0, OpFlags);
return DAG.getNode(SHISD::WRAPPER, DL, MVT::i32, Addr);
}
return SDValue();
}
-
-
-
//===----------------------------------------------------------------------===//
// ARGUMENT LOWERING
//===----------------------------------------------------------------------===//
-
-SDValue SuperHTargetLowering::LowerFormalArguments(SDValue Chain,
- CallingConv::ID CallConv, bool IsVarArg,
- const SmallVectorImpl<ISD::InputArg> &Ins,
- const SDLoc &dl, SelectionDAG &DAG,
- SmallVectorImpl<SDValue> &InVals) const {
+SDValue SuperHTargetLowering::LowerFormalArguments(
+ SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
+ const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
+ SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo &MFI = MF.getFrameInfo();
DataLayout DL = DAG.getDataLayout();
EVT PtrVT = getPointerTy(DAG.getDataLayout());
SmallVector<CCValAssign, 16> ArgLocs;
- CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext());
+ CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
+ *DAG.getContext());
CCInfo.AnalyzeFormalArguments(Ins, CC_SH);
SDValue ArgValue;
@@ -482,7 +469,7 @@ SDValue SuperHTargetLowering::LowerFormalArguments(SDValue Chain,
// Create the SelectionDAG nodes corresponding to a load
// from this parameter.
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL));
- ArgValue = DAG.getLoad(LocVT, dl, Chain, FIN,
+ ArgValue = DAG.getLoad(LocVT, dl, Chain, FIN,
MachinePointerInfo::getFixedStack(MF, FI));
}
@@ -501,10 +488,6 @@ SDValue SuperHTargetLowering::LowerFormalArguments(SDValue Chain,
return Chain;
}
-
-
-
-
//===----------------------------------------------------------------------===//
// RETURN LOWERING
//===----------------------------------------------------------------------===//
@@ -518,15 +501,16 @@ bool SuperHTargetLowering::CanLowerReturn(
return CCInfo.CheckReturn(Outs, RetCC_SH);
}
-SDValue SuperHTargetLowering::LowerReturn(SDValue Chain,
- CallingConv::ID CallConv, bool IsVarArg,
- const SmallVectorImpl<ISD::OutputArg> &Outs,
- const SmallVectorImpl<SDValue> &OutVals,
- const SDLoc &dl, SelectionDAG &DAG) const {
-
+SDValue
+SuperHTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
+ bool IsVarArg,
+ const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
+ const SDLoc &dl, SelectionDAG &DAG) const {
+
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
- *DAG.getContext());
+ *DAG.getContext());
// Analyze return values.
MachineFunction &MF = DAG.getMachineFunction();
@@ -549,27 +533,27 @@ SDValue SuperHTargetLowering::LowerReturn(SDValue Chain,
}
// Update chain.
- RetOps[0] = Chain;
+ RetOps[0] = Chain;
if (Glue.getNode())
RetOps.push_back(Glue);
return DAG.getNode(SHISD::RET_GLUE, dl, MVT::Other, RetOps);
}
-SDValue SuperHTargetLowering::getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const {
+SDValue
+SuperHTargetLowering::getPICJumpTableRelocBase(SDValue Table,
+ SelectionDAG &DAG) const {
return DAG.getRegister(Subtarget->getRegisterInfo()->getGOTRegister(),
getPointerTy(DAG.getDataLayout()));
}
-
-
-
-
//===----------------------------------------------------------------------===//
// CALL LOWERING
//===----------------------------------------------------------------------===//
-SDValue SuperHTargetLowering::LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const {
+SDValue
+SuperHTargetLowering::LowerCall(CallLoweringInfo &CLI,
+ SmallVectorImpl<SDValue> &InVals) const {
const SuperHRegisterInfo &RI = *Subtarget->getRegisterInfo();
SelectionDAG &DAG = CLI.DAG;
MachineFunction &MF = DAG.getMachineFunction();
@@ -583,8 +567,8 @@ SDValue SuperHTargetLowering::LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<S
CallingConv::ID CallConv = CLI.CallConv;
bool IsVarArg = CLI.IsVarArg;
- // TODO: This was all yoinked from AVR, it likely needs to be modified to fit the calling
- // convention of SuperH.
+ // TODO: This was all yoinked from AVR, it likely needs to be modified to fit
+ // the calling convention of SuperH.
// Tail Call Optimisation not supported yet.
IsTailCall = false;
@@ -729,7 +713,8 @@ SDValue SuperHTargetLowering::LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<S
Chain = DAG.getCALLSEQ_END(Chain, NumBytes, 0, InGlue, DL);
InGlue = Chain.getValue(1);
- return LowerCallResult(Chain, InGlue, CallConv, IsVarArg, Ins, DL, DAG, InVals);
+ return LowerCallResult(Chain, InGlue, CallConv, IsVarArg, Ins, DL, DAG,
+ InVals);
}
SDValue SuperHTargetLowering::LowerCallResult(
@@ -777,9 +762,6 @@ SDValue SuperHTargetLowering::LowerCallResult(
return Chain;
}
-
-
-
//===----------------------------------------------------------------------===//
// DIVISION LOWERING
//===----------------------------------------------------------------------===//
@@ -827,7 +809,6 @@ SDValue SuperHTargetLowering::LowerDIV(SDValue Op, SelectionDAG &DAG) const {
Type *RetTy = (Type *)StructType::get(Ty, Ty);
-
SDLoc dl(Op);
TargetLowering::CallLoweringInfo CLI(DAG);
CLI.setDebugLoc(dl)
@@ -842,9 +823,6 @@ SDValue SuperHTargetLowering::LowerDIV(SDValue Op, SelectionDAG &DAG) const {
return CallInfo.first;
}
-
-
-
//===----------------------------------------------------------------------===//
// MULTIPLICATION LOWERING
//===----------------------------------------------------------------------===//
@@ -862,17 +840,20 @@ SDValue SuperHTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
llvm_unreachable("Unexpected type for ");
case MVT::i8: {
- MachineSDNode *MUL = DAG.getMachineNode(SH::MULU, DL, VT, Op.getOperand(0), Op.getOperand(1));
+ MachineSDNode *MUL = DAG.getMachineNode(SH::MULU, DL, VT, Op.getOperand(0),
+ Op.getOperand(1));
return DAG.getCopyFromReg(SDValue(MUL, 0), DL, SH::MACLO, VT);
}
case MVT::i16: {
- MachineSDNode *MUL = DAG.getMachineNode(SH::MULS, DL, VT, Op.getOperand(0), Op.getOperand(1));
+ MachineSDNode *MUL = DAG.getMachineNode(SH::MULS, DL, VT, Op.getOperand(0),
+ Op.getOperand(1));
return DAG.getCopyFromReg(SDValue(MUL, 0), DL, SH::MACLO, VT);
}
case MVT::i32: {
- MachineSDNode *MUL = DAG.getMachineNode(SH::MULL, DL, VT, Op.getOperand(0), Op.getOperand(1));
+ MachineSDNode *MUL = DAG.getMachineNode(SH::MULL, DL, VT, Op.getOperand(0),
+ Op.getOperand(1));
return DAG.getCopyFromReg(SDValue(MUL, 0), DL, SH::MACLO, VT);
}
@@ -887,7 +868,8 @@ SDValue SuperHTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
Args.push_back(Entry);
}
- RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(RTLIB::MUL_I32);
+ RTLIB::LibcallImpl LCImpl =
+ DAG.getLibcalls().getLibcallImpl(RTLIB::MUL_I32);
if (LCImpl == RTLIB::Unsupported)
return SDValue();
@@ -896,12 +878,11 @@ SDValue SuperHTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
Type *RetTy = (Type *)StructType::get(Ty, Ty);
-
TargetLowering::CallLoweringInfo CLI(DAG);
CLI.setDebugLoc(DL)
.setChain(InChain)
- .setLibCallee(DAG.getLibcalls().getLibcallImplCallingConv(LCImpl), RetTy,
- Callee, std::move(Args))
+ .setLibCallee(DAG.getLibcalls().getLibcallImplCallingConv(LCImpl),
+ RetTy, Callee, std::move(Args))
.setInRegister();
std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
@@ -910,15 +891,13 @@ SDValue SuperHTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
}
}
-
-
-
//===----------------------------------------------------------------------===//
// CUSTOM LOWERING
//===----------------------------------------------------------------------===//
-SDValue SuperHTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
- switch(Op->getOpcode()) {
+SDValue SuperHTargetLowering::LowerOperation(SDValue Op,
+ SelectionDAG &DAG) const {
+ switch (Op->getOpcode()) {
case ISD::UDIV:
case ISD::SDIV:
return LowerDIV(Op, DAG);
@@ -948,15 +927,13 @@ SDValue SuperHTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) cons
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
-
-
-
//===----------------------------------------------------------------------===//
// SelectCC/SetCC Lowering
//===----------------------------------------------------------------------===//
-MachineBasicBlock *SuperHTargetLowering::insertSELECTCC(MachineInstr &MI,
- MachineBasicBlock *MBB) const {
+MachineBasicBlock *
+SuperHTargetLowering::insertSELECTCC(MachineInstr &MI,
+ MachineBasicBlock *MBB) const {
DEBUG_FN_PRINT()
MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
@@ -1038,20 +1015,17 @@ MachineBasicBlock *SuperHTargetLowering::insertSELECTCC(MachineInstr &MI,
return trueMBB;
}
-
-
-
//===----------------------------------------------------------------------===//
// CUSTOM LOWERING
//===----------------------------------------------------------------------===//
-MachineBasicBlock *
-SuperHTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
- MachineBasicBlock *MBB) const {
+MachineBasicBlock *SuperHTargetLowering::EmitInstrWithCustomInserter(
+ MachineInstr &MI, MachineBasicBlock *MBB) const {
int Op = MI.getOpcode();
switch (Op) {
- default: break;
+ default:
+ break;
case SH::Select8:
case SH::Select16:
case SH::Select32:
diff --git a/llvm/lib/Target/SuperH/SuperHISelLowering.h b/llvm/lib/Target/SuperH/SuperHISelLowering.h
index 5b66a6b9c..0b484c932 100644
--- a/llvm/lib/Target/SuperH/SuperHISelLowering.h
+++ b/llvm/lib/Target/SuperH/SuperHISelLowering.h
@@ -16,16 +16,16 @@
#include "SuperH.h"
#include "SuperHInstrInfo.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/GlobalValue.h"
-#include "llvm/CodeGen/MachineConstantPool.h"
namespace llvm {
class SuperHSubtarget;
class MachineConstantPool;
-class SuperHTargetLowering : public TargetLowering {
+class SuperHTargetLowering : public TargetLowering {
const SuperHSubtarget *Subtarget;
public:
@@ -34,11 +34,11 @@ public:
/// ReplaceNodeResults - Replace a node with an illegal result type
/// with a new node built out of custom code.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
- SelectionDAG &DAG) const override;
+ SelectionDAG &DAG) const override;
- // LowerToConstantPool - SuperH's compressed instruction set means that
- // immediates and displacements can not be larger than 8 bits.
- // As such we need to store said immediates and displacements within
+ // LowerToConstantPool - SuperH's compressed instruction set means that
+ // immediates and displacements can not be larger than 8 bits.
+ // As such we need to store said immediates and displacements within
// constants that are within range of the program counter.
//
// As such this function is a helper that:
@@ -46,27 +46,27 @@ public:
// 2. Inserts the target address into said slot.
// 3. Returns the neccesary, but non-legalized instruction sequence to fetch
// the address from that constant pool slot.
- template<class NodeTy>
- SDValue LowerToConstantPool(NodeTy* N, SelectionDAG &DAG) const;
-
- SDValue LowerFormalArguments(SDValue Chain,
- CallingConv::ID CallConv, bool IsVarArg,
- const SmallVectorImpl<ISD::InputArg> &Ins,
- const SDLoc &dl, SelectionDAG &DAG,
- SmallVectorImpl<SDValue> &InVals) const override;
- SDValue LowerReturn(SDValue Chain,
- CallingConv::ID CallConv, bool IsVarArg,
+ template <class NodeTy>
+ SDValue LowerToConstantPool(NodeTy *N, SelectionDAG &DAG) const;
+
+ SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
+ bool IsVarArg,
+ const SmallVectorImpl<ISD::InputArg> &Ins,
+ const SDLoc &dl, SelectionDAG &DAG,
+ SmallVectorImpl<SDValue> &InVals) const override;
+ SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
- const SmallVectorImpl<SDValue> &OutVals,
- const SDLoc &dl, SelectionDAG &DAG) const override;
- bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
- const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
- const Type *RetTy) const override;
- SDValue LowerCall(CallLoweringInfo &/*CLI*/,
- SmallVectorImpl<SDValue> &/*InVals*/) const override;
+ const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
+ SelectionDAG &DAG) const override;
+ bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
+ bool isVarArg,
+ const SmallVectorImpl<ISD::OutputArg> &Outs,
+ LLVMContext &Context, const Type *RetTy) const override;
+ SDValue LowerCall(CallLoweringInfo & /*CLI*/,
+ SmallVectorImpl<SDValue> & /*InVals*/) const override;
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
-
+
// Lowerings
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
@@ -78,28 +78,29 @@ public:
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
- SDValue getSHCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
- SDValue &OutCC, SelectionDAG &DAG, SDLoc DL) const;
+ SDValue getSHCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &OutCC,
+ SelectionDAG &DAG, SDLoc DL) const;
// Inserters
MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr &MI,
MachineBasicBlock *MBB) const override;
+
private:
- MachineBasicBlock *insertSELECTCC(MachineInstr &MI,
+ MachineBasicBlock *insertSELECTCC(MachineInstr &MI,
MachineBasicBlock *BB) const;
- MachineBasicBlock *insertLoad(MachineInstr &MI,
- MachineBasicBlock *BB) const;
- MachineBasicBlock *insertStore(MachineInstr &MI,
- MachineBasicBlock *BB) const;
+ MachineBasicBlock *insertLoad(MachineInstr &MI, MachineBasicBlock *BB) const;
+ MachineBasicBlock *insertStore(MachineInstr &MI, MachineBasicBlock *BB) const;
- SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override;
+ SDValue getPICJumpTableRelocBase(SDValue Table,
+ SelectionDAG &DAG) const override;
// Lowerings
- SDValue LowerCallResult(
- SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg,
- const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
- SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
+ SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
+ CallingConv::ID CallConv, bool isVarArg,
+ const SmallVectorImpl<ISD::InputArg> &Ins,
+ const SDLoc &dl, SelectionDAG &DAG,
+ SmallVectorImpl<SDValue> &InVals) const;
};
} // namespace llvm
diff --git a/llvm/lib/Target/SuperH/SuperHInstrInfo.cpp b/llvm/lib/Target/SuperH/SuperHInstrInfo.cpp
index c144341f3..e94486aa1 100644
--- a/llvm/lib/Target/SuperH/SuperHInstrInfo.cpp
+++ b/llvm/lib/Target/SuperH/SuperHInstrInfo.cpp
@@ -12,12 +12,12 @@
//===----------------------------------------------------------------------===//
#include "SuperHInstrInfo.h"
+#include "MCTargetDesc/SuperHInstPrinter.h"
#include "MCTargetDesc/SuperHMCTargetDesc.h"
+#include "SuperH.h"
#include "SuperHRegisterInfo.h"
#include "SuperHSubtarget.h"
#include "SuperHTargetMachine.h"
-#include "MCTargetDesc/SuperHInstPrinter.h"
-#include "SuperH.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/ISDOpcodes.h"
@@ -29,9 +29,9 @@
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
-#include "llvm/Support/ErrorHandling.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
using namespace llvm;
@@ -43,23 +43,20 @@ using namespace llvm;
SuperHInstrInfo::SuperHInstrInfo(const SuperHSubtarget &ST)
: SuperHGenInstrInfo(ST, RI, SH::ADJCALLSTACKDOWN, SH::ADJCALLSTACKUP),
- RI(ST), Subtarget(ST) { }
+ RI(ST), Subtarget(ST) {}
// Pin the vtable to this file.
void SuperHInstrInfo::anchor() {}
-
// Gets whether a given opcode can fill a delay slot.
-//
-// SuperH does not allow branch instructions of any kind to be situated
+//
+// SuperH does not allow branch instructions of any kind to be situated
// in a delay slot, nor does it allow instructions with delay slots
// to be chained together.
bool SuperHInstrInfo::canFillDelaySlot(unsigned Opcode) const {
auto Desc = this->get(Opcode);
- return !Desc.hasDelaySlot() &&
- !Desc.isBranch() &&
- !Desc.isCall() && !Desc.isReturn() &&
- !(Desc.TSFlags & 0x1);
+ return !Desc.hasDelaySlot() && !Desc.isBranch() && !Desc.isCall() &&
+ !Desc.isReturn() && !(Desc.TSFlags & 0x1);
}
/// Return the noop instruction to use for a noop.
@@ -69,7 +66,7 @@ MCInst SuperHInstrInfo::getNop() const {
return I;
}
-void SuperHInstrInfo::insertNoop(MachineBasicBlock &MBB,
+void SuperHInstrInfo::insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
BuildMI(&MBB, MI->getDebugLoc(), get(SH::NOP));
}
@@ -90,13 +87,17 @@ SHCC::CondCode SuperHInstrInfo::getCondFromBranchOp(unsigned Op) const {
SHCC::CondCode SuperHInstrInfo::getOppositeCondCode(SHCC::CondCode Op) const {
switch (Op) {
- default: return SHCC::COND_INVALID;
- case SHCC::COND_T: return SHCC::COND_F;
- case SHCC::COND_F: return SHCC::COND_T;
+ default:
+ return SHCC::COND_INVALID;
+ case SHCC::COND_T:
+ return SHCC::COND_F;
+ case SHCC::COND_F:
+ return SHCC::COND_T;
}
}
-const MCInstrDesc &SuperHInstrInfo::getBrCond(SHCC::CondCode CC, bool delaySlot) const {
+const MCInstrDesc &SuperHInstrInfo::getBrCond(SHCC::CondCode CC,
+ bool delaySlot) const {
switch (CC) {
default:
llvm_unreachable("Unknown condition code!");
@@ -129,19 +130,15 @@ unsigned SuperHInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
}
}
-
-
-
-
//===----------------------------------------------------------------------===//
// Register Managment.
//===----------------------------------------------------------------------===//
void SuperHInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI, const DebugLoc &DL,
- Register DestReg, Register SrcReg, bool KillSrc,
- bool RenamableDest,
- bool RenamableSrc) const {
+ MachineBasicBlock::iterator MI,
+ const DebugLoc &DL, Register DestReg,
+ Register SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
// Do nothing, self copy.
if (SrcReg == DestReg)
return;
@@ -149,21 +146,21 @@ void SuperHInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
// Load from MACL
if (SrcReg == SH::MACLO && SH::GPRRegClass.contains(DestReg)) {
BuildMI(MBB, MI, DL, get(SH::STSMACL), DestReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
+ .addReg(SrcReg, getKillRegState(KillSrc));
return;
}
// Store to MACL
if (SH::GPRRegClass.contains(SrcReg) && DestReg == SH::MACLO) {
BuildMI(MBB, MI, DL, get(SH::LDSMACL), DestReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
+ .addReg(SrcReg, getKillRegState(KillSrc));
return;
}
// If the targets are GPR registers, use MOV Rm, Rn.
if (SH::GPRRegClass.contains(DestReg, SrcReg)) {
BuildMI(MBB, MI, DL, get(SH::MOV), DestReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
+ .addReg(SrcReg, getKillRegState(KillSrc));
return;
};
@@ -171,15 +168,12 @@ void SuperHInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
llvm_unreachable("Impossible reg-to-reg copy");
}
-
-
-
-
//===----------------------------------------------------------------------===//
// Stack Frames
//===----------------------------------------------------------------------===//
-Register SuperHInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const {
+Register SuperHInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
+ int &FrameIndex) const {
if (MI.getOperand(0).isReg() && MI.getOperand(1).isFI() &&
MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex();
@@ -188,21 +182,23 @@ Register SuperHInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameI
return 0;
}
-void SuperHInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator II,
- Register SrcReg, bool isKill, int FrameIndex,
- const TargetRegisterClass *RC, Register VReg,
- MachineInstr::MIFlag Flags) const {
+void SuperHInstrInfo::storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator II, Register SrcReg,
+ bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
+ MachineInstr::MIFlag Flags) const {
const MachineFunction &MF = *MBB.getParent();
const MachineFrameInfo &MFI = MF.getFrameInfo();
uint ObjectSize = MFI.getObjectSize(FrameIndex);
- LLVM_DEBUG(dbgs() << "Store " << (SrcReg > RI.getNumRegs() ? "VREG" : RI.getName(SrcReg))
- << " to slot " << FrameIndex
- << " size=" << ObjectSize << "\n");
+ LLVM_DEBUG(dbgs() << "Store "
+ << (SrcReg > RI.getNumRegs() ? "VREG" : RI.getName(SrcReg))
+ << " to slot " << FrameIndex << " size=" << ObjectSize
+ << "\n");
unsigned Opc;
- switch(ObjectSize) {
- default: llvm_unreachable("Cannot store this register into stack slot!");
+ switch (ObjectSize) {
+ default:
+ llvm_unreachable("Cannot store this register into stack slot!");
case 1:
Opc = SH::MOVBSPtr;
break;
@@ -214,13 +210,14 @@ void SuperHInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBl
break;
}
BuildMI(MBB, II, DebugLoc(), get(Opc))
- .addReg(SrcReg, getKillRegState(isKill))
- .addFrameIndex(FrameIndex)
- .addImm(0);
+ .addReg(SrcReg, getKillRegState(isKill))
+ .addFrameIndex(FrameIndex)
+ .addImm(0);
}
-Register SuperHInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const {
- if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
+Register SuperHInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
MI.getOperand(1).getImm() == 0) {
FrameIndex = MI.getOperand(0).getIndex();
return MI.getOperand(2).getReg();
@@ -228,21 +225,25 @@ Register SuperHInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &Frame
return 0;
}
-void SuperHInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator II,
- Register DestReg, int FrameIndex,
- const TargetRegisterClass *RC, Register VReg,
- unsigned SubReg, MachineInstr::MIFlag Flags) const {
+void SuperHInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator II,
+ Register DestReg, int FrameIndex,
+ const TargetRegisterClass *RC,
+ Register VReg, unsigned SubReg,
+ MachineInstr::MIFlag Flags) const {
const MachineFunction &MF = *MBB.getParent();
const MachineFrameInfo &MFI = MF.getFrameInfo();
uint ObjectSize = MFI.getObjectSize(FrameIndex);
- LLVM_DEBUG(dbgs() << "Load " << (DestReg > RI.getNumRegs() ? "VREG" : RI.getName(DestReg))
- << " from slot " << FrameIndex
- << " size=" << ObjectSize << "\n");
-
+ LLVM_DEBUG(
+ dbgs() << "Load "
+ << (DestReg > RI.getNumRegs() ? "VREG" : RI.getName(DestReg))
+ << " from slot " << FrameIndex << " size=" << ObjectSize << "\n");
+
unsigned Opc;
- switch(ObjectSize) {
- default: llvm_unreachable("Cannot load this register from stack slot!");
+ switch (ObjectSize) {
+ default:
+ llvm_unreachable("Cannot load this register from stack slot!");
case 1:
Opc = SH::MOVBLPtr;
break;
@@ -255,21 +256,19 @@ void SuperHInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicB
}
BuildMI(MBB, II, DebugLoc(), get(Opc), DestReg)
- .addFrameIndex(FrameIndex)
- .addImm(0);
+ .addFrameIndex(FrameIndex)
+ .addImm(0);
}
-
-
-
//===----------------------------------------------------------------------===//
// Branch Analysis
//===----------------------------------------------------------------------===//
-bool SuperHInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
- MachineBasicBlock *&FBB,
- SmallVectorImpl<MachineOperand> &Cond,
- bool AllowModify) const {
+bool SuperHInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
+ MachineBasicBlock *&TBB,
+ MachineBasicBlock *&FBB,
+ SmallVectorImpl<MachineOperand> &Cond,
+ bool AllowModify) const {
// Start from the bottom of the block and work up, examining the
// terminator instructions.
MachineBasicBlock::iterator I = MBB.end();
@@ -380,10 +379,9 @@ bool SuperHInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&
return false;
}
-unsigned SuperHInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
- MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded) const {
+unsigned SuperHInstrInfo::insertBranch(
+ MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
+ ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
if (BytesAdded)
*BytesAdded = 0;
@@ -421,7 +419,7 @@ unsigned SuperHInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock
}
unsigned SuperHInstrInfo::removeBranch(MachineBasicBlock &MBB,
- int *BytesRemoved) const {
+ int *BytesRemoved) const {
if (BytesRemoved)
*BytesRemoved = 0;
@@ -450,8 +448,8 @@ unsigned SuperHInstrInfo::removeBranch(MachineBasicBlock &MBB,
return Count;
}
-bool
-SuperHInstrInfo::reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
+bool SuperHInstrInfo::reverseBranchCondition(
+ SmallVectorImpl<MachineOperand> &Cond) const {
assert(Cond.size() == 1 && "Invalid SH branch condition!");
SHCC::CondCode CC = (SHCC::CondCode)Cond[0].getImm();
@@ -459,7 +457,8 @@ SuperHInstrInfo::reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) c
return false;
}
-MachineBasicBlock *SuperHInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
+MachineBasicBlock *
+SuperHInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
if (MI.isBranch())
return MI.getOperand(0).getMBB();
@@ -467,7 +466,7 @@ MachineBasicBlock *SuperHInstrInfo::getBranchDestBlock(const MachineInstr &MI) c
}
bool SuperHInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
- int64_t BrOffset) const {
+ int64_t BrOffset) const {
switch (BranchOp) {
default:
llvm_unreachable("unexpected opcode!");
@@ -481,4 +480,3 @@ bool SuperHInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
return isIntN(12, BrOffset);
}
}
-
diff --git a/llvm/lib/Target/SuperH/SuperHInstrInfo.h b/llvm/lib/Target/SuperH/SuperHInstrInfo.h
index a944d2089..b74c2b286 100644
--- a/llvm/lib/Target/SuperH/SuperHInstrInfo.h
+++ b/llvm/lib/Target/SuperH/SuperHInstrInfo.h
@@ -15,10 +15,10 @@
#define LLVM_LIB_TARGET_SUPERH_SUPERHINSTRINFO_H
#include "SuperHRegisterInfo.h"
+#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
-#include "llvm/CodeGen/ISDOpcodes.h"
#define GET_INSTRINFO_HEADER
#include "SuperHGenInstrInfo.inc"
@@ -60,8 +60,8 @@ public:
const SuperHRegisterInfo &getRegisterInfo() const { return RI; }
/// Gets whether a given opcode can fill a delay slot.
- ///
- /// SuperH does not allow branch instructions of any kind to be situated
+ ///
+ /// SuperH does not allow branch instructions of any kind to be situated
/// in a delay slot, nor does it allow instructions with delay slots
/// to be chained together.
bool canFillDelaySlot(unsigned Opcode) const;
@@ -74,16 +74,14 @@ public:
/// Return the noop instruction to use for a noop.
MCInst getNop() const override;
- void insertNoop(MachineBasicBlock &MBB,
+ void insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const override;
-
// Stack Frames
- void copyPhysReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI, const DebugLoc &DL,
- Register DestReg, Register SrcReg, bool KillSrc,
- bool RenamableDest = false,
- bool RenamableSrc = false) const override;
+ void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+ const DebugLoc &DL, Register DestReg, Register SrcReg,
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
@@ -98,7 +96,6 @@ public:
Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
-
// Branch Analysis
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
@@ -120,6 +117,6 @@ public:
};
const SuperHInstrInfo *createSuperHInstrInfo(const SuperHSubtarget &STI);
-}
+} // namespace llvm
#endif // end LLVM_LIB_TARGET_SUPERH_SUPERHINSTRINFO_H
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/SuperHMCInstLower.cpp b/llvm/lib/Target/SuperH/SuperHMCInstLower.cpp
index d64518bac..dce566a20 100644
--- a/llvm/lib/Target/SuperH/SuperHMCInstLower.cpp
+++ b/llvm/lib/Target/SuperH/SuperHMCInstLower.cpp
@@ -7,14 +7,13 @@
//===----------------------------------------------------------------------===//
#include "SuperHMCInstLower.h"
-#include "MCTargetDesc/SuperHMCAsmInfo.h"
#include "MCTargetDesc/SuperHBaseInfo.h"
+#include "MCTargetDesc/SuperHMCAsmInfo.h"
#include "SuperHSubtarget.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
-
namespace llvm {
MCOperand
@@ -51,7 +50,8 @@ SuperHMCInstLower::lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym,
void SuperHMCInstLower::lowerInstruction(const MachineInstr &MI,
MCInst &OutMI) const {
- auto &Subtarget = MI.getParent()->getParent()->getSubtarget<SuperHSubtarget>();
+ auto &Subtarget =
+ MI.getParent()->getParent()->getSubtarget<SuperHSubtarget>();
OutMI.setOpcode(MI.getOpcode());
for (MachineOperand const &MO : MI.operands()) {
diff --git a/llvm/lib/Target/SuperH/SuperHMachineFunctionInfo.cpp b/llvm/lib/Target/SuperH/SuperHMachineFunctionInfo.cpp
index dd009e48c..944f196aa 100644
--- a/llvm/lib/Target/SuperH/SuperHMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/SuperH/SuperHMachineFunctionInfo.cpp
@@ -29,47 +29,42 @@ MachineFunctionInfo *SuperHMachineFunctionInfo::clone(
}
SuperHConstantPoolConstant *SuperHMachineFunctionInfo::tryGetConstant(
- GlobalAddressSDNode *N,
- SelectionDAG &DAG,
- SHCP::SHCPModifier Modifier) {
+ GlobalAddressSDNode *N, SelectionDAG &DAG, SHCP::SHCPModifier Modifier) {
// Early exit for null node.
if (!N)
return nullptr;
- // Run though the constant pool that is tied to the DAG and search for
+ // Run though the constant pool that is tied to the DAG and search for
// the constant there.
MachineConstantPool *MCP = DAG.getMachineFunction().getConstantPool();
for (auto &MC : MCP->getConstants()) {
if (MC.isMachineConstantPoolEntry()) {
- if (auto *CPV = (SuperHConstantPoolConstant*)MC.Val.MachineCPVal) {
+ if (auto *CPV = (SuperHConstantPoolConstant *)MC.Val.MachineCPVal) {
if (CPV->getGV() == N->getGlobal())
return CPV;
}
}
}
-
+
// If not found, create a new one and add it.
MachineFunction &MF = DAG.getMachineFunction();
SuperHMachineFunctionInfo *SFI = MF.getInfo<SuperHMachineFunctionInfo>();
unsigned LabelIndex = SFI->createConstIndex();
- return SuperHConstantPoolConstant::Create(
- N->getGlobal(),
- LabelIndex,
- SHCP::SHCPKind::CPValue,
- Modifier
- );
+ return SuperHConstantPoolConstant::Create(N->getGlobal(), LabelIndex,
+ SHCP::SHCPKind::CPValue, Modifier);
}
SuperHConstantPoolConstant *
-SuperHMachineFunctionInfo::tryGetConstant(const GlobalValue *G, const MachineFunction& MF) const {
+SuperHMachineFunctionInfo::tryGetConstant(const GlobalValue *G,
+ const MachineFunction &MF) const {
- // Run though the constant pool that is tied to the DAG and search for
+ // Run though the constant pool that is tied to the DAG and search for
// the constant there.
const MachineConstantPool *MCP = MF.getConstantPool();
for (auto &MC : MCP->getConstants()) {
if (MC.isMachineConstantPoolEntry()) {
- if (auto *CPV = (SuperHConstantPoolConstant*)MC.Val.MachineCPVal) {
+ if (auto *CPV = (SuperHConstantPoolConstant *)MC.Val.MachineCPVal) {
if (CPV->getGV() == G)
return CPV;
}
@@ -79,20 +74,18 @@ SuperHMachineFunctionInfo::tryGetConstant(const GlobalValue *G, const MachineFun
}
SuperHConstantPoolConstant *SuperHMachineFunctionInfo::tryGetConstant(
- BlockAddressSDNode *N,
- SelectionDAG &DAG,
- SHCP::SHCPModifier Modifier) {
+ BlockAddressSDNode *N, SelectionDAG &DAG, SHCP::SHCPModifier Modifier) {
// Early exit for null node.
if (!N)
return nullptr;
- // Run though the constant pool that is tied to the DAG and search for
+ // Run though the constant pool that is tied to the DAG and search for
// the constant there.
MachineConstantPool *MCP = DAG.getMachineFunction().getConstantPool();
for (auto &MC : MCP->getConstants()) {
if (MC.isMachineConstantPoolEntry()) {
- if (auto *CPV = (SuperHConstantPoolConstant*)MC.Val.MachineCPVal) {
+ if (auto *CPV = (SuperHConstantPoolConstant *)MC.Val.MachineCPVal) {
if (CPV->getBlockAddress() == N->getBlockAddress())
return CPV;
}
@@ -103,29 +96,25 @@ SuperHConstantPoolConstant *SuperHMachineFunctionInfo::tryGetConstant(
MachineFunction &MF = DAG.getMachineFunction();
SuperHMachineFunctionInfo *SFI = MF.getInfo<SuperHMachineFunctionInfo>();
unsigned LabelIndex = SFI->createConstIndex();
- return SuperHConstantPoolConstant::Create(
- N->getBlockAddress(),
- LabelIndex,
- SHCP::SHCPKind::CPBlockAddress,
- Modifier
- );
+ return SuperHConstantPoolConstant::Create(N->getBlockAddress(), LabelIndex,
+ SHCP::SHCPKind::CPBlockAddress,
+ Modifier);
}
-SuperHConstantPoolConstant *SuperHMachineFunctionInfo::tryGetConstant(
- ConstantSDNode *N,
- SelectionDAG &DAG,
- SHCP::SHCPModifier Modifier) {
+SuperHConstantPoolConstant *
+SuperHMachineFunctionInfo::tryGetConstant(ConstantSDNode *N, SelectionDAG &DAG,
+ SHCP::SHCPModifier Modifier) {
// Early exit for null node.
if (!N)
return nullptr;
- // Run though the constant pool that is tied to the DAG and search for
+ // Run though the constant pool that is tied to the DAG and search for
// the constant there.
MachineConstantPool *MCP = DAG.getMachineFunction().getConstantPool();
for (auto &MC : MCP->getConstants()) {
if (MC.isMachineConstantPoolEntry()) {
- if (auto *CPV = (SuperHConstantPoolConstant*)MC.Val.MachineCPVal) {
+ if (auto *CPV = (SuperHConstantPoolConstant *)MC.Val.MachineCPVal) {
if (CPV->getPromotedGlobalInit() == N->getConstantIntValue())
return CPV;
}
@@ -137,41 +126,33 @@ SuperHConstantPoolConstant *SuperHMachineFunctionInfo::tryGetConstant(
SuperHMachineFunctionInfo *SFI = MF.getInfo<SuperHMachineFunctionInfo>();
unsigned LabelIndex = SFI->createConstIndex();
return SuperHConstantPoolConstant::Create(
- N->getConstantIntValue(),
- LabelIndex,
- SHCP::SHCPKind::CPPromotedGlobal,
- Modifier
- );
+ N->getConstantIntValue(), LabelIndex, SHCP::SHCPKind::CPPromotedGlobal,
+ Modifier);
}
SuperHConstantPoolSymbol *SuperHMachineFunctionInfo::tryGetConstant(
- ExternalSymbolSDNode *N,
- SelectionDAG &DAG,
- SHCP::SHCPModifier Modifier) {
+ ExternalSymbolSDNode *N, SelectionDAG &DAG, SHCP::SHCPModifier Modifier) {
// Early exit for null node.
if (!N)
return nullptr;
- // Run though the constant pool that is tied to the DAG and search for
+ // Run though the constant pool that is tied to the DAG and search for
// the constant there.
MachineConstantPool *MCP = DAG.getMachineFunction().getConstantPool();
for (auto &MC : MCP->getConstants()) {
if (MC.isMachineConstantPoolEntry()) {
- if (auto *CPV = (SuperHConstantPoolSymbol*)MC.Val.MachineCPVal) {
+ if (auto *CPV = (SuperHConstantPoolSymbol *)MC.Val.MachineCPVal) {
if (CPV->getSymbol() == N->getSymbol())
return CPV;
}
}
}
-
+
// If not found, create a new one and add it.
MachineFunction &MF = DAG.getMachineFunction();
SuperHMachineFunctionInfo *SFI = MF.getInfo<SuperHMachineFunctionInfo>();
unsigned LabelIndex = SFI->createConstIndex();
- return SuperHConstantPoolSymbol::Create(
- *DAG.getContext(),
- N->getSymbol(),
- LabelIndex
- );
+ return SuperHConstantPoolSymbol::Create(*DAG.getContext(), N->getSymbol(),
+ LabelIndex);
}
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/SuperHMachineFunctionInfo.h b/llvm/lib/Target/SuperH/SuperHMachineFunctionInfo.h
index a162f3dc3..bc85d83de 100644
--- a/llvm/lib/Target/SuperH/SuperHMachineFunctionInfo.h
+++ b/llvm/lib/Target/SuperH/SuperHMachineFunctionInfo.h
@@ -26,7 +26,7 @@ namespace llvm {
class SuperHMachineFunctionInfo : public MachineFunctionInfo {
- /// CPIndexCount - How many constant pool indices are allocated.
+ /// CPIndexCount - How many constant pool indices are allocated.
unsigned CPIndexCount = 0;
BitVector UsedRegs;
@@ -47,9 +47,9 @@ public:
// createConstIndex - Creates a new PIC Label UId.
unsigned createConstIndex() { return CPIndexCount++; }
- // tryGetConstant - SuperH's compressed instruction set means that
- // immediates and displacements can not be larger than 8 bits.
- // As such we need to store said immediates and displacements within
+ // tryGetConstant - SuperH's compressed instruction set means that
+ // immediates and displacements can not be larger than 8 bits.
+ // As such we need to store said immediates and displacements within
// constants that are within range of the program counter.
//
// As such this function is a helper that:
@@ -57,19 +57,27 @@ public:
// 2. Inserts the target into said slot.
// 3. Returns the allocated slot, ready to be loaded via
// a PC-relative load.
- SuperHConstantPoolConstant *tryGetConstant(GlobalAddressSDNode *N, SelectionDAG &DAG, SHCP::SHCPModifier Modifier);
- SuperHConstantPoolConstant *tryGetConstant(BlockAddressSDNode *N, SelectionDAG &DAG, SHCP::SHCPModifier Modifier);
- SuperHConstantPoolConstant *tryGetConstant(ConstantSDNode *N, SelectionDAG &DAG, SHCP::SHCPModifier Modifier);
- SuperHConstantPoolSymbol *tryGetConstant(ExternalSymbolSDNode *N, SelectionDAG &DAG, SHCP::SHCPModifier Modifier);
+ SuperHConstantPoolConstant *tryGetConstant(GlobalAddressSDNode *N,
+ SelectionDAG &DAG,
+ SHCP::SHCPModifier Modifier);
+ SuperHConstantPoolConstant *tryGetConstant(BlockAddressSDNode *N,
+ SelectionDAG &DAG,
+ SHCP::SHCPModifier Modifier);
+ SuperHConstantPoolConstant *tryGetConstant(ConstantSDNode *N,
+ SelectionDAG &DAG,
+ SHCP::SHCPModifier Modifier);
+ SuperHConstantPoolSymbol *tryGetConstant(ExternalSymbolSDNode *N,
+ SelectionDAG &DAG,
+ SHCP::SHCPModifier Modifier);
// Helper for lower level passes that gets global value constants.
- SuperHConstantPoolConstant *tryGetConstant(const GlobalValue *G, const MachineFunction& MF) const;
+ SuperHConstantPoolConstant *tryGetConstant(const GlobalValue *G,
+ const MachineFunction &MF) const;
private:
- virtual void anchor();
+ virtual void anchor();
};
-
} // namespace llvm
#endif
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/SuperHRegisterInfo.cpp b/llvm/lib/Target/SuperH/SuperHRegisterInfo.cpp
index 119031c53..9699d77ff 100644
--- a/llvm/lib/Target/SuperH/SuperHRegisterInfo.cpp
+++ b/llvm/lib/Target/SuperH/SuperHRegisterInfo.cpp
@@ -13,10 +13,10 @@
#include "SuperHRegisterInfo.h"
#include "MCTargetDesc/SuperHMCTargetDesc.h"
-#include "SuperHTargetMachine.h"
+#include "SuperH.h"
#include "SuperHFrameLowering.h"
#include "SuperHSubtarget.h"
-#include "SuperH.h"
+#include "SuperHTargetMachine.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Register.h"
@@ -34,31 +34,34 @@ using namespace llvm;
#define GET_REGINFO_TARGET_DESC
#include "SuperHGenRegisterInfo.inc"
-
-
SuperHRegisterInfo::SuperHRegisterInfo(const SuperHSubtarget &ST)
- : SuperHGenRegisterInfo(SH::R0, /*DwarfFlavour*/0, /*EHFlavor*/0,
- /*PC*/SH::PC), Subtarget(ST) {}
+ : SuperHGenRegisterInfo(SH::R0, /*DwarfFlavour*/ 0, /*EHFlavor*/ 0,
+ /*PC*/ SH::PC),
+ Subtarget(ST) {}
-const TargetRegisterClass *SuperHRegisterInfo::getPointerRegClass(unsigned Kind) const {
+const TargetRegisterClass *
+SuperHRegisterInfo::getPointerRegClass(unsigned Kind) const {
return &SH::GPRRegClass;
}
-const MCPhysReg *SuperHRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
+const MCPhysReg *
+SuperHRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
return CSR_SH_SaveList;
}
-const uint32_t *SuperHRegisterInfo::getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const {
- return CSR_SH_RegMask;
+const uint32_t *
+SuperHRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
+ CallingConv::ID CC) const {
+ return CSR_SH_RegMask;
}
const uint32_t *SuperHRegisterInfo::getNoPreservedMask() const {
- return CSR_SH_RegMask;
+ return CSR_SH_RegMask;
}
const TargetRegisterClass *
SuperHRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
- const MachineFunction &MF) const {
+ const MachineFunction &MF) const {
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
if (TRI->isTypeLegalForClass(*RC, MVT::i16)) {
@@ -82,10 +85,10 @@ BitVector SuperHRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
// R0 is always reserved as some instructions can only write to it.
Reserved.set(SH::R0);
-
+
// R1 is generally used as the temporary storage for addresses.
Reserved.set(SH::R1);
-
+
// Also reserve the stack pointer.
Reserved.set(SH::R15);
@@ -109,29 +112,31 @@ static void replaceFI(const MachineFunction &MF, MachineBasicBlock::iterator II,
}
bool SuperHRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
- int SPAdj,
- unsigned FIOperandNum,
- RegScavenger *RS) const {
+ int SPAdj, unsigned FIOperandNum,
+ RegScavenger *RS) const {
MachineInstr &MI = *II;
DebugLoc DL = MI.getDebugLoc();
MachineBasicBlock &MBB = *MI.getParent();
const MachineFunction &MF = *MBB.getParent();
const MachineFrameInfo &MFI = MF.getFrameInfo();
const SuperHTargetMachine &TM = (const SuperHTargetMachine &)MF.getTarget();
- const TargetFrameLowering *TFI = TM.getSubtargetImpl(MF.getFunction())->getFrameLowering();
- const TargetInstrInfo &TII = *TM.getSubtargetImpl(MF.getFunction())->getInstrInfo();
+ const TargetFrameLowering *TFI =
+ TM.getSubtargetImpl(MF.getFunction())->getFrameLowering();
+ const TargetInstrInfo &TII =
+ *TM.getSubtargetImpl(MF.getFunction())->getInstrInfo();
int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
// Get the register offset to fetch.
Register FrameReg;
- int64_t Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg).getFixed();
+ int64_t Offset =
+ TFI->getFrameIndexReference(MF, FrameIndex, FrameReg).getFixed();
LLVM_DEBUG({
- int64_t Fo = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg).getFixed();
- dbgs() << "Eliminiate FI " << FrameIndex << " @ SP["
- << -Fo << "]...\n";
+ int64_t Fo =
+ TFI->getFrameIndexReference(MF, FrameIndex, FrameReg).getFixed();
+ dbgs() << "Eliminiate FI " << FrameIndex << " @ SP[" << -Fo << "]...\n";
});
-
+
replaceFI(MF, II, MI, DL, FIOperandNum, Offset, FrameReg);
return false;
}
@@ -141,14 +146,8 @@ Register SuperHRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
return TFI->hasFP(MF) ? SH::R14 : SH::R15;
}
-Register SuperHRegisterInfo::getFrameRegister() const {
- return SH::R14;
-}
+Register SuperHRegisterInfo::getFrameRegister() const { return SH::R14; }
-Register SuperHRegisterInfo::getStackRegister() const {
- return SH::R15;
-}
+Register SuperHRegisterInfo::getStackRegister() const { return SH::R15; }
-Register SuperHRegisterInfo::getGOTRegister() const {
- return SH::R12;
-}
\ No newline at end of file
+Register SuperHRegisterInfo::getGOTRegister() const { return SH::R12; }
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/SuperHRegisterInfo.h b/llvm/lib/Target/SuperH/SuperHRegisterInfo.h
index 921d966ae..50e43d82f 100644
--- a/llvm/lib/Target/SuperH/SuperHRegisterInfo.h
+++ b/llvm/lib/Target/SuperH/SuperHRegisterInfo.h
@@ -30,20 +30,24 @@ public:
SuperHRegisterInfo(const SuperHSubtarget &Subtarget);
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
- const uint32_t *getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override;
+ const uint32_t *getCallPreservedMask(const MachineFunction &MF,
+ CallingConv::ID CC) const override;
const uint32_t *getNoPreservedMask() const override;
- const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const override;
+ const TargetRegisterClass *
+ getPointerRegClass(unsigned Kind = 0) const override;
BitVector getReservedRegs(const MachineFunction &MF) const override;
- const TargetRegisterClass *getLargestLegalSuperClass(const TargetRegisterClass *RC,
- const MachineFunction &MF) const override;
+ const TargetRegisterClass *
+ getLargestLegalSuperClass(const TargetRegisterClass *RC,
+ const MachineFunction &MF) const override;
Register getFrameRegister(const MachineFunction &MF) const override;
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
unsigned FIOperandNum,
RegScavenger *RS = nullptr) const override;
- bool requiresRegisterScavenging(const MachineFunction &MF) const override { return true; }
-
+ bool requiresRegisterScavenging(const MachineFunction &MF) const override {
+ return true;
+ }
// Helpers
Register getFrameRegister() const;
diff --git a/llvm/lib/Target/SuperH/SuperHSubtarget.cpp b/llvm/lib/Target/SuperH/SuperHSubtarget.cpp
index 93c86db7c..12b34e416 100644
--- a/llvm/lib/Target/SuperH/SuperHSubtarget.cpp
+++ b/llvm/lib/Target/SuperH/SuperHSubtarget.cpp
@@ -28,15 +28,13 @@ using namespace llvm;
SuperHSubtarget::SuperHSubtarget(const StringRef &CPU, const StringRef &FS,
const TargetMachine &TM)
: SuperHGenSubtargetInfo(TM.getTargetTriple(), CPU, CPU, FS), TM(TM),
- InstrInfo(initializeSubtargetDependencies(CPU, FS)),
- TLInfo(TM, *this), TSInfo(), FrameLowering(*this) {
-}
+ InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
+ TSInfo(), FrameLowering(*this) {}
SuperHSubtarget::~SuperHSubtarget() = default;
-
-SuperHSubtarget &SuperHSubtarget::initializeSubtargetDependencies(
- StringRef CPU, StringRef FS) {
+SuperHSubtarget &
+SuperHSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
// Determine default and user specified characteristics
const Triple &TT = getTargetTriple();
std::string CPUName = std::string(CPU);
@@ -46,9 +44,6 @@ SuperHSubtarget &SuperHSubtarget::initializeSubtargetDependencies(
return *this;
}
-
-
-
//===----------------------------------------------------------------------===//
// Classification Functions
//===----------------------------------------------------------------------===//
@@ -63,32 +58,25 @@ SHRefClass SuperHSubtarget::classifyBlockAddressReference() const {
}
case CodeModel::Medium:
case CodeModel::Large: {
- return isPositionIndependent() ?
- SHII::MO_PCREL :
- SHII::MO_DIR;
+ return isPositionIndependent() ? SHII::MO_PCREL : SHII::MO_DIR;
}
}
}
-SHRefClass SuperHSubtarget::classifyLocalReference(const GlobalValue *GV) const {
+SHRefClass
+SuperHSubtarget::classifyLocalReference(const GlobalValue *GV) const {
switch (TM.getCodeModel()) {
default:
llvm_unreachable("Unsupported code model");
case CodeModel::Small:
case CodeModel::Kernel: {
- return isPositionIndependent() ?
- SHII::MO_PCREL :
- SHII::MO_DIR;
+ return isPositionIndependent() ? SHII::MO_PCREL : SHII::MO_DIR;
}
case CodeModel::Medium: {
- return isPositionIndependent() ?
- SHII::MO_GOTOFF :
- SHII::MO_DIR;
+ return isPositionIndependent() ? SHII::MO_GOTOFF : SHII::MO_DIR;
}
case CodeModel::Large: {
- return isPositionIndependent() ?
- SHII::MO_GOTOFF :
- SHII::MO_DIR;
+ return isPositionIndependent() ? SHII::MO_GOTOFF : SHII::MO_DIR;
}
}
}
@@ -97,17 +85,16 @@ SHRefClass SuperHSubtarget::classifyExternalReference(const Module &M) const {
if (TM.shouldAssumeDSOLocal(nullptr))
return classifyLocalReference(nullptr);
- return isPositionIndependent() ?
- SHII::MO_GOTPC :
- SHII::MO_GOT;
+ return isPositionIndependent() ? SHII::MO_GOTPC : SHII::MO_GOT;
}
-SHRefClass SuperHSubtarget::classifyGlobalReference(const GlobalValue *GV) const {
+SHRefClass
+SuperHSubtarget::classifyGlobalReference(const GlobalValue *GV) const {
return classifyGlobalReference(GV, *GV->getParent());
}
SHRefClass SuperHSubtarget::classifyGlobalReference(const GlobalValue *GV,
- const Module &M) const {
+ const Module &M) const {
if (TM.shouldAssumeDSOLocal(GV))
return classifyLocalReference(GV);
@@ -117,24 +104,20 @@ SHRefClass SuperHSubtarget::classifyGlobalReference(const GlobalValue *GV,
case CodeModel::Small:
case CodeModel::Kernel:
case CodeModel::Medium: {
- return isPositionIndependent() ?
- SHII::MO_GOTPC :
- SHII::MO_DIR;
+ return isPositionIndependent() ? SHII::MO_GOTPC : SHII::MO_DIR;
}
case CodeModel::Large: {
- return isPositionIndependent() ?
- SHII::MO_GOTOFF :
- SHII::MO_DIR;
+ return isPositionIndependent() ? SHII::MO_GOTOFF : SHII::MO_DIR;
}
}
}
-SHRefClass SuperHSubtarget::classifyGlobalFunctionReference(const GlobalValue *GV,
- const Module &M) const {
+SHRefClass
+SuperHSubtarget::classifyGlobalFunctionReference(const GlobalValue *GV,
+ const Module &M) const {
if (TM.shouldAssumeDSOLocal(GV))
return SHII::MO_NO_FLAG;
-
// If the function is marked as non-lazy, generate an indirect call
// which loads from the GOT directly. This avoids run-time overhead
// at the cost of eager binding.
@@ -143,11 +126,10 @@ SHRefClass SuperHSubtarget::classifyGlobalFunctionReference(const GlobalValue *G
return SHII::MO_GOTPC;
}
- return isPositionIndependent() ?
- SHII::MO_PLT :
- SHII::MO_DIR;
+ return isPositionIndependent() ? SHII::MO_PLT : SHII::MO_DIR;
}
-SHRefClass SuperHSubtarget::classifyGlobalFunctionReference(const GlobalValue *GV) const {
+SHRefClass
+SuperHSubtarget::classifyGlobalFunctionReference(const GlobalValue *GV) const {
return classifyGlobalFunctionReference(GV, *GV->getParent());
}
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/SuperHSubtarget.h b/llvm/lib/Target/SuperH/SuperHSubtarget.h
index 55c4a0a1e..1a442b34a 100644
--- a/llvm/lib/Target/SuperH/SuperHSubtarget.h
+++ b/llvm/lib/Target/SuperH/SuperHSubtarget.h
@@ -34,14 +34,8 @@ class StringRef;
typedef unsigned char SHRefClass;
class SuperHSubtarget : public SuperHGenSubtargetInfo {
- enum SuperHArchEnum {
- SHDefault,
- SH1,
- SH2, SH2A, SH2E,
- SH3, SH3E,
- SH4, SH4A
- };
-
+ enum SuperHArchEnum { SHDefault, SH1, SH2, SH2A, SH2E, SH3, SH3E, SH4, SH4A };
+
SuperHArchEnum SHArchVersion;
const TargetMachine &TM;
@@ -55,17 +49,25 @@ class SuperHSubtarget : public SuperHGenSubtargetInfo {
#include "SuperHGenSubtargetInfo.inc"
public:
- SuperHSubtarget(const StringRef &CPU, const StringRef &FS,
+ SuperHSubtarget(const StringRef &CPU, const StringRef &FS,
const TargetMachine &TM);
~SuperHSubtarget() override;
const Triple &getTargetTriple() const { return TM.getTargetTriple(); }
const SuperHInstrInfo *getInstrInfo() const override { return &InstrInfo; }
- const TargetFrameLowering *getFrameLowering() const override { return &FrameLowering; }
- const SuperHRegisterInfo *getRegisterInfo() const override { return &InstrInfo.getRegisterInfo(); }
- const SuperHSelectionDAGInfo *getSelectionDAGInfo() const override { return &TSInfo; }
- const SuperHTargetLowering *getTargetLowering() const override { return &TLInfo; }
+ const TargetFrameLowering *getFrameLowering() const override {
+ return &FrameLowering;
+ }
+ const SuperHRegisterInfo *getRegisterInfo() const override {
+ return &InstrInfo.getRegisterInfo();
+ }
+ const SuperHSelectionDAGInfo *getSelectionDAGInfo() const override {
+ return &TSInfo;
+ }
+ const SuperHTargetLowering *getTargetLowering() const override {
+ return &TLInfo;
+ }
bool isLittleEndian() const { return getTargetTriple().isLittleEndian(); }
bool isTargetELF() const { return getTargetTriple().isOSBinFormatELF(); }
@@ -87,7 +89,8 @@ public:
/// Classify a global function reference for the current subtarget.
SHRefClass classifyGlobalFunctionReference(const GlobalValue *GV,
const Module &M) const;
- SHRefClass classifyGlobalFunctionReference(const GlobalValue *GV) const override;
+ SHRefClass
+ classifyGlobalFunctionReference(const GlobalValue *GV) const override;
/// Classify a blockaddress reference for the current subtarget according to
/// how we should reference it in a non-pcrel context.
@@ -100,8 +103,7 @@ public:
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
- SuperHSubtarget &initializeSubtargetDependencies(StringRef CPU,
- StringRef FS);
+ SuperHSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
};
} // end namespace llvm
diff --git a/llvm/lib/Target/SuperH/SuperHTargetMachine.cpp b/llvm/lib/Target/SuperH/SuperHTargetMachine.cpp
index ecfb86165..161537b50 100644
--- a/llvm/lib/Target/SuperH/SuperHTargetMachine.cpp
+++ b/llvm/lib/Target/SuperH/SuperHTargetMachine.cpp
@@ -12,8 +12,8 @@
#include "SuperHTargetMachine.h"
#include "SuperH.h"
-#include "SuperHSubtarget.h"
#include "SuperHMachineFunctionInfo.h"
+#include "SuperHSubtarget.h"
#include "TargetInfo/SuperHTargetInfo.h"
#include "llvm/CodeGen/BranchFoldingPass.h"
#include "llvm/CodeGen/Passes.h"
@@ -46,7 +46,7 @@ namespace {
class SuperHPassConfig : public TargetPassConfig {
public:
SuperHPassConfig(SuperHTargetMachine &TM, PassManagerBase &PM)
- : TargetPassConfig(TM, PM) {}
+ : TargetPassConfig(TM, PM) {}
bool addInstSelector() override;
void addPostRegAlloc() override;
@@ -77,7 +77,6 @@ void SuperHPassConfig::addPreEmitPass2() {
} // namespace
-
//
// TARGET MACHINE
//
@@ -93,8 +92,8 @@ SuperHTargetMachine::SuperHTargetMachine(const Target &T, const Triple &TT,
CodeGenOptLevel OL, bool JIT)
: CodeGenTargetMachineImpl(T, TT.computeDataLayout(), TT, CPU, FS, Options,
RM.value_or(Reloc::Static),
- getEffectiveCodeModel(CM, CodeModel::Small),
- OL), TLOF(std::make_unique<TargetLoweringObjectFileELF>()) {
+ getEffectiveCodeModel(CM, CodeModel::Small), OL),
+ TLOF(std::make_unique<TargetLoweringObjectFileELF>()) {
initAsmInfo();
}
@@ -117,9 +116,9 @@ SuperHTargetMachine::getSubtargetImpl(const Function &F) const {
return ST.get();
}
-MachineFunctionInfo *
-SuperHTargetMachine::createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
- const TargetSubtargetInfo *STI) const {
- return SuperHMachineFunctionInfo::create<SuperHMachineFunctionInfo>(Allocator, F,
- STI);
+MachineFunctionInfo *SuperHTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return SuperHMachineFunctionInfo::create<SuperHMachineFunctionInfo>(Allocator,
+ F, STI);
}
\ No newline at end of file
diff --git a/llvm/lib/Target/SuperH/SuperHTargetMachine.h b/llvm/lib/Target/SuperH/SuperHTargetMachine.h
index 63b722fff..ae01e8395 100644
--- a/llvm/lib/Target/SuperH/SuperHTargetMachine.h
+++ b/llvm/lib/Target/SuperH/SuperHTargetMachine.h
@@ -1,4 +1,5 @@
-//===-- SuperHTargetMachine.h - Define TargetMachine for SuperH ---*- C++ -*-===//
+//===-- SuperHTargetMachine.h - Define TargetMachine for SuperH ---*- C++
+//-*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -27,10 +28,10 @@ class SuperHTargetMachine : public CodeGenTargetMachineImpl {
public:
SuperHTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
- StringRef FS, const TargetOptions &Options,
- std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
- bool JIT);
+ StringRef FS, const TargetOptions &Options,
+ std::optional<Reloc::Model> RM,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
+ bool JIT);
~SuperHTargetMachine() override;
MachineFunctionInfo *
@@ -42,7 +43,6 @@ public:
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
-
};
} // end namespace llvm
diff --git a/llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.cpp b/llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.cpp
index f206de2da..65ea51738 100644
--- a/llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.cpp
+++ b/llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.cpp
@@ -1,4 +1,5 @@
-//===-- SuperHTargetInfo.cpp - SuperH Target Implementation -----------------===//
+//===-- SuperHTargetInfo.cpp - SuperH Target Implementation
+//-----------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -22,10 +23,10 @@ Target &llvm::getTheSuperHLETarget() {
return TheSuperHLETarget;
}
-extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY
-void LLVMInitializeSuperHTargetInfo() {
- RegisterTarget<Triple::sh, /*HasJIT=*/false> X(getTheSuperHTarget(),
- "sh", "SuperH (big endian)", "SuperH");
- RegisterTarget<Triple::shl, /*HasJIT=*/false> Y(getTheSuperHLETarget(),
- "shl", "SuperH (little endian)", "SuperH");
+extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
+LLVMInitializeSuperHTargetInfo() {
+ RegisterTarget<Triple::sh, /*HasJIT=*/false> X(
+ getTheSuperHTarget(), "sh", "SuperH (big endian)", "SuperH");
+ RegisterTarget<Triple::shl, /*HasJIT=*/false> Y(
+ getTheSuperHLETarget(), "shl", "SuperH (little endian)", "SuperH");
}
diff --git a/llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.h b/llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.h
index 9dbef1aa0..0542821c4 100644
--- a/llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.h
+++ b/llvm/lib/Target/SuperH/TargetInfo/SuperHTargetInfo.h
@@ -1,4 +1,5 @@
-//===-- SuperHTargetInfo.h - SuperH Target Implementation ---------*- C++ -*-===//
+//===-- SuperHTargetInfo.h - SuperH Target Implementation ---------*- C++
+//-*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
``````````
</details>
https://github.com/llvm/llvm-project/pull/181287
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