[clang] [llvm] [AMDGPU] Implement AsyncMark Stages (PR #220442)

[Ryan Mitchell via cfe-commits]

RyanRio wrote:

Yeah I understand your POV, I'm (relatively confident) the indepedent stages are more useful in kernels. Thanks for providing the detailed example.

> I think I'm starting to come around to asyncmark(A | B) being two things you can wait on with asyncwait(A) and asyncwait(B) ... but I'd like to note that, for example, loads to and stores from LDS use different stages but the same counter, so asyncmark(ASYNC_LOAD_TO_LDS | ASYNC_STORE_FROM_LDS) might be tricky under the multiple-sequences approach?

So let's create the example -

```c++
async.load.to.lds()
async.load.to.lds()
async.store.from.lds()
asyncmark(ASYNC_LOAD_TO_LDS | ASYNC_STORE_FROM_LDS) A
...
wait_asyncmark(ASYNC_LOAD_TO_LDS) B
...
wait_asyncmark(ASYNC_STORE_FROM_LDS) C
```

2 potential lowerings -
```c++
async.load.to.lds()
async.load.to.lds()
async.store.from.lds()
; asyncmark(ASYNC_LOAD_TO_LDS | ASYNC_STORE_FROM_LDS) A
...
wait_dscnt 1
...
wait_dscnt 0
```

```c++
async.load.to.lds()
async.load.to.lds()
async.store.from.lds()
; asyncmark(ASYNC_LOAD_TO_LDS | ASYNC_STORE_FROM_LDS) A
...
wait_dscnt 0
...
; wait.asyncmark(...)
```
The first example is if async load and async store ARE ordered with each other, the compiler can know that it can do a wait_dscnt 1, vs in example B, they are not ordered with each other, the compiler has to do a wait 0. However, this translates fine to the higher level model because async_load_to_lds and async_store_from_lds are different stages, the compiler does not make any argument that at wait.asyncmark(ASYNC_STORE_FROM_LDS) **ONLY** operations in ASYNC_STORE_FROM_LDS, it says that **at least** all operations in ASYNC_STORE_FROM_LDS are complete.

https://github.com/llvm/llvm-project/pull/220442