[clang] [llvm] [RISCV] Bump experimental Zibi to version 0.7 (PR #223578)
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Mon Sep 14 19:31:09 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clang-driver
Author: Zeyi Xu (zeyi2)
<details>
<summary>Changes</summary>
The Zibi v0.1 release link is no longer available.
This commit updates the documentation to the corresponding commit v0.1 draft specification instead.
---
Full diff: https://github.com/llvm/llvm-project/pull/223578.diff
10 Files Affected:
- (modified) bolt/test/RISCV/conditional-tail-call-zibi.s (+1-1)
- (modified) bolt/test/RISCV/invert-branch-zibi.s (+1-1)
- (modified) clang/test/Driver/print-supported-extensions-riscv.c (+1-1)
- (modified) clang/test/Driver/riscv-arch.c (+4-4)
- (modified) clang/test/Preprocessor/riscv-target-features.c (+2-2)
- (modified) llvm/docs/RISCVUsage.md (+1-1)
- (modified) llvm/docs/ReleaseNotes.md (+1)
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+1-1)
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+2-2)
- (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+3-3)
``````````diff
diff --git a/bolt/test/RISCV/conditional-tail-call-zibi.s b/bolt/test/RISCV/conditional-tail-call-zibi.s
index 3bfa051339a2d..9006f0bf8b15f 100644
--- a/bolt/test/RISCV/conditional-tail-call-zibi.s
+++ b/bolt/test/RISCV/conditional-tail-call-zibi.s
@@ -22,7 +22,7 @@
// DISASM-NEXT: {{.*}} j {{.*}} <callee>
// DISASM-NEXT: {{.*}} ret
- .attribute arch, "rv64i2p1_zibi0p1"
+ .attribute arch, "rv64i2p1_zibi0p7"
.text
.globl conditional_tail_calls
diff --git a/bolt/test/RISCV/invert-branch-zibi.s b/bolt/test/RISCV/invert-branch-zibi.s
index 92cebdbef0c94..095c7d1c154a5 100644
--- a/bolt/test/RISCV/invert-branch-zibi.s
+++ b/bolt/test/RISCV/invert-branch-zibi.s
@@ -2,7 +2,7 @@
// correctly inverts the Zibi branch-with-immediate instructions
// (beqi/bnei) when the hot successor becomes the fallthrough block.
-// RUN: %clang %cflags64 -march=rv64gc_zibi0p1 -menable-experimental-extensions \
+// RUN: %clang %cflags64 -march=rv64gc_zibi0p7 -menable-experimental-extensions \
// RUN: -Wl,-q %s -o %t
// RUN: link_fdata --no-lbr %s %t %t.fdata
// RUN: llvm-bolt %t -o %t.bolt --data %t.fdata --reorder-blocks=ext-tsp
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 9953a331e67f8..824824309b8ed 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -249,7 +249,7 @@
// CHECK-NEXT: Experimental extensions
// CHECK-NEXT: p 0.21 'P' ('Base P' (Packed SIMD))
// CHECK-NEXT: y 0.98 'Y' ('Base Y' (CHERI))
-// CHECK-NEXT: zibi 0.1 'Zibi' (Branch with Immediate)
+// CHECK-NEXT: zibi 0.7 'Zibi' (Branch with Immediate)
// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad)
// CHECK-NEXT: zilx 0.1 'Zilx' (Indexed Integer Load Instructions)
// CHECK-NEXT: zvabd 0.9 'Zvabd' (Vector Absolute Difference)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 0fd389faa969f..1ad8813726a78 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -381,12 +381,12 @@
// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izibi'
// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izibi0p7 -menable-experimental-extensions -### %s \
+// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izibi0p1 -menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s
-// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izibi0p7'
-// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental extension 'zibi' (this compiler supports 0.1)
+// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izibi0p1'
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension 'zibi' (this compiler supports 0.7)
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32izibi0p1 -menable-experimental-extensions -### %s \
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izibi0p7 -menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zibi"
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 54dce4ffd93e4..e86aabb2941f7 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -868,10 +868,10 @@
// CHECK-ZHINXMIN-EXT: __riscv_zhinxmin 1000000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zibi0p1 -E -dM %s \
+// RUN: -march=rv32i_zibi0p7 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZIBI-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zibi0p1 -E -dM %s \
+// RUN: -march=rv64i_zibi0p7 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZIBI-EXT %s
// CHECK-ZIBI-EXT: __riscv_zibi
diff --git a/llvm/docs/RISCVUsage.md b/llvm/docs/RISCVUsage.md
index fd822d3627a99..4ee181281d898 100644
--- a/llvm/docs/RISCVUsage.md
+++ b/llvm/docs/RISCVUsage.md
@@ -343,7 +343,7 @@ The primary goal of experimental support is to assist in the process of ratifica
`experimental-zibi`
-: LLVM implements the [0.1 release specification](https://github.com/riscv/zibi/releases/tag/v0.1.0).
+: LLVM implements the [0.7 draft specification](https://github.com/riscv/zibi/releases/tag/riscv-isa-release-aa5e27f-2026-07-30).
`experimental-zicfilp`, `experimental-zicfiss`
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 4acfcaf3204a7..2ed39e48f0bec 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -240,6 +240,7 @@ Makes programs 10x faster by doing Special New Thing.
* Bump Svukte extension to 1.0.
* Remove experimental from Zicfiss.
* Added support for `Sspmp`, `Sspmpen` and `Smpmpdeleg` extensions.
+* Bumped the supported version of the experimental `Zibi` extension from 0.1 to 0.7.
* Removed veyron-v1 processor definition and tuning model.
* Removed support for the `Ventana Conditional Operations` extension.
* Added support for `tail symbol, rt` form that takes an address (materialisation)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index d2c24c3f22928..7acf4b72b24c7 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -79,7 +79,7 @@ def FeatureStdExtE
RISCVExtensionBitmask<0, 4>;
def FeatureStdExtZibi
- : RISCVExperimentalExtension<0, 1, "Branch with Immediate">,
+ : RISCVExperimentalExtension<0, 7, "Branch with Immediate">,
RISCVExtensionBitmask<1, 13>;
def HasStdExtZibi : Predicate<"Subtarget->hasStdExtZibi()">,
AssemblerPredicate<(all_of FeatureStdExtZibi),
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index c9542a563952c..97c27a52a83d9 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -530,7 +530,7 @@
; RV32SMCTR: .attribute 5, "rv32i2p1_smctr1p0_sscsrind1p0"
; RV32SSCTR: .attribute 5, "rv32i2p1_sscsrind1p0_ssctr1p0"
; RV32P: .attribute 5, "rv32i2p1_p0p21_zicsr2p0_zmmul1p0_zba1p0_zbb1p0"
-; RV32ZIBI: .attribute 5, "rv32i2p1_zibi0p1"
+; RV32ZIBI: .attribute 5, "rv32i2p1_zibi0p7"
; RV32ZVQWBDOTA8I: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvqwbdota8i0p2"
; RV32ZVQWBDOTA16I: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_zvqwbdota16i0p2"
; RV32ZVFWBDOTA16BF: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfwbdota16bf0p2_zvl32b1p0"
@@ -708,7 +708,7 @@
; RV64SDTRIG: .attribute 5, "rv64i2p1_sdtrig1p0"
; RV64P: .attribute 5, "rv64i2p1_p0p21_zicsr2p0_zmmul1p0_zba1p0_zbb1p0"
; RV64Y: .attribute 5, "rv64i2p1_y0p98"
-; RV64ZIBI: .attribute 5, "rv64i2p1_zibi0p1"
+; RV64ZIBI: .attribute 5, "rv64i2p1_zibi0p7"
; RV64ZVQWBDOTA8I: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvqwbdota8i0p2"
; RV64ZVQWBDOTA16I: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_zvqwbdota16i0p2"
; RV64ZVFWBDOTA16BF: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfwbdota16bf0p2_zvl32b1p0"
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 25d9a573f0ce7..727df1aace87b 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -631,7 +631,7 @@ TEST(ParseArchString,
const auto &Exts = (*MaybeISAInfo)->getExtensions();
EXPECT_EQ(Exts.size(), 2UL);
EXPECT_EQ(Exts.count("zibi"), 1U);
- auto MaybeISAInfo2 = RISCVISAInfo::parseArchString("rv64izibi0p1", true);
+ auto MaybeISAInfo2 = RISCVISAInfo::parseArchString("rv64izibi0p7", true);
ASSERT_THAT_EXPECTED(MaybeISAInfo2, Succeeded());
const auto &Exts2 = (*MaybeISAInfo2)->getExtensions();
EXPECT_EQ(Exts2.size(), 2UL);
@@ -659,7 +659,7 @@ TEST(ParseArchString, RejectsUnrecognizedVersionForExperimentalExtension) {
EXPECT_EQ(
toString(RISCVISAInfo::parseArchString("rv64izibi9p9", true).takeError()),
"unsupported version number 9.9 for experimental extension 'zibi' "
- "(this compiler supports 0.1)");
+ "(this compiler supports 0.7)");
EXPECT_EQ(
toString(RISCVISAInfo::parseArchString("rv64y0p97", true).takeError()),
"unsupported version number 0.97 for experimental extension 'y' "
@@ -1638,7 +1638,7 @@ R"(All available -march extensions for RISC-V
Experimental extensions
p 0.21
y 0.98
- zibi 0.1
+ zibi 0.7
zicfilp 1.0 This is a long dummy description
zilx 0.1
zvabd 0.9
``````````
</details>
https://github.com/llvm/llvm-project/pull/223578
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