[clang] [CIR][AArch64] Port f64 tests for v8.5 rounding NEON builtins (PR #221389)
Vicky Nguyen via cfe-commits
cfe-commits at lists.llvm.org
Tue Sep 8 22:02:38 PDT 2026
https://github.com/iamvickynguyen updated https://github.com/llvm/llvm-project/pull/221389
>From 53f30f2598c8561b88c0439acc438441cf558a5c Mon Sep 17 00:00:00 2001
From: Vicky Nguyen <vicky.trucviennguyen at gmail.com>
Date: Fri, 4 Sep 2026 21:40:49 -0700
Subject: [PATCH] [CIR][AArch64] Port f64 tests for v8.5 rounding NEON builtins
---
clang/test/CodeGen/AArch64/neon/intrinsics.c | 472 -----------------
.../test/CodeGen/AArch64/neon/rounding-v8.5.c | 140 ++++-
clang/test/CodeGen/AArch64/neon/rounding.c | 492 ++++++++++++++++++
.../AArch64/v8.5a-neon-frint3264-intrinsic.c | 145 ------
4 files changed, 624 insertions(+), 625 deletions(-)
create mode 100644 clang/test/CodeGen/AArch64/neon/rounding.c
delete mode 100644 clang/test/CodeGen/AArch64/v8.5a-neon-frint3264-intrinsic.c
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index d6da96f368fcc..6d46e7ad8a8f3 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -8320,478 +8320,6 @@ uint64x2_t test_vshll_high_n_u32(uint32x4_t a) {
return vshll_high_n_u32(a, 19);
}
-//===------------------------------------------------------===//
-// 2.1.1.9. Rounding
-//https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#rounding
-//===------------------------------------------------------===//
-
-// LLVM-LABEL: @test_vrnd_f32(
-// CIR-LABEL: @vrnd_f32(
-float32x2_t test_vrnd_f32(float32x2_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float>
-// CIR: cir.trunc [[CAST]] : !cir.vector<2 x !cir.float>
-
-// LLVM-SAME: <2 x float> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
-// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// LLVM: [[VRND_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
-// LLVM: [[VRND1_I:%.*]] = call <2 x float> @llvm.trunc.v2f32(<2 x float> [[VRND_I]])
-// LLVM: ret <2 x float> [[VRND1_I]]
- return vrnd_f32(a);
-}
-
-// LLVM-LABEL: @test_vrndq_f32(
-// CIR-LABEL: @vrndq_f32(
-float32x4_t test_vrndq_f32(float32x4_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float>
-// CIR: cir.trunc [[CAST]] : !cir.vector<4 x !cir.float>
-
-// LLVM-SAME: <4 x float> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
-// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// LLVM: [[VRND_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
-// LLVM: [[VRND1_I:%.*]] = call <4 x float> @llvm.trunc.v4f32(<4 x float> [[VRND_I]])
-// LLVM: ret <4 x float> [[VRND1_I]]
- return vrndq_f32(a);
-}
-
-// LLVM-LABEL: @test_vrnd_f64(
-// CIR-LABEL: @vrnd_f64(
-float64x1_t test_vrnd_f64(float64x1_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double>
-// CIR: cir.trunc [[CAST]] : !cir.vector<1 x !cir.double>
-
-// LLVM-SAME: <1 x double> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
-// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8>
-// LLVM: [[VRND_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double>
-// LLVM: [[VRND1_I:%.*]] = call <1 x double> @llvm.trunc.v1f64(<1 x double> [[VRND_I]])
-// LLVM: ret <1 x double> [[VRND1_I]]
- return vrnd_f64(a);
-}
-
-// LLVM-LABEL: @test_vrndq_f64(
-// CIR-LABEL: @vrndq_f64(
-float64x2_t test_vrndq_f64(float64x2_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double>
-// CIR: cir.trunc [[CAST]] : !cir.vector<2 x !cir.double>
-
-// LLVM-SAME: <2 x double> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
-// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// LLVM: [[VRND_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
-// LLVM: [[VRND1_I:%.*]] = call <2 x double> @llvm.trunc.v2f64(<2 x double> [[VRND_I]])
-// LLVM: ret <2 x double> [[VRND1_I]]
- return vrndq_f64(a);
-}
-
-// LLVM-LABEL: @test_vrndn_f32(
-// CIR-LABEL: @vrndn_f32(
-float32x2_t test_vrndn_f32(float32x2_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float>
-// CIR: cir.roundeven [[CAST]] : !cir.vector<2 x !cir.float>
-
-// LLVM-SAME: <2 x float> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
-// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// LLVM: [[VRNDN_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
-// LLVM: [[VRNDN1_I:%.*]] = call <2 x float> @llvm.roundeven.v2f32(<2 x float> [[VRNDN_I]])
-// LLVM: ret <2 x float> [[VRNDN1_I]]
- return vrndn_f32(a);
-}
-
-// LLVM-LABEL: @test_vrndnq_f32(
-// CIR-LABEL: @vrndnq_f32(
-float32x4_t test_vrndnq_f32(float32x4_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float>
-// CIR: cir.roundeven [[CAST]] : !cir.vector<4 x !cir.float>
-
-// LLVM-SAME: <4 x float> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
-// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// LLVM: [[VRNDN_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
-// LLVM: [[VRNDN1_I:%.*]] = call <4 x float> @llvm.roundeven.v4f32(<4 x float> [[VRNDN_I]])
-// LLVM: ret <4 x float> [[VRNDN1_I]]
- return vrndnq_f32(a);
-}
-
-// LLVM-LABEL: @test_vrndn_f64(
-// CIR-LABEL: @vrndn_f64(
-float64x1_t test_vrndn_f64(float64x1_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double>
-// CIR: cir.roundeven [[CAST]] : !cir.vector<1 x !cir.double>
-
-// LLVM-SAME: <1 x double> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
-// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8>
-// LLVM: [[VRNDN_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double>
-// LLVM: [[VRNDN1_I:%.*]] = call <1 x double> @llvm.roundeven.v1f64(<1 x double> [[VRNDN_I]])
-// LLVM: ret <1 x double> [[VRNDN1_I]]
- return vrndn_f64(a);
-}
-
-// LLVM-LABEL: @test_vrndnq_f64(
-// CIR-LABEL: @vrndnq_f64(
-float64x2_t test_vrndnq_f64(float64x2_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double>
-// CIR: cir.roundeven [[CAST]] : !cir.vector<2 x !cir.double>
-
-// LLVM-SAME: <2 x double> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
-// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// LLVM: [[VRNDN_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
-// LLVM: [[VRNDN1_I:%.*]] = call <2 x double> @llvm.roundeven.v2f64(<2 x double> [[VRNDN_I]])
-// LLVM: ret <2 x double> [[VRNDN1_I]]
- return vrndnq_f64(a);
-}
-
-// LLVM-LABEL: @test_vrndns_f32(
-// CIR-LABEL: @vrndns_f32(
-float32_t test_vrndns_f32(float32_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.float>, !cir.float
-// CIR: cir.roundeven [[LOAD]] : !cir.float
-
-// LLVM-SAME: float noundef [[A:%.*]])
-// LLVM: [[VRNDN_I:%.*]] = call float @llvm.roundeven.f32(float [[A]])
-// LLVM: ret float [[VRNDN_I]]
- return vrndns_f32(a);
-}
-
-// LLVM-LABEL: @test_vrndm_f32(
-// CIR-LABEL: @vrndm_f32(
-float32x2_t test_vrndm_f32(float32x2_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float>
-// CIR: cir.floor [[CAST]] : !cir.vector<2 x !cir.float>
-
-// LLVM-SAME: <2 x float> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
-// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// LLVM: [[VRNDM_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
-// LLVM: [[VRNDM1_I:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> [[VRNDM_I]])
-// LLVM: ret <2 x float> [[VRNDM1_I]]
- return vrndm_f32(a);
-}
-
-// LLVM-LABEL: @test_vrndmq_f32(
-// CIR-LABEL: @vrndmq_f32(
-float32x4_t test_vrndmq_f32(float32x4_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float>
-// CIR: cir.floor [[CAST]] : !cir.vector<4 x !cir.float>
-
-// LLVM-SAME: <4 x float> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
-// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// LLVM: [[VRNDM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
-// LLVM: [[VRNDM1_I:%.*]] = call <4 x float> @llvm.floor.v4f32(<4 x float> [[VRNDM_I]])
-// LLVM: ret <4 x float> [[VRNDM1_I]]
- return vrndmq_f32(a);
-}
-
-// LLVM-LABEL: @test_vrndm_f64(
-// CIR-LABEL: @vrndm_f64(
-float64x1_t test_vrndm_f64(float64x1_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double>
-// CIR: cir.floor [[CAST]] : !cir.vector<1 x !cir.double>
-
-// LLVM-SAME: <1 x double> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
-// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8>
-// LLVM: [[VRNDM_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double>
-// LLVM: [[VRNDM1_I:%.*]] = call <1 x double> @llvm.floor.v1f64(<1 x double> [[VRNDM_I]])
-// LLVM: ret <1 x double> [[VRNDM1_I]]
- return vrndm_f64(a);
-}
-
-// LLVM-LABEL: @test_vrndmq_f64(
-// CIR-LABEL: @vrndmq_f64(
-float64x2_t test_vrndmq_f64(float64x2_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double>
-// CIR: cir.floor [[CAST]] : !cir.vector<2 x !cir.double>
-
-// LLVM-SAME: <2 x double> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
-// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// LLVM: [[VRNDM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
-// LLVM: [[VRNDM1_I:%.*]] = call <2 x double> @llvm.floor.v2f64(<2 x double> [[VRNDM_I]])
-// LLVM: ret <2 x double> [[VRNDM1_I]]
- return vrndmq_f64(a);
-}
-
-// LLVM-LABEL: @test_vrndp_f32(
-// CIR-LABEL: @vrndp_f32(
-float32x2_t test_vrndp_f32(float32x2_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float>
-// CIR: cir.ceil [[CAST]] : !cir.vector<2 x !cir.float>
-
-// LLVM-SAME: <2 x float> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
-// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// LLVM: [[VRNDP_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
-// LLVM: [[VRNDP1_I:%.*]] = call <2 x float> @llvm.ceil.v2f32(<2 x float> [[VRNDP_I]])
-// LLVM: ret <2 x float> [[VRNDP1_I]]
- return vrndp_f32(a);
-}
-
-// LLVM-LABEL: @test_vrndpq_f32(
-// CIR-LABEL: @vrndpq_f32(
-float32x4_t test_vrndpq_f32(float32x4_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float>
-// CIR: cir.ceil [[CAST]] : !cir.vector<4 x !cir.float>
-
-// LLVM-SAME: <4 x float> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
-// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// LLVM: [[VRNDP_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
-// LLVM: [[VRNDP1_I:%.*]] = call <4 x float> @llvm.ceil.v4f32(<4 x float> [[VRNDP_I]])
-// LLVM: ret <4 x float> [[VRNDP1_I]]
- return vrndpq_f32(a);
-}
-
-// LLVM-LABEL: @test_vrndp_f64(
-// CIR-LABEL: @vrndp_f64(
-float64x1_t test_vrndp_f64(float64x1_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double>
-// CIR: cir.ceil [[CAST]] : !cir.vector<1 x !cir.double>
-
-// LLVM-SAME: <1 x double> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
-// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8>
-// LLVM: [[VRNDP_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double>
-// LLVM: [[VRNDP1_I:%.*]] = call <1 x double> @llvm.ceil.v1f64(<1 x double> [[VRNDP_I]])
-// LLVM: ret <1 x double> [[VRNDP1_I]]
- return vrndp_f64(a);
-}
-
-// LLVM-LABEL: @test_vrndpq_f64(
-// CIR-LABEL: @vrndpq_f64(
-float64x2_t test_vrndpq_f64(float64x2_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double>
-// CIR: cir.ceil [[CAST]] : !cir.vector<2 x !cir.double>
-
-// LLVM-SAME: <2 x double> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
-// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// LLVM: [[VRNDP_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
-// LLVM: [[VRNDP1_I:%.*]] = call <2 x double> @llvm.ceil.v2f64(<2 x double> [[VRNDP_I]])
-// LLVM: ret <2 x double> [[VRNDP1_I]]
- return vrndpq_f64(a);
-}
-
-// LLVM-LABEL: @test_vrnda_f32(
-// CIR-LABEL: @vrnda_f32(
-float32x2_t test_vrnda_f32(float32x2_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float>
-// CIR: cir.round [[CAST]] : !cir.vector<2 x !cir.float>
-
-// LLVM-SAME: <2 x float> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
-// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// LLVM: [[VRNDA_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
-// LLVM: [[VRNDA1_I:%.*]] = call <2 x float> @llvm.round.v2f32(<2 x float> [[VRNDA_I]])
-// LLVM: ret <2 x float> [[VRNDA1_I]]
- return vrnda_f32(a);
-}
-
-// LLVM-LABEL: @test_vrndaq_f32(
-// CIR-LABEL: @vrndaq_f32(
-float32x4_t test_vrndaq_f32(float32x4_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float>
-// CIR: cir.round [[CAST]] : !cir.vector<4 x !cir.float>
-
-// LLVM-SAME: <4 x float> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
-// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// LLVM: [[VRNDA_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
-// LLVM: [[VRNDA1_I:%.*]] = call <4 x float> @llvm.round.v4f32(<4 x float> [[VRNDA_I]])
-// LLVM: ret <4 x float> [[VRNDA1_I]]
- return vrndaq_f32(a);
-}
-
-// LLVM-LABEL: @test_vrnda_f64(
-// CIR-LABEL: @vrnda_f64(
-float64x1_t test_vrnda_f64(float64x1_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double>
-// CIR: cir.round [[CAST]] : !cir.vector<1 x !cir.double>
-
-// LLVM-SAME: <1 x double> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
-// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8>
-// LLVM: [[VRNDA_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double>
-// LLVM: [[VRNDA1_I:%.*]] = call <1 x double> @llvm.round.v1f64(<1 x double> [[VRNDA_I]])
-// LLVM: ret <1 x double> [[VRNDA1_I]]
- return vrnda_f64(a);
-}
-
-// LLVM-LABEL: @test_vrndaq_f64(
-// CIR-LABEL: @vrndaq_f64(
-float64x2_t test_vrndaq_f64(float64x2_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double>
-// CIR: cir.round [[CAST]] : !cir.vector<2 x !cir.double>
-
-// LLVM-SAME: <2 x double> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
-// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// LLVM: [[VRNDA_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
-// LLVM: [[VRNDA1_I:%.*]] = call <2 x double> @llvm.round.v2f64(<2 x double> [[VRNDA_I]])
-// LLVM: ret <2 x double> [[VRNDA1_I]]
- return vrndaq_f64(a);
-}
-
-// LLVM-LABEL: @test_vrndi_f32(
-// CIR-LABEL: @vrndi_f32(
-float32x2_t test_vrndi_f32(float32x2_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float>
-// CIR: cir.nearbyint [[CAST]] : !cir.vector<2 x !cir.float>
-
-// LLVM-SAME: <2 x float> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
-// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// LLVM: [[VRNDI_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
-// LLVM: [[VRNDI_V1_I:%.*]] = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> [[VRNDI_V_I]])
-// LLVM: ret <2 x float> [[VRNDI_V1_I]]
- return vrndi_f32(a);
-}
-
-// LLVM-LABEL: @test_vrndiq_f32(
-// CIR-LABEL: @vrndiq_f32(
-float32x4_t test_vrndiq_f32(float32x4_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float>
-// CIR: cir.nearbyint [[CAST]] : !cir.vector<4 x !cir.float>
-
-// LLVM-SAME: <4 x float> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
-// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// LLVM: [[VRNDIQ_V_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
-// LLVM: [[VRNDIQ_V1_I:%.*]] = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> [[VRNDIQ_V_I]])
-// LLVM: ret <4 x float> [[VRNDIQ_V1_I]]
- return vrndiq_f32(a);
-}
-
-// LLVM-LABEL: @test_vrndi_f64(
-// CIR-LABEL: @vrndi_f64(
-float64x1_t test_vrndi_f64(float64x1_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double>
-// CIR: cir.nearbyint [[CAST]] : !cir.vector<1 x !cir.double>
-
-// LLVM-SAME: <1 x double> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
-// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8>
-// LLVM: [[VRNDI_V_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double>
-// LLVM: [[VRNDI_V1_I:%.*]] = call <1 x double> @llvm.nearbyint.v1f64(<1 x double> [[VRNDI_V_I]])
-// LLVM: ret <1 x double> [[VRNDI_V1_I]]
- return vrndi_f64(a);
-}
-
-// LLVM-LABEL: @test_vrndiq_f64(
-// CIR-LABEL: @vrndiq_f64(
-float64x2_t test_vrndiq_f64(float64x2_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double>
-// CIR: cir.nearbyint [[CAST]] : !cir.vector<2 x !cir.double>
-
-// LLVM-SAME: <2 x double> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
-// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// LLVM: [[VRNDI_V_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
-// LLVM: [[VRNDI_V1_I:%.*]] = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> [[VRNDI_V_I]])
-// LLVM: ret <2 x double> [[VRNDI_V1_I]]
- return vrndiq_f64(a);
-}
-
-// LLVM-LABEL: @test_vrndx_f32(
-// CIR-LABEL: @vrndx_f32(
-float32x2_t test_vrndx_f32(float32x2_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float>
-// CIR: cir.rint [[CAST]] : !cir.vector<2 x !cir.float>
-
-// LLVM-SAME: <2 x float> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
-// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// LLVM: [[VRNDX_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
-// LLVM: [[VRNDX1_I:%.*]] = call <2 x float> @llvm.rint.v2f32(<2 x float> [[VRNDX_I]])
-// LLVM: ret <2 x float> [[VRNDX1_I]]
- return vrndx_f32(a);
-}
-
-// LLVM-LABEL: @test_vrndxq_f32(
-// CIR-LABEL: @vrndxq_f32(
-float32x4_t test_vrndxq_f32(float32x4_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float>
-// CIR: cir.rint [[CAST]] : !cir.vector<4 x !cir.float>
-
-// LLVM-SAME: <4 x float> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
-// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// LLVM: [[VRNDX_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
-// LLVM: [[VRNDX1_I:%.*]] = call <4 x float> @llvm.rint.v4f32(<4 x float> [[VRNDX_I]])
-// LLVM: ret <4 x float> [[VRNDX1_I]]
- return vrndxq_f32(a);
-}
-
-// LLVM-LABEL: @test_vrndx_f64(
-// CIR-LABEL: @vrndx_f64(
-float64x1_t test_vrndx_f64(float64x1_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double>
-// CIR: cir.rint [[CAST]] : !cir.vector<1 x !cir.double>
-
-// LLVM-SAME: <1 x double> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
-// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8>
-// LLVM: [[VRNDX_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double>
-// LLVM: [[VRNDX1_I:%.*]] = call <1 x double> @llvm.rint.v1f64(<1 x double> [[VRNDX_I]])
-// LLVM: ret <1 x double> [[VRNDX1_I]]
- return vrndx_f64(a);
-}
-
-// LLVM-LABEL: @test_vrndxq_f64(
-// CIR-LABEL: @vrndxq_f64(
-float64x2_t test_vrndxq_f64(float64x2_t a) {
-// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
-// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double>
-// CIR: cir.rint [[CAST]] : !cir.vector<2 x !cir.double>
-
-// LLVM-SAME: <2 x double> noundef [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
-// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// LLVM: [[VRNDX_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
-// LLVM: [[VRNDX1_I:%.*]] = call <2 x double> @llvm.rint.v2f64(<2 x double> [[VRNDX_I]])
-// LLVM: ret <2 x double> [[VRNDX1_I]]
- return vrndxq_f64(a);
-}
-
//===------------------------------------------------------===//
// 2.1.3.2.6. Vector saturating shift right and narrow
// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-saturating-shift-right-and-narrow
diff --git a/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c b/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c
index b95c63c1e611e..8506572b5fc13 100644
--- a/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c
+++ b/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c
@@ -18,7 +18,7 @@ float32x2_t test_vrnd32x_f32(float32x2_t a) {
// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float>
// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint32x" [[CAST]] : (!cir.vector<2 x !cir.float>) -> !cir.vector<2 x !cir.float>
-// LLVM-SAME: <2 x float> noundef [[A:%.*]])
+// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]])
// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
// LLVM: [[VRND32X_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
@@ -33,7 +33,7 @@ float32x4_t test_vrnd32xq_f32(float32x4_t a) {
// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float>
// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint32x" [[CAST]] : (!cir.vector<4 x !cir.float>) -> !cir.vector<4 x !cir.float>
-// LLVM-SAME: <4 x float> noundef [[A:%.*]])
+// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
// LLVM: [[VRND32XQ_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
@@ -48,7 +48,7 @@ float32x2_t test_vrnd32z_f32(float32x2_t a) {
// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float>
// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint32z" [[CAST]] : (!cir.vector<2 x !cir.float>) -> !cir.vector<2 x !cir.float>
-// LLVM-SAME: <2 x float> noundef [[A:%.*]])
+// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]])
// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
// LLVM: [[VRND32Z_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
@@ -63,7 +63,7 @@ float32x4_t test_vrnd32zq_f32(float32x4_t a) {
// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float>
// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint32z" [[CAST]] : (!cir.vector<4 x !cir.float>) -> !cir.vector<4 x !cir.float>
-// LLVM-SAME: <4 x float> noundef [[A:%.*]])
+// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
// LLVM: [[VRND32ZQ_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
@@ -78,7 +78,7 @@ float32x2_t test_vrnd64x_f32(float32x2_t a) {
// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float>
// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint64x" [[CAST]] : (!cir.vector<2 x !cir.float>) -> !cir.vector<2 x !cir.float>
-// LLVM-SAME: <2 x float> noundef [[A:%.*]])
+// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]])
// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
// LLVM: [[VRND64X_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
@@ -93,7 +93,7 @@ float32x4_t test_vrnd64xq_f32(float32x4_t a) {
// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float>
// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint64x" [[CAST]] : (!cir.vector<4 x !cir.float>) -> !cir.vector<4 x !cir.float>
-// LLVM-SAME: <4 x float> noundef [[A:%.*]])
+// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
// LLVM: [[VRND64XQ_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
@@ -108,7 +108,7 @@ float32x2_t test_vrnd64z_f32(float32x2_t a) {
// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float>
// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint64z" [[CAST]] : (!cir.vector<2 x !cir.float>) -> !cir.vector<2 x !cir.float>
-// LLVM-SAME: <2 x float> noundef [[A:%.*]])
+// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]])
// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
// LLVM: [[VRND64Z_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
@@ -123,10 +123,134 @@ float32x4_t test_vrnd64zq_f32(float32x4_t a) {
// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float>
// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint64z" [[CAST]] : (!cir.vector<4 x !cir.float>) -> !cir.vector<4 x !cir.float>
-// LLVM-SAME: <4 x float> noundef [[A:%.*]])
+// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
// LLVM: [[VRND64ZQ_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
// LLVM: [[VRND64ZQ1_I:%.*]] = call <4 x float> @llvm.aarch64.neon.frint64z.v4f32(<4 x float> [[VRND64ZQ_I]])
return vrnd64zq_f32(a);
}
+
+// LLVM-LABEL: @test_vrnd32x_f64(
+// CIR-LABEL: @vrnd32x_f64(
+float64x1_t test_vrnd32x_f64(float64x1_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double>
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint32x" [[CAST]] : (!cir.vector<1 x !cir.double>) -> !cir.vector<1 x !cir.double>
+
+// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
+// LLVM: [[INS:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
+// LLVM: [[TMP1:%.*]] = bitcast <1 x i64> [[INS]] to <8 x i8>
+// LLVM: [[VRND32X_F64_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
+// LLVM: [[VRND32X_F641_I:%.*]] = call <1 x double> @llvm.aarch64.neon.frint32x.v1f64(<1 x double> [[VRND32X_F64_I]])
+ return vrnd32x_f64(a);
+}
+
+// LLVM-LABEL: @test_vrnd32xq_f64(
+// CIR-LABEL: @vrnd32xq_f64(
+float64x2_t test_vrnd32xq_f64(float64x2_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double>
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint32x" [[CAST]] : (!cir.vector<2 x !cir.double>) -> !cir.vector<2 x !cir.double>
+
+// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// LLVM: [[VRND32XQ_F64_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
+// LLVM: [[VRND32XQ1_F64_I:%.*]] = call <2 x double> @llvm.aarch64.neon.frint32x.v2f64(<2 x double> [[VRND32XQ_F64_I]])
+ return vrnd32xq_f64(a);
+}
+
+// LLVM-LABEL: @test_vrnd32z_f64(
+// CIR-LABEL: @vrnd32z_f64(
+float64x1_t test_vrnd32z_f64(float64x1_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double>
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint32z" [[CAST]] : (!cir.vector<1 x !cir.double>) -> !cir.vector<1 x !cir.double>
+
+// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
+// LLVM: [[INS:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
+// LLVM: [[TMP1:%.*]] = bitcast <1 x i64> [[INS]] to <8 x i8>
+// LLVM: [[VRND32Z_F64_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
+// LLVM: [[VRND32Z_F641_I:%.*]] = call <1 x double> @llvm.aarch64.neon.frint32z.v1f64(<1 x double> [[VRND32Z_F64_I]])
+ return vrnd32z_f64(a);
+}
+
+// LLVM-LABEL: @test_vrnd32zq_f64(
+// CIR-LABEL: @vrnd32zq_f64(
+float64x2_t test_vrnd32zq_f64(float64x2_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double>
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint32z" [[CAST]] : (!cir.vector<2 x !cir.double>) -> !cir.vector<2 x !cir.double>
+
+// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// LLVM: [[VRND32ZQ_F64_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
+// LLVM: [[VRND32ZQ1_F64_I:%.*]] = call <2 x double> @llvm.aarch64.neon.frint32z.v2f64(<2 x double> [[VRND32ZQ_F64_I]])
+ return vrnd32zq_f64(a);
+}
+
+// LLVM-LABEL: @test_vrnd64x_f64(
+// CIR-LABEL: @vrnd64x_f64(
+float64x1_t test_vrnd64x_f64(float64x1_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double>
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint64x" [[CAST]] : (!cir.vector<1 x !cir.double>) -> !cir.vector<1 x !cir.double>
+
+// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
+// LLVM: [[INS:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
+// LLVM: [[TMP1:%.*]] = bitcast <1 x i64> [[INS]] to <8 x i8>
+// LLVM: [[VRND64X_F64_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
+// LLVM: [[VRND64X_F641_I:%.*]] = call <1 x double> @llvm.aarch64.neon.frint64x.v1f64(<1 x double> [[VRND64X_F64_I]])
+ return vrnd64x_f64(a);
+}
+
+// LLVM-LABEL: @test_vrnd64xq_f64(
+// CIR-LABEL: @vrnd64xq_f64(
+float64x2_t test_vrnd64xq_f64(float64x2_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double>
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint64x" [[CAST]] : (!cir.vector<2 x !cir.double>) -> !cir.vector<2 x !cir.double>
+
+// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// LLVM: [[VRND64XQ_F64_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
+// LLVM: [[VRND64XQ1_F64_I:%.*]] = call <2 x double> @llvm.aarch64.neon.frint64x.v2f64(<2 x double> [[VRND64XQ_F64_I]])
+ return vrnd64xq_f64(a);
+}
+
+// LLVM-LABEL: @test_vrnd64z_f64(
+// CIR-LABEL: @vrnd64z_f64(
+float64x1_t test_vrnd64z_f64(float64x1_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double>
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint64z" [[CAST]] : (!cir.vector<1 x !cir.double>) -> !cir.vector<1 x !cir.double>
+
+// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
+// LLVM: [[INS:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
+// LLVM: [[TMP1:%.*]] = bitcast <1 x i64> [[INS]] to <8 x i8>
+// LLVM: [[VRND64Z_F64_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
+// LLVM: [[VRND64Z_F641_I:%.*]] = call <1 x double> @llvm.aarch64.neon.frint64z.v1f64(<1 x double> [[VRND64Z_F64_I]])
+ return vrnd64z_f64(a);
+}
+
+// LLVM-LABEL: @test_vrnd64zq_f64(
+// CIR-LABEL: @vrnd64zq_f64(
+float64x2_t test_vrnd64zq_f64(float64x2_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double>
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint64z" [[CAST]] : (!cir.vector<2 x !cir.double>) -> !cir.vector<2 x !cir.double>
+
+// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// LLVM: [[VRND64ZQ_F64_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
+// LLVM: [[VRND64ZQ1_F64_I:%.*]] = call <2 x double> @llvm.aarch64.neon.frint64z.v2f64(<2 x double> [[VRND64ZQ_F64_I]])
+ return vrnd64zq_f64(a);
+}
diff --git a/clang/test/CodeGen/AArch64/neon/rounding.c b/clang/test/CodeGen/AArch64/neon/rounding.c
new file mode 100644
index 0000000000000..561c9dd2420e1
--- /dev/null
+++ b/clang/test/CodeGen/AArch64/neon/rounding.c
@@ -0,0 +1,492 @@
+// REQUIRES: aarch64-registered-target || arm-registered-target
+
+// RUN: %clang_cc1_cg_arm64_neon -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=LLVM
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -fclangir -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=LLVM %}
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -fclangir -emit-cir %s -disable-O0-optnone | FileCheck %s --check-prefixes=CIR %}
+
+//=============================================================================
+// NOTES
+//
+// This file contains tests that were originally located in
+// * clang/test/CodeGen/AArch64/neon-intrinsics.c.
+// The main difference is the use of RUN lines that enable ClangIR lowering;
+// therefore only builtins currently supported by ClangIR are tested here.
+//
+// Different labels for CIR stem from an additional function call that is
+// present at the AST and CIR levels, but is inlined at the LLVM IR level.
+//
+//=============================================================================
+
+#include <arm_neon.h>
+
+//===------------------------------------------------------===//
+// 2.1.1.9. Rounding
+//https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#rounding
+//===------------------------------------------------------===//
+
+// LLVM-LABEL: @test_vrnd_f32(
+// CIR-LABEL: @vrnd_f32(
+float32x2_t test_vrnd_f32(float32x2_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float>
+// CIR: cir.trunc [[CAST]] : !cir.vector<2 x !cir.float>
+
+// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
+// LLVM: [[VRND_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
+// LLVM: [[VRND1_I:%.*]] = call <2 x float> @llvm.trunc.v2f32(<2 x float> [[VRND_I]])
+// LLVM: ret <2 x float> [[VRND1_I]]
+ return vrnd_f32(a);
+}
+
+// LLVM-LABEL: @test_vrndq_f32(
+// CIR-LABEL: @vrndq_f32(
+float32x4_t test_vrndq_f32(float32x4_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float>
+// CIR: cir.trunc [[CAST]] : !cir.vector<4 x !cir.float>
+
+// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// LLVM: [[VRND_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
+// LLVM: [[VRND1_I:%.*]] = call <4 x float> @llvm.trunc.v4f32(<4 x float> [[VRND_I]])
+// LLVM: ret <4 x float> [[VRND1_I]]
+ return vrndq_f32(a);
+}
+
+// LLVM-LABEL: @test_vrnd_f64(
+// CIR-LABEL: @vrnd_f64(
+float64x1_t test_vrnd_f64(float64x1_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double>
+// CIR: cir.trunc [[CAST]] : !cir.vector<1 x !cir.double>
+
+// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
+// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
+// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8>
+// LLVM: [[VRND_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double>
+// LLVM: [[VRND1_I:%.*]] = call <1 x double> @llvm.trunc.v1f64(<1 x double> [[VRND_I]])
+// LLVM: ret <1 x double> [[VRND1_I]]
+ return vrnd_f64(a);
+}
+
+// LLVM-LABEL: @test_vrndq_f64(
+// CIR-LABEL: @vrndq_f64(
+float64x2_t test_vrndq_f64(float64x2_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double>
+// CIR: cir.trunc [[CAST]] : !cir.vector<2 x !cir.double>
+
+// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// LLVM: [[VRND_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
+// LLVM: [[VRND1_I:%.*]] = call <2 x double> @llvm.trunc.v2f64(<2 x double> [[VRND_I]])
+// LLVM: ret <2 x double> [[VRND1_I]]
+ return vrndq_f64(a);
+}
+
+// LLVM-LABEL: @test_vrndn_f32(
+// CIR-LABEL: @vrndn_f32(
+float32x2_t test_vrndn_f32(float32x2_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float>
+// CIR: cir.roundeven [[CAST]] : !cir.vector<2 x !cir.float>
+
+// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
+// LLVM: [[VRNDN_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
+// LLVM: [[VRNDN1_I:%.*]] = call <2 x float> @llvm.roundeven.v2f32(<2 x float> [[VRNDN_I]])
+// LLVM: ret <2 x float> [[VRNDN1_I]]
+ return vrndn_f32(a);
+}
+
+// LLVM-LABEL: @test_vrndnq_f32(
+// CIR-LABEL: @vrndnq_f32(
+float32x4_t test_vrndnq_f32(float32x4_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float>
+// CIR: cir.roundeven [[CAST]] : !cir.vector<4 x !cir.float>
+
+// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// LLVM: [[VRNDN_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
+// LLVM: [[VRNDN1_I:%.*]] = call <4 x float> @llvm.roundeven.v4f32(<4 x float> [[VRNDN_I]])
+// LLVM: ret <4 x float> [[VRNDN1_I]]
+ return vrndnq_f32(a);
+}
+
+// LLVM-LABEL: @test_vrndn_f64(
+// CIR-LABEL: @vrndn_f64(
+float64x1_t test_vrndn_f64(float64x1_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double>
+// CIR: cir.roundeven [[CAST]] : !cir.vector<1 x !cir.double>
+
+// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
+// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
+// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8>
+// LLVM: [[VRNDN_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double>
+// LLVM: [[VRNDN1_I:%.*]] = call <1 x double> @llvm.roundeven.v1f64(<1 x double> [[VRNDN_I]])
+// LLVM: ret <1 x double> [[VRNDN1_I]]
+ return vrndn_f64(a);
+}
+
+// LLVM-LABEL: @test_vrndnq_f64(
+// CIR-LABEL: @vrndnq_f64(
+float64x2_t test_vrndnq_f64(float64x2_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double>
+// CIR: cir.roundeven [[CAST]] : !cir.vector<2 x !cir.double>
+
+// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// LLVM: [[VRNDN_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
+// LLVM: [[VRNDN1_I:%.*]] = call <2 x double> @llvm.roundeven.v2f64(<2 x double> [[VRNDN_I]])
+// LLVM: ret <2 x double> [[VRNDN1_I]]
+ return vrndnq_f64(a);
+}
+
+// LLVM-LABEL: @test_vrndns_f32(
+// CIR-LABEL: @vrndns_f32(
+float32_t test_vrndns_f32(float32_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.float>, !cir.float
+// CIR: cir.roundeven [[LOAD]] : !cir.float
+
+// LLVM-SAME: float {{.*}} [[A:%.*]])
+// LLVM: [[VRNDN_I:%.*]] = call float @llvm.roundeven.f32(float [[A]])
+// LLVM: ret float [[VRNDN_I]]
+ return vrndns_f32(a);
+}
+
+// LLVM-LABEL: @test_vrndm_f32(
+// CIR-LABEL: @vrndm_f32(
+float32x2_t test_vrndm_f32(float32x2_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float>
+// CIR: cir.floor [[CAST]] : !cir.vector<2 x !cir.float>
+
+// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
+// LLVM: [[VRNDM_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
+// LLVM: [[VRNDM1_I:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> [[VRNDM_I]])
+// LLVM: ret <2 x float> [[VRNDM1_I]]
+ return vrndm_f32(a);
+}
+
+// LLVM-LABEL: @test_vrndmq_f32(
+// CIR-LABEL: @vrndmq_f32(
+float32x4_t test_vrndmq_f32(float32x4_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float>
+// CIR: cir.floor [[CAST]] : !cir.vector<4 x !cir.float>
+
+// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// LLVM: [[VRNDM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
+// LLVM: [[VRNDM1_I:%.*]] = call <4 x float> @llvm.floor.v4f32(<4 x float> [[VRNDM_I]])
+// LLVM: ret <4 x float> [[VRNDM1_I]]
+ return vrndmq_f32(a);
+}
+
+// LLVM-LABEL: @test_vrndm_f64(
+// CIR-LABEL: @vrndm_f64(
+float64x1_t test_vrndm_f64(float64x1_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double>
+// CIR: cir.floor [[CAST]] : !cir.vector<1 x !cir.double>
+
+// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
+// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
+// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8>
+// LLVM: [[VRNDM_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double>
+// LLVM: [[VRNDM1_I:%.*]] = call <1 x double> @llvm.floor.v1f64(<1 x double> [[VRNDM_I]])
+// LLVM: ret <1 x double> [[VRNDM1_I]]
+ return vrndm_f64(a);
+}
+
+// LLVM-LABEL: @test_vrndmq_f64(
+// CIR-LABEL: @vrndmq_f64(
+float64x2_t test_vrndmq_f64(float64x2_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double>
+// CIR: cir.floor [[CAST]] : !cir.vector<2 x !cir.double>
+
+// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// LLVM: [[VRNDM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
+// LLVM: [[VRNDM1_I:%.*]] = call <2 x double> @llvm.floor.v2f64(<2 x double> [[VRNDM_I]])
+// LLVM: ret <2 x double> [[VRNDM1_I]]
+ return vrndmq_f64(a);
+}
+
+// LLVM-LABEL: @test_vrndp_f32(
+// CIR-LABEL: @vrndp_f32(
+float32x2_t test_vrndp_f32(float32x2_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float>
+// CIR: cir.ceil [[CAST]] : !cir.vector<2 x !cir.float>
+
+// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
+// LLVM: [[VRNDP_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
+// LLVM: [[VRNDP1_I:%.*]] = call <2 x float> @llvm.ceil.v2f32(<2 x float> [[VRNDP_I]])
+// LLVM: ret <2 x float> [[VRNDP1_I]]
+ return vrndp_f32(a);
+}
+
+// LLVM-LABEL: @test_vrndpq_f32(
+// CIR-LABEL: @vrndpq_f32(
+float32x4_t test_vrndpq_f32(float32x4_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float>
+// CIR: cir.ceil [[CAST]] : !cir.vector<4 x !cir.float>
+
+// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// LLVM: [[VRNDP_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
+// LLVM: [[VRNDP1_I:%.*]] = call <4 x float> @llvm.ceil.v4f32(<4 x float> [[VRNDP_I]])
+// LLVM: ret <4 x float> [[VRNDP1_I]]
+ return vrndpq_f32(a);
+}
+
+// LLVM-LABEL: @test_vrndp_f64(
+// CIR-LABEL: @vrndp_f64(
+float64x1_t test_vrndp_f64(float64x1_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double>
+// CIR: cir.ceil [[CAST]] : !cir.vector<1 x !cir.double>
+
+// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
+// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
+// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8>
+// LLVM: [[VRNDP_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double>
+// LLVM: [[VRNDP1_I:%.*]] = call <1 x double> @llvm.ceil.v1f64(<1 x double> [[VRNDP_I]])
+// LLVM: ret <1 x double> [[VRNDP1_I]]
+ return vrndp_f64(a);
+}
+
+// LLVM-LABEL: @test_vrndpq_f64(
+// CIR-LABEL: @vrndpq_f64(
+float64x2_t test_vrndpq_f64(float64x2_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double>
+// CIR: cir.ceil [[CAST]] : !cir.vector<2 x !cir.double>
+
+// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// LLVM: [[VRNDP_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
+// LLVM: [[VRNDP1_I:%.*]] = call <2 x double> @llvm.ceil.v2f64(<2 x double> [[VRNDP_I]])
+// LLVM: ret <2 x double> [[VRNDP1_I]]
+ return vrndpq_f64(a);
+}
+
+// LLVM-LABEL: @test_vrnda_f32(
+// CIR-LABEL: @vrnda_f32(
+float32x2_t test_vrnda_f32(float32x2_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float>
+// CIR: cir.round [[CAST]] : !cir.vector<2 x !cir.float>
+
+// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
+// LLVM: [[VRNDA_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
+// LLVM: [[VRNDA1_I:%.*]] = call <2 x float> @llvm.round.v2f32(<2 x float> [[VRNDA_I]])
+// LLVM: ret <2 x float> [[VRNDA1_I]]
+ return vrnda_f32(a);
+}
+
+// LLVM-LABEL: @test_vrndaq_f32(
+// CIR-LABEL: @vrndaq_f32(
+float32x4_t test_vrndaq_f32(float32x4_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float>
+// CIR: cir.round [[CAST]] : !cir.vector<4 x !cir.float>
+
+// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// LLVM: [[VRNDA_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
+// LLVM: [[VRNDA1_I:%.*]] = call <4 x float> @llvm.round.v4f32(<4 x float> [[VRNDA_I]])
+// LLVM: ret <4 x float> [[VRNDA1_I]]
+ return vrndaq_f32(a);
+}
+
+// LLVM-LABEL: @test_vrnda_f64(
+// CIR-LABEL: @vrnda_f64(
+float64x1_t test_vrnda_f64(float64x1_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double>
+// CIR: cir.round [[CAST]] : !cir.vector<1 x !cir.double>
+
+// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
+// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
+// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8>
+// LLVM: [[VRNDA_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double>
+// LLVM: [[VRNDA1_I:%.*]] = call <1 x double> @llvm.round.v1f64(<1 x double> [[VRNDA_I]])
+// LLVM: ret <1 x double> [[VRNDA1_I]]
+ return vrnda_f64(a);
+}
+
+// LLVM-LABEL: @test_vrndaq_f64(
+// CIR-LABEL: @vrndaq_f64(
+float64x2_t test_vrndaq_f64(float64x2_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double>
+// CIR: cir.round [[CAST]] : !cir.vector<2 x !cir.double>
+
+// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// LLVM: [[VRNDA_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
+// LLVM: [[VRNDA1_I:%.*]] = call <2 x double> @llvm.round.v2f64(<2 x double> [[VRNDA_I]])
+// LLVM: ret <2 x double> [[VRNDA1_I]]
+ return vrndaq_f64(a);
+}
+
+// LLVM-LABEL: @test_vrndi_f32(
+// CIR-LABEL: @vrndi_f32(
+float32x2_t test_vrndi_f32(float32x2_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float>
+// CIR: cir.nearbyint [[CAST]] : !cir.vector<2 x !cir.float>
+
+// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
+// LLVM: [[VRNDI_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
+// LLVM: [[VRNDI_V1_I:%.*]] = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> [[VRNDI_V_I]])
+// LLVM: ret <2 x float> [[VRNDI_V1_I]]
+ return vrndi_f32(a);
+}
+
+// LLVM-LABEL: @test_vrndiq_f32(
+// CIR-LABEL: @vrndiq_f32(
+float32x4_t test_vrndiq_f32(float32x4_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float>
+// CIR: cir.nearbyint [[CAST]] : !cir.vector<4 x !cir.float>
+
+// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// LLVM: [[VRNDIQ_V_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
+// LLVM: [[VRNDIQ_V1_I:%.*]] = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> [[VRNDIQ_V_I]])
+// LLVM: ret <4 x float> [[VRNDIQ_V1_I]]
+ return vrndiq_f32(a);
+}
+
+// LLVM-LABEL: @test_vrndi_f64(
+// CIR-LABEL: @vrndi_f64(
+float64x1_t test_vrndi_f64(float64x1_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double>
+// CIR: cir.nearbyint [[CAST]] : !cir.vector<1 x !cir.double>
+
+// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
+// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
+// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8>
+// LLVM: [[VRNDI_V_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double>
+// LLVM: [[VRNDI_V1_I:%.*]] = call <1 x double> @llvm.nearbyint.v1f64(<1 x double> [[VRNDI_V_I]])
+// LLVM: ret <1 x double> [[VRNDI_V1_I]]
+ return vrndi_f64(a);
+}
+
+// LLVM-LABEL: @test_vrndiq_f64(
+// CIR-LABEL: @vrndiq_f64(
+float64x2_t test_vrndiq_f64(float64x2_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double>
+// CIR: cir.nearbyint [[CAST]] : !cir.vector<2 x !cir.double>
+
+// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// LLVM: [[VRNDI_V_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
+// LLVM: [[VRNDI_V1_I:%.*]] = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> [[VRNDI_V_I]])
+// LLVM: ret <2 x double> [[VRNDI_V1_I]]
+ return vrndiq_f64(a);
+}
+
+// LLVM-LABEL: @test_vrndx_f32(
+// CIR-LABEL: @vrndx_f32(
+float32x2_t test_vrndx_f32(float32x2_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float>
+// CIR: cir.rint [[CAST]] : !cir.vector<2 x !cir.float>
+
+// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
+// LLVM: [[VRNDX_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
+// LLVM: [[VRNDX1_I:%.*]] = call <2 x float> @llvm.rint.v2f32(<2 x float> [[VRNDX_I]])
+// LLVM: ret <2 x float> [[VRNDX1_I]]
+ return vrndx_f32(a);
+}
+
+// LLVM-LABEL: @test_vrndxq_f32(
+// CIR-LABEL: @vrndxq_f32(
+float32x4_t test_vrndxq_f32(float32x4_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float>
+// CIR: cir.rint [[CAST]] : !cir.vector<4 x !cir.float>
+
+// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// LLVM: [[VRNDX_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
+// LLVM: [[VRNDX1_I:%.*]] = call <4 x float> @llvm.rint.v4f32(<4 x float> [[VRNDX_I]])
+// LLVM: ret <4 x float> [[VRNDX1_I]]
+ return vrndxq_f32(a);
+}
+
+// LLVM-LABEL: @test_vrndx_f64(
+// CIR-LABEL: @vrndx_f64(
+float64x1_t test_vrndx_f64(float64x1_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double>
+// CIR: cir.rint [[CAST]] : !cir.vector<1 x !cir.double>
+
+// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
+// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
+// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8>
+// LLVM: [[VRNDX_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double>
+// LLVM: [[VRNDX1_I:%.*]] = call <1 x double> @llvm.rint.v1f64(<1 x double> [[VRNDX_I]])
+// LLVM: ret <1 x double> [[VRNDX1_I]]
+ return vrndx_f64(a);
+}
+
+// LLVM-LABEL: @test_vrndxq_f64(
+// CIR-LABEL: @vrndxq_f64(
+float64x2_t test_vrndxq_f64(float64x2_t a) {
+// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i>
+// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double>
+// CIR: cir.rint [[CAST]] : !cir.vector<2 x !cir.double>
+
+// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// LLVM: [[VRNDX_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
+// LLVM: [[VRNDX1_I:%.*]] = call <2 x double> @llvm.rint.v2f64(<2 x double> [[VRNDX_I]])
+// LLVM: ret <2 x double> [[VRNDX1_I]]
+ return vrndxq_f64(a);
+}
diff --git a/clang/test/CodeGen/AArch64/v8.5a-neon-frint3264-intrinsic.c b/clang/test/CodeGen/AArch64/v8.5a-neon-frint3264-intrinsic.c
deleted file mode 100644
index d10e8b8344346..0000000000000
--- a/clang/test/CodeGen/AArch64/v8.5a-neon-frint3264-intrinsic.c
+++ /dev/null
@@ -1,145 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
-// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v8.5a\
-// RUN: -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - %s \
-// RUN: | opt -S -passes=mem2reg,sroa \
-// RUN: | FileCheck %s
-
-// REQUIRES: aarch64-registered-target
-
-#include <arm_neon.h>
-
-// CHECK-LABEL: define dso_local <1 x double> @test_vrnd32x_f64(
-// CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
-// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[VRND32X_F64_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
-// CHECK-NEXT: [[VRND32X_F641_I:%.*]] = call <1 x double> @llvm.aarch64.neon.frint32x.v1f64(<1 x double> [[VRND32X_F64_I]])
-// CHECK-NEXT: [[VRND32X_F642_I:%.*]] = bitcast <1 x double> [[VRND32X_F641_I]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRND32X_F642_I]] to i64
-// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i64 0
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]] to <1 x double>
-// CHECK-NEXT: ret <1 x double> [[TMP3]]
-//
-float64x1_t test_vrnd32x_f64(float64x1_t a) {
- return vrnd32x_f64(a);
-}
-
-// CHECK-LABEL: define dso_local <2 x double> @test_vrnd32xq_f64(
-// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[VRND32XQ_F64_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
-// CHECK-NEXT: [[VRND32XQ_F641_I:%.*]] = call <2 x double> @llvm.aarch64.neon.frint32x.v2f64(<2 x double> [[VRND32XQ_F64_I]])
-// CHECK-NEXT: [[VRND32XQ_F642_I:%.*]] = bitcast <2 x double> [[VRND32XQ_F641_I]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRND32XQ_F642_I]] to <2 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to <2 x double>
-// CHECK-NEXT: ret <2 x double> [[TMP3]]
-//
-float64x2_t test_vrnd32xq_f64(float64x2_t a) {
- return vrnd32xq_f64(a);
-}
-
-// CHECK-LABEL: define dso_local <1 x double> @test_vrnd32z_f64(
-// CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
-// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[VRND32Z_F64_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
-// CHECK-NEXT: [[VRND32Z_F641_I:%.*]] = call <1 x double> @llvm.aarch64.neon.frint32z.v1f64(<1 x double> [[VRND32Z_F64_I]])
-// CHECK-NEXT: [[VRND32Z_F642_I:%.*]] = bitcast <1 x double> [[VRND32Z_F641_I]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRND32Z_F642_I]] to i64
-// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i64 0
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]] to <1 x double>
-// CHECK-NEXT: ret <1 x double> [[TMP3]]
-//
-float64x1_t test_vrnd32z_f64(float64x1_t a) {
- return vrnd32z_f64(a);
-}
-
-// CHECK-LABEL: define dso_local <2 x double> @test_vrnd32zq_f64(
-// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[VRND32ZQ_F64_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
-// CHECK-NEXT: [[VRND32ZQ_F641_I:%.*]] = call <2 x double> @llvm.aarch64.neon.frint32z.v2f64(<2 x double> [[VRND32ZQ_F64_I]])
-// CHECK-NEXT: [[VRND32ZQ_F642_I:%.*]] = bitcast <2 x double> [[VRND32ZQ_F641_I]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRND32ZQ_F642_I]] to <2 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to <2 x double>
-// CHECK-NEXT: ret <2 x double> [[TMP3]]
-//
-float64x2_t test_vrnd32zq_f64(float64x2_t a) {
- return vrnd32zq_f64(a);
-}
-
-// CHECK-LABEL: define dso_local <1 x double> @test_vrnd64x_f64(
-// CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
-// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[VRND64X_F64_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
-// CHECK-NEXT: [[VRND64X_F641_I:%.*]] = call <1 x double> @llvm.aarch64.neon.frint64x.v1f64(<1 x double> [[VRND64X_F64_I]])
-// CHECK-NEXT: [[VRND64X_F642_I:%.*]] = bitcast <1 x double> [[VRND64X_F641_I]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRND64X_F642_I]] to i64
-// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i64 0
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]] to <1 x double>
-// CHECK-NEXT: ret <1 x double> [[TMP3]]
-//
-float64x1_t test_vrnd64x_f64(float64x1_t a) {
- return vrnd64x_f64(a);
-}
-
-// CHECK-LABEL: define dso_local <2 x double> @test_vrnd64xq_f64(
-// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[VRND64XQ_F64_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
-// CHECK-NEXT: [[VRND64XQ_F641_I:%.*]] = call <2 x double> @llvm.aarch64.neon.frint64x.v2f64(<2 x double> [[VRND64XQ_F64_I]])
-// CHECK-NEXT: [[VRND64XQ_F642_I:%.*]] = bitcast <2 x double> [[VRND64XQ_F641_I]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRND64XQ_F642_I]] to <2 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to <2 x double>
-// CHECK-NEXT: ret <2 x double> [[TMP3]]
-//
-float64x2_t test_vrnd64xq_f64(float64x2_t a) {
- return vrnd64xq_f64(a);
-}
-
-// CHECK-LABEL: define dso_local <1 x double> @test_vrnd64z_f64(
-// CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
-// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[VRND64Z_F64_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
-// CHECK-NEXT: [[VRND64Z_F641_I:%.*]] = call <1 x double> @llvm.aarch64.neon.frint64z.v1f64(<1 x double> [[VRND64Z_F64_I]])
-// CHECK-NEXT: [[VRND64Z_F642_I:%.*]] = bitcast <1 x double> [[VRND64Z_F641_I]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRND64Z_F642_I]] to i64
-// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i64 0
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]] to <1 x double>
-// CHECK-NEXT: ret <1 x double> [[TMP3]]
-//
-float64x1_t test_vrnd64z_f64(float64x1_t a) {
- return vrnd64z_f64(a);
-}
-
-// CHECK-LABEL: define dso_local <2 x double> @test_vrnd64zq_f64(
-// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[VRND64ZQ_F64_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
-// CHECK-NEXT: [[VRND64ZQ_F641_I:%.*]] = call <2 x double> @llvm.aarch64.neon.frint64z.v2f64(<2 x double> [[VRND64ZQ_F64_I]])
-// CHECK-NEXT: [[VRND64ZQ_F642_I:%.*]] = bitcast <2 x double> [[VRND64ZQ_F641_I]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRND64ZQ_F642_I]] to <2 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to <2 x double>
-// CHECK-NEXT: ret <2 x double> [[TMP3]]
-//
-float64x2_t test_vrnd64zq_f64(float64x2_t a) {
- return vrnd64zq_f64(a);
-}
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