[clang] [llvm] [RISCV] Support frame pointers in SiFive CLIC preemptible handlers (PR #221318)

[Sam Elliott via cfe-commits]

lenary wrote:

Initial thoughts while I'm away, I'll return to do a longer review when I get back to my desk.

We can always just use t0, right?

The original version of this code is quite hacky (hence the debug info being wrong), because there's a few different constraints we're trying to follow. Your version might be better for both cases.

With or without frame pointers, we want to save `mcause` and `mepc`. We want to do this as "soon" as possible, but we need a scratch register to be spilled first. So in the original version of the code, we spilled the values from s0/s1, then read the two csrs into s0/s1, and then did normal spilling (which wanted to spill s0/s1 anyway). This is partly why the debug info was wrong.

I would like the debug (CFI) info to be correct. I haven't examined this patch closely to see that this fixes it. We should at least get the right CFI for the GPRs, fixing the CFI for the CSRs can come later (it's just absent right now).

I'm away right now but I will do a fuller review when I'm back.

https://github.com/llvm/llvm-project/pull/221318