[clang] [CIR][AArch64] Complete upstream vector saturating shift left NEON builtins (PR #221507)
via cfe-commits
cfe-commits at lists.llvm.org
Sat Sep 5 22:37:18 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clang
Author: Vicky Nguyen (iamvickynguyen)
<details>
<summary>Changes</summary>
Related to https://github.com/llvm/llvm-project/issues/185382
CIR lowering for the vector saturating shift left intrinsics
(https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-saturating-shift-left).
This completes the family.
Port tests from `clang/test/CodeGen/AArch64/neon-intrinsics.c` to `clang/test/CodeGen/AArch64/neon/intrinsics.c`.
---
Patch is 80.80 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/221507.diff
3 Files Affected:
- (modified) clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp (+49-6)
- (modified) clang/test/CodeGen/AArch64/neon-intrinsics.c (-704)
- (modified) clang/test/CodeGen/AArch64/neon/intrinsics.c (+793-3)
``````````diff
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index da23769632a78..4ee46b7927187 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -319,14 +319,24 @@ deriveNeonSISDIntrinsicOperandTypes(CIRGenFunction &cgf, unsigned modifier,
// that has the same scalar type as arg0. Checking the ICE bitmap prevents
// an i32 immediate from being vectorized when it has the same type as a
// data operand (e.g. vqshrns_n_s32).
+ //
+ // Exception: the `_n_` scalar saturating shift-left builtins (vqshlb_n_s8,
+ // vqshlh_n_u16, vqshlub_n_s8, ...) lower to aarch64.neon.{s,u}qshl /
+ // sqshlu, whose second operand is `LLVMMatchType<0>` - a vector, not a
+ // scalar. Their shape is a single data operand followed by the immediate,
+ // so widen that trailing immediate too. Narrowing shifts
+ // (`ArgAsWidenedRetType`) keep a scalar i32 immediate.
+ const bool widenTrailingImm = vecArgTy && ops.size() == 2 &&
+ !(modifier & ArgAsWidenedRetType) &&
+ (iceArguments & (1U << 1));
llvm::SmallVector<mlir::Type> argTypes;
argTypes.reserve(ops.size());
for (unsigned i = 0, e = ops.size(); i != e; ++i) {
bool isImmediate = iceArguments & (1U << i);
- if (vecArgTy && !isImmediate && matchesArg0Ty(ops[i].getType()))
- argTypes.push_back(vecArgTy);
- else
- argTypes.push_back(ops[i].getType());
+ bool asVector =
+ vecArgTy && ((!isImmediate && matchesArg0Ty(ops[i].getType())) ||
+ (widenTrailingImm && i == 1));
+ argTypes.push_back(asVector ? mlir::Type(vecArgTy) : ops[i].getType());
}
return {funcResTy, std::move(argTypes)};
@@ -579,6 +589,23 @@ emitCommonNeonSISDBuiltinExpr(CIRGenFunction &cgf,
case NEON::BI__builtin_neon_vqrshrnh_n_u16:
case NEON::BI__builtin_neon_vqrshruns_n_s32:
case NEON::BI__builtin_neon_vqrshrunh_n_s16:
+ case NEON::BI__builtin_neon_vqshlb_s8:
+ case NEON::BI__builtin_neon_vqshlb_u8:
+ case NEON::BI__builtin_neon_vqshlh_s16:
+ case NEON::BI__builtin_neon_vqshlh_u16:
+ case NEON::BI__builtin_neon_vqshls_s32:
+ case NEON::BI__builtin_neon_vqshls_u32:
+ case NEON::BI__builtin_neon_vqshld_s64:
+ case NEON::BI__builtin_neon_vqshld_u64:
+ case NEON::BI__builtin_neon_vqshlb_n_s8:
+ case NEON::BI__builtin_neon_vqshlb_n_u8:
+ case NEON::BI__builtin_neon_vqshlh_n_s16:
+ case NEON::BI__builtin_neon_vqshlh_n_u16:
+ case NEON::BI__builtin_neon_vqshls_n_s32:
+ case NEON::BI__builtin_neon_vqshls_n_u32:
+ case NEON::BI__builtin_neon_vqshlub_n_s8:
+ case NEON::BI__builtin_neon_vqshluh_n_s16:
+ case NEON::BI__builtin_neon_vqshlus_n_s32:
break;
}
@@ -1198,10 +1225,24 @@ static mlir::Value emitCommonNeonBuiltinExpr(
case NEON::BI__builtin_neon_vqdmulh_laneq_v:
case NEON::BI__builtin_neon_vqrdmulhq_laneq_v:
case NEON::BI__builtin_neon_vqrdmulh_laneq_v:
+ cgf.cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ ctx.BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vqshl_n_v:
- case NEON::BI__builtin_neon_vqshlq_n_v:
+ case NEON::BI__builtin_neon_vqshlq_n_v: {
+ llvm::StringRef intrName =
+ usgn ? "aarch64.neon.uqshl" : "aarch64.neon.sqshl";
+ return emitNeonCall(cgf.cgm, cgf.getBuilder(), {ty, ty}, ops, intrName, ty,
+ loc, /*isConstrainedFPIntrinsic=*/false, /*shift=*/1,
+ /*rightshift=*/false);
+ }
case NEON::BI__builtin_neon_vqshlu_n_v:
case NEON::BI__builtin_neon_vqshluq_n_v:
+ return emitNeonCall(cgf.cgm, cgf.getBuilder(), {ty, ty}, ops,
+ "aarch64.neon.sqshlu", ty, loc,
+ /*isConstrainedFPIntrinsic=*/false, /*shift=*/1,
+ /*rightshift=*/false);
case NEON::BI__builtin_neon_vrecpe_v:
case NEON::BI__builtin_neon_vrecpeq_v:
case NEON::BI__builtin_neon_vrsqrte_v:
@@ -1389,7 +1430,9 @@ static mlir::Value emitCommonNeonBuiltinExpr(
case NEON::BI__builtin_neon_vshl_v:
case NEON::BI__builtin_neon_vshlq_v:
case NEON::BI__builtin_neon_vraddhn_v:
- case NEON::BI__builtin_neon_vrsubhn_v: {
+ case NEON::BI__builtin_neon_vrsubhn_v:
+ case NEON::BI__builtin_neon_vqshl_v:
+ case NEON::BI__builtin_neon_vqshlq_v: {
// Pick the signed/unsigned intrinsic when the builtin has both
// (UnsignedAlts); otherwise there is a single intrinsic.
unsigned intrinsic =
diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c
index 7a945abca9a80..2098abb097889 100644
--- a/clang/test/CodeGen/AArch64/neon-intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c
@@ -2325,240 +2325,6 @@ uint64x2_t test_vcltq_f64(float64x2_t v1, float64x2_t v2) {
return vcltq_f64(v1, v2);
}
-// CHECK-LABEL: define dso_local <8 x i8> @test_vqshl_s8(
-// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VQSHL_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])
-// CHECK-NEXT: ret <8 x i8> [[VQSHL_V_I]]
-//
-int8x8_t test_vqshl_s8(int8x8_t a, int8x8_t b) {
- return vqshl_s8(a, b);
-}
-
-// CHECK-LABEL: define dso_local <4 x i16> @test_vqshl_s16(
-// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
-// CHECK-NEXT: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: [[VQSHL_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> [[VQSHL_V_I]], <4 x i16> [[VQSHL_V1_I]])
-// CHECK-NEXT: [[VQSHL_V3_I:%.*]] = bitcast <4 x i16> [[VQSHL_V2_I]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to <4 x i16>
-// CHECK-NEXT: ret <4 x i16> [[TMP2]]
-//
-int16x4_t test_vqshl_s16(int16x4_t a, int16x4_t b) {
- return vqshl_s16(a, b);
-}
-
-// CHECK-LABEL: define dso_local <2 x i32> @test_vqshl_s32(
-// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
-// CHECK-NEXT: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
-// CHECK-NEXT: [[VQSHL_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> [[VQSHL_V_I]], <2 x i32> [[VQSHL_V1_I]])
-// CHECK-NEXT: [[VQSHL_V3_I:%.*]] = bitcast <2 x i32> [[VQSHL_V2_I]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to <2 x i32>
-// CHECK-NEXT: ret <2 x i32> [[TMP2]]
-//
-int32x2_t test_vqshl_s32(int32x2_t a, int32x2_t b) {
- return vqshl_s32(a, b);
-}
-
-// CHECK-LABEL: define dso_local <1 x i64> @test_vqshl_s64(
-// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>
-// CHECK-NEXT: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: [[VQSHL_V2_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> [[VQSHL_V_I]], <1 x i64> [[VQSHL_V1_I]])
-// CHECK-NEXT: [[VQSHL_V3_I:%.*]] = bitcast <1 x i64> [[VQSHL_V2_I]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to i64
-// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i64 0
-// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]]
-//
-int64x1_t test_vqshl_s64(int64x1_t a, int64x1_t b) {
- return vqshl_s64(a, b);
-}
-
-// CHECK-LABEL: define dso_local <8 x i8> @test_vqshl_u8(
-// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VQSHL_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])
-// CHECK-NEXT: ret <8 x i8> [[VQSHL_V_I]]
-//
-uint8x8_t test_vqshl_u8(uint8x8_t a, int8x8_t b) {
- return vqshl_u8(a, b);
-}
-
-// CHECK-LABEL: define dso_local <4 x i16> @test_vqshl_u16(
-// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
-// CHECK-NEXT: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: [[VQSHL_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> [[VQSHL_V_I]], <4 x i16> [[VQSHL_V1_I]])
-// CHECK-NEXT: [[VQSHL_V3_I:%.*]] = bitcast <4 x i16> [[VQSHL_V2_I]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to <4 x i16>
-// CHECK-NEXT: ret <4 x i16> [[TMP2]]
-//
-uint16x4_t test_vqshl_u16(uint16x4_t a, int16x4_t b) {
- return vqshl_u16(a, b);
-}
-
-// CHECK-LABEL: define dso_local <2 x i32> @test_vqshl_u32(
-// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
-// CHECK-NEXT: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
-// CHECK-NEXT: [[VQSHL_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> [[VQSHL_V_I]], <2 x i32> [[VQSHL_V1_I]])
-// CHECK-NEXT: [[VQSHL_V3_I:%.*]] = bitcast <2 x i32> [[VQSHL_V2_I]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to <2 x i32>
-// CHECK-NEXT: ret <2 x i32> [[TMP2]]
-//
-uint32x2_t test_vqshl_u32(uint32x2_t a, int32x2_t b) {
- return vqshl_u32(a, b);
-}
-
-// CHECK-LABEL: define dso_local <1 x i64> @test_vqshl_u64(
-// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>
-// CHECK-NEXT: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: [[VQSHL_V2_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> [[VQSHL_V_I]], <1 x i64> [[VQSHL_V1_I]])
-// CHECK-NEXT: [[VQSHL_V3_I:%.*]] = bitcast <1 x i64> [[VQSHL_V2_I]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to i64
-// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i64 0
-// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]]
-//
-uint64x1_t test_vqshl_u64(uint64x1_t a, int64x1_t b) {
- return vqshl_u64(a, b);
-}
-
-// CHECK-LABEL: define dso_local <16 x i8> @test_vqshlq_s8(
-// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])
-// CHECK-NEXT: ret <16 x i8> [[VQSHLQ_V_I]]
-//
-int8x16_t test_vqshlq_s8(int8x16_t a, int8x16_t b) {
- return vqshlq_s8(a, b);
-}
-
-// CHECK-LABEL: define dso_local <8 x i16> @test_vqshlq_s16(
-// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>
-// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: [[VQSHLQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> [[VQSHLQ_V_I]], <8 x i16> [[VQSHLQ_V1_I]])
-// CHECK-NEXT: [[VQSHLQ_V3_I:%.*]] = bitcast <8 x i16> [[VQSHLQ_V2_I]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <8 x i16>
-// CHECK-NEXT: ret <8 x i16> [[TMP2]]
-//
-int16x8_t test_vqshlq_s16(int16x8_t a, int16x8_t b) {
- return vqshlq_s16(a, b);
-}
-
-// CHECK-LABEL: define dso_local <4 x i32> @test_vqshlq_s32(
-// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>
-// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
-// CHECK-NEXT: [[VQSHLQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> [[VQSHLQ_V_I]], <4 x i32> [[VQSHLQ_V1_I]])
-// CHECK-NEXT: [[VQSHLQ_V3_I:%.*]] = bitcast <4 x i32> [[VQSHLQ_V2_I]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <4 x i32>
-// CHECK-NEXT: ret <4 x i32> [[TMP2]]
-//
-int32x4_t test_vqshlq_s32(int32x4_t a, int32x4_t b) {
- return vqshlq_s32(a, b);
-}
-
-// CHECK-LABEL: define dso_local <2 x i64> @test_vqshlq_s64(
-// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>
-// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: [[VQSHLQ_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> [[VQSHLQ_V_I]], <2 x i64> [[VQSHLQ_V1_I]])
-// CHECK-NEXT: [[VQSHLQ_V3_I:%.*]] = bitcast <2 x i64> [[VQSHLQ_V2_I]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <2 x i64>
-// CHECK-NEXT: ret <2 x i64> [[TMP2]]
-//
-int64x2_t test_vqshlq_s64(int64x2_t a, int64x2_t b) {
- return vqshlq_s64(a, b);
-}
-
-// CHECK-LABEL: define dso_local <16 x i8> @test_vqshlq_u8(
-// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])
-// CHECK-NEXT: ret <16 x i8> [[VQSHLQ_V_I]]
-//
-uint8x16_t test_vqshlq_u8(uint8x16_t a, int8x16_t b) {
- return vqshlq_u8(a, b);
-}
-
-// CHECK-LABEL: define dso_local <8 x i16> @test_vqshlq_u16(
-// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>
-// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: [[VQSHLQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> [[VQSHLQ_V_I]], <8 x i16> [[VQSHLQ_V1_I]])
-// CHECK-NEXT: [[VQSHLQ_V3_I:%.*]] = bitcast <8 x i16> [[VQSHLQ_V2_I]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <8 x i16>
-// CHECK-NEXT: ret <8 x i16> [[TMP2]]
-//
-uint16x8_t test_vqshlq_u16(uint16x8_t a, int16x8_t b) {
- return vqshlq_u16(a, b);
-}
-
-// CHECK-LABEL: define dso_local <4 x i32> @test_vqshlq_u32(
-// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>
-// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
-// CHECK-NEXT: [[VQSHLQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> [[VQSHLQ_V_I]], <4 x i32> [[VQSHLQ_V1_I]])
-// CHECK-NEXT: [[VQSHLQ_V3_I:%.*]] = bitcast <4 x i32> [[VQSHLQ_V2_I]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <4 x i32>
-// CHECK-NEXT: ret <4 x i32> [[TMP2]]
-//
-uint32x4_t test_vqshlq_u32(uint32x4_t a, int32x4_t b) {
- return vqshlq_u32(a, b);
-}
-
-// CHECK-LABEL: define dso_local <2 x i64> @test_vqshlq_u64(
-// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>
-// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: [[VQSHLQ_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> [[VQSHLQ_V_I]], <2 x i64> [[VQSHLQ_V1_I]])
-// CHECK-NEXT: [[VQSHLQ_V3_I:%.*]] = bitcast <2 x i64> [[VQSHLQ_V2_I]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <2 x i64>
-// CHECK-NEXT: ret <2 x i64> [[TMP2]]
-//
-uint64x2_t test_vqshlq_u64(uint64x2_t a, int64x2_t b) {
- return vqshlq_u64(a, b);
-}
-
// CHECK-LABEL: define dso_local <8 x i8> @test_vrshl_s8(
// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -3476,86 +3242,6 @@ float64x2_t test_vmulxq_f64(float64x2_t a, float64x2_t b) {
return vmulxq_f64(a, b);
}
-// CHECK-LABEL: define dso_local <8 x i8> @test_vqshlu_n_s8(
-// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VQSHLU_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8> [[A]], <8 x i8> splat (i8 3))
-// CHECK-NEXT: ret <8 x i8> [[VQSHLU_N]]
-//
-uint8x8_t test_vqshlu_n_s8(int8x8_t a) {
- return vqshlu_n_s8(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <4 x i16> @test_vqshlu_n_s16(
-// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
-// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[VQSHLU_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16> [[VQSHLU_N]], <4 x i16> splat (i16 3))
-// CHECK-NEXT: ret <4 x i16> [[VQSHLU_N1]]
-//
-uint16x4_t test_vqshlu_n_s16(int16x4_t a) {
- return vqshlu_n_s16(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <2 x i32> @test_vqshlu_n_s32(
-// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
-// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[VQSHLU_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshlu.v2i32(<2 x i32> [[VQSHLU_N]], <2 x i32> splat (i32 3))
-// CHECK-NEXT: ret <2 x i32> [[VQSHLU_N1]]
-//
-uint32x2_t test_vqshlu_n_s32(int32x2_t a) {
- return vqshlu_n_s32(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <16 x i8> @test_vqshluq_n_s8(
-// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VQSHLU_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqshlu.v16i8(<16 x i8> [[A]], <16 x i8> splat (i8 3))
-// CHECK-NEXT: ret <16 x i8> [[VQSHLU_N]]
-//
-uint8x16_t test_vqshluq_n_s8(int8x16_t a) {
- return vqshluq_n_s8(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <8 x i16> @test_vqshluq_n_s16(
-// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
-// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitca...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/221507
More information about the cfe-commits
mailing list