[clang] [llvm] [RISCV] Remove hasCZEROLike() in favor of directly checking for Zicond (PR #221053)
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cfe-commits at lists.llvm.org
Thu Sep 3 13:53:26 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Ryan Buchner (bababuck)
<details>
<summary>Changes</summary>
Only Zicond implements a CZero-Like instruction now that Ventana Conditional Operations have been removed.
Builds on #<!-- -->221042.
---
Patch is 185.03 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/221053.diff
27 Files Affected:
- (modified) clang/test/CodeGen/RISCV/builtin-cpu-is.c (+1-19)
- (modified) clang/test/Driver/print-supported-extensions-riscv.c (-1)
- (modified) clang/test/Driver/riscv-cpus.c (-25)
- (modified) clang/test/Misc/target-invalid-cpu-note/riscv.c (-2)
- (modified) clang/test/Preprocessor/riscv-target-features.c (-9)
- (modified) llvm/docs/RISCVUsage.md (-4)
- (modified) llvm/docs/ReleaseNotes.md (+2)
- (modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (-3)
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (-12)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+8-8)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (-1)
- (removed) llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td (-32)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td (+4-6)
- (modified) llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp (-4)
- (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (-39)
- (modified) llvm/lib/Target/RISCV/RISCVSubtarget.h (-5)
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (-2)
- (modified) llvm/test/CodeGen/RISCV/condbinops.ll (-115)
- (modified) llvm/test/CodeGen/RISCV/condops.ll (-1202)
- (modified) llvm/test/CodeGen/RISCV/features-info.ll (-2)
- (modified) llvm/test/CodeGen/RISCV/pr148084.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/select-binop-identity.ll (-96)
- (modified) llvm/test/CodeGen/RISCV/select.ll (-407)
- (modified) llvm/test/CodeGen/RISCV/zicond-opts.ll (-455)
- (modified) llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll (+3-3)
- (removed) llvm/test/MC/RISCV/XVentanaCondOps-valid.s (-22)
- (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+3-5)
``````````diff
diff --git a/clang/test/CodeGen/RISCV/builtin-cpu-is.c b/clang/test/CodeGen/RISCV/builtin-cpu-is.c
index 74b7e2e49eb21..d87af8fb5d7f5 100644
--- a/clang/test/CodeGen/RISCV/builtin-cpu-is.c
+++ b/clang/test/CodeGen/RISCV/builtin-cpu-is.c
@@ -2,26 +2,8 @@
// RUN: %clang_cc1 -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm %s -o - \
// RUN: | opt -S -passes=mem2reg | FileCheck %s --check-prefix=CHECK-RV64
-// CHECK-RV64-LABEL: define dso_local signext i32 @test_cpu_is_veyron_v1(
-// CHECK-RV64-SAME: ) #[[ATTR0:[0-9]+]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 4
-// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1567
-// CHECK-RV64-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8
-// CHECK-RV64-NEXT: [[TMP3:%.*]] = icmp eq i64 [[TMP2]], -9223372036854710272
-// CHECK-RV64-NEXT: [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]]
-// CHECK-RV64-NEXT: [[TMP5:%.*]] = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8
-// CHECK-RV64-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 273
-// CHECK-RV64-NEXT: [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP6]]
-// CHECK-RV64-NEXT: [[CONV:%.*]] = zext i1 [[TMP7]] to i32
-// CHECK-RV64-NEXT: ret i32 [[CONV]]
-//
-int test_cpu_is_veyron_v1() {
- return __builtin_cpu_is("veyron-v1");
-}
-
// CHECK-RV64-LABEL: define dso_local signext i32 @test_cpu_is_spacemit_x60(
-// CHECK-RV64-SAME: ) #[[ATTR0]] {
+// CHECK-RV64-SAME: ) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
// CHECK-RV64-NEXT: [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 4
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1808
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 545cc3673fa32..2f3a7b8dc5ea2 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -241,7 +241,6 @@
// CHECK-NEXT: xtheadmempair 1.0 'XTHeadMemPair' (T-Head two-GPR Memory Operations)
// CHECK-NEXT: xtheadsync 1.0 'XTHeadSync' (T-Head multicore synchronization instructions)
// CHECK-NEXT: xtheadvdot 1.0 'XTHeadVdot' (T-Head Vector Extensions for Dot)
-// CHECK-NEXT: xventanacondops 1.0 'XVentanaCondOps' (Ventana Conditional Ops)
// CHECK-NEXT: xwchc 2.2 'Xwchc' (WCH/QingKe additional compressed opcodes)
// CHECK-EMPTY:
// CHECK-NEXT: Experimental extensions
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 89a3875adeed8..50d7ab7ab51b9 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -250,31 +250,6 @@
// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+svpbmt"
// MCPU-TT-ASCALON-X-SAME: "-target-abi" "lp64d"
-// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=veyron-v1 | FileCheck -check-prefix=MCPU-VEYRON-V1 %s
-// MCPU-VEYRON-V1: "-target-cpu" "veyron-v1"
-// MCPU-VEYRON-V1: "-target-feature" "+m"
-// MCPU-VEYRON-V1: "-target-feature" "+a"
-// MCPU-VEYRON-V1: "-target-feature" "+f"
-// MCPU-VEYRON-V1: "-target-feature" "+d"
-// MCPU-VEYRON-V1: "-target-feature" "+c"
-// MCPU-VEYRON-V1: "-target-feature" "+zicbom"
-// MCPU-VEYRON-V1: "-target-feature" "+zicbop"
-// MCPU-VEYRON-V1: "-target-feature" "+zicboz"
-// MCPU-VEYRON-V1: "-target-feature" "+zicntr"
-// MCPU-VEYRON-V1: "-target-feature" "+zicsr"
-// MCPU-VEYRON-V1: "-target-feature" "+zifencei"
-// MCPU-VEYRON-V1: "-target-feature" "+zihintpause"
-// MCPU-VEYRON-V1: "-target-feature" "+zihpm"
-// MCPU-VEYRON-V1: "-target-feature" "+zba"
-// MCPU-VEYRON-V1: "-target-feature" "+zbb"
-// MCPU-VEYRON-V1: "-target-feature" "+zbc"
-// MCPU-VEYRON-V1: "-target-feature" "+zbs"
-// MCPU-VEYRON-V1: "-target-feature" "+xventanacondops"
-// MCPU-VEYRON-V1: "-target-abi" "lp64d"
-
-// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=veyron-v1 | FileCheck -check-prefix=MTUNE-VEYRON-V1 %s
-// MTUNE-VEYRON-V1: "-tune-cpu" "veyron-v1"
-
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu | FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s
// MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu"
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index 234cc82a2bab6..546dbbdb7e043 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -59,7 +59,6 @@
// RISCV64-SAME: {{^}}, syntacore-scr5-rv64
// RISCV64-SAME: {{^}}, syntacore-scr7
// RISCV64-SAME: {{^}}, tt-ascalon-x
-// RISCV64-SAME: {{^}}, veyron-v1
// RISCV64-SAME: {{^}}, xiangshan-kunminghu
// RISCV64-SAME: {{^}}, xiangshan-nanhu
// RISCV64-SAME: {{^}}, xt-c910v2
@@ -128,7 +127,6 @@
// TUNE-RISCV64-SAME: {{^}}, syntacore-scr5-rv64
// TUNE-RISCV64-SAME: {{^}}, syntacore-scr7
// TUNE-RISCV64-SAME: {{^}}, tt-ascalon-x
-// TUNE-RISCV64-SAME: {{^}}, veyron-v1
// TUNE-RISCV64-SAME: {{^}}, xiangshan-kunminghu
// TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
// TUNE-RISCV64-SAME: {{^}}, xt-c910v2
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index cadd95f843592..7c79640c0769a 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -83,7 +83,6 @@
// CHECK-NOT: __riscv_v_intrinsic {{.*$}}
// CHECK-NOT: __riscv_v_min_vlen {{.*$}}
// CHECK-NOT: __riscv_vector {{.*$}}
-// CHECK-NOT: __riscv_xventanacondops {{.*$}}
// CHECK-NOT: __riscv_za128rs {{.*$}}
// CHECK-NOT: __riscv_za64rs {{.*$}}
// CHECK-NOT: __riscv_zaamo {{.*$}}
@@ -572,14 +571,6 @@
// CHECK-V-EXT: __riscv_v_min_vlen 128
// CHECK-V-EXT: __riscv_vector 1
-// RUN: %clang --target=riscv32-unknown-linux-gnu \
-// RUN: -march=rv32ixventanacondops -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s
-// RUN: %clang --target=riscv64-unknown-linux-gnu \
-// RUN: -march=rv64ixventanacondops -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s
-// CHECK-XVENTANACONDOPS-EXT: __riscv_xventanacondops 1000000{{$}}
-
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32iza128rs -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZA128RS-EXT %s
diff --git a/llvm/docs/RISCVUsage.md b/llvm/docs/RISCVUsage.md
index 1e89c8d7d82bd..c013068479b97 100644
--- a/llvm/docs/RISCVUsage.md
+++ b/llvm/docs/RISCVUsage.md
@@ -462,10 +462,6 @@ The current vendor extensions supported are:
: LLVM implements [version 1.0.0 of the THeadV-family custom instructions specification](https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.0/xthead-2022-12-04-2.2.0.pdf) by T-HEAD of Alibaba. All instructions are prefixed with `th.` as described in the specification, and the riscv-toolchain-convention document linked above.
-`XVentanaCondOps`
-
-: LLVM implements [version 1.0.0 of the VTx-family custom instructions specification](https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf) by Ventana Micro Systems. All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for riscv64 at this time.
-
`Xsfmm*`
: LLVM implements [version 0.6 of the Xsfmm Family of Attached Matrix Extensions Specification](https://www.sifive.com/document-file/xsfmm-matrix-extensions-specification) by SiFive. All instructions are prefixed with `sf.` as described in the specification.
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index ef90a1f1f1c41..c8a829d2c9aa5 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -217,6 +217,8 @@ Makes programs 10x faster by doing Special New Thing.
push/pop extensions.
* Bump Svukte extension to 1.0.
* Remove experimental from Zicfiss.
+* Removes veyron-v1 processor definition and tuning model.
+* Removes support for the `Ventana Conditional Operations` extension.
### Changes to the WebAssembly Backend
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 99066346f0411..72a2823ad6be5 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -586,9 +586,6 @@ static constexpr DecoderListEntry DecoderList32[]{
// Vendor Extensions
{DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},
{DecoderTableXqci32, XqciFeatureGroup, "Qualcomm uC Extensions"},
- {DecoderTableXVentana32,
- {RISCV::FeatureVendorXVentanaCondOps},
- "XVentanaCondOps"},
{DecoderTableXTHead32, XTHeadGroup, "T-Head extensions"},
{DecoderTableXSfvector32, XSfVectorGroup, "SiFive vector extensions"},
{DecoderTableXSfsystem32, XSfSystemGroup, "SiFive system extensions"},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index d388e0ea81c19..ca8df64862f7e 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1305,14 +1305,6 @@ def HasStdExtY : Predicate<"Subtarget->hasStdExtY()">,
// Vendor extensions
//===----------------------------------------------------------------------===//
-// Ventana Extensions
-
-def FeatureVendorXVentanaCondOps
- : RISCVExtension<1, 0, "Ventana Conditional Ops">;
-def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()">,
- AssemblerPredicate<(all_of FeatureVendorXVentanaCondOps),
- "'XVentanaCondOps' (Ventana Conditional Ops)">;
-
// T-Head Extensions
def FeatureVendorXTHeadBa
@@ -2238,7 +2230,3 @@ def TuneMIPSP8700
def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
"SiFive 7-Series processors", [], InlineIgnore>;
-
-def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron",
- "Ventana Veyron-Series processors",
- [], InlineIgnore>;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 3ed01728057d6..d8a9c4ee31f1e 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -10346,10 +10346,10 @@ static SDValue lowerSelectToBinOp(SDNode *N, SelectionDAG &DAG,
return DAG.getNode(ISD::OR, DL, VT, Neg, DAG.getFreeze(TrueV));
}
- const bool HasCZero = VT.isScalarInteger() && Subtarget.hasCZEROLike();
+ const bool HasZicond = VT.isScalarInteger() && Subtarget.hasStdExtZicond();
// (select c, 0, y) -> (c-1) & y
- if (isNullConstant(TrueV) && (!HasCZero || isSimm12Constant(FalseV))) {
+ if (isNullConstant(TrueV) && (!HasZicond || isSimm12Constant(FalseV))) {
SDValue Neg =
DAG.getNode(ISD::ADD, DL, VT, CondV, DAG.getAllOnesConstant(DL, VT));
return DAG.getNode(ISD::AND, DL, VT, Neg, DAG.getFreeze(FalseV));
@@ -10373,7 +10373,7 @@ static SDValue lowerSelectToBinOp(SDNode *N, SelectionDAG &DAG,
}
}
// (select c, y, 0) -> -c & y
- if (!HasCZero || isSimm12Constant(TrueV)) {
+ if (!HasZicond || isSimm12Constant(TrueV)) {
SDValue Neg = DAG.getNegative(CondV, DL, VT);
return DAG.getNode(ISD::AND, DL, VT, Neg, DAG.getFreeze(TrueV));
}
@@ -10558,11 +10558,11 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
return DAG.getBitcast(VT, ResultInt);
}
- // When Zicond or XVentanaCondOps is present, emit CZERO_EQZ and CZERO_NEZ
+ // When Zicond is present, emit CZERO_EQZ and CZERO_NEZ
// nodes to implement the SELECT. Performing the lowering here allows for
// greater control over when CZERO_{EQZ/NEZ} are used vs another branchless
// sequence or RISCVISD::SELECT_CC node (branch-based select).
- if (Subtarget.hasCZEROLike() && VT.isScalarInteger()) {
+ if (Subtarget.hasStdExtZicond() && VT.isScalarInteger()) {
// (select c, t, 0) -> (czero_eqz t, c)
if (isNullConstant(FalseV))
@@ -17856,7 +17856,7 @@ static SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
if (!Subtarget.hasConditionalMoveFusion()) {
// (select cond, x, (and x, c)) has custom lowering with Zicond.
- if (!Subtarget.hasCZEROLike() || N->getOpcode() != ISD::AND)
+ if (!Subtarget.hasStdExtZicond() || N->getOpcode() != ISD::AND)
return SDValue();
// Maybe harmful when condition code has multiple use.
@@ -22192,7 +22192,7 @@ static SDValue useInversedSetcc(SDNode *N, SelectionDAG &DAG,
// Replace (setcc eq (and x, C)) with (setcc ne (and x, C))) to generate
// BEXTI, where C is power of 2.
if (Subtarget.hasBEXTILike() && VT.isScalarInteger() &&
- (Subtarget.hasCZEROLike() || Subtarget.hasVendorXTHeadCondMov())) {
+ (Subtarget.hasStdExtZicond() || Subtarget.hasVendorXTHeadCondMov())) {
SDValue LHS = Cond.getOperand(0);
SDValue RHS = Cond.getOperand(1);
ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
@@ -29158,7 +29158,7 @@ RISCVTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
bool RISCVTargetLowering::shouldFoldSelectWithSingleBitTest(
EVT VT, const APInt &AndMask) const {
- if (Subtarget.hasCZEROLike() || Subtarget.hasVendorXTHeadCondMov())
+ if (Subtarget.hasStdExtZicond() || Subtarget.hasVendorXTHeadCondMov())
return !Subtarget.hasBEXTILike() && AndMask.ugt(1024);
return TargetLowering::shouldFoldSelectWithSingleBitTest(VT, AndMask);
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 1a0f85271a9b1..ea8c85645a981 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2471,7 +2471,6 @@ include "RISCVInstrInfoY.td"
// Vendor extensions
//===----------------------------------------------------------------------===//
-include "RISCVInstrInfoXVentana.td"
include "RISCVInstrInfoXTHead.td"
include "RISCVInstrInfoXSf.td"
include "RISCVInstrInfoXSfmm.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
deleted file mode 100644
index 8cec2558f9923..0000000000000
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
+++ /dev/null
@@ -1,32 +0,0 @@
-//===-- RISCVInstrInfoXVentana.td --------------------------*- tablegen -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes the vendor extensions defined by Ventana Micro Systems.
-//
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// XVentanaCondOps
-//===----------------------------------------------------------------------===//
-
-let Predicates = [HasVendorXVentanaCondOps], hasSideEffects = 0,
- mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, DecoderNamespace = "XVentana" in
-class VTMaskedMove<bits<3> funct3, string opcodestr>
- : RVInstR<0b0000000, funct3, OPC_CUSTOM_3, (outs GPR:$rd),
- (ins GPR:$rs1, GPR:$rs2), opcodestr,
- "$rd, $rs1, $rs2"> {
-}
-
-def VT_MASKC : VTMaskedMove<0b110, "vt.maskc">,
- Sched<[WriteIALU, ReadIALU, ReadIALU]>;
-
-def VT_MASKCN : VTMaskedMove<0b111, "vt.maskcn">,
- Sched<[WriteIALU, ReadIALU, ReadIALU]>;
-
-let Predicates = [HasVendorXVentanaCondOps] in
-defm : CondOpsPat<VT_MASKC, VT_MASKCN>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
index 2059d2b5c2ddc..5e94c81c63475 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
@@ -15,10 +15,9 @@
// RISC-V specific DAG Nodes.
//===----------------------------------------------------------------------===//
-// Branchless select operations, matching the semantics of the instructions
-// defined in Zicond or XVentanaCondOps
-def riscv_czero_eqz : RVSDNode<"CZERO_EQZ", SDTIntBinOp>; // vt.maskc for XVentanaCondOps.
-def riscv_czero_nez : RVSDNode<"CZERO_NEZ", SDTIntBinOp>; // vt.maskcn for XVentanaCondOps.
+// Branchless select operations, matching the semantics of Zicond instructions.
+def riscv_czero_eqz : RVSDNode<"CZERO_EQZ", SDTIntBinOp>;
+def riscv_czero_nez : RVSDNode<"CZERO_NEZ", SDTIntBinOp>;
//===----------------------------------------------------------------------===//
// Instructions
@@ -35,8 +34,7 @@ def CZERO_NEZ : ALU_rr<0b0000111, 0b111, "czero.nez">,
// Pseudo-instructions and codegen patterns
//===----------------------------------------------------------------------===//
-// Zero (eqz) is instantiated with CZERO_EQZ or a compatible custom
-// instruction, and nez with CZERO_NEZ or a compatible custom instruction.
+// Zero (eqz) is instantiated with CZERO_EQZ and nez with CZERO_NEZ.
multiclass CondOpsPat<Instruction eqz, Instruction nez> {
def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, GPR:$rc)),
(eqz GPR:$rs1, GPR:$rc)>;
diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index 45e119a1c03d5..608f381254c41 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -358,8 +358,6 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
case RISCV::CZERO_EQZ:
case RISCV::CZERO_NEZ:
- case RISCV::VT_MASKC:
- case RISCV::VT_MASKCN:
if (OpIdx != 1)
return false;
Worklist.emplace_back(UserMI, Bits);
@@ -648,8 +646,6 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
case RISCV::CZERO_EQZ:
case RISCV::CZERO_NEZ:
- case RISCV::VT_MASKC:
- case RISCV::VT_MASKCN:
// Instructions return zero or operand 1. Result is sign extended if
// operand 1 is sign extended.
if (!AddRegToWorkList(MI->getOperand(1).getReg()))
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index b1f7f99d63f66..7fe808e254b7f 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -764,45 +764,6 @@ def TENSTORRENT_ASCALON_X : RISCVProcessorModel<"tt-ascalon-x",
TuneOptimizedZeroStrideLoad,
TunePostRAScheduler]>;
-def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
- NoSchedModel,
- [Feature64Bit,
- FeatureStdExtI,
- FeatureStdExtZifencei,
- FeatureStdExtZicsr,
- FeatureStdExtZicntr,
- FeatureStdExtZihpm,
- FeatureStdExtZihintpause,
- FeatureStdExtM,
- FeatureStdExtA,
- FeatureStdExtF,
- FeatureStdExtD,
- FeatureStdExtC,
- FeatureStdExtZba,
- FeatureStdExtZbb,
- FeatureStdExtZbc,
- FeatureStdExtZbs,
- FeatureStdExtZicbom,
- FeatureStdExtZicbop,
- FeatureStdExtZicboz,
- FeatureV...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/221053
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