[clang] [llvm] [RegAlloc] [X86] Enable callee saved register optimization for x86 (PR #220090)

[David Li via cfe-commits]

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@@ -1296,3 +1296,13 @@ bool X86RegisterInfo::isNonRex2RegClass(const TargetRegisterClass *RC) const {
     return true;
   }
 }
+
+unsigned X86RegisterInfo::getCSRFirstUseCost(const MachineFunction &MF) const {
+  // If PPX is implemented, push/pop pairs don't access memory.
+  const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
+  if (ST.is64Bit() && ST.hasPPX())
+    return 0;
+
+  // push + pop.
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david-xl wrote:

Better controlled by an option instead of hard coded with 2.

https://github.com/llvm/llvm-project/pull/220090