[clang] ca70db3 - [Clang][OpenMP] Canonicalize Intra-tiles in Loop Tiling (#191114)
via cfe-commits
cfe-commits at lists.llvm.org
Wed Sep 2 02:14:40 PDT 2026
Author: Amit Tiwari
Date: 2026-09-02T14:44:34+05:30
New Revision: ca70db3c250f25f9286ff1aeb9164d4b93a5fdc6
URL: https://github.com/llvm/llvm-project/commit/ca70db3c250f25f9286ff1aeb9164d4b93a5fdc6
DIFF: https://github.com/llvm/llvm-project/commit/ca70db3c250f25f9286ff1aeb9164d4b93a5fdc6.diff
LOG: [Clang][OpenMP] Canonicalize Intra-tiles in Loop Tiling (#191114)
This PR canonicalizes the intra-tile loop in OpenMP loop tiling.
Take a simple example:
```cpp
#pragma omp tile sizes(4)
for (int i = 0; i < 6; ++i)
body(i);
```
`clang` turns the above into **2 nested loops**:
- Outer (aka *floor*) loop iterating in steps of 4.
- Inner (aka *intra-tile*) loop iterating over the tiles — `(0, 1, 2,
3)` and `(4, 5)` — since 6 is not a multiple of 4, this results in the
last **partial tile**.
So, to make sure the partial/remainder tile doesn't overshoot, we may
enforce two kinds of intra-tile shapes, where both shapes produce the
same visible result:
**Shape 1** (*vectorized form*; default):
```cpp
for (i = floor; i < min(floor + 4, 6); ++i)
body(i);
```
**Shape 2** (*canonicalized form*):
```cpp
for (i = floor; i < floor + 4; ++i)
if (i < 6) // guard: skip the overshoot
body(i);
```
A subtle point: Shape 2 should be kept **only when the intra-tile is
consumed by a parent directive** (e.g. `collapse`). This further
promotes no disruption in the generic C/C++ for-loop codegen pipeline
and also preserves the vectorized form (saving iterations), unless
otherwise.
## Solution
Always preserve **Shape 1** wrapped in a new internal droppable
attribute `OMPInvariantPredicateBoundAttr` carrying three expressions:
- **`RectCond`** — a rectangular bound (`.tile.iv < .floor.iv +
tilesize`)
- **`Predicate`** — a body guard for the remainder tile (`.tile.iv < N`)
- **`TileSize`** — the floor-independent, loop-nest invariant per-tile
trip count
If nothing ever reads the note, it's completely invisible — the loop
just runs in its natural shape, exactly like plain `clang`. That's why
it's *droppable*.
Only when `collapse` (or a similar directive) actually consumes this
loop does Clang (`checkOpenMPIterationSpace` / `checkOpenMPLoop`) read
the hint and reinterpret the loop as rectangular.
Added:
clang/test/OpenMP/tile_collapse_messages.cpp
clang/test/OpenMP/tile_collapse_reinterpret_codegen.cpp
clang/test/OpenMP/tile_rect_codegen_ir.cpp
clang/test/OpenMP/tile_vectorize_codegen.cpp
openmp/runtime/test/transform/tile/parallel-wsloop-collapse-stacked-tile.cpp
openmp/runtime/test/transform/tile/parallel-wsloop-collapse-through-tile-2d.cpp
openmp/runtime/test/transform/tile/parallel-wsloop-collapse-through-tile-compose.cpp
openmp/runtime/test/transform/tile/parallel-wsloop-collapse-through-tile-iterator.cpp
openmp/runtime/test/transform/tile/parallel-wsloop-collapse-through-tile.cpp
Modified:
clang/docs/OpenMPSupport.md
clang/docs/ReleaseNotes.md
clang/include/clang/AST/StmtOpenMP.h
clang/include/clang/Basic/Attr.td
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/lib/AST/StmtOpenMP.cpp
clang/lib/CodeGen/CGStmtOpenMP.cpp
clang/lib/Sema/SemaOpenMP.cpp
clang/test/OpenMP/interchange_codegen.cpp
clang/test/OpenMP/tile_codegen.cpp
clang/test/OpenMP/tile_messages.cpp
clang/unittests/AST/AttrTest.cpp
Removed:
################################################################################
diff --git a/clang/docs/OpenMPSupport.md b/clang/docs/OpenMPSupport.md
index 47440be886c8e..def67f21b0ac1 100644
--- a/clang/docs/OpenMPSupport.md
+++ b/clang/docs/OpenMPSupport.md
@@ -182,7 +182,7 @@ implementation.
| device | allow virtual functions calls for mapped object on device | {part}`partial` | |
| device | interop construct | {part}`partial` | parsing/sema done: [D98558][D98558], [D98834][D98834], [D98815][D98815] |
| device | assorted routines for querying interoperable properties | {part}`partial` | [D106674][D106674] |
-| loop | Loop tiling transformation | {good}`done` | [D76342][D76342] |
+| loop | Loop tiling transformation | {good}`done` | [D76342][D76342], canonicalisation of intra-tile loops: [PR191114][PR191114] (stacked tile not yet supported) |
| loop | Loop unrolling transformation | {good}`done` | [D99459][D99459] |
| loop | 'reproducible'/'unconstrained' modifiers in 'order' clause | {part}`partial` | [D127855][D127855] |
| memory management | alignment for allocate directive and clause | {good}`done` | [D115683][D115683] |
@@ -559,6 +559,7 @@ considered for standardization. Please post on the
[PR174659]: https://github.com/llvm/llvm-project/pull/174659
[PR186281]: https://github.com/llvm/llvm-project/pull/186281
[PR189347]: https://github.com/llvm/llvm-project/pull/189347
+[PR191114]: https://github.com/llvm/llvm-project/pull/191114
[PR194168]: https://github.com/llvm/llvm-project/pull/194168
[PR195829]: https://github.com/llvm/llvm-project/pull/195829
[PR196431]: https://github.com/llvm/llvm-project/pull/196431
diff --git a/clang/docs/ReleaseNotes.md b/clang/docs/ReleaseNotes.md
index 4c2bf55f6ebdd..492f13dafa297 100644
--- a/clang/docs/ReleaseNotes.md
+++ b/clang/docs/ReleaseNotes.md
@@ -786,6 +786,21 @@ The `alpha.cplusplus.UseAfterLifetimeEnd` checker was renamed to `alpha.core.Use
### OpenMP Support
+- Canonicalize intra-tiles in loop tiling. `#pragma omp tile` still emits a
+ min-bounded inner loop, which vectorizes well. When a parent directive such as
+ `for collapse(n)` needs a constant per-tile trip count, Clang rereads a
+ droppable hint and treats that inner loop as rectangular, with an overshoot
+ guard only if the last tile can be partial.
+
+ Not yet supported (diagnosed, left as follow-up):
+
+ - `collapse` through stacked `#pragma omp tile` (the inner floor is not a
+ collapsed counter).
+ - A loop transformation (`tile`, `unroll`, `interchange`, ...) that consumes
+ another tile's intra-tile loop.
+
+- Added parsing and semantic support for `dims` modifier in `num_teams` and
+ `thread_limit` clauses for OpenMP 6.1 or later.
- Added parsing and semantic support for `dims` modifier in `num_teams`,
`thread_limit` and `num_threads` clauses for OpenMP 6.1 or later.
- Map-type-modifying modifiers applied to a list item with a user-defined mapper
diff --git a/clang/include/clang/AST/StmtOpenMP.h b/clang/include/clang/AST/StmtOpenMP.h
index cb154866e1ca2..bd95080707e1e 100644
--- a/clang/include/clang/AST/StmtOpenMP.h
+++ b/clang/include/clang/AST/StmtOpenMP.h
@@ -25,6 +25,8 @@
namespace clang {
+class OMPInvariantPredicateBoundAttr;
+
//===----------------------------------------------------------------------===//
// AST classes for directives.
//===----------------------------------------------------------------------===//
@@ -892,15 +894,46 @@ class OMPLoopBasedDirective : public OMPExecutableDirective {
TryImperfectlyNestedLoops);
}
+ /// Returns the intra-tile reinterpretation hint attached to \p S, or nullptr
+ /// if \p S does not carry one. See OMPInvariantPredicateBoundAttr.
+ static const OMPInvariantPredicateBoundAttr *getIntraTileHint(const Stmt *S);
+
+ /// If \p S is an intra-tile reinterpretation wrapper, returns the loop it
+ /// annotates; otherwise returns \p S unchanged.
+ static Stmt *ignoreIntraTileHint(Stmt *S);
+ static const Stmt *ignoreIntraTileHint(const Stmt *S) {
+ return ignoreIntraTileHint(const_cast<Stmt *>(S));
+ }
+
/// Calls the specified callback function for all the loops in \p CurStmt,
/// from the outermost to the innermost.
+ ///
+ /// \p Loop is always a ForStmt or CXXForRangeStmt. \p HintWrapper is the
+ /// intra-tile OMPInvariantPredicateBoundAttr wrapper around that loop, or
+ /// nullptr if the loop has no such hint. Callers that need the hint (see
+ /// checkOpenMPIterationSpace) can peel \p HintWrapper themselves; everyone
+ /// else can ignore it.
static bool
doForAllLoops(Stmt *CurStmt, bool TryImperfectlyNestedLoops,
unsigned NumLoops,
- llvm::function_ref<bool(unsigned, Stmt *)> Callback,
+ llvm::function_ref<bool(unsigned /*Cnt*/, Stmt * /*Loop*/,
+ Stmt * /*HintWrapper*/)>
+ Callback,
llvm::function_ref<void(OMPLoopTransformationDirective *)>
OnTransformationCallback);
static bool
+ doForAllLoops(Stmt *CurStmt, bool TryImperfectlyNestedLoops,
+ unsigned NumLoops,
+ llvm::function_ref<bool(unsigned, Stmt *)> Callback,
+ llvm::function_ref<void(OMPLoopTransformationDirective *)>
+ OnTransformationCallback) {
+ auto &&NewCallback = [Callback](unsigned Cnt, Stmt *Loop, Stmt *) {
+ return Callback(Cnt, Loop);
+ };
+ return doForAllLoops(CurStmt, TryImperfectlyNestedLoops, NumLoops,
+ NewCallback, OnTransformationCallback);
+ }
+ static bool
doForAllLoops(const Stmt *CurStmt, bool TryImperfectlyNestedLoops,
unsigned NumLoops,
llvm::function_ref<bool(unsigned, const Stmt *)> Callback,
diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td
index 8530216f2c214..66142ed95090a 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -4882,6 +4882,20 @@ def OMPAssume : InheritableAttr {
let Args = [StringArgument<"Assumption">];
}
+def OMPInvariantPredicateBound : StmtAttr {
+ // Internal droppable hint on an `#pragma omp tile` intra-tile loop.
+ // RectCond: rectangular bound (`t < floor + T`) used instead of the stored
+ // `min(floor + T, N)` condition.
+ // TileSize: constant intra-tile trip count T.
+ // Predicate: optional overshoot guard (`t < N`); omitted when N % T == 0.
+ let Spellings = [];
+ let SemaHandler = 0;
+ let Subjects = SubjectList<[Stmt], ErrorDiag>;
+ let Args = [ExprArgument<"RectCond">, ExprArgument<"TileSize">,
+ ExprArgument<"Predicate", 1>];
+ let Documentation = [InternalOnly];
+}
+
def InternalLinkage : InheritableAttr {
let Spellings = [Clang<"internal_linkage">];
let Subjects = SubjectList<[Var, Function, CXXRecord]>;
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 8f2fcfcef58e1..b5100b67dccd7 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -12328,6 +12328,10 @@ def err_omp_loop_bad_collapse_var : Error<
"cannot use variable %1 in collapsed imperfectly-nested loop %select{init|condition|increment}0 statement">;
def err_omp_loop_var_reused_in_collapsed_loop : Error<
"loop iteration variable %0 cannot be reused in a nested loop of a collapsed loop nest">;
+def err_omp_collapse_stacked_tile : Error<
+ "cannot %select{collapse|apply a loop transformation to}0 the intra-tile loop "
+ "of a '#pragma omp tile' that is nested inside another loop-transforming "
+ "directive; OpenMP permits this construct, but it is not yet supported">;
def err_omp_simd_region_cannot_use_stmt : Error<
"'%0' statement cannot be used in OpenMP simd region">;
def warn_omp_loop_64_bit_var : Warning<
diff --git a/clang/lib/AST/StmtOpenMP.cpp b/clang/lib/AST/StmtOpenMP.cpp
index 0a0cf6352808f..44656266bcf08 100644
--- a/clang/lib/AST/StmtOpenMP.cpp
+++ b/clang/lib/AST/StmtOpenMP.cpp
@@ -10,12 +10,53 @@
//
//===----------------------------------------------------------------------===//
-#include "clang/AST/ASTContext.h"
#include "clang/AST/StmtOpenMP.h"
+#include "clang/AST/ASTContext.h"
+#include "clang/AST/Attr.h"
+#include "clang/AST/Stmt.h"
using namespace clang;
using namespace llvm::omp;
+/// Returns the intra-tile hint attribute for the given statement.
+const OMPInvariantPredicateBoundAttr *
+OMPLoopBasedDirective::getIntraTileHint(const Stmt *S) {
+ if (const auto *AS = dyn_cast_or_null<AttributedStmt>(S))
+ return getSpecificAttr<OMPInvariantPredicateBoundAttr>(AS->getAttrs());
+ return nullptr;
+}
+
+/// Peek through an intra-tile hint wrapper to return the underlying loop.
+Stmt *OMPLoopBasedDirective::ignoreIntraTileHint(Stmt *S) {
+ if (auto *AS = dyn_cast_or_null<AttributedStmt>(S))
+ if (hasSpecificAttr<OMPInvariantPredicateBoundAttr>(AS->getAttrs()))
+ return AS->getSubStmt();
+ return S;
+}
+
+/// Like `Stmt::IgnoreContainers`, but stops at (and preserves) an intra-tile
+/// hint wrapper so that the enclosing loop walker can deliver the hint to
+/// loop-associated analysis (e.g. `collapse`). Non-hint attributed statements
+/// and single-statement compounds are still skipped.
+static Stmt *ignoreContainersKeepingIntraTileHint(Stmt *S) {
+ while (true) {
+ if (auto *AS = dyn_cast_or_null<AttributedStmt>(S)) {
+ if (hasSpecificAttr<OMPInvariantPredicateBoundAttr>(AS->getAttrs()))
+ break;
+ S = AS->getSubStmt();
+ continue;
+ }
+ if (auto *CS = dyn_cast_or_null<CompoundStmt>(S)) {
+ if (CS->size() != 1)
+ break;
+ S = CS->body_back();
+ continue;
+ }
+ break;
+ }
+ return S;
+}
+
size_t OMPChildren::size(unsigned NumClauses, bool HasAssociatedStmt,
unsigned NumChildren) {
return llvm::alignTo(
@@ -78,7 +119,7 @@ Stmt *
OMPLoopBasedDirective::tryToFindNextInnerLoop(Stmt *CurStmt,
bool TryImperfectlyNestedLoops) {
Stmt *OrigStmt = CurStmt;
- CurStmt = CurStmt->IgnoreContainers();
+ CurStmt = ignoreContainersKeepingIntraTileHint(CurStmt);
// Additional work for imperfectly nested loops, introduced in OpenMP 5.0.
if (TryImperfectlyNestedLoops) {
if (auto *CS = dyn_cast<CompoundStmt>(CurStmt)) {
@@ -92,10 +133,17 @@ OMPLoopBasedDirective::tryToFindNextInnerLoop(Stmt *CurStmt,
for (Stmt *S : CS->body()) {
if (!S)
continue;
- if (auto *CanonLoop = dyn_cast<OMPCanonicalLoop>(S))
- S = CanonLoop->getLoopStmt();
- if (isa<ForStmt>(S) || isa<CXXForRangeStmt>(S) ||
- (isa<OMPLoopBasedDirective>(S) && !isa<OMPLoopDirective>(S))) {
+ // Peek past an OMPCanonicalLoop wrapper and/or an intra-tile hint to
+ // check whether this child is loop-like; keep the original (wrapped)
+ // node in CurStmt so the hint still reaches the loop-analysis
+ // callback.
+ Stmt *Inner = S;
+ if (auto *CanonLoop = dyn_cast<OMPCanonicalLoop>(Inner))
+ Inner = CanonLoop->getLoopStmt();
+ Inner = OMPLoopBasedDirective::ignoreIntraTileHint(Inner);
+ if (isa<ForStmt>(Inner) || isa<CXXForRangeStmt>(Inner) ||
+ (isa<OMPLoopBasedDirective>(Inner) &&
+ !isa<OMPLoopDirective>(Inner))) {
// Only single loop construct is allowed.
if (CurStmt) {
CurStmt = OrigStmt;
@@ -124,10 +172,10 @@ OMPLoopBasedDirective::tryToFindNextInnerLoop(Stmt *CurStmt,
bool OMPLoopBasedDirective::doForAllLoops(
Stmt *CurStmt, bool TryImperfectlyNestedLoops, unsigned NumLoops,
- llvm::function_ref<bool(unsigned, Stmt *)> Callback,
+ llvm::function_ref<bool(unsigned, Stmt *, Stmt *)> Callback,
llvm::function_ref<void(OMPLoopTransformationDirective *)>
OnTransformationCallback) {
- CurStmt = CurStmt->IgnoreContainers();
+ CurStmt = ignoreContainersKeepingIntraTileHint(CurStmt);
for (unsigned Cnt = 0; Cnt < NumLoops; ++Cnt) {
while (true) {
auto *Dir = dyn_cast<OMPLoopTransformationDirective>(CurStmt);
@@ -157,19 +205,23 @@ bool OMPLoopBasedDirective::doForAllLoops(
}
if (auto *CanonLoop = dyn_cast<OMPCanonicalLoop>(CurStmt))
CurStmt = CanonLoop->getLoopStmt();
- if (Callback(Cnt, CurStmt))
+ // Always hand the real loop to the callback and pass the hint wrapper
+ // separately so the callee can read it.
+ Stmt *LoopStmt = ignoreIntraTileHint(CurStmt);
+ Stmt *HintWrapper = LoopStmt != CurStmt ? CurStmt : nullptr;
+ if (Callback(Cnt, LoopStmt, HintWrapper))
return false;
// Move on to the next nested for loop, or to the loop body.
// OpenMP [2.8.1, simd construct, Restrictions]
// All loops associated with the construct must be perfectly nested; that
// is, there must be no intervening code nor any OpenMP directive between
// any two loops.
- if (auto *For = dyn_cast<ForStmt>(CurStmt)) {
+ if (auto *For = dyn_cast<ForStmt>(LoopStmt)) {
CurStmt = For->getBody();
} else {
- assert(isa<CXXForRangeStmt>(CurStmt) &&
+ assert(isa<CXXForRangeStmt>(LoopStmt) &&
"Expected canonical for or range-based for loops.");
- CurStmt = cast<CXXForRangeStmt>(CurStmt)->getBody();
+ CurStmt = cast<CXXForRangeStmt>(LoopStmt)->getBody();
}
CurStmt = OMPLoopBasedDirective::tryToFindNextInnerLoop(
CurStmt, TryImperfectlyNestedLoops);
diff --git a/clang/lib/CodeGen/CGStmtOpenMP.cpp b/clang/lib/CodeGen/CGStmtOpenMP.cpp
index a761ac6bbf816..edb665e94df3b 100644
--- a/clang/lib/CodeGen/CGStmtOpenMP.cpp
+++ b/clang/lib/CodeGen/CGStmtOpenMP.cpp
@@ -2247,7 +2247,11 @@ static void emitBody(CodeGenFunction &CGF, const Stmt *S, const Stmt *NextLoop,
emitBody(CGF, CurStmt, NextLoop, MaxLevel, Level);
return;
}
- if (SimplifiedS == NextLoop) {
+
+ // `tryToFindNextInnerLoop` keeps the intra-tile hint wrapper around, so match
+ // against the loop it annotates. The tile overshoot guard is emitted
+ // separately via EmitOMPLoopBody's finals-conditions handling.
+ if (SimplifiedS == OMPLoopBasedDirective::ignoreIntraTileHint(NextLoop)) {
if (auto *Dir = dyn_cast<OMPLoopTransformationDirective>(SimplifiedS))
SimplifiedS = Dir->getTransformedStmt();
if (const auto *CanonLoop = dyn_cast<OMPCanonicalLoop>(SimplifiedS))
diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp
index 985ffd968fdde..3b4b9df767e73 100644
--- a/clang/lib/Sema/SemaOpenMP.cpp
+++ b/clang/lib/Sema/SemaOpenMP.cpp
@@ -17,6 +17,7 @@
#include "TreeTransform.h"
#include "clang/AST/ASTContext.h"
#include "clang/AST/ASTMutationListener.h"
+#include "clang/AST/Attr.h"
#include "clang/AST/CXXInheritance.h"
#include "clang/AST/Decl.h"
#include "clang/AST/DeclCXX.h"
@@ -9645,11 +9646,32 @@ static bool checkOpenMPIterationSpace(
const llvm::SmallPtrSetImpl<const Decl *> &CollapsedLoopVarDecls,
llvm::SmallPtrSetImpl<const Decl *> &CollapsedLoopInductionVars) {
bool SupportsNonRectangular = !isOpenMPLoopTransformationDirective(DKind);
+
+ // See the tile reinterpretation design note in ActOnOpenMPTileDirective.
+ // If the loop carries the hint, analyze its rectangular form instead.
+ //
+ // Only directives that emit the per-iteration body guard (i.e. those going
+ // through EmitOMPLoopBody's finals-conditions handling) may reinterpret the
+ // loop; a loop transformation such as an enclosing 'tile' has nowhere to put
+ // the overshoot guard, so for those the stored min-bounded form is analyzed
+ // exactly as it is on a build without this hint.
// OpenMP [2.9.1, Canonical Loop Form]
// for (init-expr; test-expr; incr-expr) structured-block
// for (range-decl: range-expr) structured-block
if (auto *CanonLoop = dyn_cast_or_null<OMPCanonicalLoop>(S))
S = CanonLoop->getLoopStmt();
+ const OMPInvariantPredicateBoundAttr *IntraTileHint =
+ OMPLoopBasedDirective::getIntraTileHint(S);
+ if (IntraTileHint)
+ S = OMPLoopBasedDirective::ignoreIntraTileHint(S);
+ Expr *TileRectCond = nullptr;
+ Expr *TileBodyPredicate = nullptr;
+ Expr *TileTripCount = nullptr;
+ if (IntraTileHint && !isOpenMPLoopTransformationDirective(DKind)) {
+ TileRectCond = IntraTileHint->getRectCond();
+ TileBodyPredicate = IntraTileHint->getPredicate();
+ TileTripCount = IntraTileHint->getTileSize();
+ }
auto *For = dyn_cast_or_null<ForStmt>(S);
auto *CXXFor = dyn_cast_or_null<CXXForRangeStmt>(S);
// Ranged for is supported only in OpenMP 5.0.
@@ -9694,6 +9716,11 @@ static bool checkOpenMPIterationSpace(
bool HasErrors = false;
+ // Condition used for iteration-space analysis: the rectangular hint when
+ // reinterpreting an intra-tile loop, otherwise the loop's own condition.
+ Expr *EffectiveCond =
+ TileRectCond ? TileRectCond : (For ? For->getCond() : CXXFor->getCond());
+
// Check loop variable's type.
if (ValueDecl *LCDecl = ISC.getLoopDecl()) {
// OpenMP [2.6, Canonical Loop Form]
@@ -9726,7 +9753,7 @@ static bool checkOpenMPIterationSpace(
"DSA for non-loop vars");
// Check test-expr.
- HasErrors |= ISC.checkAndSetCond(For ? For->getCond() : CXXFor->getCond());
+ HasErrors |= ISC.checkAndSetCond(EffectiveCond);
// Check incr-expr.
HasErrors |= ISC.checkAndSetInc(For ? For->getInc() : CXXFor->getInc());
@@ -9736,16 +9763,33 @@ static bool checkOpenMPIterationSpace(
return HasErrors;
// Build the loop's iteration space representation.
- ResultIterSpaces[CurrentNestedLoopCount].PreCond = ISC.buildPreCond(
- DSA.getCurScope(), For ? For->getCond() : CXXFor->getCond(), Captures);
- ResultIterSpaces[CurrentNestedLoopCount].NumIterations =
- ISC.buildNumIterations(DSA.getCurScope(), ResultIterSpaces,
- (isOpenMPWorksharingDirective(DKind) ||
- isOpenMPGenericLoopDirective(DKind) ||
- isOpenMPTaskLoopDirective(DKind) ||
- isOpenMPDistributeDirective(DKind) ||
- isOpenMPLoopTransformationDirective(DKind)),
- Captures);
+ //
+ // A reinterpreted intra-tile loop takes all three of these from the hint
+ // instead of deriving them: the precondition is trivially true (the floor
+ // loop's own precondition already covers an empty iteration space), the trip
+ // count is the constant tile size, and any overshoot on the remainder tile
+ // is handled by the body guard.
+ if (TileRectCond) {
+ ResultIterSpaces[CurrentNestedLoopCount].PreCond =
+ SemaRef
+ .PerformImplicitConversion(
+ SemaRef.ActOnIntegerConstant(SourceLocation(), 1).get(),
+ SemaRef.Context.BoolTy, AssignmentAction::Casting,
+ /*AllowExplicit=*/true)
+ .get();
+ ResultIterSpaces[CurrentNestedLoopCount].NumIterations = TileTripCount;
+ } else {
+ ResultIterSpaces[CurrentNestedLoopCount].PreCond =
+ ISC.buildPreCond(DSA.getCurScope(), EffectiveCond, Captures);
+ ResultIterSpaces[CurrentNestedLoopCount].NumIterations =
+ ISC.buildNumIterations(DSA.getCurScope(), ResultIterSpaces,
+ (isOpenMPWorksharingDirective(DKind) ||
+ isOpenMPGenericLoopDirective(DKind) ||
+ isOpenMPTaskLoopDirective(DKind) ||
+ isOpenMPDistributeDirective(DKind) ||
+ isOpenMPLoopTransformationDirective(DKind)),
+ Captures);
+ }
ResultIterSpaces[CurrentNestedLoopCount].CounterVar =
ISC.buildCounterVar(Captures, DSA);
ResultIterSpaces[CurrentNestedLoopCount].PrivateCounterVar =
@@ -9763,14 +9807,53 @@ static bool checkOpenMPIterationSpace(
std::tie(ResultIterSpaces[CurrentNestedLoopCount].MinValue,
ResultIterSpaces[CurrentNestedLoopCount].MaxValue) =
ISC.buildMinMaxValues(DSA.getCurScope(), Captures);
- ResultIterSpaces[CurrentNestedLoopCount].FinalCondition =
- ISC.buildFinalCondition(DSA.getCurScope());
- ResultIterSpaces[CurrentNestedLoopCount].IsNonRectangularLB =
- ISC.doesInitDependOnLC();
- ResultIterSpaces[CurrentNestedLoopCount].IsNonRectangularUB =
- ISC.doesCondDependOnLC();
- ResultIterSpaces[CurrentNestedLoopCount].LoopDependentIdx =
- ISC.getLoopDependentIdx();
+ if (TileRectCond) {
+ // Floor is not a registered loop-control variable, so this helper is null.
+ // Use the overshoot guard only (null when N % T == 0).
+ assert(!ISC.buildFinalCondition(DSA.getCurScope()) &&
+ "intra-tile floor is not a registered loop-control variable");
+ ResultIterSpaces[CurrentNestedLoopCount].FinalCondition = TileBodyPredicate;
+
+ // Re-read .floor.iv each outer trip. Match it to an outer collapsed
+ // counter.
+ bool FoundFloor = false;
+ if (Expr *InitExpr = ResultIterSpaces[CurrentNestedLoopCount].CounterInit) {
+ if (const auto *LBRef =
+ dyn_cast<DeclRefExpr>(InitExpr->IgnoreParenImpCasts())) {
+ const Decl *FloorDecl = LBRef->getDecl()->getCanonicalDecl();
+ for (unsigned K = 0; K < CurrentNestedLoopCount; ++K) {
+ const auto *CV =
+ dyn_cast_or_null<DeclRefExpr>(ResultIterSpaces[K].CounterVar);
+ if (CV && CV->getDecl()->getCanonicalDecl() == FloorDecl) {
+ ResultIterSpaces[CurrentNestedLoopCount].IsNonRectangularLB = true;
+ ResultIterSpaces[CurrentNestedLoopCount].LoopDependentIdx = K + 1;
+ FoundFloor = true;
+ break;
+ }
+ }
+ }
+ }
+ if (!FoundFloor) {
+ // The floor this intra-tile loop starts from is not one of the
+ // collapsed counters: it is assigned in the body of an enclosing
+ // transformed loop, so the collapsed nest would read a stale value
+ // instead of recomputing it per iteration. Diagnose to avoid silently
+ // producing the wrong iteration space.
+ SemaRef.Diag(ISC.getInitSrcRange().getBegin(),
+ diag::err_omp_collapse_stacked_tile)
+ << /*Collapse=*/0;
+ return true;
+ }
+ } else {
+ ResultIterSpaces[CurrentNestedLoopCount].FinalCondition =
+ ISC.buildFinalCondition(DSA.getCurScope());
+ ResultIterSpaces[CurrentNestedLoopCount].IsNonRectangularLB =
+ ISC.doesInitDependOnLC();
+ ResultIterSpaces[CurrentNestedLoopCount].IsNonRectangularUB =
+ ISC.doesCondDependOnLC();
+ ResultIterSpaces[CurrentNestedLoopCount].LoopDependentIdx =
+ ISC.getLoopDependentIdx();
+ }
HasErrors |=
(ResultIterSpaces[CurrentNestedLoopCount].PreCond == nullptr ||
@@ -10162,7 +10245,9 @@ checkOpenMPLoop(OpenMPDirectiveKind DKind, Expr *CollapseLoopCountExpr,
[DKind, &SemaRef, &DSA, NumLoops, NestedLoopCount,
CollapseLoopCountExpr, OrderedLoopCountExpr, &VarsWithImplicitDSA,
&IterSpaces, &Captures, &CollapsedLoopVarDecls,
- &CollapsedLoopInductionVars](unsigned Cnt, Stmt *CurStmt) {
+ &CollapsedLoopInductionVars](unsigned Cnt, Stmt *Loop,
+ Stmt *HintWrapper) {
+ Stmt *CurStmt = HintWrapper ? HintWrapper : Loop;
if (checkOpenMPIterationSpace(
DKind, CurStmt, SemaRef, DSA, Cnt, NestedLoopCount,
NumLoops, CollapseLoopCountExpr, OrderedLoopCountExpr,
@@ -10761,11 +10846,13 @@ checkOpenMPLoop(OpenMPDirectiveKind DKind, Expr *CollapseLoopCountExpr,
Built.Finals[Cnt] = Final.get();
Built.DependentCounters[Cnt] = nullptr;
Built.DependentInits[Cnt] = nullptr;
- Built.FinalsConditions[Cnt] = nullptr;
+ // Transfer the body-guard condition: the loop condition for
+ // non-rectangular loops, the overshoot predicate for reinterpreted tiles,
+ // null otherwise.
+ Built.FinalsConditions[Cnt] = IS.FinalCondition;
if (IS.IsNonRectangularLB || IS.IsNonRectangularUB) {
Built.DependentCounters[Cnt] = Built.Counters[IS.LoopDependentIdx - 1];
Built.DependentInits[Cnt] = Built.Inits[IS.LoopDependentIdx - 1];
- Built.FinalsConditions[Cnt] = IS.FinalCondition;
}
}
}
@@ -14758,8 +14845,17 @@ bool SemaOpenMP::checkTransformableLoopNest(
OriginalInits.emplace_back();
bool Result = OMPLoopBasedDirective::doForAllLoops(
AStmt->IgnoreContainers(), /*TryImperfectlyNestedLoops=*/false, NumLoops,
- [this, &LoopHelpers, &Body, &OriginalInits, Kind](unsigned Cnt,
- Stmt *CurStmt) {
+ [this, &LoopHelpers, &Body, &OriginalInits,
+ Kind](unsigned Cnt, Stmt *CurStmt, Stmt *HintWrapper) {
+ // The start of this loop is a floor set in the enclosing tile's body.
+ // Loop analysis reads a start only once, so the nest would repeat the
+ // first tile. Reject instead of emitting wrong loops.
+ if (HintWrapper) {
+ SemaRef.Diag(CurStmt->getBeginLoc(),
+ diag::err_omp_collapse_stacked_tile)
+ << /*LoopTransform=*/1;
+ return true;
+ }
VarsWithInheritedDSAType TmpDSA;
unsigned SingleNumLoops =
checkOpenMPLoop(Kind, nullptr, nullptr, CurStmt, SemaRef, *DSAStack,
@@ -15238,6 +15334,29 @@ StmtResult SemaOpenMP::ActOnOpenMPTileDirective(ArrayRef<OMPClause *> Clauses,
};
// Create tile loops from the inside to the outside.
+ //
+ // Each intra-tile loop is emitted in its natural min-bounded form, which has
+ // no per-iteration body predicate and vectorizes well when run directly:
+ // for (.tile.iv = .floor.iv; .tile.iv < min(.floor.iv + T, N); ++.tile.iv)
+ //
+ // A loop-associated directive that *consumes* this loop (e.g. `collapse`)
+ // instead needs a constant, floor-independent trip count to linearize the
+ // nest, which the min() bound cannot give it. Rather than change the
+ // emitted loop, we attach a droppable OMPInvariantPredicateBoundAttr hint
+ // below carrying an equivalent rectangular reinterpretation:
+ // RectCond : .tile.iv < .floor.iv + T -- rectangular bound, analyzed by
+ // checkOpenMPIterationSpace in place of the stored condition
+ // TileSize : T -- constant per-tile trip count
+ // Predicate : .tile.iv < N -- remainder-tile overshoot,
+ // applied as a body guard instead of shortening the trip count;
+ // omitted when N is known to be a multiple of T, as there is
+ // then no partial tile to guard against
+ // Because the reinterpreted lower bound is still `.floor.iv`,
+ // checkOpenMPIterationSpace sets IsNonRectangularLB on the matching floor
+ // counter, so a collapsed `.tile.iv` re-reads the floor's current value
+ // instead of a stale preheader snapshot. Collapsing through stacked tiles
+ // (tile-of-tile) is not supported: the inner floor is not itself a collapsed
+ // counter.
for (int I = NumLoops - 1; I >= 0; --I) {
OMPLoopBasedDirective::HelperExprs &LoopHelper = LoopHelpers[I];
Expr *NumIterations = LoopHelper.NumIterations;
@@ -15302,6 +15421,55 @@ StmtResult SemaOpenMP::ActOnOpenMPTileDirective(ArrayRef<OMPClause *> Clauses,
if (!IncrStmt.isUsable())
return StmtError();
+ // Build OMPInvariantPredicateBoundAttr hint (RectCond, TileSize,
+ // Predicate).
+ Expr *RectDimTileSize = MakeDimTileSize(I);
+ if (!RectDimTileSize)
+ return StmtError();
+ ExprResult RectEndOfTile = SemaRef.BuildBinOp(
+ CurScope, LoopHelper.Cond->getExprLoc(), BO_Add,
+ makeFloorIVRef(SemaRef, FloorIndVars, I, IVTy, OrigCntVar),
+ RectDimTileSize);
+ if (!RectEndOfTile.isUsable())
+ return StmtError();
+ ExprResult RectCond =
+ SemaRef.BuildBinOp(CurScope, LoopHelper.Cond->getExprLoc(), BO_LT,
+ MakeTileIVRef(), RectEndOfTile.get());
+ Expr *TileSizeExpr = MakeDimTileSize(I);
+ if (!TileSizeExpr)
+ return StmtError();
+ ExprResult TileSize = SemaRef.PerformImplicitConversion(
+ TileSizeExpr, IVTy, AssignmentAction::Converting,
+ /*AllowExplicit=*/true);
+ if (!RectCond.isUsable() || !TileSize.isUsable())
+ return StmtError();
+
+ // The overshoot guard is only needed if the last tile can be partial. When
+ // both the trip count and the tile size are known at compile time and the
+ // former is a multiple of the latter, every tile is full, so leave the
+ // predicate out. A dependent or run-time value makes
+ // the evaluation fail, which keeps the guard.
+ bool NoPartialTile = false;
+ Expr::EvalResult TileSizeVal, NumIterationsVal;
+ if (TileSizeExpr->EvaluateAsInt(TileSizeVal, Context) &&
+ NumIterations->EvaluateAsInt(NumIterationsVal, Context)) {
+ llvm::APSInt TS = TileSizeVal.Val.getInt();
+ llvm::APSInt N = NumIterationsVal.Val.getInt();
+ unsigned Width = std::max(TS.getBitWidth(), N.getBitWidth());
+ TS = TS.extend(Width);
+ N = N.extend(Width);
+ NoPartialTile =
+ TS.isStrictlyPositive() && N.isStrictlyPositive() && N.urem(TS) == 0;
+ }
+
+ ExprResult Predicate;
+ if (!NoPartialTile) {
+ Predicate = SemaRef.BuildBinOp(CurScope, LoopHelper.Cond->getExprLoc(),
+ BO_LT, MakeTileIVRef(), NumIterations);
+ if (!Predicate.isUsable())
+ return StmtError();
+ }
+
// Statements to set the original iteration variable's value from the
// logical iteration number.
// Generated for loop is:
@@ -15329,6 +15497,14 @@ StmtResult SemaOpenMP::ActOnOpenMPTileDirective(ArrayRef<OMPClause *> Clauses,
ForStmt(Context, InitStmt.get(), CondExpr.get(), nullptr,
IncrStmt.get(), Inner, LoopHelper.Init->getBeginLoc(),
LoopHelper.Init->getBeginLoc(), LoopHelper.Inc->getEndLoc());
+
+ // Attach the droppable reinterpretation attribute to the intra-tile loop.
+ auto *Hint = OMPInvariantPredicateBoundAttr::CreateImplicit(
+ Context, RectCond.get(), TileSize.get(),
+ Predicate.isUsable() ? Predicate.get() : nullptr,
+ Inner->getSourceRange());
+ Inner =
+ AttributedStmt::Create(Context, Inner->getBeginLoc(), {Hint}, Inner);
}
// Create floor loops from the inside to the outside.
diff --git a/clang/test/OpenMP/interchange_codegen.cpp b/clang/test/OpenMP/interchange_codegen.cpp
index 8e833c9df324c..cc6e644ac70ac 100644
--- a/clang/test/OpenMP/interchange_codegen.cpp
+++ b/clang/test/OpenMP/interchange_codegen.cpp
@@ -123,6 +123,7 @@ extern "C" void foo10() {
#endif /* HEADER */
+
// CHECK1-LABEL: define {{[^@]+}}@body
// CHECK1-SAME: (...) #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry:
@@ -156,7 +157,7 @@ extern "C" void foo10() {
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
// CHECK1: for.end:
// CHECK1-NEXT: ret void
//
@@ -262,14 +263,14 @@ extern "C" void foo10() {
// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
// CHECK1-NEXT: [[INC:%.*]] = add i32 [[TMP28]], 1
// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND16]], !llvm.loop [[LOOP5:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND16]], !llvm.loop [[LOOP4:![0-9]+]]
// CHECK1: for.end:
// CHECK1-NEXT: br label [[FOR_INC22:%.*]]
// CHECK1: for.inc22:
// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
// CHECK1-NEXT: [[INC23:%.*]] = add i32 [[TMP29]], 1
// CHECK1-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 4
-// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
// CHECK1: for.end24:
// CHECK1-NEXT: ret void
//
@@ -342,7 +343,7 @@ extern "C" void foo10() {
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1
// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
// CHECK1: for.end:
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
@@ -439,7 +440,7 @@ extern "C" void foo10() {
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1
// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
// CHECK1: for.end:
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
@@ -754,28 +755,28 @@ extern "C" void foo10() {
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 4
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1
// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_3_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP9:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP8:![0-9]+]]
// CHECK1: for.end:
// CHECK1-NEXT: br label [[FOR_INC16:%.*]]
// CHECK1: for.inc16:
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 4
// CHECK1-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1
// CHECK1-NEXT: store i32 [[INC17]], ptr [[DOTPERMUTED_2_IV_L]], align 4
-// CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP10:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP9:![0-9]+]]
// CHECK1: for.end18:
// CHECK1-NEXT: br label [[FOR_INC19:%.*]]
// CHECK1: for.inc19:
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 4
// CHECK1-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP14]], 1
// CHECK1-NEXT: store i32 [[INC20]], ptr [[DOTPERMUTED_1_IV_K]], align 4
-// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP11:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP10:![0-9]+]]
// CHECK1: for.end21:
// CHECK1-NEXT: br label [[FOR_INC22:%.*]]
// CHECK1: for.inc22:
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
// CHECK1-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1
// CHECK1-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 4
-// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
// CHECK1: for.end24:
// CHECK1-NEXT: ret void
//
@@ -813,19 +814,20 @@ extern "C" void foo10() {
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTFLOOR_0_IV_K:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[_TMP35:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[I49:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[J50:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTFLOOR_0_IV_K51:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTTILE_0_IV_K52:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[I39:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[J40:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTFLOOR_0_IV_K41:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTTILE_0_IV_K42:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
// CHECK1-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4
// CHECK1-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4
@@ -865,628 +867,453 @@ extern "C" void foo10() {
// CHECK1-NEXT: store i32 [[ADD15]], ptr [[DOTCAPTURE_EXPR_14]], align 4
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[_TMP2]], align 4
// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
-// CHECK1-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 1
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[_TMP2]], align 4
-// CHECK1-NEXT: [[ADD19:%.*]] = add i32 [[TMP18]], 32
-// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD18]], [[ADD19]]
-// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK1: cond.true:
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
-// CHECK1-NEXT: [[ADD20:%.*]] = add i32 [[TMP19]], 1
-// CHECK1-NEXT: br label [[COND_END:%.*]]
-// CHECK1: cond.false:
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[_TMP2]], align 4
-// CHECK1-NEXT: [[ADD21:%.*]] = add i32 [[TMP20]], 32
-// CHECK1-NEXT: br label [[COND_END]]
-// CHECK1: cond.end:
-// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[ADD20]], [[COND_TRUE]] ], [ [[ADD21]], [[COND_FALSE]] ]
-// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
-// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[SUB23:%.*]] = sub i32 [[TMP21]], [[TMP22]]
-// CHECK1-NEXT: [[SUB24:%.*]] = sub i32 [[SUB23]], 1
-// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
-// CHECK1-NEXT: [[ADD25:%.*]] = add i32 [[SUB24]], [[TMP23]]
-// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
-// CHECK1-NEXT: [[DIV26:%.*]] = udiv i32 [[ADD25]], [[TMP24]]
-// CHECK1-NEXT: [[CONV:%.*]] = zext i32 [[DIV26]] to i64
-// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB27:%.*]] = sub i32 [[TMP25]], [[TMP26]]
-// CHECK1-NEXT: [[SUB28:%.*]] = sub i32 [[SUB27]], 1
-// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD29:%.*]] = add i32 [[SUB28]], [[TMP27]]
-// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV30:%.*]] = udiv i32 [[ADD29]], [[TMP28]]
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[_TMP2]], align 4
+// CHECK1-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 32
+// CHECK1-NEXT: store i32 [[ADD18]], ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[SUB20:%.*]] = sub i32 [[TMP18]], [[TMP19]]
+// CHECK1-NEXT: [[SUB21:%.*]] = sub i32 [[SUB20]], 1
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK1-NEXT: [[ADD22:%.*]] = add i32 [[SUB21]], [[TMP20]]
+// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK1-NEXT: [[DIV23:%.*]] = udiv i32 [[ADD22]], [[TMP21]]
+// CHECK1-NEXT: [[CONV:%.*]] = zext i32 [[DIV23]] to i64
+// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB24:%.*]] = sub i32 [[TMP22]], [[TMP23]]
+// CHECK1-NEXT: [[SUB25:%.*]] = sub i32 [[SUB24]], 1
+// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD26:%.*]] = add i32 [[SUB25]], [[TMP24]]
+// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV27:%.*]] = udiv i32 [[ADD26]], [[TMP25]]
+// CHECK1-NEXT: [[CONV28:%.*]] = zext i32 [[DIV27]] to i64
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV28]]
+// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB29:%.*]] = sub i32 [[TMP26]], -31
+// CHECK1-NEXT: [[DIV30:%.*]] = udiv i32 [[SUB29]], 32
// CHECK1-NEXT: [[CONV31:%.*]] = zext i32 [[DIV30]] to i64
-// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV31]]
-// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB32:%.*]] = sub i32 [[TMP29]], -31
-// CHECK1-NEXT: [[DIV33:%.*]] = udiv i32 [[SUB32]], 32
-// CHECK1-NEXT: [[CONV34:%.*]] = zext i32 [[DIV33]] to i64
-// CHECK1-NEXT: [[MUL35:%.*]] = mul nsw i64 [[MUL]], [[CONV34]]
-// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB36:%.*]] = sub i32 [[TMP30]], [[TMP31]]
-// CHECK1-NEXT: [[SUB37:%.*]] = sub i32 [[SUB36]], 1
-// CHECK1-NEXT: [[ADD38:%.*]] = add i32 [[SUB37]], 1
-// CHECK1-NEXT: [[DIV39:%.*]] = udiv i32 [[ADD38]], 1
-// CHECK1-NEXT: [[CONV40:%.*]] = zext i32 [[DIV39]] to i64
-// CHECK1-NEXT: [[MUL41:%.*]] = mul nsw i64 [[MUL35]], [[CONV40]]
-// CHECK1-NEXT: [[SUB42:%.*]] = sub nsw i64 [[MUL41]], 1
-// CHECK1-NEXT: store i64 [[SUB42]], ptr [[DOTCAPTURE_EXPR_22]], align 8
-// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: store i32 [[TMP32]], ptr [[I]], align 4
-// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: store i32 [[TMP33]], ptr [[J]], align 4
+// CHECK1-NEXT: [[MUL32:%.*]] = mul nsw i64 [[MUL]], [[CONV31]]
+// CHECK1-NEXT: [[MUL33:%.*]] = mul nsw i64 [[MUL32]], 32
+// CHECK1-NEXT: [[SUB34:%.*]] = sub nsw i64 [[MUL33]], 1
+// CHECK1-NEXT: store i64 [[SUB34]], ptr [[DOTCAPTURE_EXPR_19]], align 8
+// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: store i32 [[TMP27]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: store i32 [[TMP28]], ptr [[J]], align 4
// CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_K]], align 4
-// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: store i32 [[TMP34]], ptr [[DOTTILE_0_IV_K]], align 4
-// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
-// CHECK1-NEXT: [[CMP43:%.*]] = icmp slt i32 [[TMP35]], [[TMP36]]
-// CHECK1-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
+// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_K]], align 4
+// CHECK1-NEXT: store i32 [[TMP29]], ptr [[DOTTILE_0_IV_K]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[_TMP35]], align 4
+// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
+// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP30]], [[TMP31]]
+// CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK1: land.lhs.true:
-// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]]
-// CHECK1-NEXT: br i1 [[CMP44]], label [[LAND_LHS_TRUE45:%.*]], label [[OMP_PRECOND_END]]
-// CHECK1: land.lhs.true45:
-// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[CMP46:%.*]] = icmp ult i32 0, [[TMP39]]
-// CHECK1-NEXT: br i1 [[CMP46]], label [[LAND_LHS_TRUE47:%.*]], label [[OMP_PRECOND_END]]
-// CHECK1: land.lhs.true47:
-// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[CMP48:%.*]] = icmp ult i32 [[TMP40]], [[TMP41]]
-// CHECK1-NEXT: br i1 [[CMP48]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
+// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[CMP36:%.*]] = icmp slt i32 [[TMP32]], [[TMP33]]
+// CHECK1-NEXT: br i1 [[CMP36]], label [[LAND_LHS_TRUE37:%.*]], label [[OMP_PRECOND_END]]
+// CHECK1: land.lhs.true37:
+// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[CMP38:%.*]] = icmp ult i32 0, [[TMP34]]
+// CHECK1-NEXT: br i1 [[CMP38]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
// CHECK1: omp.precond.then:
// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
-// CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
-// CHECK1-NEXT: store i64 [[TMP42]], ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: [[TMP35:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_19]], align 8
+// CHECK1-NEXT: store i64 [[TMP35]], ptr [[DOTOMP_UB]], align 8
// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
-// CHECK1-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
-// CHECK1-NEXT: [[CMP53:%.*]] = icmp sgt i64 [[TMP43]], [[TMP44]]
-// CHECK1-NEXT: br i1 [[CMP53]], label [[COND_TRUE54:%.*]], label [[COND_FALSE55:%.*]]
-// CHECK1: cond.true54:
-// CHECK1-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
-// CHECK1-NEXT: br label [[COND_END56:%.*]]
-// CHECK1: cond.false55:
-// CHECK1-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK1-NEXT: br label [[COND_END56]]
-// CHECK1: cond.end56:
-// CHECK1-NEXT: [[COND57:%.*]] = phi i64 [ [[TMP45]], [[COND_TRUE54]] ], [ [[TMP46]], [[COND_FALSE55]] ]
-// CHECK1-NEXT: store i64 [[COND57]], ptr [[DOTOMP_UB]], align 8
-// CHECK1-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
-// CHECK1-NEXT: store i64 [[TMP47]], ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP36:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_19]], align 8
+// CHECK1-NEXT: [[CMP43:%.*]] = icmp sgt i64 [[TMP36]], [[TMP37]]
+// CHECK1-NEXT: br i1 [[CMP43]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK1: cond.true:
+// CHECK1-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_19]], align 8
+// CHECK1-NEXT: br label [[COND_END:%.*]]
+// CHECK1: cond.false:
+// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: br label [[COND_END]]
+// CHECK1: cond.end:
+// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ [[TMP38]], [[COND_TRUE]] ], [ [[TMP39]], [[COND_FALSE]] ]
+// CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: [[TMP40:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
+// CHECK1-NEXT: store i64 [[TMP40]], ptr [[DOTOMP_IV]], align 8
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK1-NEXT: [[CMP58:%.*]] = icmp sle i64 [[TMP48]], [[TMP49]]
-// CHECK1-NEXT: br i1 [[CMP58]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK1-NEXT: [[TMP41:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: [[CMP44:%.*]] = icmp sle i64 [[TMP41]], [[TMP42]]
+// CHECK1-NEXT: br i1 [[CMP44]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[CONV59:%.*]] = sext i32 [[TMP50]] to i64
-// CHECK1-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB60:%.*]] = sub i32 [[TMP52]], [[TMP53]]
-// CHECK1-NEXT: [[SUB61:%.*]] = sub i32 [[SUB60]], 1
-// CHECK1-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD62:%.*]] = add i32 [[SUB61]], [[TMP54]]
-// CHECK1-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV63:%.*]] = udiv i32 [[ADD62]], [[TMP55]]
-// CHECK1-NEXT: [[MUL64:%.*]] = mul i32 1, [[DIV63]]
-// CHECK1-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB65:%.*]] = sub i32 [[TMP56]], -31
-// CHECK1-NEXT: [[DIV66:%.*]] = udiv i32 [[SUB65]], 32
-// CHECK1-NEXT: [[MUL67:%.*]] = mul i32 [[MUL64]], [[DIV66]]
-// CHECK1-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB68:%.*]] = sub i32 [[TMP57]], [[TMP58]]
-// CHECK1-NEXT: [[SUB69:%.*]] = sub i32 [[SUB68]], 1
-// CHECK1-NEXT: [[ADD70:%.*]] = add i32 [[SUB69]], 1
-// CHECK1-NEXT: [[DIV71:%.*]] = udiv i32 [[ADD70]], 1
-// CHECK1-NEXT: [[MUL72:%.*]] = mul i32 [[MUL67]], [[DIV71]]
-// CHECK1-NEXT: [[CONV73:%.*]] = zext i32 [[MUL72]] to i64
-// CHECK1-NEXT: [[DIV74:%.*]] = sdiv i64 [[TMP51]], [[CONV73]]
-// CHECK1-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
-// CHECK1-NEXT: [[CONV75:%.*]] = sext i32 [[TMP59]] to i64
-// CHECK1-NEXT: [[MUL76:%.*]] = mul nsw i64 [[DIV74]], [[CONV75]]
-// CHECK1-NEXT: [[ADD77:%.*]] = add nsw i64 [[CONV59]], [[MUL76]]
-// CHECK1-NEXT: [[CONV78:%.*]] = trunc i64 [[ADD77]] to i32
-// CHECK1-NEXT: store i32 [[CONV78]], ptr [[I49]], align 4
+// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[CONV45:%.*]] = sext i32 [[TMP43]] to i64
+// CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB46:%.*]] = sub i32 [[TMP45]], [[TMP46]]
+// CHECK1-NEXT: [[SUB47:%.*]] = sub i32 [[SUB46]], 1
+// CHECK1-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD48:%.*]] = add i32 [[SUB47]], [[TMP47]]
+// CHECK1-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV49:%.*]] = udiv i32 [[ADD48]], [[TMP48]]
+// CHECK1-NEXT: [[MUL50:%.*]] = mul i32 1, [[DIV49]]
+// CHECK1-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB51:%.*]] = sub i32 [[TMP49]], -31
+// CHECK1-NEXT: [[DIV52:%.*]] = udiv i32 [[SUB51]], 32
+// CHECK1-NEXT: [[MUL53:%.*]] = mul i32 [[MUL50]], [[DIV52]]
+// CHECK1-NEXT: [[MUL54:%.*]] = mul i32 [[MUL53]], 32
+// CHECK1-NEXT: [[CONV55:%.*]] = zext i32 [[MUL54]] to i64
+// CHECK1-NEXT: [[DIV56:%.*]] = sdiv i64 [[TMP44]], [[CONV55]]
+// CHECK1-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK1-NEXT: [[CONV57:%.*]] = sext i32 [[TMP50]] to i64
+// CHECK1-NEXT: [[MUL58:%.*]] = mul nsw i64 [[DIV56]], [[CONV57]]
+// CHECK1-NEXT: [[ADD59:%.*]] = add nsw i64 [[CONV45]], [[MUL58]]
+// CHECK1-NEXT: [[CONV60:%.*]] = trunc i64 [[ADD59]] to i32
+// CHECK1-NEXT: store i32 [[CONV60]], ptr [[I39]], align 4
+// CHECK1-NEXT: [[TMP51:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[CONV61:%.*]] = sext i32 [[TMP51]] to i64
+// CHECK1-NEXT: [[TMP52:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP53:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB62:%.*]] = sub i32 [[TMP54]], [[TMP55]]
+// CHECK1-NEXT: [[SUB63:%.*]] = sub i32 [[SUB62]], 1
+// CHECK1-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD64:%.*]] = add i32 [[SUB63]], [[TMP56]]
+// CHECK1-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV65:%.*]] = udiv i32 [[ADD64]], [[TMP57]]
+// CHECK1-NEXT: [[MUL66:%.*]] = mul i32 1, [[DIV65]]
+// CHECK1-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB67:%.*]] = sub i32 [[TMP58]], -31
+// CHECK1-NEXT: [[DIV68:%.*]] = udiv i32 [[SUB67]], 32
+// CHECK1-NEXT: [[MUL69:%.*]] = mul i32 [[MUL66]], [[DIV68]]
+// CHECK1-NEXT: [[MUL70:%.*]] = mul i32 [[MUL69]], 32
+// CHECK1-NEXT: [[CONV71:%.*]] = zext i32 [[MUL70]] to i64
+// CHECK1-NEXT: [[DIV72:%.*]] = sdiv i64 [[TMP53]], [[CONV71]]
+// CHECK1-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
// CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[CONV79:%.*]] = sext i32 [[TMP60]] to i64
-// CHECK1-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB80:%.*]] = sub i32 [[TMP63]], [[TMP64]]
-// CHECK1-NEXT: [[SUB81:%.*]] = sub i32 [[SUB80]], 1
-// CHECK1-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD82:%.*]] = add i32 [[SUB81]], [[TMP65]]
-// CHECK1-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV83:%.*]] = udiv i32 [[ADD82]], [[TMP66]]
-// CHECK1-NEXT: [[MUL84:%.*]] = mul i32 1, [[DIV83]]
-// CHECK1-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB85:%.*]] = sub i32 [[TMP67]], -31
+// CHECK1-NEXT: [[SUB73:%.*]] = sub i32 [[TMP59]], [[TMP60]]
+// CHECK1-NEXT: [[SUB74:%.*]] = sub i32 [[SUB73]], 1
+// CHECK1-NEXT: [[TMP61:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD75:%.*]] = add i32 [[SUB74]], [[TMP61]]
+// CHECK1-NEXT: [[TMP62:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV76:%.*]] = udiv i32 [[ADD75]], [[TMP62]]
+// CHECK1-NEXT: [[MUL77:%.*]] = mul i32 1, [[DIV76]]
+// CHECK1-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB78:%.*]] = sub i32 [[TMP63]], -31
+// CHECK1-NEXT: [[DIV79:%.*]] = udiv i32 [[SUB78]], 32
+// CHECK1-NEXT: [[MUL80:%.*]] = mul i32 [[MUL77]], [[DIV79]]
+// CHECK1-NEXT: [[MUL81:%.*]] = mul i32 [[MUL80]], 32
+// CHECK1-NEXT: [[CONV82:%.*]] = zext i32 [[MUL81]] to i64
+// CHECK1-NEXT: [[MUL83:%.*]] = mul nsw i64 [[DIV72]], [[CONV82]]
+// CHECK1-NEXT: [[SUB84:%.*]] = sub nsw i64 [[TMP52]], [[MUL83]]
+// CHECK1-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB85:%.*]] = sub i32 [[TMP64]], -31
// CHECK1-NEXT: [[DIV86:%.*]] = udiv i32 [[SUB85]], 32
-// CHECK1-NEXT: [[MUL87:%.*]] = mul i32 [[MUL84]], [[DIV86]]
-// CHECK1-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB88:%.*]] = sub i32 [[TMP68]], [[TMP69]]
-// CHECK1-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 1
-// CHECK1-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 1
-// CHECK1-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 1
-// CHECK1-NEXT: [[MUL92:%.*]] = mul i32 [[MUL87]], [[DIV91]]
-// CHECK1-NEXT: [[CONV93:%.*]] = zext i32 [[MUL92]] to i64
-// CHECK1-NEXT: [[DIV94:%.*]] = sdiv i64 [[TMP62]], [[CONV93]]
-// CHECK1-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB95:%.*]] = sub i32 [[TMP70]], [[TMP71]]
+// CHECK1-NEXT: [[MUL87:%.*]] = mul i32 1, [[DIV86]]
+// CHECK1-NEXT: [[MUL88:%.*]] = mul i32 [[MUL87]], 32
+// CHECK1-NEXT: [[CONV89:%.*]] = zext i32 [[MUL88]] to i64
+// CHECK1-NEXT: [[DIV90:%.*]] = sdiv i64 [[SUB84]], [[CONV89]]
+// CHECK1-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[CONV91:%.*]] = sext i32 [[TMP65]] to i64
+// CHECK1-NEXT: [[MUL92:%.*]] = mul nsw i64 [[DIV90]], [[CONV91]]
+// CHECK1-NEXT: [[ADD93:%.*]] = add nsw i64 [[CONV61]], [[MUL92]]
+// CHECK1-NEXT: [[CONV94:%.*]] = trunc i64 [[ADD93]] to i32
+// CHECK1-NEXT: store i32 [[CONV94]], ptr [[J40]], align 4
+// CHECK1-NEXT: [[TMP66:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP67:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB95:%.*]] = sub i32 [[TMP68]], [[TMP69]]
// CHECK1-NEXT: [[SUB96:%.*]] = sub i32 [[SUB95]], 1
-// CHECK1-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP72]]
-// CHECK1-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP73]]
+// CHECK1-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP70]]
+// CHECK1-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP71]]
// CHECK1-NEXT: [[MUL99:%.*]] = mul i32 1, [[DIV98]]
-// CHECK1-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB100:%.*]] = sub i32 [[TMP74]], -31
+// CHECK1-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB100:%.*]] = sub i32 [[TMP72]], -31
// CHECK1-NEXT: [[DIV101:%.*]] = udiv i32 [[SUB100]], 32
// CHECK1-NEXT: [[MUL102:%.*]] = mul i32 [[MUL99]], [[DIV101]]
-// CHECK1-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB103:%.*]] = sub i32 [[TMP75]], [[TMP76]]
-// CHECK1-NEXT: [[SUB104:%.*]] = sub i32 [[SUB103]], 1
-// CHECK1-NEXT: [[ADD105:%.*]] = add i32 [[SUB104]], 1
-// CHECK1-NEXT: [[DIV106:%.*]] = udiv i32 [[ADD105]], 1
-// CHECK1-NEXT: [[MUL107:%.*]] = mul i32 [[MUL102]], [[DIV106]]
-// CHECK1-NEXT: [[CONV108:%.*]] = zext i32 [[MUL107]] to i64
-// CHECK1-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV94]], [[CONV108]]
-// CHECK1-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP61]], [[MUL109]]
+// CHECK1-NEXT: [[MUL103:%.*]] = mul i32 [[MUL102]], 32
+// CHECK1-NEXT: [[CONV104:%.*]] = zext i32 [[MUL103]] to i64
+// CHECK1-NEXT: [[DIV105:%.*]] = sdiv i64 [[TMP67]], [[CONV104]]
+// CHECK1-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB106:%.*]] = sub i32 [[TMP73]], [[TMP74]]
+// CHECK1-NEXT: [[SUB107:%.*]] = sub i32 [[SUB106]], 1
+// CHECK1-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD108:%.*]] = add i32 [[SUB107]], [[TMP75]]
+// CHECK1-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV109:%.*]] = udiv i32 [[ADD108]], [[TMP76]]
+// CHECK1-NEXT: [[MUL110:%.*]] = mul i32 1, [[DIV109]]
// CHECK1-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
// CHECK1-NEXT: [[SUB111:%.*]] = sub i32 [[TMP77]], -31
// CHECK1-NEXT: [[DIV112:%.*]] = udiv i32 [[SUB111]], 32
-// CHECK1-NEXT: [[MUL113:%.*]] = mul i32 1, [[DIV112]]
-// CHECK1-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB114:%.*]] = sub i32 [[TMP78]], [[TMP79]]
-// CHECK1-NEXT: [[SUB115:%.*]] = sub i32 [[SUB114]], 1
-// CHECK1-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], 1
-// CHECK1-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], 1
-// CHECK1-NEXT: [[MUL118:%.*]] = mul i32 [[MUL113]], [[DIV117]]
-// CHECK1-NEXT: [[CONV119:%.*]] = zext i32 [[MUL118]] to i64
-// CHECK1-NEXT: [[DIV120:%.*]] = sdiv i64 [[SUB110]], [[CONV119]]
-// CHECK1-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[CONV121:%.*]] = sext i32 [[TMP80]] to i64
-// CHECK1-NEXT: [[MUL122:%.*]] = mul nsw i64 [[DIV120]], [[CONV121]]
-// CHECK1-NEXT: [[ADD123:%.*]] = add nsw i64 [[CONV79]], [[MUL122]]
-// CHECK1-NEXT: [[CONV124:%.*]] = trunc i64 [[ADD123]] to i32
-// CHECK1-NEXT: store i32 [[CONV124]], ptr [[J50]], align 4
-// CHECK1-NEXT: [[TMP81:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP82:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB125:%.*]] = sub i32 [[TMP83]], [[TMP84]]
-// CHECK1-NEXT: [[SUB126:%.*]] = sub i32 [[SUB125]], 1
-// CHECK1-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP85]]
-// CHECK1-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP86]]
-// CHECK1-NEXT: [[MUL129:%.*]] = mul i32 1, [[DIV128]]
-// CHECK1-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB130:%.*]] = sub i32 [[TMP87]], -31
-// CHECK1-NEXT: [[DIV131:%.*]] = udiv i32 [[SUB130]], 32
-// CHECK1-NEXT: [[MUL132:%.*]] = mul i32 [[MUL129]], [[DIV131]]
-// CHECK1-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB133:%.*]] = sub i32 [[TMP88]], [[TMP89]]
-// CHECK1-NEXT: [[SUB134:%.*]] = sub i32 [[SUB133]], 1
-// CHECK1-NEXT: [[ADD135:%.*]] = add i32 [[SUB134]], 1
-// CHECK1-NEXT: [[DIV136:%.*]] = udiv i32 [[ADD135]], 1
-// CHECK1-NEXT: [[MUL137:%.*]] = mul i32 [[MUL132]], [[DIV136]]
+// CHECK1-NEXT: [[MUL113:%.*]] = mul i32 [[MUL110]], [[DIV112]]
+// CHECK1-NEXT: [[MUL114:%.*]] = mul i32 [[MUL113]], 32
+// CHECK1-NEXT: [[CONV115:%.*]] = zext i32 [[MUL114]] to i64
+// CHECK1-NEXT: [[MUL116:%.*]] = mul nsw i64 [[DIV105]], [[CONV115]]
+// CHECK1-NEXT: [[SUB117:%.*]] = sub nsw i64 [[TMP66]], [[MUL116]]
+// CHECK1-NEXT: [[TMP78:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP79:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP81:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB118:%.*]] = sub i32 [[TMP80]], [[TMP81]]
+// CHECK1-NEXT: [[SUB119:%.*]] = sub i32 [[SUB118]], 1
+// CHECK1-NEXT: [[TMP82:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD120:%.*]] = add i32 [[SUB119]], [[TMP82]]
+// CHECK1-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV121:%.*]] = udiv i32 [[ADD120]], [[TMP83]]
+// CHECK1-NEXT: [[MUL122:%.*]] = mul i32 1, [[DIV121]]
+// CHECK1-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB123:%.*]] = sub i32 [[TMP84]], -31
+// CHECK1-NEXT: [[DIV124:%.*]] = udiv i32 [[SUB123]], 32
+// CHECK1-NEXT: [[MUL125:%.*]] = mul i32 [[MUL122]], [[DIV124]]
+// CHECK1-NEXT: [[MUL126:%.*]] = mul i32 [[MUL125]], 32
+// CHECK1-NEXT: [[CONV127:%.*]] = zext i32 [[MUL126]] to i64
+// CHECK1-NEXT: [[DIV128:%.*]] = sdiv i64 [[TMP79]], [[CONV127]]
+// CHECK1-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB129:%.*]] = sub i32 [[TMP85]], [[TMP86]]
+// CHECK1-NEXT: [[SUB130:%.*]] = sub i32 [[SUB129]], 1
+// CHECK1-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD131:%.*]] = add i32 [[SUB130]], [[TMP87]]
+// CHECK1-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV132:%.*]] = udiv i32 [[ADD131]], [[TMP88]]
+// CHECK1-NEXT: [[MUL133:%.*]] = mul i32 1, [[DIV132]]
+// CHECK1-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB134:%.*]] = sub i32 [[TMP89]], -31
+// CHECK1-NEXT: [[DIV135:%.*]] = udiv i32 [[SUB134]], 32
+// CHECK1-NEXT: [[MUL136:%.*]] = mul i32 [[MUL133]], [[DIV135]]
+// CHECK1-NEXT: [[MUL137:%.*]] = mul i32 [[MUL136]], 32
// CHECK1-NEXT: [[CONV138:%.*]] = zext i32 [[MUL137]] to i64
-// CHECK1-NEXT: [[DIV139:%.*]] = sdiv i64 [[TMP82]], [[CONV138]]
-// CHECK1-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB140:%.*]] = sub i32 [[TMP90]], [[TMP91]]
-// CHECK1-NEXT: [[SUB141:%.*]] = sub i32 [[SUB140]], 1
-// CHECK1-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD142:%.*]] = add i32 [[SUB141]], [[TMP92]]
-// CHECK1-NEXT: [[TMP93:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV143:%.*]] = udiv i32 [[ADD142]], [[TMP93]]
-// CHECK1-NEXT: [[MUL144:%.*]] = mul i32 1, [[DIV143]]
-// CHECK1-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB145:%.*]] = sub i32 [[TMP94]], -31
-// CHECK1-NEXT: [[DIV146:%.*]] = udiv i32 [[SUB145]], 32
-// CHECK1-NEXT: [[MUL147:%.*]] = mul i32 [[MUL144]], [[DIV146]]
-// CHECK1-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB148:%.*]] = sub i32 [[TMP95]], [[TMP96]]
-// CHECK1-NEXT: [[SUB149:%.*]] = sub i32 [[SUB148]], 1
-// CHECK1-NEXT: [[ADD150:%.*]] = add i32 [[SUB149]], 1
-// CHECK1-NEXT: [[DIV151:%.*]] = udiv i32 [[ADD150]], 1
-// CHECK1-NEXT: [[MUL152:%.*]] = mul i32 [[MUL147]], [[DIV151]]
-// CHECK1-NEXT: [[CONV153:%.*]] = zext i32 [[MUL152]] to i64
-// CHECK1-NEXT: [[MUL154:%.*]] = mul nsw i64 [[DIV139]], [[CONV153]]
-// CHECK1-NEXT: [[SUB155:%.*]] = sub nsw i64 [[TMP81]], [[MUL154]]
-// CHECK1-NEXT: [[TMP97:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP98:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB156:%.*]] = sub i32 [[TMP99]], [[TMP100]]
-// CHECK1-NEXT: [[SUB157:%.*]] = sub i32 [[SUB156]], 1
-// CHECK1-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD158:%.*]] = add i32 [[SUB157]], [[TMP101]]
+// CHECK1-NEXT: [[MUL139:%.*]] = mul nsw i64 [[DIV128]], [[CONV138]]
+// CHECK1-NEXT: [[SUB140:%.*]] = sub nsw i64 [[TMP78]], [[MUL139]]
+// CHECK1-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB141:%.*]] = sub i32 [[TMP90]], -31
+// CHECK1-NEXT: [[DIV142:%.*]] = udiv i32 [[SUB141]], 32
+// CHECK1-NEXT: [[MUL143:%.*]] = mul i32 1, [[DIV142]]
+// CHECK1-NEXT: [[MUL144:%.*]] = mul i32 [[MUL143]], 32
+// CHECK1-NEXT: [[CONV145:%.*]] = zext i32 [[MUL144]] to i64
+// CHECK1-NEXT: [[DIV146:%.*]] = sdiv i64 [[SUB140]], [[CONV145]]
+// CHECK1-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB147:%.*]] = sub i32 [[TMP91]], -31
+// CHECK1-NEXT: [[DIV148:%.*]] = udiv i32 [[SUB147]], 32
+// CHECK1-NEXT: [[MUL149:%.*]] = mul i32 1, [[DIV148]]
+// CHECK1-NEXT: [[MUL150:%.*]] = mul i32 [[MUL149]], 32
+// CHECK1-NEXT: [[CONV151:%.*]] = zext i32 [[MUL150]] to i64
+// CHECK1-NEXT: [[MUL152:%.*]] = mul nsw i64 [[DIV146]], [[CONV151]]
+// CHECK1-NEXT: [[SUB153:%.*]] = sub nsw i64 [[SUB117]], [[MUL152]]
+// CHECK1-NEXT: [[DIV154:%.*]] = sdiv i64 [[SUB153]], 32
+// CHECK1-NEXT: [[MUL155:%.*]] = mul nsw i64 [[DIV154]], 32
+// CHECK1-NEXT: [[ADD156:%.*]] = add nsw i64 0, [[MUL155]]
+// CHECK1-NEXT: [[CONV157:%.*]] = trunc i64 [[ADD156]] to i32
+// CHECK1-NEXT: store i32 [[CONV157]], ptr [[DOTFLOOR_0_IV_K41]], align 4
+// CHECK1-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_K41]], align 4
+// CHECK1-NEXT: [[CONV158:%.*]] = zext i32 [[TMP92]] to i64
+// CHECK1-NEXT: [[TMP93:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP94:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB159:%.*]] = sub i32 [[TMP95]], [[TMP96]]
+// CHECK1-NEXT: [[SUB160:%.*]] = sub i32 [[SUB159]], 1
+// CHECK1-NEXT: [[TMP97:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD161:%.*]] = add i32 [[SUB160]], [[TMP97]]
+// CHECK1-NEXT: [[TMP98:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV162:%.*]] = udiv i32 [[ADD161]], [[TMP98]]
+// CHECK1-NEXT: [[MUL163:%.*]] = mul i32 1, [[DIV162]]
+// CHECK1-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB164:%.*]] = sub i32 [[TMP99]], -31
+// CHECK1-NEXT: [[DIV165:%.*]] = udiv i32 [[SUB164]], 32
+// CHECK1-NEXT: [[MUL166:%.*]] = mul i32 [[MUL163]], [[DIV165]]
+// CHECK1-NEXT: [[MUL167:%.*]] = mul i32 [[MUL166]], 32
+// CHECK1-NEXT: [[CONV168:%.*]] = zext i32 [[MUL167]] to i64
+// CHECK1-NEXT: [[DIV169:%.*]] = sdiv i64 [[TMP94]], [[CONV168]]
+// CHECK1-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB170:%.*]] = sub i32 [[TMP100]], [[TMP101]]
+// CHECK1-NEXT: [[SUB171:%.*]] = sub i32 [[SUB170]], 1
// CHECK1-NEXT: [[TMP102:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV159:%.*]] = udiv i32 [[ADD158]], [[TMP102]]
-// CHECK1-NEXT: [[MUL160:%.*]] = mul i32 1, [[DIV159]]
-// CHECK1-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB161:%.*]] = sub i32 [[TMP103]], -31
-// CHECK1-NEXT: [[DIV162:%.*]] = udiv i32 [[SUB161]], 32
-// CHECK1-NEXT: [[MUL163:%.*]] = mul i32 [[MUL160]], [[DIV162]]
-// CHECK1-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB164:%.*]] = sub i32 [[TMP104]], [[TMP105]]
-// CHECK1-NEXT: [[SUB165:%.*]] = sub i32 [[SUB164]], 1
-// CHECK1-NEXT: [[ADD166:%.*]] = add i32 [[SUB165]], 1
-// CHECK1-NEXT: [[DIV167:%.*]] = udiv i32 [[ADD166]], 1
-// CHECK1-NEXT: [[MUL168:%.*]] = mul i32 [[MUL163]], [[DIV167]]
-// CHECK1-NEXT: [[CONV169:%.*]] = zext i32 [[MUL168]] to i64
-// CHECK1-NEXT: [[DIV170:%.*]] = sdiv i64 [[TMP98]], [[CONV169]]
-// CHECK1-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB171:%.*]] = sub i32 [[TMP106]], [[TMP107]]
-// CHECK1-NEXT: [[SUB172:%.*]] = sub i32 [[SUB171]], 1
-// CHECK1-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD173:%.*]] = add i32 [[SUB172]], [[TMP108]]
+// CHECK1-NEXT: [[ADD172:%.*]] = add i32 [[SUB171]], [[TMP102]]
+// CHECK1-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV173:%.*]] = udiv i32 [[ADD172]], [[TMP103]]
+// CHECK1-NEXT: [[MUL174:%.*]] = mul i32 1, [[DIV173]]
+// CHECK1-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB175:%.*]] = sub i32 [[TMP104]], -31
+// CHECK1-NEXT: [[DIV176:%.*]] = udiv i32 [[SUB175]], 32
+// CHECK1-NEXT: [[MUL177:%.*]] = mul i32 [[MUL174]], [[DIV176]]
+// CHECK1-NEXT: [[MUL178:%.*]] = mul i32 [[MUL177]], 32
+// CHECK1-NEXT: [[CONV179:%.*]] = zext i32 [[MUL178]] to i64
+// CHECK1-NEXT: [[MUL180:%.*]] = mul nsw i64 [[DIV169]], [[CONV179]]
+// CHECK1-NEXT: [[SUB181:%.*]] = sub nsw i64 [[TMP93]], [[MUL180]]
+// CHECK1-NEXT: [[TMP105:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP106:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB182:%.*]] = sub i32 [[TMP107]], [[TMP108]]
+// CHECK1-NEXT: [[SUB183:%.*]] = sub i32 [[SUB182]], 1
// CHECK1-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV174:%.*]] = udiv i32 [[ADD173]], [[TMP109]]
-// CHECK1-NEXT: [[MUL175:%.*]] = mul i32 1, [[DIV174]]
-// CHECK1-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB176:%.*]] = sub i32 [[TMP110]], -31
-// CHECK1-NEXT: [[DIV177:%.*]] = udiv i32 [[SUB176]], 32
-// CHECK1-NEXT: [[MUL178:%.*]] = mul i32 [[MUL175]], [[DIV177]]
-// CHECK1-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB179:%.*]] = sub i32 [[TMP111]], [[TMP112]]
-// CHECK1-NEXT: [[SUB180:%.*]] = sub i32 [[SUB179]], 1
-// CHECK1-NEXT: [[ADD181:%.*]] = add i32 [[SUB180]], 1
-// CHECK1-NEXT: [[DIV182:%.*]] = udiv i32 [[ADD181]], 1
-// CHECK1-NEXT: [[MUL183:%.*]] = mul i32 [[MUL178]], [[DIV182]]
-// CHECK1-NEXT: [[CONV184:%.*]] = zext i32 [[MUL183]] to i64
-// CHECK1-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV170]], [[CONV184]]
-// CHECK1-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP97]], [[MUL185]]
-// CHECK1-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB187:%.*]] = sub i32 [[TMP113]], -31
+// CHECK1-NEXT: [[ADD184:%.*]] = add i32 [[SUB183]], [[TMP109]]
+// CHECK1-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV185:%.*]] = udiv i32 [[ADD184]], [[TMP110]]
+// CHECK1-NEXT: [[MUL186:%.*]] = mul i32 1, [[DIV185]]
+// CHECK1-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB187:%.*]] = sub i32 [[TMP111]], -31
// CHECK1-NEXT: [[DIV188:%.*]] = udiv i32 [[SUB187]], 32
-// CHECK1-NEXT: [[MUL189:%.*]] = mul i32 1, [[DIV188]]
-// CHECK1-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB190:%.*]] = sub i32 [[TMP114]], [[TMP115]]
-// CHECK1-NEXT: [[SUB191:%.*]] = sub i32 [[SUB190]], 1
-// CHECK1-NEXT: [[ADD192:%.*]] = add i32 [[SUB191]], 1
-// CHECK1-NEXT: [[DIV193:%.*]] = udiv i32 [[ADD192]], 1
-// CHECK1-NEXT: [[MUL194:%.*]] = mul i32 [[MUL189]], [[DIV193]]
-// CHECK1-NEXT: [[CONV195:%.*]] = zext i32 [[MUL194]] to i64
-// CHECK1-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB186]], [[CONV195]]
+// CHECK1-NEXT: [[MUL189:%.*]] = mul i32 [[MUL186]], [[DIV188]]
+// CHECK1-NEXT: [[MUL190:%.*]] = mul i32 [[MUL189]], 32
+// CHECK1-NEXT: [[CONV191:%.*]] = zext i32 [[MUL190]] to i64
+// CHECK1-NEXT: [[DIV192:%.*]] = sdiv i64 [[TMP106]], [[CONV191]]
+// CHECK1-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB193:%.*]] = sub i32 [[TMP112]], [[TMP113]]
+// CHECK1-NEXT: [[SUB194:%.*]] = sub i32 [[SUB193]], 1
+// CHECK1-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD195:%.*]] = add i32 [[SUB194]], [[TMP114]]
+// CHECK1-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV196:%.*]] = udiv i32 [[ADD195]], [[TMP115]]
+// CHECK1-NEXT: [[MUL197:%.*]] = mul i32 1, [[DIV196]]
// CHECK1-NEXT: [[TMP116:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB197:%.*]] = sub i32 [[TMP116]], -31
-// CHECK1-NEXT: [[DIV198:%.*]] = udiv i32 [[SUB197]], 32
-// CHECK1-NEXT: [[MUL199:%.*]] = mul i32 1, [[DIV198]]
-// CHECK1-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB200:%.*]] = sub i32 [[TMP117]], [[TMP118]]
-// CHECK1-NEXT: [[SUB201:%.*]] = sub i32 [[SUB200]], 1
-// CHECK1-NEXT: [[ADD202:%.*]] = add i32 [[SUB201]], 1
-// CHECK1-NEXT: [[DIV203:%.*]] = udiv i32 [[ADD202]], 1
-// CHECK1-NEXT: [[MUL204:%.*]] = mul i32 [[MUL199]], [[DIV203]]
-// CHECK1-NEXT: [[CONV205:%.*]] = zext i32 [[MUL204]] to i64
-// CHECK1-NEXT: [[MUL206:%.*]] = mul nsw i64 [[DIV196]], [[CONV205]]
-// CHECK1-NEXT: [[SUB207:%.*]] = sub nsw i64 [[SUB155]], [[MUL206]]
-// CHECK1-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB208:%.*]] = sub i32 [[TMP119]], [[TMP120]]
-// CHECK1-NEXT: [[SUB209:%.*]] = sub i32 [[SUB208]], 1
-// CHECK1-NEXT: [[ADD210:%.*]] = add i32 [[SUB209]], 1
-// CHECK1-NEXT: [[DIV211:%.*]] = udiv i32 [[ADD210]], 1
-// CHECK1-NEXT: [[MUL212:%.*]] = mul i32 1, [[DIV211]]
-// CHECK1-NEXT: [[CONV213:%.*]] = zext i32 [[MUL212]] to i64
-// CHECK1-NEXT: [[DIV214:%.*]] = sdiv i64 [[SUB207]], [[CONV213]]
-// CHECK1-NEXT: [[MUL215:%.*]] = mul nsw i64 [[DIV214]], 32
-// CHECK1-NEXT: [[ADD216:%.*]] = add nsw i64 0, [[MUL215]]
-// CHECK1-NEXT: [[CONV217:%.*]] = trunc i64 [[ADD216]] to i32
-// CHECK1-NEXT: store i32 [[CONV217]], ptr [[DOTFLOOR_0_IV_K51]], align 4
-// CHECK1-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[CONV218:%.*]] = zext i32 [[TMP121]] to i64
-// CHECK1-NEXT: [[TMP122:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP123:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB219:%.*]] = sub i32 [[TMP124]], [[TMP125]]
-// CHECK1-NEXT: [[SUB220:%.*]] = sub i32 [[SUB219]], 1
-// CHECK1-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD221:%.*]] = add i32 [[SUB220]], [[TMP126]]
-// CHECK1-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV222:%.*]] = udiv i32 [[ADD221]], [[TMP127]]
-// CHECK1-NEXT: [[MUL223:%.*]] = mul i32 1, [[DIV222]]
-// CHECK1-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB224:%.*]] = sub i32 [[TMP128]], -31
-// CHECK1-NEXT: [[DIV225:%.*]] = udiv i32 [[SUB224]], 32
-// CHECK1-NEXT: [[MUL226:%.*]] = mul i32 [[MUL223]], [[DIV225]]
-// CHECK1-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB227:%.*]] = sub i32 [[TMP129]], [[TMP130]]
-// CHECK1-NEXT: [[SUB228:%.*]] = sub i32 [[SUB227]], 1
-// CHECK1-NEXT: [[ADD229:%.*]] = add i32 [[SUB228]], 1
-// CHECK1-NEXT: [[DIV230:%.*]] = udiv i32 [[ADD229]], 1
-// CHECK1-NEXT: [[MUL231:%.*]] = mul i32 [[MUL226]], [[DIV230]]
-// CHECK1-NEXT: [[CONV232:%.*]] = zext i32 [[MUL231]] to i64
-// CHECK1-NEXT: [[DIV233:%.*]] = sdiv i64 [[TMP123]], [[CONV232]]
-// CHECK1-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB234:%.*]] = sub i32 [[TMP131]], [[TMP132]]
-// CHECK1-NEXT: [[SUB235:%.*]] = sub i32 [[SUB234]], 1
-// CHECK1-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD236:%.*]] = add i32 [[SUB235]], [[TMP133]]
-// CHECK1-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV237:%.*]] = udiv i32 [[ADD236]], [[TMP134]]
-// CHECK1-NEXT: [[MUL238:%.*]] = mul i32 1, [[DIV237]]
-// CHECK1-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB239:%.*]] = sub i32 [[TMP135]], -31
-// CHECK1-NEXT: [[DIV240:%.*]] = udiv i32 [[SUB239]], 32
-// CHECK1-NEXT: [[MUL241:%.*]] = mul i32 [[MUL238]], [[DIV240]]
-// CHECK1-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB242:%.*]] = sub i32 [[TMP136]], [[TMP137]]
-// CHECK1-NEXT: [[SUB243:%.*]] = sub i32 [[SUB242]], 1
-// CHECK1-NEXT: [[ADD244:%.*]] = add i32 [[SUB243]], 1
-// CHECK1-NEXT: [[DIV245:%.*]] = udiv i32 [[ADD244]], 1
-// CHECK1-NEXT: [[MUL246:%.*]] = mul i32 [[MUL241]], [[DIV245]]
-// CHECK1-NEXT: [[CONV247:%.*]] = zext i32 [[MUL246]] to i64
-// CHECK1-NEXT: [[MUL248:%.*]] = mul nsw i64 [[DIV233]], [[CONV247]]
-// CHECK1-NEXT: [[SUB249:%.*]] = sub nsw i64 [[TMP122]], [[MUL248]]
-// CHECK1-NEXT: [[TMP138:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP139:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB250:%.*]] = sub i32 [[TMP140]], [[TMP141]]
-// CHECK1-NEXT: [[SUB251:%.*]] = sub i32 [[SUB250]], 1
-// CHECK1-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD252:%.*]] = add i32 [[SUB251]], [[TMP142]]
-// CHECK1-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV253:%.*]] = udiv i32 [[ADD252]], [[TMP143]]
-// CHECK1-NEXT: [[MUL254:%.*]] = mul i32 1, [[DIV253]]
+// CHECK1-NEXT: [[SUB198:%.*]] = sub i32 [[TMP116]], -31
+// CHECK1-NEXT: [[DIV199:%.*]] = udiv i32 [[SUB198]], 32
+// CHECK1-NEXT: [[MUL200:%.*]] = mul i32 [[MUL197]], [[DIV199]]
+// CHECK1-NEXT: [[MUL201:%.*]] = mul i32 [[MUL200]], 32
+// CHECK1-NEXT: [[CONV202:%.*]] = zext i32 [[MUL201]] to i64
+// CHECK1-NEXT: [[MUL203:%.*]] = mul nsw i64 [[DIV192]], [[CONV202]]
+// CHECK1-NEXT: [[SUB204:%.*]] = sub nsw i64 [[TMP105]], [[MUL203]]
+// CHECK1-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB205:%.*]] = sub i32 [[TMP117]], -31
+// CHECK1-NEXT: [[DIV206:%.*]] = udiv i32 [[SUB205]], 32
+// CHECK1-NEXT: [[MUL207:%.*]] = mul i32 1, [[DIV206]]
+// CHECK1-NEXT: [[MUL208:%.*]] = mul i32 [[MUL207]], 32
+// CHECK1-NEXT: [[CONV209:%.*]] = zext i32 [[MUL208]] to i64
+// CHECK1-NEXT: [[DIV210:%.*]] = sdiv i64 [[SUB204]], [[CONV209]]
+// CHECK1-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB211:%.*]] = sub i32 [[TMP118]], -31
+// CHECK1-NEXT: [[DIV212:%.*]] = udiv i32 [[SUB211]], 32
+// CHECK1-NEXT: [[MUL213:%.*]] = mul i32 1, [[DIV212]]
+// CHECK1-NEXT: [[MUL214:%.*]] = mul i32 [[MUL213]], 32
+// CHECK1-NEXT: [[CONV215:%.*]] = zext i32 [[MUL214]] to i64
+// CHECK1-NEXT: [[MUL216:%.*]] = mul nsw i64 [[DIV210]], [[CONV215]]
+// CHECK1-NEXT: [[SUB217:%.*]] = sub nsw i64 [[SUB181]], [[MUL216]]
+// CHECK1-NEXT: [[TMP119:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP120:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP122:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB218:%.*]] = sub i32 [[TMP121]], [[TMP122]]
+// CHECK1-NEXT: [[SUB219:%.*]] = sub i32 [[SUB218]], 1
+// CHECK1-NEXT: [[TMP123:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD220:%.*]] = add i32 [[SUB219]], [[TMP123]]
+// CHECK1-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV221:%.*]] = udiv i32 [[ADD220]], [[TMP124]]
+// CHECK1-NEXT: [[MUL222:%.*]] = mul i32 1, [[DIV221]]
+// CHECK1-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB223:%.*]] = sub i32 [[TMP125]], -31
+// CHECK1-NEXT: [[DIV224:%.*]] = udiv i32 [[SUB223]], 32
+// CHECK1-NEXT: [[MUL225:%.*]] = mul i32 [[MUL222]], [[DIV224]]
+// CHECK1-NEXT: [[MUL226:%.*]] = mul i32 [[MUL225]], 32
+// CHECK1-NEXT: [[CONV227:%.*]] = zext i32 [[MUL226]] to i64
+// CHECK1-NEXT: [[DIV228:%.*]] = sdiv i64 [[TMP120]], [[CONV227]]
+// CHECK1-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB229:%.*]] = sub i32 [[TMP126]], [[TMP127]]
+// CHECK1-NEXT: [[SUB230:%.*]] = sub i32 [[SUB229]], 1
+// CHECK1-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD231:%.*]] = add i32 [[SUB230]], [[TMP128]]
+// CHECK1-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV232:%.*]] = udiv i32 [[ADD231]], [[TMP129]]
+// CHECK1-NEXT: [[MUL233:%.*]] = mul i32 1, [[DIV232]]
+// CHECK1-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB234:%.*]] = sub i32 [[TMP130]], -31
+// CHECK1-NEXT: [[DIV235:%.*]] = udiv i32 [[SUB234]], 32
+// CHECK1-NEXT: [[MUL236:%.*]] = mul i32 [[MUL233]], [[DIV235]]
+// CHECK1-NEXT: [[MUL237:%.*]] = mul i32 [[MUL236]], 32
+// CHECK1-NEXT: [[CONV238:%.*]] = zext i32 [[MUL237]] to i64
+// CHECK1-NEXT: [[MUL239:%.*]] = mul nsw i64 [[DIV228]], [[CONV238]]
+// CHECK1-NEXT: [[SUB240:%.*]] = sub nsw i64 [[TMP119]], [[MUL239]]
+// CHECK1-NEXT: [[TMP131:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP132:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB241:%.*]] = sub i32 [[TMP133]], [[TMP134]]
+// CHECK1-NEXT: [[SUB242:%.*]] = sub i32 [[SUB241]], 1
+// CHECK1-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD243:%.*]] = add i32 [[SUB242]], [[TMP135]]
+// CHECK1-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV244:%.*]] = udiv i32 [[ADD243]], [[TMP136]]
+// CHECK1-NEXT: [[MUL245:%.*]] = mul i32 1, [[DIV244]]
+// CHECK1-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB246:%.*]] = sub i32 [[TMP137]], -31
+// CHECK1-NEXT: [[DIV247:%.*]] = udiv i32 [[SUB246]], 32
+// CHECK1-NEXT: [[MUL248:%.*]] = mul i32 [[MUL245]], [[DIV247]]
+// CHECK1-NEXT: [[MUL249:%.*]] = mul i32 [[MUL248]], 32
+// CHECK1-NEXT: [[CONV250:%.*]] = zext i32 [[MUL249]] to i64
+// CHECK1-NEXT: [[DIV251:%.*]] = sdiv i64 [[TMP132]], [[CONV250]]
+// CHECK1-NEXT: [[TMP138:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP139:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB252:%.*]] = sub i32 [[TMP138]], [[TMP139]]
+// CHECK1-NEXT: [[SUB253:%.*]] = sub i32 [[SUB252]], 1
+// CHECK1-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD254:%.*]] = add i32 [[SUB253]], [[TMP140]]
+// CHECK1-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV255:%.*]] = udiv i32 [[ADD254]], [[TMP141]]
+// CHECK1-NEXT: [[MUL256:%.*]] = mul i32 1, [[DIV255]]
+// CHECK1-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB257:%.*]] = sub i32 [[TMP142]], -31
+// CHECK1-NEXT: [[DIV258:%.*]] = udiv i32 [[SUB257]], 32
+// CHECK1-NEXT: [[MUL259:%.*]] = mul i32 [[MUL256]], [[DIV258]]
+// CHECK1-NEXT: [[MUL260:%.*]] = mul i32 [[MUL259]], 32
+// CHECK1-NEXT: [[CONV261:%.*]] = zext i32 [[MUL260]] to i64
+// CHECK1-NEXT: [[MUL262:%.*]] = mul nsw i64 [[DIV251]], [[CONV261]]
+// CHECK1-NEXT: [[SUB263:%.*]] = sub nsw i64 [[TMP131]], [[MUL262]]
+// CHECK1-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB264:%.*]] = sub i32 [[TMP143]], -31
+// CHECK1-NEXT: [[DIV265:%.*]] = udiv i32 [[SUB264]], 32
+// CHECK1-NEXT: [[MUL266:%.*]] = mul i32 1, [[DIV265]]
+// CHECK1-NEXT: [[MUL267:%.*]] = mul i32 [[MUL266]], 32
+// CHECK1-NEXT: [[CONV268:%.*]] = zext i32 [[MUL267]] to i64
+// CHECK1-NEXT: [[DIV269:%.*]] = sdiv i64 [[SUB263]], [[CONV268]]
// CHECK1-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB255:%.*]] = sub i32 [[TMP144]], -31
-// CHECK1-NEXT: [[DIV256:%.*]] = udiv i32 [[SUB255]], 32
-// CHECK1-NEXT: [[MUL257:%.*]] = mul i32 [[MUL254]], [[DIV256]]
-// CHECK1-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB258:%.*]] = sub i32 [[TMP145]], [[TMP146]]
-// CHECK1-NEXT: [[SUB259:%.*]] = sub i32 [[SUB258]], 1
-// CHECK1-NEXT: [[ADD260:%.*]] = add i32 [[SUB259]], 1
-// CHECK1-NEXT: [[DIV261:%.*]] = udiv i32 [[ADD260]], 1
-// CHECK1-NEXT: [[MUL262:%.*]] = mul i32 [[MUL257]], [[DIV261]]
-// CHECK1-NEXT: [[CONV263:%.*]] = zext i32 [[MUL262]] to i64
-// CHECK1-NEXT: [[DIV264:%.*]] = sdiv i64 [[TMP139]], [[CONV263]]
-// CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB265:%.*]] = sub i32 [[TMP147]], [[TMP148]]
-// CHECK1-NEXT: [[SUB266:%.*]] = sub i32 [[SUB265]], 1
-// CHECK1-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD267:%.*]] = add i32 [[SUB266]], [[TMP149]]
-// CHECK1-NEXT: [[TMP150:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV268:%.*]] = udiv i32 [[ADD267]], [[TMP150]]
-// CHECK1-NEXT: [[MUL269:%.*]] = mul i32 1, [[DIV268]]
-// CHECK1-NEXT: [[TMP151:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB270:%.*]] = sub i32 [[TMP151]], -31
+// CHECK1-NEXT: [[SUB270:%.*]] = sub i32 [[TMP144]], -31
// CHECK1-NEXT: [[DIV271:%.*]] = udiv i32 [[SUB270]], 32
-// CHECK1-NEXT: [[MUL272:%.*]] = mul i32 [[MUL269]], [[DIV271]]
-// CHECK1-NEXT: [[TMP152:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP153:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB273:%.*]] = sub i32 [[TMP152]], [[TMP153]]
-// CHECK1-NEXT: [[SUB274:%.*]] = sub i32 [[SUB273]], 1
-// CHECK1-NEXT: [[ADD275:%.*]] = add i32 [[SUB274]], 1
-// CHECK1-NEXT: [[DIV276:%.*]] = udiv i32 [[ADD275]], 1
-// CHECK1-NEXT: [[MUL277:%.*]] = mul i32 [[MUL272]], [[DIV276]]
-// CHECK1-NEXT: [[CONV278:%.*]] = zext i32 [[MUL277]] to i64
-// CHECK1-NEXT: [[MUL279:%.*]] = mul nsw i64 [[DIV264]], [[CONV278]]
-// CHECK1-NEXT: [[SUB280:%.*]] = sub nsw i64 [[TMP138]], [[MUL279]]
-// CHECK1-NEXT: [[TMP154:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB281:%.*]] = sub i32 [[TMP154]], -31
-// CHECK1-NEXT: [[DIV282:%.*]] = udiv i32 [[SUB281]], 32
-// CHECK1-NEXT: [[MUL283:%.*]] = mul i32 1, [[DIV282]]
-// CHECK1-NEXT: [[TMP155:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP156:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB284:%.*]] = sub i32 [[TMP155]], [[TMP156]]
-// CHECK1-NEXT: [[SUB285:%.*]] = sub i32 [[SUB284]], 1
-// CHECK1-NEXT: [[ADD286:%.*]] = add i32 [[SUB285]], 1
-// CHECK1-NEXT: [[DIV287:%.*]] = udiv i32 [[ADD286]], 1
-// CHECK1-NEXT: [[MUL288:%.*]] = mul i32 [[MUL283]], [[DIV287]]
-// CHECK1-NEXT: [[CONV289:%.*]] = zext i32 [[MUL288]] to i64
-// CHECK1-NEXT: [[DIV290:%.*]] = sdiv i64 [[SUB280]], [[CONV289]]
-// CHECK1-NEXT: [[TMP157:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB291:%.*]] = sub i32 [[TMP157]], -31
-// CHECK1-NEXT: [[DIV292:%.*]] = udiv i32 [[SUB291]], 32
-// CHECK1-NEXT: [[MUL293:%.*]] = mul i32 1, [[DIV292]]
-// CHECK1-NEXT: [[TMP158:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP159:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB294:%.*]] = sub i32 [[TMP158]], [[TMP159]]
-// CHECK1-NEXT: [[SUB295:%.*]] = sub i32 [[SUB294]], 1
-// CHECK1-NEXT: [[ADD296:%.*]] = add i32 [[SUB295]], 1
-// CHECK1-NEXT: [[DIV297:%.*]] = udiv i32 [[ADD296]], 1
-// CHECK1-NEXT: [[MUL298:%.*]] = mul i32 [[MUL293]], [[DIV297]]
-// CHECK1-NEXT: [[CONV299:%.*]] = zext i32 [[MUL298]] to i64
-// CHECK1-NEXT: [[MUL300:%.*]] = mul nsw i64 [[DIV290]], [[CONV299]]
-// CHECK1-NEXT: [[SUB301:%.*]] = sub nsw i64 [[SUB249]], [[MUL300]]
-// CHECK1-NEXT: [[TMP160:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP161:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP162:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP163:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB302:%.*]] = sub i32 [[TMP162]], [[TMP163]]
-// CHECK1-NEXT: [[SUB303:%.*]] = sub i32 [[SUB302]], 1
-// CHECK1-NEXT: [[TMP164:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD304:%.*]] = add i32 [[SUB303]], [[TMP164]]
-// CHECK1-NEXT: [[TMP165:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV305:%.*]] = udiv i32 [[ADD304]], [[TMP165]]
-// CHECK1-NEXT: [[MUL306:%.*]] = mul i32 1, [[DIV305]]
-// CHECK1-NEXT: [[TMP166:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB307:%.*]] = sub i32 [[TMP166]], -31
-// CHECK1-NEXT: [[DIV308:%.*]] = udiv i32 [[SUB307]], 32
-// CHECK1-NEXT: [[MUL309:%.*]] = mul i32 [[MUL306]], [[DIV308]]
-// CHECK1-NEXT: [[TMP167:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP168:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB310:%.*]] = sub i32 [[TMP167]], [[TMP168]]
-// CHECK1-NEXT: [[SUB311:%.*]] = sub i32 [[SUB310]], 1
-// CHECK1-NEXT: [[ADD312:%.*]] = add i32 [[SUB311]], 1
-// CHECK1-NEXT: [[DIV313:%.*]] = udiv i32 [[ADD312]], 1
-// CHECK1-NEXT: [[MUL314:%.*]] = mul i32 [[MUL309]], [[DIV313]]
-// CHECK1-NEXT: [[CONV315:%.*]] = zext i32 [[MUL314]] to i64
-// CHECK1-NEXT: [[DIV316:%.*]] = sdiv i64 [[TMP161]], [[CONV315]]
-// CHECK1-NEXT: [[TMP169:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP170:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB317:%.*]] = sub i32 [[TMP169]], [[TMP170]]
-// CHECK1-NEXT: [[SUB318:%.*]] = sub i32 [[SUB317]], 1
-// CHECK1-NEXT: [[TMP171:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD319:%.*]] = add i32 [[SUB318]], [[TMP171]]
-// CHECK1-NEXT: [[TMP172:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV320:%.*]] = udiv i32 [[ADD319]], [[TMP172]]
-// CHECK1-NEXT: [[MUL321:%.*]] = mul i32 1, [[DIV320]]
-// CHECK1-NEXT: [[TMP173:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB322:%.*]] = sub i32 [[TMP173]], -31
-// CHECK1-NEXT: [[DIV323:%.*]] = udiv i32 [[SUB322]], 32
-// CHECK1-NEXT: [[MUL324:%.*]] = mul i32 [[MUL321]], [[DIV323]]
-// CHECK1-NEXT: [[TMP174:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP175:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB325:%.*]] = sub i32 [[TMP174]], [[TMP175]]
-// CHECK1-NEXT: [[SUB326:%.*]] = sub i32 [[SUB325]], 1
-// CHECK1-NEXT: [[ADD327:%.*]] = add i32 [[SUB326]], 1
-// CHECK1-NEXT: [[DIV328:%.*]] = udiv i32 [[ADD327]], 1
-// CHECK1-NEXT: [[MUL329:%.*]] = mul i32 [[MUL324]], [[DIV328]]
-// CHECK1-NEXT: [[CONV330:%.*]] = zext i32 [[MUL329]] to i64
-// CHECK1-NEXT: [[MUL331:%.*]] = mul nsw i64 [[DIV316]], [[CONV330]]
-// CHECK1-NEXT: [[SUB332:%.*]] = sub nsw i64 [[TMP160]], [[MUL331]]
-// CHECK1-NEXT: [[TMP176:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP177:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP178:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP179:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB333:%.*]] = sub i32 [[TMP178]], [[TMP179]]
-// CHECK1-NEXT: [[SUB334:%.*]] = sub i32 [[SUB333]], 1
-// CHECK1-NEXT: [[TMP180:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD335:%.*]] = add i32 [[SUB334]], [[TMP180]]
-// CHECK1-NEXT: [[TMP181:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV336:%.*]] = udiv i32 [[ADD335]], [[TMP181]]
-// CHECK1-NEXT: [[MUL337:%.*]] = mul i32 1, [[DIV336]]
-// CHECK1-NEXT: [[TMP182:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB338:%.*]] = sub i32 [[TMP182]], -31
-// CHECK1-NEXT: [[DIV339:%.*]] = udiv i32 [[SUB338]], 32
-// CHECK1-NEXT: [[MUL340:%.*]] = mul i32 [[MUL337]], [[DIV339]]
-// CHECK1-NEXT: [[TMP183:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP184:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB341:%.*]] = sub i32 [[TMP183]], [[TMP184]]
-// CHECK1-NEXT: [[SUB342:%.*]] = sub i32 [[SUB341]], 1
-// CHECK1-NEXT: [[ADD343:%.*]] = add i32 [[SUB342]], 1
-// CHECK1-NEXT: [[DIV344:%.*]] = udiv i32 [[ADD343]], 1
-// CHECK1-NEXT: [[MUL345:%.*]] = mul i32 [[MUL340]], [[DIV344]]
-// CHECK1-NEXT: [[CONV346:%.*]] = zext i32 [[MUL345]] to i64
-// CHECK1-NEXT: [[DIV347:%.*]] = sdiv i64 [[TMP177]], [[CONV346]]
-// CHECK1-NEXT: [[TMP185:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP186:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB348:%.*]] = sub i32 [[TMP185]], [[TMP186]]
-// CHECK1-NEXT: [[SUB349:%.*]] = sub i32 [[SUB348]], 1
-// CHECK1-NEXT: [[TMP187:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD350:%.*]] = add i32 [[SUB349]], [[TMP187]]
-// CHECK1-NEXT: [[TMP188:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV351:%.*]] = udiv i32 [[ADD350]], [[TMP188]]
-// CHECK1-NEXT: [[MUL352:%.*]] = mul i32 1, [[DIV351]]
-// CHECK1-NEXT: [[TMP189:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB353:%.*]] = sub i32 [[TMP189]], -31
-// CHECK1-NEXT: [[DIV354:%.*]] = udiv i32 [[SUB353]], 32
-// CHECK1-NEXT: [[MUL355:%.*]] = mul i32 [[MUL352]], [[DIV354]]
-// CHECK1-NEXT: [[TMP190:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP191:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB356:%.*]] = sub i32 [[TMP190]], [[TMP191]]
-// CHECK1-NEXT: [[SUB357:%.*]] = sub i32 [[SUB356]], 1
-// CHECK1-NEXT: [[ADD358:%.*]] = add i32 [[SUB357]], 1
-// CHECK1-NEXT: [[DIV359:%.*]] = udiv i32 [[ADD358]], 1
-// CHECK1-NEXT: [[MUL360:%.*]] = mul i32 [[MUL355]], [[DIV359]]
-// CHECK1-NEXT: [[CONV361:%.*]] = zext i32 [[MUL360]] to i64
-// CHECK1-NEXT: [[MUL362:%.*]] = mul nsw i64 [[DIV347]], [[CONV361]]
-// CHECK1-NEXT: [[SUB363:%.*]] = sub nsw i64 [[TMP176]], [[MUL362]]
-// CHECK1-NEXT: [[TMP192:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB364:%.*]] = sub i32 [[TMP192]], -31
-// CHECK1-NEXT: [[DIV365:%.*]] = udiv i32 [[SUB364]], 32
-// CHECK1-NEXT: [[MUL366:%.*]] = mul i32 1, [[DIV365]]
-// CHECK1-NEXT: [[TMP193:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP194:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB367:%.*]] = sub i32 [[TMP193]], [[TMP194]]
-// CHECK1-NEXT: [[SUB368:%.*]] = sub i32 [[SUB367]], 1
-// CHECK1-NEXT: [[ADD369:%.*]] = add i32 [[SUB368]], 1
-// CHECK1-NEXT: [[DIV370:%.*]] = udiv i32 [[ADD369]], 1
-// CHECK1-NEXT: [[MUL371:%.*]] = mul i32 [[MUL366]], [[DIV370]]
-// CHECK1-NEXT: [[CONV372:%.*]] = zext i32 [[MUL371]] to i64
-// CHECK1-NEXT: [[DIV373:%.*]] = sdiv i64 [[SUB363]], [[CONV372]]
-// CHECK1-NEXT: [[TMP195:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB374:%.*]] = sub i32 [[TMP195]], -31
-// CHECK1-NEXT: [[DIV375:%.*]] = udiv i32 [[SUB374]], 32
-// CHECK1-NEXT: [[MUL376:%.*]] = mul i32 1, [[DIV375]]
-// CHECK1-NEXT: [[TMP196:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP197:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB377:%.*]] = sub i32 [[TMP196]], [[TMP197]]
-// CHECK1-NEXT: [[SUB378:%.*]] = sub i32 [[SUB377]], 1
-// CHECK1-NEXT: [[ADD379:%.*]] = add i32 [[SUB378]], 1
-// CHECK1-NEXT: [[DIV380:%.*]] = udiv i32 [[ADD379]], 1
-// CHECK1-NEXT: [[MUL381:%.*]] = mul i32 [[MUL376]], [[DIV380]]
-// CHECK1-NEXT: [[CONV382:%.*]] = zext i32 [[MUL381]] to i64
-// CHECK1-NEXT: [[MUL383:%.*]] = mul nsw i64 [[DIV373]], [[CONV382]]
-// CHECK1-NEXT: [[SUB384:%.*]] = sub nsw i64 [[SUB332]], [[MUL383]]
-// CHECK1-NEXT: [[TMP198:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP199:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB385:%.*]] = sub i32 [[TMP198]], [[TMP199]]
-// CHECK1-NEXT: [[SUB386:%.*]] = sub i32 [[SUB385]], 1
-// CHECK1-NEXT: [[ADD387:%.*]] = add i32 [[SUB386]], 1
-// CHECK1-NEXT: [[DIV388:%.*]] = udiv i32 [[ADD387]], 1
-// CHECK1-NEXT: [[MUL389:%.*]] = mul i32 1, [[DIV388]]
-// CHECK1-NEXT: [[CONV390:%.*]] = zext i32 [[MUL389]] to i64
-// CHECK1-NEXT: [[DIV391:%.*]] = sdiv i64 [[SUB384]], [[CONV390]]
-// CHECK1-NEXT: [[TMP200:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP201:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB392:%.*]] = sub i32 [[TMP200]], [[TMP201]]
-// CHECK1-NEXT: [[SUB393:%.*]] = sub i32 [[SUB392]], 1
-// CHECK1-NEXT: [[ADD394:%.*]] = add i32 [[SUB393]], 1
-// CHECK1-NEXT: [[DIV395:%.*]] = udiv i32 [[ADD394]], 1
-// CHECK1-NEXT: [[MUL396:%.*]] = mul i32 1, [[DIV395]]
-// CHECK1-NEXT: [[CONV397:%.*]] = zext i32 [[MUL396]] to i64
-// CHECK1-NEXT: [[MUL398:%.*]] = mul nsw i64 [[DIV391]], [[CONV397]]
-// CHECK1-NEXT: [[SUB399:%.*]] = sub nsw i64 [[SUB301]], [[MUL398]]
-// CHECK1-NEXT: [[MUL400:%.*]] = mul nsw i64 [[SUB399]], 1
-// CHECK1-NEXT: [[ADD401:%.*]] = add nsw i64 [[CONV218]], [[MUL400]]
-// CHECK1-NEXT: [[CONV402:%.*]] = trunc i64 [[ADD401]] to i32
-// CHECK1-NEXT: store i32 [[CONV402]], ptr [[DOTTILE_0_IV_K52]], align 4
-// CHECK1-NEXT: [[TMP202:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4
-// CHECK1-NEXT: [[TMP203:%.*]] = load i32, ptr [[DOTTILE_0_IV_K52]], align 4
-// CHECK1-NEXT: [[TMP204:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4
-// CHECK1-NEXT: [[MUL403:%.*]] = mul i32 [[TMP203]], [[TMP204]]
-// CHECK1-NEXT: [[ADD404:%.*]] = add i32 [[TMP202]], [[MUL403]]
-// CHECK1-NEXT: store i32 [[ADD404]], ptr [[K]], align 4
-// CHECK1-NEXT: [[TMP205:%.*]] = load i32, ptr [[I49]], align 4
-// CHECK1-NEXT: [[TMP206:%.*]] = load i32, ptr [[J50]], align 4
-// CHECK1-NEXT: [[TMP207:%.*]] = load i32, ptr [[K]], align 4
-// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP205]], i32 noundef [[TMP206]], i32 noundef [[TMP207]])
-// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK1-NEXT: [[MUL272:%.*]] = mul i32 1, [[DIV271]]
+// CHECK1-NEXT: [[MUL273:%.*]] = mul i32 [[MUL272]], 32
+// CHECK1-NEXT: [[CONV274:%.*]] = zext i32 [[MUL273]] to i64
+// CHECK1-NEXT: [[MUL275:%.*]] = mul nsw i64 [[DIV269]], [[CONV274]]
+// CHECK1-NEXT: [[SUB276:%.*]] = sub nsw i64 [[SUB240]], [[MUL275]]
+// CHECK1-NEXT: [[DIV277:%.*]] = sdiv i64 [[SUB276]], 32
+// CHECK1-NEXT: [[MUL278:%.*]] = mul nsw i64 [[DIV277]], 32
+// CHECK1-NEXT: [[SUB279:%.*]] = sub nsw i64 [[SUB217]], [[MUL278]]
+// CHECK1-NEXT: [[MUL280:%.*]] = mul nsw i64 [[SUB279]], 1
+// CHECK1-NEXT: [[ADD281:%.*]] = add nsw i64 [[CONV158]], [[MUL280]]
+// CHECK1-NEXT: [[CONV282:%.*]] = trunc i64 [[ADD281]] to i32
+// CHECK1-NEXT: store i32 [[CONV282]], ptr [[DOTTILE_0_IV_K42]], align 4
+// CHECK1-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTTILE_0_IV_K42]], align 4
+// CHECK1-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
+// CHECK1-NEXT: [[ADD283:%.*]] = add i32 [[TMP146]], 1
+// CHECK1-NEXT: [[CMP284:%.*]] = icmp ult i32 [[TMP145]], [[ADD283]]
+// CHECK1-NEXT: br i1 [[CMP284]], label [[OMP_BODY_NEXT:%.*]], label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK1: omp.body.next:
+// CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4
+// CHECK1-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTTILE_0_IV_K42]], align 4
+// CHECK1-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4
+// CHECK1-NEXT: [[MUL285:%.*]] = mul i32 [[TMP148]], [[TMP149]]
+// CHECK1-NEXT: [[ADD286:%.*]] = add i32 [[TMP147]], [[MUL285]]
+// CHECK1-NEXT: store i32 [[ADD286]], ptr [[K]], align 4
+// CHECK1-NEXT: [[TMP150:%.*]] = load i32, ptr [[I39]], align 4
+// CHECK1-NEXT: [[TMP151:%.*]] = load i32, ptr [[J40]], align 4
+// CHECK1-NEXT: [[TMP152:%.*]] = load i32, ptr [[K]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP150]], i32 noundef [[TMP151]], i32 noundef [[TMP152]])
+// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP208:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[ADD405:%.*]] = add nsw i64 [[TMP208]], 1
-// CHECK1-NEXT: store i64 [[ADD405]], ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP153:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[ADD287:%.*]] = add nsw i64 [[TMP153]], 1
+// CHECK1-NEXT: store i64 [[ADD287]], ptr [[DOTOMP_IV]], align 8
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
@@ -1523,19 +1350,20 @@ extern "C" void foo10() {
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTFLOOR_0_IV_K:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[_TMP35:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[I49:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[J50:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTFLOOR_0_IV_K51:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTTILE_0_IV_K52:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[I39:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[J40:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTFLOOR_0_IV_K41:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTTILE_0_IV_K42:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
// CHECK1-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4
// CHECK1-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4
@@ -1575,628 +1403,453 @@ extern "C" void foo10() {
// CHECK1-NEXT: store i32 [[ADD15]], ptr [[DOTCAPTURE_EXPR_14]], align 4
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[_TMP2]], align 4
// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
-// CHECK1-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 1
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[_TMP2]], align 4
-// CHECK1-NEXT: [[ADD19:%.*]] = add i32 [[TMP18]], 64
-// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD18]], [[ADD19]]
-// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK1: cond.true:
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
-// CHECK1-NEXT: [[ADD20:%.*]] = add i32 [[TMP19]], 1
-// CHECK1-NEXT: br label [[COND_END:%.*]]
-// CHECK1: cond.false:
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[_TMP2]], align 4
-// CHECK1-NEXT: [[ADD21:%.*]] = add i32 [[TMP20]], 64
-// CHECK1-NEXT: br label [[COND_END]]
-// CHECK1: cond.end:
-// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[ADD20]], [[COND_TRUE]] ], [ [[ADD21]], [[COND_FALSE]] ]
-// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
-// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[SUB23:%.*]] = sub i32 [[TMP21]], [[TMP22]]
-// CHECK1-NEXT: [[SUB24:%.*]] = sub i32 [[SUB23]], 1
-// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
-// CHECK1-NEXT: [[ADD25:%.*]] = add i32 [[SUB24]], [[TMP23]]
-// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
-// CHECK1-NEXT: [[DIV26:%.*]] = udiv i32 [[ADD25]], [[TMP24]]
-// CHECK1-NEXT: [[CONV:%.*]] = zext i32 [[DIV26]] to i64
-// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB27:%.*]] = sub i32 [[TMP25]], [[TMP26]]
-// CHECK1-NEXT: [[SUB28:%.*]] = sub i32 [[SUB27]], 1
-// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD29:%.*]] = add i32 [[SUB28]], [[TMP27]]
-// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV30:%.*]] = udiv i32 [[ADD29]], [[TMP28]]
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[_TMP2]], align 4
+// CHECK1-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 64
+// CHECK1-NEXT: store i32 [[ADD18]], ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[SUB20:%.*]] = sub i32 [[TMP18]], [[TMP19]]
+// CHECK1-NEXT: [[SUB21:%.*]] = sub i32 [[SUB20]], 1
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK1-NEXT: [[ADD22:%.*]] = add i32 [[SUB21]], [[TMP20]]
+// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK1-NEXT: [[DIV23:%.*]] = udiv i32 [[ADD22]], [[TMP21]]
+// CHECK1-NEXT: [[CONV:%.*]] = zext i32 [[DIV23]] to i64
+// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB24:%.*]] = sub i32 [[TMP22]], [[TMP23]]
+// CHECK1-NEXT: [[SUB25:%.*]] = sub i32 [[SUB24]], 1
+// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD26:%.*]] = add i32 [[SUB25]], [[TMP24]]
+// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV27:%.*]] = udiv i32 [[ADD26]], [[TMP25]]
+// CHECK1-NEXT: [[CONV28:%.*]] = zext i32 [[DIV27]] to i64
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV28]]
+// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB29:%.*]] = sub i32 [[TMP26]], -63
+// CHECK1-NEXT: [[DIV30:%.*]] = udiv i32 [[SUB29]], 64
// CHECK1-NEXT: [[CONV31:%.*]] = zext i32 [[DIV30]] to i64
-// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV31]]
-// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB32:%.*]] = sub i32 [[TMP29]], -63
-// CHECK1-NEXT: [[DIV33:%.*]] = udiv i32 [[SUB32]], 64
-// CHECK1-NEXT: [[CONV34:%.*]] = zext i32 [[DIV33]] to i64
-// CHECK1-NEXT: [[MUL35:%.*]] = mul nsw i64 [[MUL]], [[CONV34]]
-// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB36:%.*]] = sub i32 [[TMP30]], [[TMP31]]
-// CHECK1-NEXT: [[SUB37:%.*]] = sub i32 [[SUB36]], 1
-// CHECK1-NEXT: [[ADD38:%.*]] = add i32 [[SUB37]], 1
-// CHECK1-NEXT: [[DIV39:%.*]] = udiv i32 [[ADD38]], 1
-// CHECK1-NEXT: [[CONV40:%.*]] = zext i32 [[DIV39]] to i64
-// CHECK1-NEXT: [[MUL41:%.*]] = mul nsw i64 [[MUL35]], [[CONV40]]
-// CHECK1-NEXT: [[SUB42:%.*]] = sub nsw i64 [[MUL41]], 1
-// CHECK1-NEXT: store i64 [[SUB42]], ptr [[DOTCAPTURE_EXPR_22]], align 8
-// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: store i32 [[TMP32]], ptr [[I]], align 4
-// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: store i32 [[TMP33]], ptr [[J]], align 4
+// CHECK1-NEXT: [[MUL32:%.*]] = mul nsw i64 [[MUL]], [[CONV31]]
+// CHECK1-NEXT: [[MUL33:%.*]] = mul nsw i64 [[MUL32]], 64
+// CHECK1-NEXT: [[SUB34:%.*]] = sub nsw i64 [[MUL33]], 1
+// CHECK1-NEXT: store i64 [[SUB34]], ptr [[DOTCAPTURE_EXPR_19]], align 8
+// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: store i32 [[TMP27]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: store i32 [[TMP28]], ptr [[J]], align 4
// CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_K]], align 4
-// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: store i32 [[TMP34]], ptr [[DOTTILE_0_IV_K]], align 4
-// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
-// CHECK1-NEXT: [[CMP43:%.*]] = icmp slt i32 [[TMP35]], [[TMP36]]
-// CHECK1-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
+// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_K]], align 4
+// CHECK1-NEXT: store i32 [[TMP29]], ptr [[DOTTILE_0_IV_K]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[_TMP35]], align 4
+// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
+// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP30]], [[TMP31]]
+// CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK1: land.lhs.true:
-// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]]
-// CHECK1-NEXT: br i1 [[CMP44]], label [[LAND_LHS_TRUE45:%.*]], label [[OMP_PRECOND_END]]
-// CHECK1: land.lhs.true45:
-// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[CMP46:%.*]] = icmp ult i32 0, [[TMP39]]
-// CHECK1-NEXT: br i1 [[CMP46]], label [[LAND_LHS_TRUE47:%.*]], label [[OMP_PRECOND_END]]
-// CHECK1: land.lhs.true47:
-// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[CMP48:%.*]] = icmp ult i32 [[TMP40]], [[TMP41]]
-// CHECK1-NEXT: br i1 [[CMP48]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
+// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[CMP36:%.*]] = icmp slt i32 [[TMP32]], [[TMP33]]
+// CHECK1-NEXT: br i1 [[CMP36]], label [[LAND_LHS_TRUE37:%.*]], label [[OMP_PRECOND_END]]
+// CHECK1: land.lhs.true37:
+// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[CMP38:%.*]] = icmp ult i32 0, [[TMP34]]
+// CHECK1-NEXT: br i1 [[CMP38]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
// CHECK1: omp.precond.then:
// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
-// CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
-// CHECK1-NEXT: store i64 [[TMP42]], ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: [[TMP35:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_19]], align 8
+// CHECK1-NEXT: store i64 [[TMP35]], ptr [[DOTOMP_UB]], align 8
// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
-// CHECK1-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
-// CHECK1-NEXT: [[CMP53:%.*]] = icmp sgt i64 [[TMP43]], [[TMP44]]
-// CHECK1-NEXT: br i1 [[CMP53]], label [[COND_TRUE54:%.*]], label [[COND_FALSE55:%.*]]
-// CHECK1: cond.true54:
-// CHECK1-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
-// CHECK1-NEXT: br label [[COND_END56:%.*]]
-// CHECK1: cond.false55:
-// CHECK1-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK1-NEXT: br label [[COND_END56]]
-// CHECK1: cond.end56:
-// CHECK1-NEXT: [[COND57:%.*]] = phi i64 [ [[TMP45]], [[COND_TRUE54]] ], [ [[TMP46]], [[COND_FALSE55]] ]
-// CHECK1-NEXT: store i64 [[COND57]], ptr [[DOTOMP_UB]], align 8
-// CHECK1-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
-// CHECK1-NEXT: store i64 [[TMP47]], ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP36:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_19]], align 8
+// CHECK1-NEXT: [[CMP43:%.*]] = icmp sgt i64 [[TMP36]], [[TMP37]]
+// CHECK1-NEXT: br i1 [[CMP43]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK1: cond.true:
+// CHECK1-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_19]], align 8
+// CHECK1-NEXT: br label [[COND_END:%.*]]
+// CHECK1: cond.false:
+// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: br label [[COND_END]]
+// CHECK1: cond.end:
+// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ [[TMP38]], [[COND_TRUE]] ], [ [[TMP39]], [[COND_FALSE]] ]
+// CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: [[TMP40:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
+// CHECK1-NEXT: store i64 [[TMP40]], ptr [[DOTOMP_IV]], align 8
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK1-NEXT: [[CMP58:%.*]] = icmp sle i64 [[TMP48]], [[TMP49]]
-// CHECK1-NEXT: br i1 [[CMP58]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK1-NEXT: [[TMP41:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: [[CMP44:%.*]] = icmp sle i64 [[TMP41]], [[TMP42]]
+// CHECK1-NEXT: br i1 [[CMP44]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[CONV59:%.*]] = sext i32 [[TMP50]] to i64
-// CHECK1-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB60:%.*]] = sub i32 [[TMP52]], [[TMP53]]
-// CHECK1-NEXT: [[SUB61:%.*]] = sub i32 [[SUB60]], 1
-// CHECK1-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD62:%.*]] = add i32 [[SUB61]], [[TMP54]]
-// CHECK1-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV63:%.*]] = udiv i32 [[ADD62]], [[TMP55]]
-// CHECK1-NEXT: [[MUL64:%.*]] = mul i32 1, [[DIV63]]
-// CHECK1-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB65:%.*]] = sub i32 [[TMP56]], -63
-// CHECK1-NEXT: [[DIV66:%.*]] = udiv i32 [[SUB65]], 64
-// CHECK1-NEXT: [[MUL67:%.*]] = mul i32 [[MUL64]], [[DIV66]]
-// CHECK1-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB68:%.*]] = sub i32 [[TMP57]], [[TMP58]]
-// CHECK1-NEXT: [[SUB69:%.*]] = sub i32 [[SUB68]], 1
-// CHECK1-NEXT: [[ADD70:%.*]] = add i32 [[SUB69]], 1
-// CHECK1-NEXT: [[DIV71:%.*]] = udiv i32 [[ADD70]], 1
-// CHECK1-NEXT: [[MUL72:%.*]] = mul i32 [[MUL67]], [[DIV71]]
-// CHECK1-NEXT: [[CONV73:%.*]] = zext i32 [[MUL72]] to i64
-// CHECK1-NEXT: [[DIV74:%.*]] = sdiv i64 [[TMP51]], [[CONV73]]
-// CHECK1-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
-// CHECK1-NEXT: [[CONV75:%.*]] = sext i32 [[TMP59]] to i64
-// CHECK1-NEXT: [[MUL76:%.*]] = mul nsw i64 [[DIV74]], [[CONV75]]
-// CHECK1-NEXT: [[ADD77:%.*]] = add nsw i64 [[CONV59]], [[MUL76]]
-// CHECK1-NEXT: [[CONV78:%.*]] = trunc i64 [[ADD77]] to i32
-// CHECK1-NEXT: store i32 [[CONV78]], ptr [[I49]], align 4
+// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[CONV45:%.*]] = sext i32 [[TMP43]] to i64
+// CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB46:%.*]] = sub i32 [[TMP45]], [[TMP46]]
+// CHECK1-NEXT: [[SUB47:%.*]] = sub i32 [[SUB46]], 1
+// CHECK1-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD48:%.*]] = add i32 [[SUB47]], [[TMP47]]
+// CHECK1-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV49:%.*]] = udiv i32 [[ADD48]], [[TMP48]]
+// CHECK1-NEXT: [[MUL50:%.*]] = mul i32 1, [[DIV49]]
+// CHECK1-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB51:%.*]] = sub i32 [[TMP49]], -63
+// CHECK1-NEXT: [[DIV52:%.*]] = udiv i32 [[SUB51]], 64
+// CHECK1-NEXT: [[MUL53:%.*]] = mul i32 [[MUL50]], [[DIV52]]
+// CHECK1-NEXT: [[MUL54:%.*]] = mul i32 [[MUL53]], 64
+// CHECK1-NEXT: [[CONV55:%.*]] = zext i32 [[MUL54]] to i64
+// CHECK1-NEXT: [[DIV56:%.*]] = sdiv i64 [[TMP44]], [[CONV55]]
+// CHECK1-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK1-NEXT: [[CONV57:%.*]] = sext i32 [[TMP50]] to i64
+// CHECK1-NEXT: [[MUL58:%.*]] = mul nsw i64 [[DIV56]], [[CONV57]]
+// CHECK1-NEXT: [[ADD59:%.*]] = add nsw i64 [[CONV45]], [[MUL58]]
+// CHECK1-NEXT: [[CONV60:%.*]] = trunc i64 [[ADD59]] to i32
+// CHECK1-NEXT: store i32 [[CONV60]], ptr [[I39]], align 4
+// CHECK1-NEXT: [[TMP51:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[CONV61:%.*]] = sext i32 [[TMP51]] to i64
+// CHECK1-NEXT: [[TMP52:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP53:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB62:%.*]] = sub i32 [[TMP54]], [[TMP55]]
+// CHECK1-NEXT: [[SUB63:%.*]] = sub i32 [[SUB62]], 1
+// CHECK1-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD64:%.*]] = add i32 [[SUB63]], [[TMP56]]
+// CHECK1-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV65:%.*]] = udiv i32 [[ADD64]], [[TMP57]]
+// CHECK1-NEXT: [[MUL66:%.*]] = mul i32 1, [[DIV65]]
+// CHECK1-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB67:%.*]] = sub i32 [[TMP58]], -63
+// CHECK1-NEXT: [[DIV68:%.*]] = udiv i32 [[SUB67]], 64
+// CHECK1-NEXT: [[MUL69:%.*]] = mul i32 [[MUL66]], [[DIV68]]
+// CHECK1-NEXT: [[MUL70:%.*]] = mul i32 [[MUL69]], 64
+// CHECK1-NEXT: [[CONV71:%.*]] = zext i32 [[MUL70]] to i64
+// CHECK1-NEXT: [[DIV72:%.*]] = sdiv i64 [[TMP53]], [[CONV71]]
+// CHECK1-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
// CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[CONV79:%.*]] = sext i32 [[TMP60]] to i64
-// CHECK1-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB80:%.*]] = sub i32 [[TMP63]], [[TMP64]]
-// CHECK1-NEXT: [[SUB81:%.*]] = sub i32 [[SUB80]], 1
-// CHECK1-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD82:%.*]] = add i32 [[SUB81]], [[TMP65]]
-// CHECK1-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV83:%.*]] = udiv i32 [[ADD82]], [[TMP66]]
-// CHECK1-NEXT: [[MUL84:%.*]] = mul i32 1, [[DIV83]]
-// CHECK1-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB85:%.*]] = sub i32 [[TMP67]], -63
+// CHECK1-NEXT: [[SUB73:%.*]] = sub i32 [[TMP59]], [[TMP60]]
+// CHECK1-NEXT: [[SUB74:%.*]] = sub i32 [[SUB73]], 1
+// CHECK1-NEXT: [[TMP61:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD75:%.*]] = add i32 [[SUB74]], [[TMP61]]
+// CHECK1-NEXT: [[TMP62:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV76:%.*]] = udiv i32 [[ADD75]], [[TMP62]]
+// CHECK1-NEXT: [[MUL77:%.*]] = mul i32 1, [[DIV76]]
+// CHECK1-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB78:%.*]] = sub i32 [[TMP63]], -63
+// CHECK1-NEXT: [[DIV79:%.*]] = udiv i32 [[SUB78]], 64
+// CHECK1-NEXT: [[MUL80:%.*]] = mul i32 [[MUL77]], [[DIV79]]
+// CHECK1-NEXT: [[MUL81:%.*]] = mul i32 [[MUL80]], 64
+// CHECK1-NEXT: [[CONV82:%.*]] = zext i32 [[MUL81]] to i64
+// CHECK1-NEXT: [[MUL83:%.*]] = mul nsw i64 [[DIV72]], [[CONV82]]
+// CHECK1-NEXT: [[SUB84:%.*]] = sub nsw i64 [[TMP52]], [[MUL83]]
+// CHECK1-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB85:%.*]] = sub i32 [[TMP64]], -63
// CHECK1-NEXT: [[DIV86:%.*]] = udiv i32 [[SUB85]], 64
-// CHECK1-NEXT: [[MUL87:%.*]] = mul i32 [[MUL84]], [[DIV86]]
-// CHECK1-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB88:%.*]] = sub i32 [[TMP68]], [[TMP69]]
-// CHECK1-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 1
-// CHECK1-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 1
-// CHECK1-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 1
-// CHECK1-NEXT: [[MUL92:%.*]] = mul i32 [[MUL87]], [[DIV91]]
-// CHECK1-NEXT: [[CONV93:%.*]] = zext i32 [[MUL92]] to i64
-// CHECK1-NEXT: [[DIV94:%.*]] = sdiv i64 [[TMP62]], [[CONV93]]
-// CHECK1-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB95:%.*]] = sub i32 [[TMP70]], [[TMP71]]
+// CHECK1-NEXT: [[MUL87:%.*]] = mul i32 1, [[DIV86]]
+// CHECK1-NEXT: [[MUL88:%.*]] = mul i32 [[MUL87]], 64
+// CHECK1-NEXT: [[CONV89:%.*]] = zext i32 [[MUL88]] to i64
+// CHECK1-NEXT: [[DIV90:%.*]] = sdiv i64 [[SUB84]], [[CONV89]]
+// CHECK1-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[CONV91:%.*]] = sext i32 [[TMP65]] to i64
+// CHECK1-NEXT: [[MUL92:%.*]] = mul nsw i64 [[DIV90]], [[CONV91]]
+// CHECK1-NEXT: [[ADD93:%.*]] = add nsw i64 [[CONV61]], [[MUL92]]
+// CHECK1-NEXT: [[CONV94:%.*]] = trunc i64 [[ADD93]] to i32
+// CHECK1-NEXT: store i32 [[CONV94]], ptr [[J40]], align 4
+// CHECK1-NEXT: [[TMP66:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP67:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB95:%.*]] = sub i32 [[TMP68]], [[TMP69]]
// CHECK1-NEXT: [[SUB96:%.*]] = sub i32 [[SUB95]], 1
-// CHECK1-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP72]]
-// CHECK1-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP73]]
+// CHECK1-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP70]]
+// CHECK1-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP71]]
// CHECK1-NEXT: [[MUL99:%.*]] = mul i32 1, [[DIV98]]
-// CHECK1-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB100:%.*]] = sub i32 [[TMP74]], -63
+// CHECK1-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB100:%.*]] = sub i32 [[TMP72]], -63
// CHECK1-NEXT: [[DIV101:%.*]] = udiv i32 [[SUB100]], 64
// CHECK1-NEXT: [[MUL102:%.*]] = mul i32 [[MUL99]], [[DIV101]]
-// CHECK1-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB103:%.*]] = sub i32 [[TMP75]], [[TMP76]]
-// CHECK1-NEXT: [[SUB104:%.*]] = sub i32 [[SUB103]], 1
-// CHECK1-NEXT: [[ADD105:%.*]] = add i32 [[SUB104]], 1
-// CHECK1-NEXT: [[DIV106:%.*]] = udiv i32 [[ADD105]], 1
-// CHECK1-NEXT: [[MUL107:%.*]] = mul i32 [[MUL102]], [[DIV106]]
-// CHECK1-NEXT: [[CONV108:%.*]] = zext i32 [[MUL107]] to i64
-// CHECK1-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV94]], [[CONV108]]
-// CHECK1-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP61]], [[MUL109]]
+// CHECK1-NEXT: [[MUL103:%.*]] = mul i32 [[MUL102]], 64
+// CHECK1-NEXT: [[CONV104:%.*]] = zext i32 [[MUL103]] to i64
+// CHECK1-NEXT: [[DIV105:%.*]] = sdiv i64 [[TMP67]], [[CONV104]]
+// CHECK1-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB106:%.*]] = sub i32 [[TMP73]], [[TMP74]]
+// CHECK1-NEXT: [[SUB107:%.*]] = sub i32 [[SUB106]], 1
+// CHECK1-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD108:%.*]] = add i32 [[SUB107]], [[TMP75]]
+// CHECK1-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV109:%.*]] = udiv i32 [[ADD108]], [[TMP76]]
+// CHECK1-NEXT: [[MUL110:%.*]] = mul i32 1, [[DIV109]]
// CHECK1-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
// CHECK1-NEXT: [[SUB111:%.*]] = sub i32 [[TMP77]], -63
// CHECK1-NEXT: [[DIV112:%.*]] = udiv i32 [[SUB111]], 64
-// CHECK1-NEXT: [[MUL113:%.*]] = mul i32 1, [[DIV112]]
-// CHECK1-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB114:%.*]] = sub i32 [[TMP78]], [[TMP79]]
-// CHECK1-NEXT: [[SUB115:%.*]] = sub i32 [[SUB114]], 1
-// CHECK1-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], 1
-// CHECK1-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], 1
-// CHECK1-NEXT: [[MUL118:%.*]] = mul i32 [[MUL113]], [[DIV117]]
-// CHECK1-NEXT: [[CONV119:%.*]] = zext i32 [[MUL118]] to i64
-// CHECK1-NEXT: [[DIV120:%.*]] = sdiv i64 [[SUB110]], [[CONV119]]
-// CHECK1-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[CONV121:%.*]] = sext i32 [[TMP80]] to i64
-// CHECK1-NEXT: [[MUL122:%.*]] = mul nsw i64 [[DIV120]], [[CONV121]]
-// CHECK1-NEXT: [[ADD123:%.*]] = add nsw i64 [[CONV79]], [[MUL122]]
-// CHECK1-NEXT: [[CONV124:%.*]] = trunc i64 [[ADD123]] to i32
-// CHECK1-NEXT: store i32 [[CONV124]], ptr [[J50]], align 4
-// CHECK1-NEXT: [[TMP81:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP82:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB125:%.*]] = sub i32 [[TMP83]], [[TMP84]]
-// CHECK1-NEXT: [[SUB126:%.*]] = sub i32 [[SUB125]], 1
-// CHECK1-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP85]]
-// CHECK1-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP86]]
-// CHECK1-NEXT: [[MUL129:%.*]] = mul i32 1, [[DIV128]]
-// CHECK1-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB130:%.*]] = sub i32 [[TMP87]], -63
-// CHECK1-NEXT: [[DIV131:%.*]] = udiv i32 [[SUB130]], 64
-// CHECK1-NEXT: [[MUL132:%.*]] = mul i32 [[MUL129]], [[DIV131]]
-// CHECK1-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB133:%.*]] = sub i32 [[TMP88]], [[TMP89]]
-// CHECK1-NEXT: [[SUB134:%.*]] = sub i32 [[SUB133]], 1
-// CHECK1-NEXT: [[ADD135:%.*]] = add i32 [[SUB134]], 1
-// CHECK1-NEXT: [[DIV136:%.*]] = udiv i32 [[ADD135]], 1
-// CHECK1-NEXT: [[MUL137:%.*]] = mul i32 [[MUL132]], [[DIV136]]
+// CHECK1-NEXT: [[MUL113:%.*]] = mul i32 [[MUL110]], [[DIV112]]
+// CHECK1-NEXT: [[MUL114:%.*]] = mul i32 [[MUL113]], 64
+// CHECK1-NEXT: [[CONV115:%.*]] = zext i32 [[MUL114]] to i64
+// CHECK1-NEXT: [[MUL116:%.*]] = mul nsw i64 [[DIV105]], [[CONV115]]
+// CHECK1-NEXT: [[SUB117:%.*]] = sub nsw i64 [[TMP66]], [[MUL116]]
+// CHECK1-NEXT: [[TMP78:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP79:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP81:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB118:%.*]] = sub i32 [[TMP80]], [[TMP81]]
+// CHECK1-NEXT: [[SUB119:%.*]] = sub i32 [[SUB118]], 1
+// CHECK1-NEXT: [[TMP82:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD120:%.*]] = add i32 [[SUB119]], [[TMP82]]
+// CHECK1-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV121:%.*]] = udiv i32 [[ADD120]], [[TMP83]]
+// CHECK1-NEXT: [[MUL122:%.*]] = mul i32 1, [[DIV121]]
+// CHECK1-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB123:%.*]] = sub i32 [[TMP84]], -63
+// CHECK1-NEXT: [[DIV124:%.*]] = udiv i32 [[SUB123]], 64
+// CHECK1-NEXT: [[MUL125:%.*]] = mul i32 [[MUL122]], [[DIV124]]
+// CHECK1-NEXT: [[MUL126:%.*]] = mul i32 [[MUL125]], 64
+// CHECK1-NEXT: [[CONV127:%.*]] = zext i32 [[MUL126]] to i64
+// CHECK1-NEXT: [[DIV128:%.*]] = sdiv i64 [[TMP79]], [[CONV127]]
+// CHECK1-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB129:%.*]] = sub i32 [[TMP85]], [[TMP86]]
+// CHECK1-NEXT: [[SUB130:%.*]] = sub i32 [[SUB129]], 1
+// CHECK1-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD131:%.*]] = add i32 [[SUB130]], [[TMP87]]
+// CHECK1-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV132:%.*]] = udiv i32 [[ADD131]], [[TMP88]]
+// CHECK1-NEXT: [[MUL133:%.*]] = mul i32 1, [[DIV132]]
+// CHECK1-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB134:%.*]] = sub i32 [[TMP89]], -63
+// CHECK1-NEXT: [[DIV135:%.*]] = udiv i32 [[SUB134]], 64
+// CHECK1-NEXT: [[MUL136:%.*]] = mul i32 [[MUL133]], [[DIV135]]
+// CHECK1-NEXT: [[MUL137:%.*]] = mul i32 [[MUL136]], 64
// CHECK1-NEXT: [[CONV138:%.*]] = zext i32 [[MUL137]] to i64
-// CHECK1-NEXT: [[DIV139:%.*]] = sdiv i64 [[TMP82]], [[CONV138]]
-// CHECK1-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB140:%.*]] = sub i32 [[TMP90]], [[TMP91]]
-// CHECK1-NEXT: [[SUB141:%.*]] = sub i32 [[SUB140]], 1
-// CHECK1-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD142:%.*]] = add i32 [[SUB141]], [[TMP92]]
-// CHECK1-NEXT: [[TMP93:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV143:%.*]] = udiv i32 [[ADD142]], [[TMP93]]
-// CHECK1-NEXT: [[MUL144:%.*]] = mul i32 1, [[DIV143]]
-// CHECK1-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB145:%.*]] = sub i32 [[TMP94]], -63
-// CHECK1-NEXT: [[DIV146:%.*]] = udiv i32 [[SUB145]], 64
-// CHECK1-NEXT: [[MUL147:%.*]] = mul i32 [[MUL144]], [[DIV146]]
-// CHECK1-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB148:%.*]] = sub i32 [[TMP95]], [[TMP96]]
-// CHECK1-NEXT: [[SUB149:%.*]] = sub i32 [[SUB148]], 1
-// CHECK1-NEXT: [[ADD150:%.*]] = add i32 [[SUB149]], 1
-// CHECK1-NEXT: [[DIV151:%.*]] = udiv i32 [[ADD150]], 1
-// CHECK1-NEXT: [[MUL152:%.*]] = mul i32 [[MUL147]], [[DIV151]]
-// CHECK1-NEXT: [[CONV153:%.*]] = zext i32 [[MUL152]] to i64
-// CHECK1-NEXT: [[MUL154:%.*]] = mul nsw i64 [[DIV139]], [[CONV153]]
-// CHECK1-NEXT: [[SUB155:%.*]] = sub nsw i64 [[TMP81]], [[MUL154]]
-// CHECK1-NEXT: [[TMP97:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP98:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB156:%.*]] = sub i32 [[TMP99]], [[TMP100]]
-// CHECK1-NEXT: [[SUB157:%.*]] = sub i32 [[SUB156]], 1
-// CHECK1-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD158:%.*]] = add i32 [[SUB157]], [[TMP101]]
+// CHECK1-NEXT: [[MUL139:%.*]] = mul nsw i64 [[DIV128]], [[CONV138]]
+// CHECK1-NEXT: [[SUB140:%.*]] = sub nsw i64 [[TMP78]], [[MUL139]]
+// CHECK1-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB141:%.*]] = sub i32 [[TMP90]], -63
+// CHECK1-NEXT: [[DIV142:%.*]] = udiv i32 [[SUB141]], 64
+// CHECK1-NEXT: [[MUL143:%.*]] = mul i32 1, [[DIV142]]
+// CHECK1-NEXT: [[MUL144:%.*]] = mul i32 [[MUL143]], 64
+// CHECK1-NEXT: [[CONV145:%.*]] = zext i32 [[MUL144]] to i64
+// CHECK1-NEXT: [[DIV146:%.*]] = sdiv i64 [[SUB140]], [[CONV145]]
+// CHECK1-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB147:%.*]] = sub i32 [[TMP91]], -63
+// CHECK1-NEXT: [[DIV148:%.*]] = udiv i32 [[SUB147]], 64
+// CHECK1-NEXT: [[MUL149:%.*]] = mul i32 1, [[DIV148]]
+// CHECK1-NEXT: [[MUL150:%.*]] = mul i32 [[MUL149]], 64
+// CHECK1-NEXT: [[CONV151:%.*]] = zext i32 [[MUL150]] to i64
+// CHECK1-NEXT: [[MUL152:%.*]] = mul nsw i64 [[DIV146]], [[CONV151]]
+// CHECK1-NEXT: [[SUB153:%.*]] = sub nsw i64 [[SUB117]], [[MUL152]]
+// CHECK1-NEXT: [[DIV154:%.*]] = sdiv i64 [[SUB153]], 64
+// CHECK1-NEXT: [[MUL155:%.*]] = mul nsw i64 [[DIV154]], 64
+// CHECK1-NEXT: [[ADD156:%.*]] = add nsw i64 0, [[MUL155]]
+// CHECK1-NEXT: [[CONV157:%.*]] = trunc i64 [[ADD156]] to i32
+// CHECK1-NEXT: store i32 [[CONV157]], ptr [[DOTFLOOR_0_IV_K41]], align 4
+// CHECK1-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_K41]], align 4
+// CHECK1-NEXT: [[CONV158:%.*]] = zext i32 [[TMP92]] to i64
+// CHECK1-NEXT: [[TMP93:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP94:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB159:%.*]] = sub i32 [[TMP95]], [[TMP96]]
+// CHECK1-NEXT: [[SUB160:%.*]] = sub i32 [[SUB159]], 1
+// CHECK1-NEXT: [[TMP97:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD161:%.*]] = add i32 [[SUB160]], [[TMP97]]
+// CHECK1-NEXT: [[TMP98:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV162:%.*]] = udiv i32 [[ADD161]], [[TMP98]]
+// CHECK1-NEXT: [[MUL163:%.*]] = mul i32 1, [[DIV162]]
+// CHECK1-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB164:%.*]] = sub i32 [[TMP99]], -63
+// CHECK1-NEXT: [[DIV165:%.*]] = udiv i32 [[SUB164]], 64
+// CHECK1-NEXT: [[MUL166:%.*]] = mul i32 [[MUL163]], [[DIV165]]
+// CHECK1-NEXT: [[MUL167:%.*]] = mul i32 [[MUL166]], 64
+// CHECK1-NEXT: [[CONV168:%.*]] = zext i32 [[MUL167]] to i64
+// CHECK1-NEXT: [[DIV169:%.*]] = sdiv i64 [[TMP94]], [[CONV168]]
+// CHECK1-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB170:%.*]] = sub i32 [[TMP100]], [[TMP101]]
+// CHECK1-NEXT: [[SUB171:%.*]] = sub i32 [[SUB170]], 1
// CHECK1-NEXT: [[TMP102:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV159:%.*]] = udiv i32 [[ADD158]], [[TMP102]]
-// CHECK1-NEXT: [[MUL160:%.*]] = mul i32 1, [[DIV159]]
-// CHECK1-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB161:%.*]] = sub i32 [[TMP103]], -63
-// CHECK1-NEXT: [[DIV162:%.*]] = udiv i32 [[SUB161]], 64
-// CHECK1-NEXT: [[MUL163:%.*]] = mul i32 [[MUL160]], [[DIV162]]
-// CHECK1-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB164:%.*]] = sub i32 [[TMP104]], [[TMP105]]
-// CHECK1-NEXT: [[SUB165:%.*]] = sub i32 [[SUB164]], 1
-// CHECK1-NEXT: [[ADD166:%.*]] = add i32 [[SUB165]], 1
-// CHECK1-NEXT: [[DIV167:%.*]] = udiv i32 [[ADD166]], 1
-// CHECK1-NEXT: [[MUL168:%.*]] = mul i32 [[MUL163]], [[DIV167]]
-// CHECK1-NEXT: [[CONV169:%.*]] = zext i32 [[MUL168]] to i64
-// CHECK1-NEXT: [[DIV170:%.*]] = sdiv i64 [[TMP98]], [[CONV169]]
-// CHECK1-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB171:%.*]] = sub i32 [[TMP106]], [[TMP107]]
-// CHECK1-NEXT: [[SUB172:%.*]] = sub i32 [[SUB171]], 1
-// CHECK1-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD173:%.*]] = add i32 [[SUB172]], [[TMP108]]
+// CHECK1-NEXT: [[ADD172:%.*]] = add i32 [[SUB171]], [[TMP102]]
+// CHECK1-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV173:%.*]] = udiv i32 [[ADD172]], [[TMP103]]
+// CHECK1-NEXT: [[MUL174:%.*]] = mul i32 1, [[DIV173]]
+// CHECK1-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB175:%.*]] = sub i32 [[TMP104]], -63
+// CHECK1-NEXT: [[DIV176:%.*]] = udiv i32 [[SUB175]], 64
+// CHECK1-NEXT: [[MUL177:%.*]] = mul i32 [[MUL174]], [[DIV176]]
+// CHECK1-NEXT: [[MUL178:%.*]] = mul i32 [[MUL177]], 64
+// CHECK1-NEXT: [[CONV179:%.*]] = zext i32 [[MUL178]] to i64
+// CHECK1-NEXT: [[MUL180:%.*]] = mul nsw i64 [[DIV169]], [[CONV179]]
+// CHECK1-NEXT: [[SUB181:%.*]] = sub nsw i64 [[TMP93]], [[MUL180]]
+// CHECK1-NEXT: [[TMP105:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP106:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB182:%.*]] = sub i32 [[TMP107]], [[TMP108]]
+// CHECK1-NEXT: [[SUB183:%.*]] = sub i32 [[SUB182]], 1
// CHECK1-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV174:%.*]] = udiv i32 [[ADD173]], [[TMP109]]
-// CHECK1-NEXT: [[MUL175:%.*]] = mul i32 1, [[DIV174]]
-// CHECK1-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB176:%.*]] = sub i32 [[TMP110]], -63
-// CHECK1-NEXT: [[DIV177:%.*]] = udiv i32 [[SUB176]], 64
-// CHECK1-NEXT: [[MUL178:%.*]] = mul i32 [[MUL175]], [[DIV177]]
-// CHECK1-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB179:%.*]] = sub i32 [[TMP111]], [[TMP112]]
-// CHECK1-NEXT: [[SUB180:%.*]] = sub i32 [[SUB179]], 1
-// CHECK1-NEXT: [[ADD181:%.*]] = add i32 [[SUB180]], 1
-// CHECK1-NEXT: [[DIV182:%.*]] = udiv i32 [[ADD181]], 1
-// CHECK1-NEXT: [[MUL183:%.*]] = mul i32 [[MUL178]], [[DIV182]]
-// CHECK1-NEXT: [[CONV184:%.*]] = zext i32 [[MUL183]] to i64
-// CHECK1-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV170]], [[CONV184]]
-// CHECK1-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP97]], [[MUL185]]
-// CHECK1-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB187:%.*]] = sub i32 [[TMP113]], -63
+// CHECK1-NEXT: [[ADD184:%.*]] = add i32 [[SUB183]], [[TMP109]]
+// CHECK1-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV185:%.*]] = udiv i32 [[ADD184]], [[TMP110]]
+// CHECK1-NEXT: [[MUL186:%.*]] = mul i32 1, [[DIV185]]
+// CHECK1-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB187:%.*]] = sub i32 [[TMP111]], -63
// CHECK1-NEXT: [[DIV188:%.*]] = udiv i32 [[SUB187]], 64
-// CHECK1-NEXT: [[MUL189:%.*]] = mul i32 1, [[DIV188]]
-// CHECK1-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB190:%.*]] = sub i32 [[TMP114]], [[TMP115]]
-// CHECK1-NEXT: [[SUB191:%.*]] = sub i32 [[SUB190]], 1
-// CHECK1-NEXT: [[ADD192:%.*]] = add i32 [[SUB191]], 1
-// CHECK1-NEXT: [[DIV193:%.*]] = udiv i32 [[ADD192]], 1
-// CHECK1-NEXT: [[MUL194:%.*]] = mul i32 [[MUL189]], [[DIV193]]
-// CHECK1-NEXT: [[CONV195:%.*]] = zext i32 [[MUL194]] to i64
-// CHECK1-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB186]], [[CONV195]]
+// CHECK1-NEXT: [[MUL189:%.*]] = mul i32 [[MUL186]], [[DIV188]]
+// CHECK1-NEXT: [[MUL190:%.*]] = mul i32 [[MUL189]], 64
+// CHECK1-NEXT: [[CONV191:%.*]] = zext i32 [[MUL190]] to i64
+// CHECK1-NEXT: [[DIV192:%.*]] = sdiv i64 [[TMP106]], [[CONV191]]
+// CHECK1-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB193:%.*]] = sub i32 [[TMP112]], [[TMP113]]
+// CHECK1-NEXT: [[SUB194:%.*]] = sub i32 [[SUB193]], 1
+// CHECK1-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD195:%.*]] = add i32 [[SUB194]], [[TMP114]]
+// CHECK1-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV196:%.*]] = udiv i32 [[ADD195]], [[TMP115]]
+// CHECK1-NEXT: [[MUL197:%.*]] = mul i32 1, [[DIV196]]
// CHECK1-NEXT: [[TMP116:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB197:%.*]] = sub i32 [[TMP116]], -63
-// CHECK1-NEXT: [[DIV198:%.*]] = udiv i32 [[SUB197]], 64
-// CHECK1-NEXT: [[MUL199:%.*]] = mul i32 1, [[DIV198]]
-// CHECK1-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB200:%.*]] = sub i32 [[TMP117]], [[TMP118]]
-// CHECK1-NEXT: [[SUB201:%.*]] = sub i32 [[SUB200]], 1
-// CHECK1-NEXT: [[ADD202:%.*]] = add i32 [[SUB201]], 1
-// CHECK1-NEXT: [[DIV203:%.*]] = udiv i32 [[ADD202]], 1
-// CHECK1-NEXT: [[MUL204:%.*]] = mul i32 [[MUL199]], [[DIV203]]
-// CHECK1-NEXT: [[CONV205:%.*]] = zext i32 [[MUL204]] to i64
-// CHECK1-NEXT: [[MUL206:%.*]] = mul nsw i64 [[DIV196]], [[CONV205]]
-// CHECK1-NEXT: [[SUB207:%.*]] = sub nsw i64 [[SUB155]], [[MUL206]]
-// CHECK1-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB208:%.*]] = sub i32 [[TMP119]], [[TMP120]]
-// CHECK1-NEXT: [[SUB209:%.*]] = sub i32 [[SUB208]], 1
-// CHECK1-NEXT: [[ADD210:%.*]] = add i32 [[SUB209]], 1
-// CHECK1-NEXT: [[DIV211:%.*]] = udiv i32 [[ADD210]], 1
-// CHECK1-NEXT: [[MUL212:%.*]] = mul i32 1, [[DIV211]]
-// CHECK1-NEXT: [[CONV213:%.*]] = zext i32 [[MUL212]] to i64
-// CHECK1-NEXT: [[DIV214:%.*]] = sdiv i64 [[SUB207]], [[CONV213]]
-// CHECK1-NEXT: [[MUL215:%.*]] = mul nsw i64 [[DIV214]], 64
-// CHECK1-NEXT: [[ADD216:%.*]] = add nsw i64 0, [[MUL215]]
-// CHECK1-NEXT: [[CONV217:%.*]] = trunc i64 [[ADD216]] to i32
-// CHECK1-NEXT: store i32 [[CONV217]], ptr [[DOTFLOOR_0_IV_K51]], align 4
-// CHECK1-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[CONV218:%.*]] = zext i32 [[TMP121]] to i64
-// CHECK1-NEXT: [[TMP122:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP123:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB219:%.*]] = sub i32 [[TMP124]], [[TMP125]]
-// CHECK1-NEXT: [[SUB220:%.*]] = sub i32 [[SUB219]], 1
-// CHECK1-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD221:%.*]] = add i32 [[SUB220]], [[TMP126]]
-// CHECK1-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV222:%.*]] = udiv i32 [[ADD221]], [[TMP127]]
-// CHECK1-NEXT: [[MUL223:%.*]] = mul i32 1, [[DIV222]]
-// CHECK1-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB224:%.*]] = sub i32 [[TMP128]], -63
-// CHECK1-NEXT: [[DIV225:%.*]] = udiv i32 [[SUB224]], 64
-// CHECK1-NEXT: [[MUL226:%.*]] = mul i32 [[MUL223]], [[DIV225]]
-// CHECK1-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB227:%.*]] = sub i32 [[TMP129]], [[TMP130]]
-// CHECK1-NEXT: [[SUB228:%.*]] = sub i32 [[SUB227]], 1
-// CHECK1-NEXT: [[ADD229:%.*]] = add i32 [[SUB228]], 1
-// CHECK1-NEXT: [[DIV230:%.*]] = udiv i32 [[ADD229]], 1
-// CHECK1-NEXT: [[MUL231:%.*]] = mul i32 [[MUL226]], [[DIV230]]
-// CHECK1-NEXT: [[CONV232:%.*]] = zext i32 [[MUL231]] to i64
-// CHECK1-NEXT: [[DIV233:%.*]] = sdiv i64 [[TMP123]], [[CONV232]]
-// CHECK1-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB234:%.*]] = sub i32 [[TMP131]], [[TMP132]]
-// CHECK1-NEXT: [[SUB235:%.*]] = sub i32 [[SUB234]], 1
-// CHECK1-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD236:%.*]] = add i32 [[SUB235]], [[TMP133]]
-// CHECK1-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV237:%.*]] = udiv i32 [[ADD236]], [[TMP134]]
-// CHECK1-NEXT: [[MUL238:%.*]] = mul i32 1, [[DIV237]]
-// CHECK1-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB239:%.*]] = sub i32 [[TMP135]], -63
-// CHECK1-NEXT: [[DIV240:%.*]] = udiv i32 [[SUB239]], 64
-// CHECK1-NEXT: [[MUL241:%.*]] = mul i32 [[MUL238]], [[DIV240]]
-// CHECK1-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB242:%.*]] = sub i32 [[TMP136]], [[TMP137]]
-// CHECK1-NEXT: [[SUB243:%.*]] = sub i32 [[SUB242]], 1
-// CHECK1-NEXT: [[ADD244:%.*]] = add i32 [[SUB243]], 1
-// CHECK1-NEXT: [[DIV245:%.*]] = udiv i32 [[ADD244]], 1
-// CHECK1-NEXT: [[MUL246:%.*]] = mul i32 [[MUL241]], [[DIV245]]
-// CHECK1-NEXT: [[CONV247:%.*]] = zext i32 [[MUL246]] to i64
-// CHECK1-NEXT: [[MUL248:%.*]] = mul nsw i64 [[DIV233]], [[CONV247]]
-// CHECK1-NEXT: [[SUB249:%.*]] = sub nsw i64 [[TMP122]], [[MUL248]]
-// CHECK1-NEXT: [[TMP138:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP139:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB250:%.*]] = sub i32 [[TMP140]], [[TMP141]]
-// CHECK1-NEXT: [[SUB251:%.*]] = sub i32 [[SUB250]], 1
-// CHECK1-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD252:%.*]] = add i32 [[SUB251]], [[TMP142]]
-// CHECK1-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV253:%.*]] = udiv i32 [[ADD252]], [[TMP143]]
-// CHECK1-NEXT: [[MUL254:%.*]] = mul i32 1, [[DIV253]]
+// CHECK1-NEXT: [[SUB198:%.*]] = sub i32 [[TMP116]], -63
+// CHECK1-NEXT: [[DIV199:%.*]] = udiv i32 [[SUB198]], 64
+// CHECK1-NEXT: [[MUL200:%.*]] = mul i32 [[MUL197]], [[DIV199]]
+// CHECK1-NEXT: [[MUL201:%.*]] = mul i32 [[MUL200]], 64
+// CHECK1-NEXT: [[CONV202:%.*]] = zext i32 [[MUL201]] to i64
+// CHECK1-NEXT: [[MUL203:%.*]] = mul nsw i64 [[DIV192]], [[CONV202]]
+// CHECK1-NEXT: [[SUB204:%.*]] = sub nsw i64 [[TMP105]], [[MUL203]]
+// CHECK1-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB205:%.*]] = sub i32 [[TMP117]], -63
+// CHECK1-NEXT: [[DIV206:%.*]] = udiv i32 [[SUB205]], 64
+// CHECK1-NEXT: [[MUL207:%.*]] = mul i32 1, [[DIV206]]
+// CHECK1-NEXT: [[MUL208:%.*]] = mul i32 [[MUL207]], 64
+// CHECK1-NEXT: [[CONV209:%.*]] = zext i32 [[MUL208]] to i64
+// CHECK1-NEXT: [[DIV210:%.*]] = sdiv i64 [[SUB204]], [[CONV209]]
+// CHECK1-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB211:%.*]] = sub i32 [[TMP118]], -63
+// CHECK1-NEXT: [[DIV212:%.*]] = udiv i32 [[SUB211]], 64
+// CHECK1-NEXT: [[MUL213:%.*]] = mul i32 1, [[DIV212]]
+// CHECK1-NEXT: [[MUL214:%.*]] = mul i32 [[MUL213]], 64
+// CHECK1-NEXT: [[CONV215:%.*]] = zext i32 [[MUL214]] to i64
+// CHECK1-NEXT: [[MUL216:%.*]] = mul nsw i64 [[DIV210]], [[CONV215]]
+// CHECK1-NEXT: [[SUB217:%.*]] = sub nsw i64 [[SUB181]], [[MUL216]]
+// CHECK1-NEXT: [[TMP119:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP120:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP122:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB218:%.*]] = sub i32 [[TMP121]], [[TMP122]]
+// CHECK1-NEXT: [[SUB219:%.*]] = sub i32 [[SUB218]], 1
+// CHECK1-NEXT: [[TMP123:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD220:%.*]] = add i32 [[SUB219]], [[TMP123]]
+// CHECK1-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV221:%.*]] = udiv i32 [[ADD220]], [[TMP124]]
+// CHECK1-NEXT: [[MUL222:%.*]] = mul i32 1, [[DIV221]]
+// CHECK1-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB223:%.*]] = sub i32 [[TMP125]], -63
+// CHECK1-NEXT: [[DIV224:%.*]] = udiv i32 [[SUB223]], 64
+// CHECK1-NEXT: [[MUL225:%.*]] = mul i32 [[MUL222]], [[DIV224]]
+// CHECK1-NEXT: [[MUL226:%.*]] = mul i32 [[MUL225]], 64
+// CHECK1-NEXT: [[CONV227:%.*]] = zext i32 [[MUL226]] to i64
+// CHECK1-NEXT: [[DIV228:%.*]] = sdiv i64 [[TMP120]], [[CONV227]]
+// CHECK1-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB229:%.*]] = sub i32 [[TMP126]], [[TMP127]]
+// CHECK1-NEXT: [[SUB230:%.*]] = sub i32 [[SUB229]], 1
+// CHECK1-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD231:%.*]] = add i32 [[SUB230]], [[TMP128]]
+// CHECK1-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV232:%.*]] = udiv i32 [[ADD231]], [[TMP129]]
+// CHECK1-NEXT: [[MUL233:%.*]] = mul i32 1, [[DIV232]]
+// CHECK1-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB234:%.*]] = sub i32 [[TMP130]], -63
+// CHECK1-NEXT: [[DIV235:%.*]] = udiv i32 [[SUB234]], 64
+// CHECK1-NEXT: [[MUL236:%.*]] = mul i32 [[MUL233]], [[DIV235]]
+// CHECK1-NEXT: [[MUL237:%.*]] = mul i32 [[MUL236]], 64
+// CHECK1-NEXT: [[CONV238:%.*]] = zext i32 [[MUL237]] to i64
+// CHECK1-NEXT: [[MUL239:%.*]] = mul nsw i64 [[DIV228]], [[CONV238]]
+// CHECK1-NEXT: [[SUB240:%.*]] = sub nsw i64 [[TMP119]], [[MUL239]]
+// CHECK1-NEXT: [[TMP131:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP132:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB241:%.*]] = sub i32 [[TMP133]], [[TMP134]]
+// CHECK1-NEXT: [[SUB242:%.*]] = sub i32 [[SUB241]], 1
+// CHECK1-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD243:%.*]] = add i32 [[SUB242]], [[TMP135]]
+// CHECK1-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV244:%.*]] = udiv i32 [[ADD243]], [[TMP136]]
+// CHECK1-NEXT: [[MUL245:%.*]] = mul i32 1, [[DIV244]]
+// CHECK1-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB246:%.*]] = sub i32 [[TMP137]], -63
+// CHECK1-NEXT: [[DIV247:%.*]] = udiv i32 [[SUB246]], 64
+// CHECK1-NEXT: [[MUL248:%.*]] = mul i32 [[MUL245]], [[DIV247]]
+// CHECK1-NEXT: [[MUL249:%.*]] = mul i32 [[MUL248]], 64
+// CHECK1-NEXT: [[CONV250:%.*]] = zext i32 [[MUL249]] to i64
+// CHECK1-NEXT: [[DIV251:%.*]] = sdiv i64 [[TMP132]], [[CONV250]]
+// CHECK1-NEXT: [[TMP138:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP139:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB252:%.*]] = sub i32 [[TMP138]], [[TMP139]]
+// CHECK1-NEXT: [[SUB253:%.*]] = sub i32 [[SUB252]], 1
+// CHECK1-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD254:%.*]] = add i32 [[SUB253]], [[TMP140]]
+// CHECK1-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV255:%.*]] = udiv i32 [[ADD254]], [[TMP141]]
+// CHECK1-NEXT: [[MUL256:%.*]] = mul i32 1, [[DIV255]]
+// CHECK1-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB257:%.*]] = sub i32 [[TMP142]], -63
+// CHECK1-NEXT: [[DIV258:%.*]] = udiv i32 [[SUB257]], 64
+// CHECK1-NEXT: [[MUL259:%.*]] = mul i32 [[MUL256]], [[DIV258]]
+// CHECK1-NEXT: [[MUL260:%.*]] = mul i32 [[MUL259]], 64
+// CHECK1-NEXT: [[CONV261:%.*]] = zext i32 [[MUL260]] to i64
+// CHECK1-NEXT: [[MUL262:%.*]] = mul nsw i64 [[DIV251]], [[CONV261]]
+// CHECK1-NEXT: [[SUB263:%.*]] = sub nsw i64 [[TMP131]], [[MUL262]]
+// CHECK1-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB264:%.*]] = sub i32 [[TMP143]], -63
+// CHECK1-NEXT: [[DIV265:%.*]] = udiv i32 [[SUB264]], 64
+// CHECK1-NEXT: [[MUL266:%.*]] = mul i32 1, [[DIV265]]
+// CHECK1-NEXT: [[MUL267:%.*]] = mul i32 [[MUL266]], 64
+// CHECK1-NEXT: [[CONV268:%.*]] = zext i32 [[MUL267]] to i64
+// CHECK1-NEXT: [[DIV269:%.*]] = sdiv i64 [[SUB263]], [[CONV268]]
// CHECK1-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB255:%.*]] = sub i32 [[TMP144]], -63
-// CHECK1-NEXT: [[DIV256:%.*]] = udiv i32 [[SUB255]], 64
-// CHECK1-NEXT: [[MUL257:%.*]] = mul i32 [[MUL254]], [[DIV256]]
-// CHECK1-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB258:%.*]] = sub i32 [[TMP145]], [[TMP146]]
-// CHECK1-NEXT: [[SUB259:%.*]] = sub i32 [[SUB258]], 1
-// CHECK1-NEXT: [[ADD260:%.*]] = add i32 [[SUB259]], 1
-// CHECK1-NEXT: [[DIV261:%.*]] = udiv i32 [[ADD260]], 1
-// CHECK1-NEXT: [[MUL262:%.*]] = mul i32 [[MUL257]], [[DIV261]]
-// CHECK1-NEXT: [[CONV263:%.*]] = zext i32 [[MUL262]] to i64
-// CHECK1-NEXT: [[DIV264:%.*]] = sdiv i64 [[TMP139]], [[CONV263]]
-// CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB265:%.*]] = sub i32 [[TMP147]], [[TMP148]]
-// CHECK1-NEXT: [[SUB266:%.*]] = sub i32 [[SUB265]], 1
-// CHECK1-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD267:%.*]] = add i32 [[SUB266]], [[TMP149]]
-// CHECK1-NEXT: [[TMP150:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV268:%.*]] = udiv i32 [[ADD267]], [[TMP150]]
-// CHECK1-NEXT: [[MUL269:%.*]] = mul i32 1, [[DIV268]]
-// CHECK1-NEXT: [[TMP151:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB270:%.*]] = sub i32 [[TMP151]], -63
+// CHECK1-NEXT: [[SUB270:%.*]] = sub i32 [[TMP144]], -63
// CHECK1-NEXT: [[DIV271:%.*]] = udiv i32 [[SUB270]], 64
-// CHECK1-NEXT: [[MUL272:%.*]] = mul i32 [[MUL269]], [[DIV271]]
-// CHECK1-NEXT: [[TMP152:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP153:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB273:%.*]] = sub i32 [[TMP152]], [[TMP153]]
-// CHECK1-NEXT: [[SUB274:%.*]] = sub i32 [[SUB273]], 1
-// CHECK1-NEXT: [[ADD275:%.*]] = add i32 [[SUB274]], 1
-// CHECK1-NEXT: [[DIV276:%.*]] = udiv i32 [[ADD275]], 1
-// CHECK1-NEXT: [[MUL277:%.*]] = mul i32 [[MUL272]], [[DIV276]]
-// CHECK1-NEXT: [[CONV278:%.*]] = zext i32 [[MUL277]] to i64
-// CHECK1-NEXT: [[MUL279:%.*]] = mul nsw i64 [[DIV264]], [[CONV278]]
-// CHECK1-NEXT: [[SUB280:%.*]] = sub nsw i64 [[TMP138]], [[MUL279]]
-// CHECK1-NEXT: [[TMP154:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB281:%.*]] = sub i32 [[TMP154]], -63
-// CHECK1-NEXT: [[DIV282:%.*]] = udiv i32 [[SUB281]], 64
-// CHECK1-NEXT: [[MUL283:%.*]] = mul i32 1, [[DIV282]]
-// CHECK1-NEXT: [[TMP155:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP156:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB284:%.*]] = sub i32 [[TMP155]], [[TMP156]]
-// CHECK1-NEXT: [[SUB285:%.*]] = sub i32 [[SUB284]], 1
-// CHECK1-NEXT: [[ADD286:%.*]] = add i32 [[SUB285]], 1
-// CHECK1-NEXT: [[DIV287:%.*]] = udiv i32 [[ADD286]], 1
-// CHECK1-NEXT: [[MUL288:%.*]] = mul i32 [[MUL283]], [[DIV287]]
-// CHECK1-NEXT: [[CONV289:%.*]] = zext i32 [[MUL288]] to i64
-// CHECK1-NEXT: [[DIV290:%.*]] = sdiv i64 [[SUB280]], [[CONV289]]
-// CHECK1-NEXT: [[TMP157:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB291:%.*]] = sub i32 [[TMP157]], -63
-// CHECK1-NEXT: [[DIV292:%.*]] = udiv i32 [[SUB291]], 64
-// CHECK1-NEXT: [[MUL293:%.*]] = mul i32 1, [[DIV292]]
-// CHECK1-NEXT: [[TMP158:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP159:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB294:%.*]] = sub i32 [[TMP158]], [[TMP159]]
-// CHECK1-NEXT: [[SUB295:%.*]] = sub i32 [[SUB294]], 1
-// CHECK1-NEXT: [[ADD296:%.*]] = add i32 [[SUB295]], 1
-// CHECK1-NEXT: [[DIV297:%.*]] = udiv i32 [[ADD296]], 1
-// CHECK1-NEXT: [[MUL298:%.*]] = mul i32 [[MUL293]], [[DIV297]]
-// CHECK1-NEXT: [[CONV299:%.*]] = zext i32 [[MUL298]] to i64
-// CHECK1-NEXT: [[MUL300:%.*]] = mul nsw i64 [[DIV290]], [[CONV299]]
-// CHECK1-NEXT: [[SUB301:%.*]] = sub nsw i64 [[SUB249]], [[MUL300]]
-// CHECK1-NEXT: [[TMP160:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP161:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP162:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP163:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB302:%.*]] = sub i32 [[TMP162]], [[TMP163]]
-// CHECK1-NEXT: [[SUB303:%.*]] = sub i32 [[SUB302]], 1
-// CHECK1-NEXT: [[TMP164:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD304:%.*]] = add i32 [[SUB303]], [[TMP164]]
-// CHECK1-NEXT: [[TMP165:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV305:%.*]] = udiv i32 [[ADD304]], [[TMP165]]
-// CHECK1-NEXT: [[MUL306:%.*]] = mul i32 1, [[DIV305]]
-// CHECK1-NEXT: [[TMP166:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB307:%.*]] = sub i32 [[TMP166]], -63
-// CHECK1-NEXT: [[DIV308:%.*]] = udiv i32 [[SUB307]], 64
-// CHECK1-NEXT: [[MUL309:%.*]] = mul i32 [[MUL306]], [[DIV308]]
-// CHECK1-NEXT: [[TMP167:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP168:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB310:%.*]] = sub i32 [[TMP167]], [[TMP168]]
-// CHECK1-NEXT: [[SUB311:%.*]] = sub i32 [[SUB310]], 1
-// CHECK1-NEXT: [[ADD312:%.*]] = add i32 [[SUB311]], 1
-// CHECK1-NEXT: [[DIV313:%.*]] = udiv i32 [[ADD312]], 1
-// CHECK1-NEXT: [[MUL314:%.*]] = mul i32 [[MUL309]], [[DIV313]]
-// CHECK1-NEXT: [[CONV315:%.*]] = zext i32 [[MUL314]] to i64
-// CHECK1-NEXT: [[DIV316:%.*]] = sdiv i64 [[TMP161]], [[CONV315]]
-// CHECK1-NEXT: [[TMP169:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP170:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB317:%.*]] = sub i32 [[TMP169]], [[TMP170]]
-// CHECK1-NEXT: [[SUB318:%.*]] = sub i32 [[SUB317]], 1
-// CHECK1-NEXT: [[TMP171:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD319:%.*]] = add i32 [[SUB318]], [[TMP171]]
-// CHECK1-NEXT: [[TMP172:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV320:%.*]] = udiv i32 [[ADD319]], [[TMP172]]
-// CHECK1-NEXT: [[MUL321:%.*]] = mul i32 1, [[DIV320]]
-// CHECK1-NEXT: [[TMP173:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB322:%.*]] = sub i32 [[TMP173]], -63
-// CHECK1-NEXT: [[DIV323:%.*]] = udiv i32 [[SUB322]], 64
-// CHECK1-NEXT: [[MUL324:%.*]] = mul i32 [[MUL321]], [[DIV323]]
-// CHECK1-NEXT: [[TMP174:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP175:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB325:%.*]] = sub i32 [[TMP174]], [[TMP175]]
-// CHECK1-NEXT: [[SUB326:%.*]] = sub i32 [[SUB325]], 1
-// CHECK1-NEXT: [[ADD327:%.*]] = add i32 [[SUB326]], 1
-// CHECK1-NEXT: [[DIV328:%.*]] = udiv i32 [[ADD327]], 1
-// CHECK1-NEXT: [[MUL329:%.*]] = mul i32 [[MUL324]], [[DIV328]]
-// CHECK1-NEXT: [[CONV330:%.*]] = zext i32 [[MUL329]] to i64
-// CHECK1-NEXT: [[MUL331:%.*]] = mul nsw i64 [[DIV316]], [[CONV330]]
-// CHECK1-NEXT: [[SUB332:%.*]] = sub nsw i64 [[TMP160]], [[MUL331]]
-// CHECK1-NEXT: [[TMP176:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP177:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP178:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP179:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB333:%.*]] = sub i32 [[TMP178]], [[TMP179]]
-// CHECK1-NEXT: [[SUB334:%.*]] = sub i32 [[SUB333]], 1
-// CHECK1-NEXT: [[TMP180:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD335:%.*]] = add i32 [[SUB334]], [[TMP180]]
-// CHECK1-NEXT: [[TMP181:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV336:%.*]] = udiv i32 [[ADD335]], [[TMP181]]
-// CHECK1-NEXT: [[MUL337:%.*]] = mul i32 1, [[DIV336]]
-// CHECK1-NEXT: [[TMP182:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB338:%.*]] = sub i32 [[TMP182]], -63
-// CHECK1-NEXT: [[DIV339:%.*]] = udiv i32 [[SUB338]], 64
-// CHECK1-NEXT: [[MUL340:%.*]] = mul i32 [[MUL337]], [[DIV339]]
-// CHECK1-NEXT: [[TMP183:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP184:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB341:%.*]] = sub i32 [[TMP183]], [[TMP184]]
-// CHECK1-NEXT: [[SUB342:%.*]] = sub i32 [[SUB341]], 1
-// CHECK1-NEXT: [[ADD343:%.*]] = add i32 [[SUB342]], 1
-// CHECK1-NEXT: [[DIV344:%.*]] = udiv i32 [[ADD343]], 1
-// CHECK1-NEXT: [[MUL345:%.*]] = mul i32 [[MUL340]], [[DIV344]]
-// CHECK1-NEXT: [[CONV346:%.*]] = zext i32 [[MUL345]] to i64
-// CHECK1-NEXT: [[DIV347:%.*]] = sdiv i64 [[TMP177]], [[CONV346]]
-// CHECK1-NEXT: [[TMP185:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK1-NEXT: [[TMP186:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK1-NEXT: [[SUB348:%.*]] = sub i32 [[TMP185]], [[TMP186]]
-// CHECK1-NEXT: [[SUB349:%.*]] = sub i32 [[SUB348]], 1
-// CHECK1-NEXT: [[TMP187:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[ADD350:%.*]] = add i32 [[SUB349]], [[TMP187]]
-// CHECK1-NEXT: [[TMP188:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK1-NEXT: [[DIV351:%.*]] = udiv i32 [[ADD350]], [[TMP188]]
-// CHECK1-NEXT: [[MUL352:%.*]] = mul i32 1, [[DIV351]]
-// CHECK1-NEXT: [[TMP189:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB353:%.*]] = sub i32 [[TMP189]], -63
-// CHECK1-NEXT: [[DIV354:%.*]] = udiv i32 [[SUB353]], 64
-// CHECK1-NEXT: [[MUL355:%.*]] = mul i32 [[MUL352]], [[DIV354]]
-// CHECK1-NEXT: [[TMP190:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP191:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB356:%.*]] = sub i32 [[TMP190]], [[TMP191]]
-// CHECK1-NEXT: [[SUB357:%.*]] = sub i32 [[SUB356]], 1
-// CHECK1-NEXT: [[ADD358:%.*]] = add i32 [[SUB357]], 1
-// CHECK1-NEXT: [[DIV359:%.*]] = udiv i32 [[ADD358]], 1
-// CHECK1-NEXT: [[MUL360:%.*]] = mul i32 [[MUL355]], [[DIV359]]
-// CHECK1-NEXT: [[CONV361:%.*]] = zext i32 [[MUL360]] to i64
-// CHECK1-NEXT: [[MUL362:%.*]] = mul nsw i64 [[DIV347]], [[CONV361]]
-// CHECK1-NEXT: [[SUB363:%.*]] = sub nsw i64 [[TMP176]], [[MUL362]]
-// CHECK1-NEXT: [[TMP192:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB364:%.*]] = sub i32 [[TMP192]], -63
-// CHECK1-NEXT: [[DIV365:%.*]] = udiv i32 [[SUB364]], 64
-// CHECK1-NEXT: [[MUL366:%.*]] = mul i32 1, [[DIV365]]
-// CHECK1-NEXT: [[TMP193:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP194:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB367:%.*]] = sub i32 [[TMP193]], [[TMP194]]
-// CHECK1-NEXT: [[SUB368:%.*]] = sub i32 [[SUB367]], 1
-// CHECK1-NEXT: [[ADD369:%.*]] = add i32 [[SUB368]], 1
-// CHECK1-NEXT: [[DIV370:%.*]] = udiv i32 [[ADD369]], 1
-// CHECK1-NEXT: [[MUL371:%.*]] = mul i32 [[MUL366]], [[DIV370]]
-// CHECK1-NEXT: [[CONV372:%.*]] = zext i32 [[MUL371]] to i64
-// CHECK1-NEXT: [[DIV373:%.*]] = sdiv i64 [[SUB363]], [[CONV372]]
-// CHECK1-NEXT: [[TMP195:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK1-NEXT: [[SUB374:%.*]] = sub i32 [[TMP195]], -63
-// CHECK1-NEXT: [[DIV375:%.*]] = udiv i32 [[SUB374]], 64
-// CHECK1-NEXT: [[MUL376:%.*]] = mul i32 1, [[DIV375]]
-// CHECK1-NEXT: [[TMP196:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP197:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB377:%.*]] = sub i32 [[TMP196]], [[TMP197]]
-// CHECK1-NEXT: [[SUB378:%.*]] = sub i32 [[SUB377]], 1
-// CHECK1-NEXT: [[ADD379:%.*]] = add i32 [[SUB378]], 1
-// CHECK1-NEXT: [[DIV380:%.*]] = udiv i32 [[ADD379]], 1
-// CHECK1-NEXT: [[MUL381:%.*]] = mul i32 [[MUL376]], [[DIV380]]
-// CHECK1-NEXT: [[CONV382:%.*]] = zext i32 [[MUL381]] to i64
-// CHECK1-NEXT: [[MUL383:%.*]] = mul nsw i64 [[DIV373]], [[CONV382]]
-// CHECK1-NEXT: [[SUB384:%.*]] = sub nsw i64 [[SUB332]], [[MUL383]]
-// CHECK1-NEXT: [[TMP198:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP199:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB385:%.*]] = sub i32 [[TMP198]], [[TMP199]]
-// CHECK1-NEXT: [[SUB386:%.*]] = sub i32 [[SUB385]], 1
-// CHECK1-NEXT: [[ADD387:%.*]] = add i32 [[SUB386]], 1
-// CHECK1-NEXT: [[DIV388:%.*]] = udiv i32 [[ADD387]], 1
-// CHECK1-NEXT: [[MUL389:%.*]] = mul i32 1, [[DIV388]]
-// CHECK1-NEXT: [[CONV390:%.*]] = zext i32 [[MUL389]] to i64
-// CHECK1-NEXT: [[DIV391:%.*]] = sdiv i64 [[SUB384]], [[CONV390]]
-// CHECK1-NEXT: [[TMP200:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK1-NEXT: [[TMP201:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK1-NEXT: [[SUB392:%.*]] = sub i32 [[TMP200]], [[TMP201]]
-// CHECK1-NEXT: [[SUB393:%.*]] = sub i32 [[SUB392]], 1
-// CHECK1-NEXT: [[ADD394:%.*]] = add i32 [[SUB393]], 1
-// CHECK1-NEXT: [[DIV395:%.*]] = udiv i32 [[ADD394]], 1
-// CHECK1-NEXT: [[MUL396:%.*]] = mul i32 1, [[DIV395]]
-// CHECK1-NEXT: [[CONV397:%.*]] = zext i32 [[MUL396]] to i64
-// CHECK1-NEXT: [[MUL398:%.*]] = mul nsw i64 [[DIV391]], [[CONV397]]
-// CHECK1-NEXT: [[SUB399:%.*]] = sub nsw i64 [[SUB301]], [[MUL398]]
-// CHECK1-NEXT: [[MUL400:%.*]] = mul nsw i64 [[SUB399]], 1
-// CHECK1-NEXT: [[ADD401:%.*]] = add nsw i64 [[CONV218]], [[MUL400]]
-// CHECK1-NEXT: [[CONV402:%.*]] = trunc i64 [[ADD401]] to i32
-// CHECK1-NEXT: store i32 [[CONV402]], ptr [[DOTTILE_0_IV_K52]], align 4
-// CHECK1-NEXT: [[TMP202:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4
-// CHECK1-NEXT: [[TMP203:%.*]] = load i32, ptr [[DOTTILE_0_IV_K52]], align 4
-// CHECK1-NEXT: [[TMP204:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4
-// CHECK1-NEXT: [[MUL403:%.*]] = mul i32 [[TMP203]], [[TMP204]]
-// CHECK1-NEXT: [[ADD404:%.*]] = add i32 [[TMP202]], [[MUL403]]
-// CHECK1-NEXT: store i32 [[ADD404]], ptr [[K]], align 4
-// CHECK1-NEXT: [[TMP205:%.*]] = load i32, ptr [[I49]], align 4
-// CHECK1-NEXT: [[TMP206:%.*]] = load i32, ptr [[J50]], align 4
-// CHECK1-NEXT: [[TMP207:%.*]] = load i32, ptr [[K]], align 4
-// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP205]], i32 noundef [[TMP206]], i32 noundef [[TMP207]])
-// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK1-NEXT: [[MUL272:%.*]] = mul i32 1, [[DIV271]]
+// CHECK1-NEXT: [[MUL273:%.*]] = mul i32 [[MUL272]], 64
+// CHECK1-NEXT: [[CONV274:%.*]] = zext i32 [[MUL273]] to i64
+// CHECK1-NEXT: [[MUL275:%.*]] = mul nsw i64 [[DIV269]], [[CONV274]]
+// CHECK1-NEXT: [[SUB276:%.*]] = sub nsw i64 [[SUB240]], [[MUL275]]
+// CHECK1-NEXT: [[DIV277:%.*]] = sdiv i64 [[SUB276]], 64
+// CHECK1-NEXT: [[MUL278:%.*]] = mul nsw i64 [[DIV277]], 64
+// CHECK1-NEXT: [[SUB279:%.*]] = sub nsw i64 [[SUB217]], [[MUL278]]
+// CHECK1-NEXT: [[MUL280:%.*]] = mul nsw i64 [[SUB279]], 1
+// CHECK1-NEXT: [[ADD281:%.*]] = add nsw i64 [[CONV158]], [[MUL280]]
+// CHECK1-NEXT: [[CONV282:%.*]] = trunc i64 [[ADD281]] to i32
+// CHECK1-NEXT: store i32 [[CONV282]], ptr [[DOTTILE_0_IV_K42]], align 4
+// CHECK1-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTTILE_0_IV_K42]], align 4
+// CHECK1-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
+// CHECK1-NEXT: [[ADD283:%.*]] = add i32 [[TMP146]], 1
+// CHECK1-NEXT: [[CMP284:%.*]] = icmp ult i32 [[TMP145]], [[ADD283]]
+// CHECK1-NEXT: br i1 [[CMP284]], label [[OMP_BODY_NEXT:%.*]], label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK1: omp.body.next:
+// CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4
+// CHECK1-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTTILE_0_IV_K42]], align 4
+// CHECK1-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4
+// CHECK1-NEXT: [[MUL285:%.*]] = mul i32 [[TMP148]], [[TMP149]]
+// CHECK1-NEXT: [[ADD286:%.*]] = add i32 [[TMP147]], [[MUL285]]
+// CHECK1-NEXT: store i32 [[ADD286]], ptr [[K]], align 4
+// CHECK1-NEXT: [[TMP150:%.*]] = load i32, ptr [[I39]], align 4
+// CHECK1-NEXT: [[TMP151:%.*]] = load i32, ptr [[J40]], align 4
+// CHECK1-NEXT: [[TMP152:%.*]] = load i32, ptr [[K]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP150]], i32 noundef [[TMP151]], i32 noundef [[TMP152]])
+// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP208:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[ADD405:%.*]] = add nsw i64 [[TMP208]], 1
-// CHECK1-NEXT: store i64 [[ADD405]], ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP153:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[ADD287:%.*]] = add nsw i64 [[TMP153]], 1
+// CHECK1-NEXT: store i64 [[ADD287]], ptr [[DOTOMP_IV]], align 8
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
@@ -2225,14 +1878,14 @@ extern "C" void foo10() {
// CHECK1-NEXT: [[V:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store double 4.200000e+01, ptr [[C]], align 8
// CHECK1-NEXT: store ptr [[ARR]], ptr [[__RANGE2]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META12:![0-9]+]], !align [[META13:![0-9]+]]
// CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP0]], i64 0, i64 0
// CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 128
// CHECK1-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META12]], !align [[META13]]
// CHECK1-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP1]], i64 0, i64 0
// CHECK1-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META12]], !align [[META13]]
// CHECK1-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP2]], i64 0, i64 0
// CHECK1-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 8
@@ -2277,7 +1930,7 @@ extern "C" void foo10() {
// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[__BEGIN2]], align 8
// CHECK1-NEXT: store ptr [[TMP12]], ptr [[V]], align 8
// CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[C]], align 8
-// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[V]], align 8
+// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[V]], align 8, !nonnull [[META12]], !align [[META13]]
// CHECK1-NEXT: [[TMP15:%.*]] = load double, ptr [[TMP14]], align 8
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4
// CHECK1-NEXT: call void (...) @body(double noundef [[TMP13]], double noundef [[TMP15]], i32 noundef [[TMP16]])
@@ -2286,14 +1939,14 @@ extern "C" void foo10() {
// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8
// CHECK1-NEXT: [[INC:%.*]] = add nsw i64 [[TMP17]], 1
// CHECK1-NEXT: store i64 [[INC]], ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8
-// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP13:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP14:![0-9]+]]
// CHECK1: for.end:
// CHECK1-NEXT: br label [[FOR_INC13:%.*]]
// CHECK1: for.inc13:
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 4
// CHECK1-NEXT: [[INC14:%.*]] = add nsw i32 [[TMP18]], 1
// CHECK1-NEXT: store i32 [[INC14]], ptr [[DOTPERMUTED_0_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
// CHECK1: for.end15:
// CHECK1-NEXT: ret void
//
@@ -2342,14 +1995,14 @@ extern "C" void foo10() {
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
// CHECK1-NEXT: store double 4.200000e+01, ptr [[C]], align 8
// CHECK1-NEXT: store ptr [[A]], ptr [[__RANGE3]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE3]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE3]], align 8, !nonnull [[META12]], !align [[META13]]
// CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP1]], i64 0, i64 0
// CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 128
// CHECK1-NEXT: store ptr [[ADD_PTR]], ptr [[__END3]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE3]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE3]], align 8, !nonnull [[META12]], !align [[META13]]
// CHECK1-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP2]], i64 0, i64 0
// CHECK1-NEXT: store ptr [[ARRAYDECAY4]], ptr [[__BEGIN3]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__RANGE3]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__RANGE3]], align 8, !nonnull [[META12]], !align [[META13]]
// CHECK1-NEXT: [[ARRAYDECAY5:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP3]], i64 0, i64 0
// CHECK1-NEXT: store ptr [[ARRAYDECAY5]], ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__END3]], align 8
@@ -2367,14 +2020,14 @@ extern "C" void foo10() {
// CHECK1-NEXT: store i64 [[SUB8]], ptr [[DOTCAPTURE_EXPR_7]], align 8
// CHECK1-NEXT: store double 4.200000e+01, ptr [[D]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[__RANGE4]], align 8
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[__RANGE4]], align 8
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[__RANGE4]], align 8, !nonnull [[META12]], !align [[META13]]
// CHECK1-NEXT: [[ARRAYDECAY9:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP7]], i64 0, i64 0
// CHECK1-NEXT: [[ADD_PTR10:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY9]], i64 16
// CHECK1-NEXT: store ptr [[ADD_PTR10]], ptr [[__END4]], align 8
-// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__RANGE4]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__RANGE4]], align 8, !nonnull [[META12]], !align [[META13]]
// CHECK1-NEXT: [[ARRAYDECAY11:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP8]], i64 0, i64 0
// CHECK1-NEXT: store ptr [[ARRAYDECAY11]], ptr [[__BEGIN4]], align 8
-// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__RANGE4]], align 8
+// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__RANGE4]], align 8, !nonnull [[META12]], !align [[META13]]
// CHECK1-NEXT: [[ARRAYDECAY13:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP9]], i64 0, i64 0
// CHECK1-NEXT: store ptr [[ARRAYDECAY13]], ptr [[DOTCAPTURE_EXPR_12]], align 8
// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[__END4]], align 8
@@ -2701,7 +2354,7 @@ extern "C" void foo10() {
// CHECK1-NEXT: [[TMP87:%.*]] = load double, ptr [[C]], align 8
// CHECK1-NEXT: [[TMP88:%.*]] = load double, ptr [[AA]], align 8
// CHECK1-NEXT: [[TMP89:%.*]] = load double, ptr [[D]], align 8
-// CHECK1-NEXT: [[TMP90:%.*]] = load ptr, ptr [[BB]], align 8
+// CHECK1-NEXT: [[TMP90:%.*]] = load ptr, ptr [[BB]], align 8, !nonnull [[META12]], !align [[META13]]
// CHECK1-NEXT: [[TMP91:%.*]] = load double, ptr [[TMP90]], align 8
// CHECK1-NEXT: [[TMP92:%.*]] = load i32, ptr [[J40]], align 4
// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP86]], double noundef [[TMP87]], double noundef [[TMP88]], double noundef [[TMP89]], double noundef [[TMP91]], i32 noundef [[TMP92]])
@@ -2756,7 +2409,7 @@ extern "C" void foo10() {
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
// CHECK2: for.end:
// CHECK2-NEXT: ret void
//
@@ -2805,14 +2458,14 @@ extern "C" void foo10() {
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK2-NEXT: store double 4.200000e+01, ptr [[C]], align 8
// CHECK2-NEXT: store ptr [[A]], ptr [[__RANGE3]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE3]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE3]], align 8, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]]
// CHECK2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP1]], i64 0, i64 0
// CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 128
// CHECK2-NEXT: store ptr [[ADD_PTR]], ptr [[__END3]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE3]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE3]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP2]], i64 0, i64 0
// CHECK2-NEXT: store ptr [[ARRAYDECAY4]], ptr [[__BEGIN3]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__RANGE3]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__RANGE3]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: [[ARRAYDECAY5:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP3]], i64 0, i64 0
// CHECK2-NEXT: store ptr [[ARRAYDECAY5]], ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__END3]], align 8
@@ -2830,14 +2483,14 @@ extern "C" void foo10() {
// CHECK2-NEXT: store i64 [[SUB8]], ptr [[DOTCAPTURE_EXPR_7]], align 8
// CHECK2-NEXT: store double 4.200000e+01, ptr [[D]], align 8
// CHECK2-NEXT: store ptr [[B]], ptr [[__RANGE4]], align 8
-// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[__RANGE4]], align 8
+// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[__RANGE4]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: [[ARRAYDECAY9:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP7]], i64 0, i64 0
// CHECK2-NEXT: [[ADD_PTR10:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY9]], i64 16
// CHECK2-NEXT: store ptr [[ADD_PTR10]], ptr [[__END4]], align 8
-// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__RANGE4]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__RANGE4]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: [[ARRAYDECAY11:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP8]], i64 0, i64 0
// CHECK2-NEXT: store ptr [[ARRAYDECAY11]], ptr [[__BEGIN4]], align 8
-// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__RANGE4]], align 8
+// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__RANGE4]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: [[ARRAYDECAY13:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP9]], i64 0, i64 0
// CHECK2-NEXT: store ptr [[ARRAYDECAY13]], ptr [[DOTCAPTURE_EXPR_12]], align 8
// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[__END4]], align 8
@@ -3164,7 +2817,7 @@ extern "C" void foo10() {
// CHECK2-NEXT: [[TMP87:%.*]] = load double, ptr [[C]], align 8
// CHECK2-NEXT: [[TMP88:%.*]] = load double, ptr [[AA]], align 8
// CHECK2-NEXT: [[TMP89:%.*]] = load double, ptr [[D]], align 8
-// CHECK2-NEXT: [[TMP90:%.*]] = load ptr, ptr [[BB]], align 8
+// CHECK2-NEXT: [[TMP90:%.*]] = load ptr, ptr [[BB]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: [[TMP91:%.*]] = load double, ptr [[TMP90]], align 8
// CHECK2-NEXT: [[TMP92:%.*]] = load i32, ptr [[J40]], align 4
// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP86]], double noundef [[TMP87]], double noundef [[TMP88]], double noundef [[TMP89]], double noundef [[TMP91]], i32 noundef [[TMP92]])
@@ -3287,14 +2940,14 @@ extern "C" void foo10() {
// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
// CHECK2-NEXT: [[INC:%.*]] = add i32 [[TMP28]], 1
// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND16]], !llvm.loop [[LOOP5:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND16]], !llvm.loop [[LOOP6:![0-9]+]]
// CHECK2: for.end:
// CHECK2-NEXT: br label [[FOR_INC22:%.*]]
// CHECK2: for.inc22:
// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
// CHECK2-NEXT: [[INC23:%.*]] = add i32 [[TMP29]], 1
// CHECK2-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 4
-// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
// CHECK2: for.end24:
// CHECK2-NEXT: ret void
//
@@ -3367,7 +3020,7 @@ extern "C" void foo10() {
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1
// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
// CHECK2: for.end:
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
@@ -3464,7 +3117,7 @@ extern "C" void foo10() {
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1
// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
// CHECK2: for.end:
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
@@ -3779,28 +3432,28 @@ extern "C" void foo10() {
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 4
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1
// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_3_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP9:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP10:![0-9]+]]
// CHECK2: for.end:
// CHECK2-NEXT: br label [[FOR_INC16:%.*]]
// CHECK2: for.inc16:
// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 4
// CHECK2-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1
// CHECK2-NEXT: store i32 [[INC17]], ptr [[DOTPERMUTED_2_IV_L]], align 4
-// CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP10:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP11:![0-9]+]]
// CHECK2: for.end18:
// CHECK2-NEXT: br label [[FOR_INC19:%.*]]
// CHECK2: for.inc19:
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 4
// CHECK2-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP14]], 1
// CHECK2-NEXT: store i32 [[INC20]], ptr [[DOTPERMUTED_1_IV_K]], align 4
-// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP11:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP12:![0-9]+]]
// CHECK2: for.end21:
// CHECK2-NEXT: br label [[FOR_INC22:%.*]]
// CHECK2: for.inc22:
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
// CHECK2-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1
// CHECK2-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 4
-// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
// CHECK2: for.end24:
// CHECK2-NEXT: ret void
//
@@ -3822,14 +3475,14 @@ extern "C" void foo10() {
// CHECK2-NEXT: [[V:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: store double 4.200000e+01, ptr [[C]], align 8
// CHECK2-NEXT: store ptr [[ARR]], ptr [[__RANGE2]], align 8
-// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP0]], i64 0, i64 0
// CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 128
// CHECK2-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP1]], i64 0, i64 0
// CHECK2-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP2]], i64 0, i64 0
// CHECK2-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 8
@@ -3874,7 +3527,7 @@ extern "C" void foo10() {
// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[__BEGIN2]], align 8
// CHECK2-NEXT: store ptr [[TMP12]], ptr [[V]], align 8
// CHECK2-NEXT: [[TMP13:%.*]] = load double, ptr [[C]], align 8
-// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[V]], align 8
+// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[V]], align 8, !nonnull [[META4]], !align [[META5]]
// CHECK2-NEXT: [[TMP15:%.*]] = load double, ptr [[TMP14]], align 8
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4
// CHECK2-NEXT: call void (...) @body(double noundef [[TMP13]], double noundef [[TMP15]], i32 noundef [[TMP16]])
@@ -3883,14 +3536,14 @@ extern "C" void foo10() {
// CHECK2-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8
// CHECK2-NEXT: [[INC:%.*]] = add nsw i64 [[TMP17]], 1
// CHECK2-NEXT: store i64 [[INC]], ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8
-// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP13:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP14:![0-9]+]]
// CHECK2: for.end:
// CHECK2-NEXT: br label [[FOR_INC13:%.*]]
// CHECK2: for.inc13:
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 4
// CHECK2-NEXT: [[INC14:%.*]] = add nsw i32 [[TMP18]], 1
// CHECK2-NEXT: store i32 [[INC14]], ptr [[DOTPERMUTED_0_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
// CHECK2: for.end15:
// CHECK2-NEXT: ret void
//
@@ -3928,19 +3581,20 @@ extern "C" void foo10() {
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTFLOOR_0_IV_K:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[_TMP35:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[I49:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[J50:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTFLOOR_0_IV_K51:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTTILE_0_IV_K52:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[I39:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[J40:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTFLOOR_0_IV_K41:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTTILE_0_IV_K42:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
// CHECK2-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4
// CHECK2-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4
@@ -3980,628 +3634,453 @@ extern "C" void foo10() {
// CHECK2-NEXT: store i32 [[ADD15]], ptr [[DOTCAPTURE_EXPR_14]], align 4
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[_TMP2]], align 4
// CHECK2-NEXT: store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
-// CHECK2-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 1
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[_TMP2]], align 4
-// CHECK2-NEXT: [[ADD19:%.*]] = add i32 [[TMP18]], 32
-// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD18]], [[ADD19]]
-// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK2: cond.true:
-// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
-// CHECK2-NEXT: [[ADD20:%.*]] = add i32 [[TMP19]], 1
-// CHECK2-NEXT: br label [[COND_END:%.*]]
-// CHECK2: cond.false:
-// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[_TMP2]], align 4
-// CHECK2-NEXT: [[ADD21:%.*]] = add i32 [[TMP20]], 32
-// CHECK2-NEXT: br label [[COND_END]]
-// CHECK2: cond.end:
-// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[ADD20]], [[COND_TRUE]] ], [ [[ADD21]], [[COND_FALSE]] ]
-// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
-// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[SUB23:%.*]] = sub i32 [[TMP21]], [[TMP22]]
-// CHECK2-NEXT: [[SUB24:%.*]] = sub i32 [[SUB23]], 1
-// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
-// CHECK2-NEXT: [[ADD25:%.*]] = add i32 [[SUB24]], [[TMP23]]
-// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
-// CHECK2-NEXT: [[DIV26:%.*]] = udiv i32 [[ADD25]], [[TMP24]]
-// CHECK2-NEXT: [[CONV:%.*]] = zext i32 [[DIV26]] to i64
-// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB27:%.*]] = sub i32 [[TMP25]], [[TMP26]]
-// CHECK2-NEXT: [[SUB28:%.*]] = sub i32 [[SUB27]], 1
-// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD29:%.*]] = add i32 [[SUB28]], [[TMP27]]
-// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV30:%.*]] = udiv i32 [[ADD29]], [[TMP28]]
+// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[_TMP2]], align 4
+// CHECK2-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 32
+// CHECK2-NEXT: store i32 [[ADD18]], ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
+// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[SUB20:%.*]] = sub i32 [[TMP18]], [[TMP19]]
+// CHECK2-NEXT: [[SUB21:%.*]] = sub i32 [[SUB20]], 1
+// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK2-NEXT: [[ADD22:%.*]] = add i32 [[SUB21]], [[TMP20]]
+// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK2-NEXT: [[DIV23:%.*]] = udiv i32 [[ADD22]], [[TMP21]]
+// CHECK2-NEXT: [[CONV:%.*]] = zext i32 [[DIV23]] to i64
+// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB24:%.*]] = sub i32 [[TMP22]], [[TMP23]]
+// CHECK2-NEXT: [[SUB25:%.*]] = sub i32 [[SUB24]], 1
+// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD26:%.*]] = add i32 [[SUB25]], [[TMP24]]
+// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV27:%.*]] = udiv i32 [[ADD26]], [[TMP25]]
+// CHECK2-NEXT: [[CONV28:%.*]] = zext i32 [[DIV27]] to i64
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV28]]
+// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB29:%.*]] = sub i32 [[TMP26]], -31
+// CHECK2-NEXT: [[DIV30:%.*]] = udiv i32 [[SUB29]], 32
// CHECK2-NEXT: [[CONV31:%.*]] = zext i32 [[DIV30]] to i64
-// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV31]]
-// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB32:%.*]] = sub i32 [[TMP29]], -31
-// CHECK2-NEXT: [[DIV33:%.*]] = udiv i32 [[SUB32]], 32
-// CHECK2-NEXT: [[CONV34:%.*]] = zext i32 [[DIV33]] to i64
-// CHECK2-NEXT: [[MUL35:%.*]] = mul nsw i64 [[MUL]], [[CONV34]]
-// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB36:%.*]] = sub i32 [[TMP30]], [[TMP31]]
-// CHECK2-NEXT: [[SUB37:%.*]] = sub i32 [[SUB36]], 1
-// CHECK2-NEXT: [[ADD38:%.*]] = add i32 [[SUB37]], 1
-// CHECK2-NEXT: [[DIV39:%.*]] = udiv i32 [[ADD38]], 1
-// CHECK2-NEXT: [[CONV40:%.*]] = zext i32 [[DIV39]] to i64
-// CHECK2-NEXT: [[MUL41:%.*]] = mul nsw i64 [[MUL35]], [[CONV40]]
-// CHECK2-NEXT: [[SUB42:%.*]] = sub nsw i64 [[MUL41]], 1
-// CHECK2-NEXT: store i64 [[SUB42]], ptr [[DOTCAPTURE_EXPR_22]], align 8
-// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: store i32 [[TMP32]], ptr [[I]], align 4
-// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: store i32 [[TMP33]], ptr [[J]], align 4
+// CHECK2-NEXT: [[MUL32:%.*]] = mul nsw i64 [[MUL]], [[CONV31]]
+// CHECK2-NEXT: [[MUL33:%.*]] = mul nsw i64 [[MUL32]], 32
+// CHECK2-NEXT: [[SUB34:%.*]] = sub nsw i64 [[MUL33]], 1
+// CHECK2-NEXT: store i64 [[SUB34]], ptr [[DOTCAPTURE_EXPR_19]], align 8
+// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: store i32 [[TMP27]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: store i32 [[TMP28]], ptr [[J]], align 4
// CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_K]], align 4
-// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: store i32 [[TMP34]], ptr [[DOTTILE_0_IV_K]], align 4
-// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
-// CHECK2-NEXT: [[CMP43:%.*]] = icmp slt i32 [[TMP35]], [[TMP36]]
-// CHECK2-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
+// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_K]], align 4
+// CHECK2-NEXT: store i32 [[TMP29]], ptr [[DOTTILE_0_IV_K]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[_TMP35]], align 4
+// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
+// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP30]], [[TMP31]]
+// CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK2: land.lhs.true:
-// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]]
-// CHECK2-NEXT: br i1 [[CMP44]], label [[LAND_LHS_TRUE45:%.*]], label [[OMP_PRECOND_END]]
-// CHECK2: land.lhs.true45:
-// CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[CMP46:%.*]] = icmp ult i32 0, [[TMP39]]
-// CHECK2-NEXT: br i1 [[CMP46]], label [[LAND_LHS_TRUE47:%.*]], label [[OMP_PRECOND_END]]
-// CHECK2: land.lhs.true47:
-// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[CMP48:%.*]] = icmp ult i32 [[TMP40]], [[TMP41]]
-// CHECK2-NEXT: br i1 [[CMP48]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
+// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[CMP36:%.*]] = icmp slt i32 [[TMP32]], [[TMP33]]
+// CHECK2-NEXT: br i1 [[CMP36]], label [[LAND_LHS_TRUE37:%.*]], label [[OMP_PRECOND_END]]
+// CHECK2: land.lhs.true37:
+// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[CMP38:%.*]] = icmp ult i32 0, [[TMP34]]
+// CHECK2-NEXT: br i1 [[CMP38]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
// CHECK2: omp.precond.then:
// CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
-// CHECK2-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
-// CHECK2-NEXT: store i64 [[TMP42]], ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: [[TMP35:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_19]], align 8
+// CHECK2-NEXT: store i64 [[TMP35]], ptr [[DOTOMP_UB]], align 8
// CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
-// CHECK2-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK2-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
-// CHECK2-NEXT: [[CMP53:%.*]] = icmp sgt i64 [[TMP43]], [[TMP44]]
-// CHECK2-NEXT: br i1 [[CMP53]], label [[COND_TRUE54:%.*]], label [[COND_FALSE55:%.*]]
-// CHECK2: cond.true54:
-// CHECK2-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
-// CHECK2-NEXT: br label [[COND_END56:%.*]]
-// CHECK2: cond.false55:
-// CHECK2-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK2-NEXT: br label [[COND_END56]]
-// CHECK2: cond.end56:
-// CHECK2-NEXT: [[COND57:%.*]] = phi i64 [ [[TMP45]], [[COND_TRUE54]] ], [ [[TMP46]], [[COND_FALSE55]] ]
-// CHECK2-NEXT: store i64 [[COND57]], ptr [[DOTOMP_UB]], align 8
-// CHECK2-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
-// CHECK2-NEXT: store i64 [[TMP47]], ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP36:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_19]], align 8
+// CHECK2-NEXT: [[CMP43:%.*]] = icmp sgt i64 [[TMP36]], [[TMP37]]
+// CHECK2-NEXT: br i1 [[CMP43]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK2: cond.true:
+// CHECK2-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_19]], align 8
+// CHECK2-NEXT: br label [[COND_END:%.*]]
+// CHECK2: cond.false:
+// CHECK2-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: br label [[COND_END]]
+// CHECK2: cond.end:
+// CHECK2-NEXT: [[COND:%.*]] = phi i64 [ [[TMP38]], [[COND_TRUE]] ], [ [[TMP39]], [[COND_FALSE]] ]
+// CHECK2-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: [[TMP40:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
+// CHECK2-NEXT: store i64 [[TMP40]], ptr [[DOTOMP_IV]], align 8
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK2-NEXT: [[CMP58:%.*]] = icmp sle i64 [[TMP48]], [[TMP49]]
-// CHECK2-NEXT: br i1 [[CMP58]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK2-NEXT: [[TMP41:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: [[CMP44:%.*]] = icmp sle i64 [[TMP41]], [[TMP42]]
+// CHECK2-NEXT: br i1 [[CMP44]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[CONV59:%.*]] = sext i32 [[TMP50]] to i64
-// CHECK2-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB60:%.*]] = sub i32 [[TMP52]], [[TMP53]]
-// CHECK2-NEXT: [[SUB61:%.*]] = sub i32 [[SUB60]], 1
-// CHECK2-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD62:%.*]] = add i32 [[SUB61]], [[TMP54]]
-// CHECK2-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV63:%.*]] = udiv i32 [[ADD62]], [[TMP55]]
-// CHECK2-NEXT: [[MUL64:%.*]] = mul i32 1, [[DIV63]]
-// CHECK2-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB65:%.*]] = sub i32 [[TMP56]], -31
-// CHECK2-NEXT: [[DIV66:%.*]] = udiv i32 [[SUB65]], 32
-// CHECK2-NEXT: [[MUL67:%.*]] = mul i32 [[MUL64]], [[DIV66]]
-// CHECK2-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB68:%.*]] = sub i32 [[TMP57]], [[TMP58]]
-// CHECK2-NEXT: [[SUB69:%.*]] = sub i32 [[SUB68]], 1
-// CHECK2-NEXT: [[ADD70:%.*]] = add i32 [[SUB69]], 1
-// CHECK2-NEXT: [[DIV71:%.*]] = udiv i32 [[ADD70]], 1
-// CHECK2-NEXT: [[MUL72:%.*]] = mul i32 [[MUL67]], [[DIV71]]
-// CHECK2-NEXT: [[CONV73:%.*]] = zext i32 [[MUL72]] to i64
-// CHECK2-NEXT: [[DIV74:%.*]] = sdiv i64 [[TMP51]], [[CONV73]]
-// CHECK2-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
-// CHECK2-NEXT: [[CONV75:%.*]] = sext i32 [[TMP59]] to i64
-// CHECK2-NEXT: [[MUL76:%.*]] = mul nsw i64 [[DIV74]], [[CONV75]]
-// CHECK2-NEXT: [[ADD77:%.*]] = add nsw i64 [[CONV59]], [[MUL76]]
-// CHECK2-NEXT: [[CONV78:%.*]] = trunc i64 [[ADD77]] to i32
-// CHECK2-NEXT: store i32 [[CONV78]], ptr [[I49]], align 4
+// CHECK2-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[CONV45:%.*]] = sext i32 [[TMP43]] to i64
+// CHECK2-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB46:%.*]] = sub i32 [[TMP45]], [[TMP46]]
+// CHECK2-NEXT: [[SUB47:%.*]] = sub i32 [[SUB46]], 1
+// CHECK2-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD48:%.*]] = add i32 [[SUB47]], [[TMP47]]
+// CHECK2-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV49:%.*]] = udiv i32 [[ADD48]], [[TMP48]]
+// CHECK2-NEXT: [[MUL50:%.*]] = mul i32 1, [[DIV49]]
+// CHECK2-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB51:%.*]] = sub i32 [[TMP49]], -31
+// CHECK2-NEXT: [[DIV52:%.*]] = udiv i32 [[SUB51]], 32
+// CHECK2-NEXT: [[MUL53:%.*]] = mul i32 [[MUL50]], [[DIV52]]
+// CHECK2-NEXT: [[MUL54:%.*]] = mul i32 [[MUL53]], 32
+// CHECK2-NEXT: [[CONV55:%.*]] = zext i32 [[MUL54]] to i64
+// CHECK2-NEXT: [[DIV56:%.*]] = sdiv i64 [[TMP44]], [[CONV55]]
+// CHECK2-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK2-NEXT: [[CONV57:%.*]] = sext i32 [[TMP50]] to i64
+// CHECK2-NEXT: [[MUL58:%.*]] = mul nsw i64 [[DIV56]], [[CONV57]]
+// CHECK2-NEXT: [[ADD59:%.*]] = add nsw i64 [[CONV45]], [[MUL58]]
+// CHECK2-NEXT: [[CONV60:%.*]] = trunc i64 [[ADD59]] to i32
+// CHECK2-NEXT: store i32 [[CONV60]], ptr [[I39]], align 4
+// CHECK2-NEXT: [[TMP51:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[CONV61:%.*]] = sext i32 [[TMP51]] to i64
+// CHECK2-NEXT: [[TMP52:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP53:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB62:%.*]] = sub i32 [[TMP54]], [[TMP55]]
+// CHECK2-NEXT: [[SUB63:%.*]] = sub i32 [[SUB62]], 1
+// CHECK2-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD64:%.*]] = add i32 [[SUB63]], [[TMP56]]
+// CHECK2-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV65:%.*]] = udiv i32 [[ADD64]], [[TMP57]]
+// CHECK2-NEXT: [[MUL66:%.*]] = mul i32 1, [[DIV65]]
+// CHECK2-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB67:%.*]] = sub i32 [[TMP58]], -31
+// CHECK2-NEXT: [[DIV68:%.*]] = udiv i32 [[SUB67]], 32
+// CHECK2-NEXT: [[MUL69:%.*]] = mul i32 [[MUL66]], [[DIV68]]
+// CHECK2-NEXT: [[MUL70:%.*]] = mul i32 [[MUL69]], 32
+// CHECK2-NEXT: [[CONV71:%.*]] = zext i32 [[MUL70]] to i64
+// CHECK2-NEXT: [[DIV72:%.*]] = sdiv i64 [[TMP53]], [[CONV71]]
+// CHECK2-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
// CHECK2-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[CONV79:%.*]] = sext i32 [[TMP60]] to i64
-// CHECK2-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB80:%.*]] = sub i32 [[TMP63]], [[TMP64]]
-// CHECK2-NEXT: [[SUB81:%.*]] = sub i32 [[SUB80]], 1
-// CHECK2-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD82:%.*]] = add i32 [[SUB81]], [[TMP65]]
-// CHECK2-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV83:%.*]] = udiv i32 [[ADD82]], [[TMP66]]
-// CHECK2-NEXT: [[MUL84:%.*]] = mul i32 1, [[DIV83]]
-// CHECK2-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB85:%.*]] = sub i32 [[TMP67]], -31
+// CHECK2-NEXT: [[SUB73:%.*]] = sub i32 [[TMP59]], [[TMP60]]
+// CHECK2-NEXT: [[SUB74:%.*]] = sub i32 [[SUB73]], 1
+// CHECK2-NEXT: [[TMP61:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD75:%.*]] = add i32 [[SUB74]], [[TMP61]]
+// CHECK2-NEXT: [[TMP62:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV76:%.*]] = udiv i32 [[ADD75]], [[TMP62]]
+// CHECK2-NEXT: [[MUL77:%.*]] = mul i32 1, [[DIV76]]
+// CHECK2-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB78:%.*]] = sub i32 [[TMP63]], -31
+// CHECK2-NEXT: [[DIV79:%.*]] = udiv i32 [[SUB78]], 32
+// CHECK2-NEXT: [[MUL80:%.*]] = mul i32 [[MUL77]], [[DIV79]]
+// CHECK2-NEXT: [[MUL81:%.*]] = mul i32 [[MUL80]], 32
+// CHECK2-NEXT: [[CONV82:%.*]] = zext i32 [[MUL81]] to i64
+// CHECK2-NEXT: [[MUL83:%.*]] = mul nsw i64 [[DIV72]], [[CONV82]]
+// CHECK2-NEXT: [[SUB84:%.*]] = sub nsw i64 [[TMP52]], [[MUL83]]
+// CHECK2-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB85:%.*]] = sub i32 [[TMP64]], -31
// CHECK2-NEXT: [[DIV86:%.*]] = udiv i32 [[SUB85]], 32
-// CHECK2-NEXT: [[MUL87:%.*]] = mul i32 [[MUL84]], [[DIV86]]
-// CHECK2-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB88:%.*]] = sub i32 [[TMP68]], [[TMP69]]
-// CHECK2-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 1
-// CHECK2-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 1
-// CHECK2-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 1
-// CHECK2-NEXT: [[MUL92:%.*]] = mul i32 [[MUL87]], [[DIV91]]
-// CHECK2-NEXT: [[CONV93:%.*]] = zext i32 [[MUL92]] to i64
-// CHECK2-NEXT: [[DIV94:%.*]] = sdiv i64 [[TMP62]], [[CONV93]]
-// CHECK2-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB95:%.*]] = sub i32 [[TMP70]], [[TMP71]]
+// CHECK2-NEXT: [[MUL87:%.*]] = mul i32 1, [[DIV86]]
+// CHECK2-NEXT: [[MUL88:%.*]] = mul i32 [[MUL87]], 32
+// CHECK2-NEXT: [[CONV89:%.*]] = zext i32 [[MUL88]] to i64
+// CHECK2-NEXT: [[DIV90:%.*]] = sdiv i64 [[SUB84]], [[CONV89]]
+// CHECK2-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[CONV91:%.*]] = sext i32 [[TMP65]] to i64
+// CHECK2-NEXT: [[MUL92:%.*]] = mul nsw i64 [[DIV90]], [[CONV91]]
+// CHECK2-NEXT: [[ADD93:%.*]] = add nsw i64 [[CONV61]], [[MUL92]]
+// CHECK2-NEXT: [[CONV94:%.*]] = trunc i64 [[ADD93]] to i32
+// CHECK2-NEXT: store i32 [[CONV94]], ptr [[J40]], align 4
+// CHECK2-NEXT: [[TMP66:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP67:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB95:%.*]] = sub i32 [[TMP68]], [[TMP69]]
// CHECK2-NEXT: [[SUB96:%.*]] = sub i32 [[SUB95]], 1
-// CHECK2-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP72]]
-// CHECK2-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP73]]
+// CHECK2-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP70]]
+// CHECK2-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP71]]
// CHECK2-NEXT: [[MUL99:%.*]] = mul i32 1, [[DIV98]]
-// CHECK2-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB100:%.*]] = sub i32 [[TMP74]], -31
+// CHECK2-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB100:%.*]] = sub i32 [[TMP72]], -31
// CHECK2-NEXT: [[DIV101:%.*]] = udiv i32 [[SUB100]], 32
// CHECK2-NEXT: [[MUL102:%.*]] = mul i32 [[MUL99]], [[DIV101]]
-// CHECK2-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB103:%.*]] = sub i32 [[TMP75]], [[TMP76]]
-// CHECK2-NEXT: [[SUB104:%.*]] = sub i32 [[SUB103]], 1
-// CHECK2-NEXT: [[ADD105:%.*]] = add i32 [[SUB104]], 1
-// CHECK2-NEXT: [[DIV106:%.*]] = udiv i32 [[ADD105]], 1
-// CHECK2-NEXT: [[MUL107:%.*]] = mul i32 [[MUL102]], [[DIV106]]
-// CHECK2-NEXT: [[CONV108:%.*]] = zext i32 [[MUL107]] to i64
-// CHECK2-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV94]], [[CONV108]]
-// CHECK2-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP61]], [[MUL109]]
+// CHECK2-NEXT: [[MUL103:%.*]] = mul i32 [[MUL102]], 32
+// CHECK2-NEXT: [[CONV104:%.*]] = zext i32 [[MUL103]] to i64
+// CHECK2-NEXT: [[DIV105:%.*]] = sdiv i64 [[TMP67]], [[CONV104]]
+// CHECK2-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB106:%.*]] = sub i32 [[TMP73]], [[TMP74]]
+// CHECK2-NEXT: [[SUB107:%.*]] = sub i32 [[SUB106]], 1
+// CHECK2-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD108:%.*]] = add i32 [[SUB107]], [[TMP75]]
+// CHECK2-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV109:%.*]] = udiv i32 [[ADD108]], [[TMP76]]
+// CHECK2-NEXT: [[MUL110:%.*]] = mul i32 1, [[DIV109]]
// CHECK2-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
// CHECK2-NEXT: [[SUB111:%.*]] = sub i32 [[TMP77]], -31
// CHECK2-NEXT: [[DIV112:%.*]] = udiv i32 [[SUB111]], 32
-// CHECK2-NEXT: [[MUL113:%.*]] = mul i32 1, [[DIV112]]
-// CHECK2-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB114:%.*]] = sub i32 [[TMP78]], [[TMP79]]
-// CHECK2-NEXT: [[SUB115:%.*]] = sub i32 [[SUB114]], 1
-// CHECK2-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], 1
-// CHECK2-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], 1
-// CHECK2-NEXT: [[MUL118:%.*]] = mul i32 [[MUL113]], [[DIV117]]
-// CHECK2-NEXT: [[CONV119:%.*]] = zext i32 [[MUL118]] to i64
-// CHECK2-NEXT: [[DIV120:%.*]] = sdiv i64 [[SUB110]], [[CONV119]]
-// CHECK2-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[CONV121:%.*]] = sext i32 [[TMP80]] to i64
-// CHECK2-NEXT: [[MUL122:%.*]] = mul nsw i64 [[DIV120]], [[CONV121]]
-// CHECK2-NEXT: [[ADD123:%.*]] = add nsw i64 [[CONV79]], [[MUL122]]
-// CHECK2-NEXT: [[CONV124:%.*]] = trunc i64 [[ADD123]] to i32
-// CHECK2-NEXT: store i32 [[CONV124]], ptr [[J50]], align 4
-// CHECK2-NEXT: [[TMP81:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP82:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB125:%.*]] = sub i32 [[TMP83]], [[TMP84]]
-// CHECK2-NEXT: [[SUB126:%.*]] = sub i32 [[SUB125]], 1
-// CHECK2-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP85]]
-// CHECK2-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP86]]
-// CHECK2-NEXT: [[MUL129:%.*]] = mul i32 1, [[DIV128]]
-// CHECK2-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB130:%.*]] = sub i32 [[TMP87]], -31
-// CHECK2-NEXT: [[DIV131:%.*]] = udiv i32 [[SUB130]], 32
-// CHECK2-NEXT: [[MUL132:%.*]] = mul i32 [[MUL129]], [[DIV131]]
-// CHECK2-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB133:%.*]] = sub i32 [[TMP88]], [[TMP89]]
-// CHECK2-NEXT: [[SUB134:%.*]] = sub i32 [[SUB133]], 1
-// CHECK2-NEXT: [[ADD135:%.*]] = add i32 [[SUB134]], 1
-// CHECK2-NEXT: [[DIV136:%.*]] = udiv i32 [[ADD135]], 1
-// CHECK2-NEXT: [[MUL137:%.*]] = mul i32 [[MUL132]], [[DIV136]]
+// CHECK2-NEXT: [[MUL113:%.*]] = mul i32 [[MUL110]], [[DIV112]]
+// CHECK2-NEXT: [[MUL114:%.*]] = mul i32 [[MUL113]], 32
+// CHECK2-NEXT: [[CONV115:%.*]] = zext i32 [[MUL114]] to i64
+// CHECK2-NEXT: [[MUL116:%.*]] = mul nsw i64 [[DIV105]], [[CONV115]]
+// CHECK2-NEXT: [[SUB117:%.*]] = sub nsw i64 [[TMP66]], [[MUL116]]
+// CHECK2-NEXT: [[TMP78:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP79:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP81:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB118:%.*]] = sub i32 [[TMP80]], [[TMP81]]
+// CHECK2-NEXT: [[SUB119:%.*]] = sub i32 [[SUB118]], 1
+// CHECK2-NEXT: [[TMP82:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD120:%.*]] = add i32 [[SUB119]], [[TMP82]]
+// CHECK2-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV121:%.*]] = udiv i32 [[ADD120]], [[TMP83]]
+// CHECK2-NEXT: [[MUL122:%.*]] = mul i32 1, [[DIV121]]
+// CHECK2-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB123:%.*]] = sub i32 [[TMP84]], -31
+// CHECK2-NEXT: [[DIV124:%.*]] = udiv i32 [[SUB123]], 32
+// CHECK2-NEXT: [[MUL125:%.*]] = mul i32 [[MUL122]], [[DIV124]]
+// CHECK2-NEXT: [[MUL126:%.*]] = mul i32 [[MUL125]], 32
+// CHECK2-NEXT: [[CONV127:%.*]] = zext i32 [[MUL126]] to i64
+// CHECK2-NEXT: [[DIV128:%.*]] = sdiv i64 [[TMP79]], [[CONV127]]
+// CHECK2-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB129:%.*]] = sub i32 [[TMP85]], [[TMP86]]
+// CHECK2-NEXT: [[SUB130:%.*]] = sub i32 [[SUB129]], 1
+// CHECK2-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD131:%.*]] = add i32 [[SUB130]], [[TMP87]]
+// CHECK2-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV132:%.*]] = udiv i32 [[ADD131]], [[TMP88]]
+// CHECK2-NEXT: [[MUL133:%.*]] = mul i32 1, [[DIV132]]
+// CHECK2-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB134:%.*]] = sub i32 [[TMP89]], -31
+// CHECK2-NEXT: [[DIV135:%.*]] = udiv i32 [[SUB134]], 32
+// CHECK2-NEXT: [[MUL136:%.*]] = mul i32 [[MUL133]], [[DIV135]]
+// CHECK2-NEXT: [[MUL137:%.*]] = mul i32 [[MUL136]], 32
// CHECK2-NEXT: [[CONV138:%.*]] = zext i32 [[MUL137]] to i64
-// CHECK2-NEXT: [[DIV139:%.*]] = sdiv i64 [[TMP82]], [[CONV138]]
-// CHECK2-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB140:%.*]] = sub i32 [[TMP90]], [[TMP91]]
-// CHECK2-NEXT: [[SUB141:%.*]] = sub i32 [[SUB140]], 1
-// CHECK2-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD142:%.*]] = add i32 [[SUB141]], [[TMP92]]
-// CHECK2-NEXT: [[TMP93:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV143:%.*]] = udiv i32 [[ADD142]], [[TMP93]]
-// CHECK2-NEXT: [[MUL144:%.*]] = mul i32 1, [[DIV143]]
-// CHECK2-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB145:%.*]] = sub i32 [[TMP94]], -31
-// CHECK2-NEXT: [[DIV146:%.*]] = udiv i32 [[SUB145]], 32
-// CHECK2-NEXT: [[MUL147:%.*]] = mul i32 [[MUL144]], [[DIV146]]
-// CHECK2-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB148:%.*]] = sub i32 [[TMP95]], [[TMP96]]
-// CHECK2-NEXT: [[SUB149:%.*]] = sub i32 [[SUB148]], 1
-// CHECK2-NEXT: [[ADD150:%.*]] = add i32 [[SUB149]], 1
-// CHECK2-NEXT: [[DIV151:%.*]] = udiv i32 [[ADD150]], 1
-// CHECK2-NEXT: [[MUL152:%.*]] = mul i32 [[MUL147]], [[DIV151]]
-// CHECK2-NEXT: [[CONV153:%.*]] = zext i32 [[MUL152]] to i64
-// CHECK2-NEXT: [[MUL154:%.*]] = mul nsw i64 [[DIV139]], [[CONV153]]
-// CHECK2-NEXT: [[SUB155:%.*]] = sub nsw i64 [[TMP81]], [[MUL154]]
-// CHECK2-NEXT: [[TMP97:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP98:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB156:%.*]] = sub i32 [[TMP99]], [[TMP100]]
-// CHECK2-NEXT: [[SUB157:%.*]] = sub i32 [[SUB156]], 1
-// CHECK2-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD158:%.*]] = add i32 [[SUB157]], [[TMP101]]
+// CHECK2-NEXT: [[MUL139:%.*]] = mul nsw i64 [[DIV128]], [[CONV138]]
+// CHECK2-NEXT: [[SUB140:%.*]] = sub nsw i64 [[TMP78]], [[MUL139]]
+// CHECK2-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB141:%.*]] = sub i32 [[TMP90]], -31
+// CHECK2-NEXT: [[DIV142:%.*]] = udiv i32 [[SUB141]], 32
+// CHECK2-NEXT: [[MUL143:%.*]] = mul i32 1, [[DIV142]]
+// CHECK2-NEXT: [[MUL144:%.*]] = mul i32 [[MUL143]], 32
+// CHECK2-NEXT: [[CONV145:%.*]] = zext i32 [[MUL144]] to i64
+// CHECK2-NEXT: [[DIV146:%.*]] = sdiv i64 [[SUB140]], [[CONV145]]
+// CHECK2-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB147:%.*]] = sub i32 [[TMP91]], -31
+// CHECK2-NEXT: [[DIV148:%.*]] = udiv i32 [[SUB147]], 32
+// CHECK2-NEXT: [[MUL149:%.*]] = mul i32 1, [[DIV148]]
+// CHECK2-NEXT: [[MUL150:%.*]] = mul i32 [[MUL149]], 32
+// CHECK2-NEXT: [[CONV151:%.*]] = zext i32 [[MUL150]] to i64
+// CHECK2-NEXT: [[MUL152:%.*]] = mul nsw i64 [[DIV146]], [[CONV151]]
+// CHECK2-NEXT: [[SUB153:%.*]] = sub nsw i64 [[SUB117]], [[MUL152]]
+// CHECK2-NEXT: [[DIV154:%.*]] = sdiv i64 [[SUB153]], 32
+// CHECK2-NEXT: [[MUL155:%.*]] = mul nsw i64 [[DIV154]], 32
+// CHECK2-NEXT: [[ADD156:%.*]] = add nsw i64 0, [[MUL155]]
+// CHECK2-NEXT: [[CONV157:%.*]] = trunc i64 [[ADD156]] to i32
+// CHECK2-NEXT: store i32 [[CONV157]], ptr [[DOTFLOOR_0_IV_K41]], align 4
+// CHECK2-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_K41]], align 4
+// CHECK2-NEXT: [[CONV158:%.*]] = zext i32 [[TMP92]] to i64
+// CHECK2-NEXT: [[TMP93:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP94:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB159:%.*]] = sub i32 [[TMP95]], [[TMP96]]
+// CHECK2-NEXT: [[SUB160:%.*]] = sub i32 [[SUB159]], 1
+// CHECK2-NEXT: [[TMP97:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD161:%.*]] = add i32 [[SUB160]], [[TMP97]]
+// CHECK2-NEXT: [[TMP98:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV162:%.*]] = udiv i32 [[ADD161]], [[TMP98]]
+// CHECK2-NEXT: [[MUL163:%.*]] = mul i32 1, [[DIV162]]
+// CHECK2-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB164:%.*]] = sub i32 [[TMP99]], -31
+// CHECK2-NEXT: [[DIV165:%.*]] = udiv i32 [[SUB164]], 32
+// CHECK2-NEXT: [[MUL166:%.*]] = mul i32 [[MUL163]], [[DIV165]]
+// CHECK2-NEXT: [[MUL167:%.*]] = mul i32 [[MUL166]], 32
+// CHECK2-NEXT: [[CONV168:%.*]] = zext i32 [[MUL167]] to i64
+// CHECK2-NEXT: [[DIV169:%.*]] = sdiv i64 [[TMP94]], [[CONV168]]
+// CHECK2-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB170:%.*]] = sub i32 [[TMP100]], [[TMP101]]
+// CHECK2-NEXT: [[SUB171:%.*]] = sub i32 [[SUB170]], 1
// CHECK2-NEXT: [[TMP102:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV159:%.*]] = udiv i32 [[ADD158]], [[TMP102]]
-// CHECK2-NEXT: [[MUL160:%.*]] = mul i32 1, [[DIV159]]
-// CHECK2-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB161:%.*]] = sub i32 [[TMP103]], -31
-// CHECK2-NEXT: [[DIV162:%.*]] = udiv i32 [[SUB161]], 32
-// CHECK2-NEXT: [[MUL163:%.*]] = mul i32 [[MUL160]], [[DIV162]]
-// CHECK2-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB164:%.*]] = sub i32 [[TMP104]], [[TMP105]]
-// CHECK2-NEXT: [[SUB165:%.*]] = sub i32 [[SUB164]], 1
-// CHECK2-NEXT: [[ADD166:%.*]] = add i32 [[SUB165]], 1
-// CHECK2-NEXT: [[DIV167:%.*]] = udiv i32 [[ADD166]], 1
-// CHECK2-NEXT: [[MUL168:%.*]] = mul i32 [[MUL163]], [[DIV167]]
-// CHECK2-NEXT: [[CONV169:%.*]] = zext i32 [[MUL168]] to i64
-// CHECK2-NEXT: [[DIV170:%.*]] = sdiv i64 [[TMP98]], [[CONV169]]
-// CHECK2-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB171:%.*]] = sub i32 [[TMP106]], [[TMP107]]
-// CHECK2-NEXT: [[SUB172:%.*]] = sub i32 [[SUB171]], 1
-// CHECK2-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD173:%.*]] = add i32 [[SUB172]], [[TMP108]]
+// CHECK2-NEXT: [[ADD172:%.*]] = add i32 [[SUB171]], [[TMP102]]
+// CHECK2-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV173:%.*]] = udiv i32 [[ADD172]], [[TMP103]]
+// CHECK2-NEXT: [[MUL174:%.*]] = mul i32 1, [[DIV173]]
+// CHECK2-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB175:%.*]] = sub i32 [[TMP104]], -31
+// CHECK2-NEXT: [[DIV176:%.*]] = udiv i32 [[SUB175]], 32
+// CHECK2-NEXT: [[MUL177:%.*]] = mul i32 [[MUL174]], [[DIV176]]
+// CHECK2-NEXT: [[MUL178:%.*]] = mul i32 [[MUL177]], 32
+// CHECK2-NEXT: [[CONV179:%.*]] = zext i32 [[MUL178]] to i64
+// CHECK2-NEXT: [[MUL180:%.*]] = mul nsw i64 [[DIV169]], [[CONV179]]
+// CHECK2-NEXT: [[SUB181:%.*]] = sub nsw i64 [[TMP93]], [[MUL180]]
+// CHECK2-NEXT: [[TMP105:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP106:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB182:%.*]] = sub i32 [[TMP107]], [[TMP108]]
+// CHECK2-NEXT: [[SUB183:%.*]] = sub i32 [[SUB182]], 1
// CHECK2-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV174:%.*]] = udiv i32 [[ADD173]], [[TMP109]]
-// CHECK2-NEXT: [[MUL175:%.*]] = mul i32 1, [[DIV174]]
-// CHECK2-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB176:%.*]] = sub i32 [[TMP110]], -31
-// CHECK2-NEXT: [[DIV177:%.*]] = udiv i32 [[SUB176]], 32
-// CHECK2-NEXT: [[MUL178:%.*]] = mul i32 [[MUL175]], [[DIV177]]
-// CHECK2-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB179:%.*]] = sub i32 [[TMP111]], [[TMP112]]
-// CHECK2-NEXT: [[SUB180:%.*]] = sub i32 [[SUB179]], 1
-// CHECK2-NEXT: [[ADD181:%.*]] = add i32 [[SUB180]], 1
-// CHECK2-NEXT: [[DIV182:%.*]] = udiv i32 [[ADD181]], 1
-// CHECK2-NEXT: [[MUL183:%.*]] = mul i32 [[MUL178]], [[DIV182]]
-// CHECK2-NEXT: [[CONV184:%.*]] = zext i32 [[MUL183]] to i64
-// CHECK2-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV170]], [[CONV184]]
-// CHECK2-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP97]], [[MUL185]]
-// CHECK2-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB187:%.*]] = sub i32 [[TMP113]], -31
+// CHECK2-NEXT: [[ADD184:%.*]] = add i32 [[SUB183]], [[TMP109]]
+// CHECK2-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV185:%.*]] = udiv i32 [[ADD184]], [[TMP110]]
+// CHECK2-NEXT: [[MUL186:%.*]] = mul i32 1, [[DIV185]]
+// CHECK2-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB187:%.*]] = sub i32 [[TMP111]], -31
// CHECK2-NEXT: [[DIV188:%.*]] = udiv i32 [[SUB187]], 32
-// CHECK2-NEXT: [[MUL189:%.*]] = mul i32 1, [[DIV188]]
-// CHECK2-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB190:%.*]] = sub i32 [[TMP114]], [[TMP115]]
-// CHECK2-NEXT: [[SUB191:%.*]] = sub i32 [[SUB190]], 1
-// CHECK2-NEXT: [[ADD192:%.*]] = add i32 [[SUB191]], 1
-// CHECK2-NEXT: [[DIV193:%.*]] = udiv i32 [[ADD192]], 1
-// CHECK2-NEXT: [[MUL194:%.*]] = mul i32 [[MUL189]], [[DIV193]]
-// CHECK2-NEXT: [[CONV195:%.*]] = zext i32 [[MUL194]] to i64
-// CHECK2-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB186]], [[CONV195]]
+// CHECK2-NEXT: [[MUL189:%.*]] = mul i32 [[MUL186]], [[DIV188]]
+// CHECK2-NEXT: [[MUL190:%.*]] = mul i32 [[MUL189]], 32
+// CHECK2-NEXT: [[CONV191:%.*]] = zext i32 [[MUL190]] to i64
+// CHECK2-NEXT: [[DIV192:%.*]] = sdiv i64 [[TMP106]], [[CONV191]]
+// CHECK2-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB193:%.*]] = sub i32 [[TMP112]], [[TMP113]]
+// CHECK2-NEXT: [[SUB194:%.*]] = sub i32 [[SUB193]], 1
+// CHECK2-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD195:%.*]] = add i32 [[SUB194]], [[TMP114]]
+// CHECK2-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV196:%.*]] = udiv i32 [[ADD195]], [[TMP115]]
+// CHECK2-NEXT: [[MUL197:%.*]] = mul i32 1, [[DIV196]]
// CHECK2-NEXT: [[TMP116:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB197:%.*]] = sub i32 [[TMP116]], -31
-// CHECK2-NEXT: [[DIV198:%.*]] = udiv i32 [[SUB197]], 32
-// CHECK2-NEXT: [[MUL199:%.*]] = mul i32 1, [[DIV198]]
-// CHECK2-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB200:%.*]] = sub i32 [[TMP117]], [[TMP118]]
-// CHECK2-NEXT: [[SUB201:%.*]] = sub i32 [[SUB200]], 1
-// CHECK2-NEXT: [[ADD202:%.*]] = add i32 [[SUB201]], 1
-// CHECK2-NEXT: [[DIV203:%.*]] = udiv i32 [[ADD202]], 1
-// CHECK2-NEXT: [[MUL204:%.*]] = mul i32 [[MUL199]], [[DIV203]]
-// CHECK2-NEXT: [[CONV205:%.*]] = zext i32 [[MUL204]] to i64
-// CHECK2-NEXT: [[MUL206:%.*]] = mul nsw i64 [[DIV196]], [[CONV205]]
-// CHECK2-NEXT: [[SUB207:%.*]] = sub nsw i64 [[SUB155]], [[MUL206]]
-// CHECK2-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB208:%.*]] = sub i32 [[TMP119]], [[TMP120]]
-// CHECK2-NEXT: [[SUB209:%.*]] = sub i32 [[SUB208]], 1
-// CHECK2-NEXT: [[ADD210:%.*]] = add i32 [[SUB209]], 1
-// CHECK2-NEXT: [[DIV211:%.*]] = udiv i32 [[ADD210]], 1
-// CHECK2-NEXT: [[MUL212:%.*]] = mul i32 1, [[DIV211]]
-// CHECK2-NEXT: [[CONV213:%.*]] = zext i32 [[MUL212]] to i64
-// CHECK2-NEXT: [[DIV214:%.*]] = sdiv i64 [[SUB207]], [[CONV213]]
-// CHECK2-NEXT: [[MUL215:%.*]] = mul nsw i64 [[DIV214]], 32
-// CHECK2-NEXT: [[ADD216:%.*]] = add nsw i64 0, [[MUL215]]
-// CHECK2-NEXT: [[CONV217:%.*]] = trunc i64 [[ADD216]] to i32
-// CHECK2-NEXT: store i32 [[CONV217]], ptr [[DOTFLOOR_0_IV_K51]], align 4
-// CHECK2-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[CONV218:%.*]] = zext i32 [[TMP121]] to i64
-// CHECK2-NEXT: [[TMP122:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP123:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB219:%.*]] = sub i32 [[TMP124]], [[TMP125]]
-// CHECK2-NEXT: [[SUB220:%.*]] = sub i32 [[SUB219]], 1
-// CHECK2-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD221:%.*]] = add i32 [[SUB220]], [[TMP126]]
-// CHECK2-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV222:%.*]] = udiv i32 [[ADD221]], [[TMP127]]
-// CHECK2-NEXT: [[MUL223:%.*]] = mul i32 1, [[DIV222]]
-// CHECK2-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB224:%.*]] = sub i32 [[TMP128]], -31
-// CHECK2-NEXT: [[DIV225:%.*]] = udiv i32 [[SUB224]], 32
-// CHECK2-NEXT: [[MUL226:%.*]] = mul i32 [[MUL223]], [[DIV225]]
-// CHECK2-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB227:%.*]] = sub i32 [[TMP129]], [[TMP130]]
-// CHECK2-NEXT: [[SUB228:%.*]] = sub i32 [[SUB227]], 1
-// CHECK2-NEXT: [[ADD229:%.*]] = add i32 [[SUB228]], 1
-// CHECK2-NEXT: [[DIV230:%.*]] = udiv i32 [[ADD229]], 1
-// CHECK2-NEXT: [[MUL231:%.*]] = mul i32 [[MUL226]], [[DIV230]]
-// CHECK2-NEXT: [[CONV232:%.*]] = zext i32 [[MUL231]] to i64
-// CHECK2-NEXT: [[DIV233:%.*]] = sdiv i64 [[TMP123]], [[CONV232]]
-// CHECK2-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB234:%.*]] = sub i32 [[TMP131]], [[TMP132]]
-// CHECK2-NEXT: [[SUB235:%.*]] = sub i32 [[SUB234]], 1
-// CHECK2-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD236:%.*]] = add i32 [[SUB235]], [[TMP133]]
-// CHECK2-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV237:%.*]] = udiv i32 [[ADD236]], [[TMP134]]
-// CHECK2-NEXT: [[MUL238:%.*]] = mul i32 1, [[DIV237]]
-// CHECK2-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB239:%.*]] = sub i32 [[TMP135]], -31
-// CHECK2-NEXT: [[DIV240:%.*]] = udiv i32 [[SUB239]], 32
-// CHECK2-NEXT: [[MUL241:%.*]] = mul i32 [[MUL238]], [[DIV240]]
-// CHECK2-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB242:%.*]] = sub i32 [[TMP136]], [[TMP137]]
-// CHECK2-NEXT: [[SUB243:%.*]] = sub i32 [[SUB242]], 1
-// CHECK2-NEXT: [[ADD244:%.*]] = add i32 [[SUB243]], 1
-// CHECK2-NEXT: [[DIV245:%.*]] = udiv i32 [[ADD244]], 1
-// CHECK2-NEXT: [[MUL246:%.*]] = mul i32 [[MUL241]], [[DIV245]]
-// CHECK2-NEXT: [[CONV247:%.*]] = zext i32 [[MUL246]] to i64
-// CHECK2-NEXT: [[MUL248:%.*]] = mul nsw i64 [[DIV233]], [[CONV247]]
-// CHECK2-NEXT: [[SUB249:%.*]] = sub nsw i64 [[TMP122]], [[MUL248]]
-// CHECK2-NEXT: [[TMP138:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP139:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB250:%.*]] = sub i32 [[TMP140]], [[TMP141]]
-// CHECK2-NEXT: [[SUB251:%.*]] = sub i32 [[SUB250]], 1
-// CHECK2-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD252:%.*]] = add i32 [[SUB251]], [[TMP142]]
-// CHECK2-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV253:%.*]] = udiv i32 [[ADD252]], [[TMP143]]
-// CHECK2-NEXT: [[MUL254:%.*]] = mul i32 1, [[DIV253]]
+// CHECK2-NEXT: [[SUB198:%.*]] = sub i32 [[TMP116]], -31
+// CHECK2-NEXT: [[DIV199:%.*]] = udiv i32 [[SUB198]], 32
+// CHECK2-NEXT: [[MUL200:%.*]] = mul i32 [[MUL197]], [[DIV199]]
+// CHECK2-NEXT: [[MUL201:%.*]] = mul i32 [[MUL200]], 32
+// CHECK2-NEXT: [[CONV202:%.*]] = zext i32 [[MUL201]] to i64
+// CHECK2-NEXT: [[MUL203:%.*]] = mul nsw i64 [[DIV192]], [[CONV202]]
+// CHECK2-NEXT: [[SUB204:%.*]] = sub nsw i64 [[TMP105]], [[MUL203]]
+// CHECK2-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB205:%.*]] = sub i32 [[TMP117]], -31
+// CHECK2-NEXT: [[DIV206:%.*]] = udiv i32 [[SUB205]], 32
+// CHECK2-NEXT: [[MUL207:%.*]] = mul i32 1, [[DIV206]]
+// CHECK2-NEXT: [[MUL208:%.*]] = mul i32 [[MUL207]], 32
+// CHECK2-NEXT: [[CONV209:%.*]] = zext i32 [[MUL208]] to i64
+// CHECK2-NEXT: [[DIV210:%.*]] = sdiv i64 [[SUB204]], [[CONV209]]
+// CHECK2-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB211:%.*]] = sub i32 [[TMP118]], -31
+// CHECK2-NEXT: [[DIV212:%.*]] = udiv i32 [[SUB211]], 32
+// CHECK2-NEXT: [[MUL213:%.*]] = mul i32 1, [[DIV212]]
+// CHECK2-NEXT: [[MUL214:%.*]] = mul i32 [[MUL213]], 32
+// CHECK2-NEXT: [[CONV215:%.*]] = zext i32 [[MUL214]] to i64
+// CHECK2-NEXT: [[MUL216:%.*]] = mul nsw i64 [[DIV210]], [[CONV215]]
+// CHECK2-NEXT: [[SUB217:%.*]] = sub nsw i64 [[SUB181]], [[MUL216]]
+// CHECK2-NEXT: [[TMP119:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP120:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP122:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB218:%.*]] = sub i32 [[TMP121]], [[TMP122]]
+// CHECK2-NEXT: [[SUB219:%.*]] = sub i32 [[SUB218]], 1
+// CHECK2-NEXT: [[TMP123:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD220:%.*]] = add i32 [[SUB219]], [[TMP123]]
+// CHECK2-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV221:%.*]] = udiv i32 [[ADD220]], [[TMP124]]
+// CHECK2-NEXT: [[MUL222:%.*]] = mul i32 1, [[DIV221]]
+// CHECK2-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB223:%.*]] = sub i32 [[TMP125]], -31
+// CHECK2-NEXT: [[DIV224:%.*]] = udiv i32 [[SUB223]], 32
+// CHECK2-NEXT: [[MUL225:%.*]] = mul i32 [[MUL222]], [[DIV224]]
+// CHECK2-NEXT: [[MUL226:%.*]] = mul i32 [[MUL225]], 32
+// CHECK2-NEXT: [[CONV227:%.*]] = zext i32 [[MUL226]] to i64
+// CHECK2-NEXT: [[DIV228:%.*]] = sdiv i64 [[TMP120]], [[CONV227]]
+// CHECK2-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB229:%.*]] = sub i32 [[TMP126]], [[TMP127]]
+// CHECK2-NEXT: [[SUB230:%.*]] = sub i32 [[SUB229]], 1
+// CHECK2-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD231:%.*]] = add i32 [[SUB230]], [[TMP128]]
+// CHECK2-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV232:%.*]] = udiv i32 [[ADD231]], [[TMP129]]
+// CHECK2-NEXT: [[MUL233:%.*]] = mul i32 1, [[DIV232]]
+// CHECK2-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB234:%.*]] = sub i32 [[TMP130]], -31
+// CHECK2-NEXT: [[DIV235:%.*]] = udiv i32 [[SUB234]], 32
+// CHECK2-NEXT: [[MUL236:%.*]] = mul i32 [[MUL233]], [[DIV235]]
+// CHECK2-NEXT: [[MUL237:%.*]] = mul i32 [[MUL236]], 32
+// CHECK2-NEXT: [[CONV238:%.*]] = zext i32 [[MUL237]] to i64
+// CHECK2-NEXT: [[MUL239:%.*]] = mul nsw i64 [[DIV228]], [[CONV238]]
+// CHECK2-NEXT: [[SUB240:%.*]] = sub nsw i64 [[TMP119]], [[MUL239]]
+// CHECK2-NEXT: [[TMP131:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP132:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB241:%.*]] = sub i32 [[TMP133]], [[TMP134]]
+// CHECK2-NEXT: [[SUB242:%.*]] = sub i32 [[SUB241]], 1
+// CHECK2-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD243:%.*]] = add i32 [[SUB242]], [[TMP135]]
+// CHECK2-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV244:%.*]] = udiv i32 [[ADD243]], [[TMP136]]
+// CHECK2-NEXT: [[MUL245:%.*]] = mul i32 1, [[DIV244]]
+// CHECK2-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB246:%.*]] = sub i32 [[TMP137]], -31
+// CHECK2-NEXT: [[DIV247:%.*]] = udiv i32 [[SUB246]], 32
+// CHECK2-NEXT: [[MUL248:%.*]] = mul i32 [[MUL245]], [[DIV247]]
+// CHECK2-NEXT: [[MUL249:%.*]] = mul i32 [[MUL248]], 32
+// CHECK2-NEXT: [[CONV250:%.*]] = zext i32 [[MUL249]] to i64
+// CHECK2-NEXT: [[DIV251:%.*]] = sdiv i64 [[TMP132]], [[CONV250]]
+// CHECK2-NEXT: [[TMP138:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP139:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB252:%.*]] = sub i32 [[TMP138]], [[TMP139]]
+// CHECK2-NEXT: [[SUB253:%.*]] = sub i32 [[SUB252]], 1
+// CHECK2-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD254:%.*]] = add i32 [[SUB253]], [[TMP140]]
+// CHECK2-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV255:%.*]] = udiv i32 [[ADD254]], [[TMP141]]
+// CHECK2-NEXT: [[MUL256:%.*]] = mul i32 1, [[DIV255]]
+// CHECK2-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB257:%.*]] = sub i32 [[TMP142]], -31
+// CHECK2-NEXT: [[DIV258:%.*]] = udiv i32 [[SUB257]], 32
+// CHECK2-NEXT: [[MUL259:%.*]] = mul i32 [[MUL256]], [[DIV258]]
+// CHECK2-NEXT: [[MUL260:%.*]] = mul i32 [[MUL259]], 32
+// CHECK2-NEXT: [[CONV261:%.*]] = zext i32 [[MUL260]] to i64
+// CHECK2-NEXT: [[MUL262:%.*]] = mul nsw i64 [[DIV251]], [[CONV261]]
+// CHECK2-NEXT: [[SUB263:%.*]] = sub nsw i64 [[TMP131]], [[MUL262]]
+// CHECK2-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB264:%.*]] = sub i32 [[TMP143]], -31
+// CHECK2-NEXT: [[DIV265:%.*]] = udiv i32 [[SUB264]], 32
+// CHECK2-NEXT: [[MUL266:%.*]] = mul i32 1, [[DIV265]]
+// CHECK2-NEXT: [[MUL267:%.*]] = mul i32 [[MUL266]], 32
+// CHECK2-NEXT: [[CONV268:%.*]] = zext i32 [[MUL267]] to i64
+// CHECK2-NEXT: [[DIV269:%.*]] = sdiv i64 [[SUB263]], [[CONV268]]
// CHECK2-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB255:%.*]] = sub i32 [[TMP144]], -31
-// CHECK2-NEXT: [[DIV256:%.*]] = udiv i32 [[SUB255]], 32
-// CHECK2-NEXT: [[MUL257:%.*]] = mul i32 [[MUL254]], [[DIV256]]
-// CHECK2-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB258:%.*]] = sub i32 [[TMP145]], [[TMP146]]
-// CHECK2-NEXT: [[SUB259:%.*]] = sub i32 [[SUB258]], 1
-// CHECK2-NEXT: [[ADD260:%.*]] = add i32 [[SUB259]], 1
-// CHECK2-NEXT: [[DIV261:%.*]] = udiv i32 [[ADD260]], 1
-// CHECK2-NEXT: [[MUL262:%.*]] = mul i32 [[MUL257]], [[DIV261]]
-// CHECK2-NEXT: [[CONV263:%.*]] = zext i32 [[MUL262]] to i64
-// CHECK2-NEXT: [[DIV264:%.*]] = sdiv i64 [[TMP139]], [[CONV263]]
-// CHECK2-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB265:%.*]] = sub i32 [[TMP147]], [[TMP148]]
-// CHECK2-NEXT: [[SUB266:%.*]] = sub i32 [[SUB265]], 1
-// CHECK2-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD267:%.*]] = add i32 [[SUB266]], [[TMP149]]
-// CHECK2-NEXT: [[TMP150:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV268:%.*]] = udiv i32 [[ADD267]], [[TMP150]]
-// CHECK2-NEXT: [[MUL269:%.*]] = mul i32 1, [[DIV268]]
-// CHECK2-NEXT: [[TMP151:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB270:%.*]] = sub i32 [[TMP151]], -31
+// CHECK2-NEXT: [[SUB270:%.*]] = sub i32 [[TMP144]], -31
// CHECK2-NEXT: [[DIV271:%.*]] = udiv i32 [[SUB270]], 32
-// CHECK2-NEXT: [[MUL272:%.*]] = mul i32 [[MUL269]], [[DIV271]]
-// CHECK2-NEXT: [[TMP152:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP153:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB273:%.*]] = sub i32 [[TMP152]], [[TMP153]]
-// CHECK2-NEXT: [[SUB274:%.*]] = sub i32 [[SUB273]], 1
-// CHECK2-NEXT: [[ADD275:%.*]] = add i32 [[SUB274]], 1
-// CHECK2-NEXT: [[DIV276:%.*]] = udiv i32 [[ADD275]], 1
-// CHECK2-NEXT: [[MUL277:%.*]] = mul i32 [[MUL272]], [[DIV276]]
-// CHECK2-NEXT: [[CONV278:%.*]] = zext i32 [[MUL277]] to i64
-// CHECK2-NEXT: [[MUL279:%.*]] = mul nsw i64 [[DIV264]], [[CONV278]]
-// CHECK2-NEXT: [[SUB280:%.*]] = sub nsw i64 [[TMP138]], [[MUL279]]
-// CHECK2-NEXT: [[TMP154:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB281:%.*]] = sub i32 [[TMP154]], -31
-// CHECK2-NEXT: [[DIV282:%.*]] = udiv i32 [[SUB281]], 32
-// CHECK2-NEXT: [[MUL283:%.*]] = mul i32 1, [[DIV282]]
-// CHECK2-NEXT: [[TMP155:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP156:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB284:%.*]] = sub i32 [[TMP155]], [[TMP156]]
-// CHECK2-NEXT: [[SUB285:%.*]] = sub i32 [[SUB284]], 1
-// CHECK2-NEXT: [[ADD286:%.*]] = add i32 [[SUB285]], 1
-// CHECK2-NEXT: [[DIV287:%.*]] = udiv i32 [[ADD286]], 1
-// CHECK2-NEXT: [[MUL288:%.*]] = mul i32 [[MUL283]], [[DIV287]]
-// CHECK2-NEXT: [[CONV289:%.*]] = zext i32 [[MUL288]] to i64
-// CHECK2-NEXT: [[DIV290:%.*]] = sdiv i64 [[SUB280]], [[CONV289]]
-// CHECK2-NEXT: [[TMP157:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB291:%.*]] = sub i32 [[TMP157]], -31
-// CHECK2-NEXT: [[DIV292:%.*]] = udiv i32 [[SUB291]], 32
-// CHECK2-NEXT: [[MUL293:%.*]] = mul i32 1, [[DIV292]]
-// CHECK2-NEXT: [[TMP158:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP159:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB294:%.*]] = sub i32 [[TMP158]], [[TMP159]]
-// CHECK2-NEXT: [[SUB295:%.*]] = sub i32 [[SUB294]], 1
-// CHECK2-NEXT: [[ADD296:%.*]] = add i32 [[SUB295]], 1
-// CHECK2-NEXT: [[DIV297:%.*]] = udiv i32 [[ADD296]], 1
-// CHECK2-NEXT: [[MUL298:%.*]] = mul i32 [[MUL293]], [[DIV297]]
-// CHECK2-NEXT: [[CONV299:%.*]] = zext i32 [[MUL298]] to i64
-// CHECK2-NEXT: [[MUL300:%.*]] = mul nsw i64 [[DIV290]], [[CONV299]]
-// CHECK2-NEXT: [[SUB301:%.*]] = sub nsw i64 [[SUB249]], [[MUL300]]
-// CHECK2-NEXT: [[TMP160:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP161:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP162:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP163:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB302:%.*]] = sub i32 [[TMP162]], [[TMP163]]
-// CHECK2-NEXT: [[SUB303:%.*]] = sub i32 [[SUB302]], 1
-// CHECK2-NEXT: [[TMP164:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD304:%.*]] = add i32 [[SUB303]], [[TMP164]]
-// CHECK2-NEXT: [[TMP165:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV305:%.*]] = udiv i32 [[ADD304]], [[TMP165]]
-// CHECK2-NEXT: [[MUL306:%.*]] = mul i32 1, [[DIV305]]
-// CHECK2-NEXT: [[TMP166:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB307:%.*]] = sub i32 [[TMP166]], -31
-// CHECK2-NEXT: [[DIV308:%.*]] = udiv i32 [[SUB307]], 32
-// CHECK2-NEXT: [[MUL309:%.*]] = mul i32 [[MUL306]], [[DIV308]]
-// CHECK2-NEXT: [[TMP167:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP168:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB310:%.*]] = sub i32 [[TMP167]], [[TMP168]]
-// CHECK2-NEXT: [[SUB311:%.*]] = sub i32 [[SUB310]], 1
-// CHECK2-NEXT: [[ADD312:%.*]] = add i32 [[SUB311]], 1
-// CHECK2-NEXT: [[DIV313:%.*]] = udiv i32 [[ADD312]], 1
-// CHECK2-NEXT: [[MUL314:%.*]] = mul i32 [[MUL309]], [[DIV313]]
-// CHECK2-NEXT: [[CONV315:%.*]] = zext i32 [[MUL314]] to i64
-// CHECK2-NEXT: [[DIV316:%.*]] = sdiv i64 [[TMP161]], [[CONV315]]
-// CHECK2-NEXT: [[TMP169:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP170:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB317:%.*]] = sub i32 [[TMP169]], [[TMP170]]
-// CHECK2-NEXT: [[SUB318:%.*]] = sub i32 [[SUB317]], 1
-// CHECK2-NEXT: [[TMP171:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD319:%.*]] = add i32 [[SUB318]], [[TMP171]]
-// CHECK2-NEXT: [[TMP172:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV320:%.*]] = udiv i32 [[ADD319]], [[TMP172]]
-// CHECK2-NEXT: [[MUL321:%.*]] = mul i32 1, [[DIV320]]
-// CHECK2-NEXT: [[TMP173:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB322:%.*]] = sub i32 [[TMP173]], -31
-// CHECK2-NEXT: [[DIV323:%.*]] = udiv i32 [[SUB322]], 32
-// CHECK2-NEXT: [[MUL324:%.*]] = mul i32 [[MUL321]], [[DIV323]]
-// CHECK2-NEXT: [[TMP174:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP175:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB325:%.*]] = sub i32 [[TMP174]], [[TMP175]]
-// CHECK2-NEXT: [[SUB326:%.*]] = sub i32 [[SUB325]], 1
-// CHECK2-NEXT: [[ADD327:%.*]] = add i32 [[SUB326]], 1
-// CHECK2-NEXT: [[DIV328:%.*]] = udiv i32 [[ADD327]], 1
-// CHECK2-NEXT: [[MUL329:%.*]] = mul i32 [[MUL324]], [[DIV328]]
-// CHECK2-NEXT: [[CONV330:%.*]] = zext i32 [[MUL329]] to i64
-// CHECK2-NEXT: [[MUL331:%.*]] = mul nsw i64 [[DIV316]], [[CONV330]]
-// CHECK2-NEXT: [[SUB332:%.*]] = sub nsw i64 [[TMP160]], [[MUL331]]
-// CHECK2-NEXT: [[TMP176:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP177:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP178:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP179:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB333:%.*]] = sub i32 [[TMP178]], [[TMP179]]
-// CHECK2-NEXT: [[SUB334:%.*]] = sub i32 [[SUB333]], 1
-// CHECK2-NEXT: [[TMP180:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD335:%.*]] = add i32 [[SUB334]], [[TMP180]]
-// CHECK2-NEXT: [[TMP181:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV336:%.*]] = udiv i32 [[ADD335]], [[TMP181]]
-// CHECK2-NEXT: [[MUL337:%.*]] = mul i32 1, [[DIV336]]
-// CHECK2-NEXT: [[TMP182:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB338:%.*]] = sub i32 [[TMP182]], -31
-// CHECK2-NEXT: [[DIV339:%.*]] = udiv i32 [[SUB338]], 32
-// CHECK2-NEXT: [[MUL340:%.*]] = mul i32 [[MUL337]], [[DIV339]]
-// CHECK2-NEXT: [[TMP183:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP184:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB341:%.*]] = sub i32 [[TMP183]], [[TMP184]]
-// CHECK2-NEXT: [[SUB342:%.*]] = sub i32 [[SUB341]], 1
-// CHECK2-NEXT: [[ADD343:%.*]] = add i32 [[SUB342]], 1
-// CHECK2-NEXT: [[DIV344:%.*]] = udiv i32 [[ADD343]], 1
-// CHECK2-NEXT: [[MUL345:%.*]] = mul i32 [[MUL340]], [[DIV344]]
-// CHECK2-NEXT: [[CONV346:%.*]] = zext i32 [[MUL345]] to i64
-// CHECK2-NEXT: [[DIV347:%.*]] = sdiv i64 [[TMP177]], [[CONV346]]
-// CHECK2-NEXT: [[TMP185:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP186:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB348:%.*]] = sub i32 [[TMP185]], [[TMP186]]
-// CHECK2-NEXT: [[SUB349:%.*]] = sub i32 [[SUB348]], 1
-// CHECK2-NEXT: [[TMP187:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD350:%.*]] = add i32 [[SUB349]], [[TMP187]]
-// CHECK2-NEXT: [[TMP188:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV351:%.*]] = udiv i32 [[ADD350]], [[TMP188]]
-// CHECK2-NEXT: [[MUL352:%.*]] = mul i32 1, [[DIV351]]
-// CHECK2-NEXT: [[TMP189:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB353:%.*]] = sub i32 [[TMP189]], -31
-// CHECK2-NEXT: [[DIV354:%.*]] = udiv i32 [[SUB353]], 32
-// CHECK2-NEXT: [[MUL355:%.*]] = mul i32 [[MUL352]], [[DIV354]]
-// CHECK2-NEXT: [[TMP190:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP191:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB356:%.*]] = sub i32 [[TMP190]], [[TMP191]]
-// CHECK2-NEXT: [[SUB357:%.*]] = sub i32 [[SUB356]], 1
-// CHECK2-NEXT: [[ADD358:%.*]] = add i32 [[SUB357]], 1
-// CHECK2-NEXT: [[DIV359:%.*]] = udiv i32 [[ADD358]], 1
-// CHECK2-NEXT: [[MUL360:%.*]] = mul i32 [[MUL355]], [[DIV359]]
-// CHECK2-NEXT: [[CONV361:%.*]] = zext i32 [[MUL360]] to i64
-// CHECK2-NEXT: [[MUL362:%.*]] = mul nsw i64 [[DIV347]], [[CONV361]]
-// CHECK2-NEXT: [[SUB363:%.*]] = sub nsw i64 [[TMP176]], [[MUL362]]
-// CHECK2-NEXT: [[TMP192:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB364:%.*]] = sub i32 [[TMP192]], -31
-// CHECK2-NEXT: [[DIV365:%.*]] = udiv i32 [[SUB364]], 32
-// CHECK2-NEXT: [[MUL366:%.*]] = mul i32 1, [[DIV365]]
-// CHECK2-NEXT: [[TMP193:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP194:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB367:%.*]] = sub i32 [[TMP193]], [[TMP194]]
-// CHECK2-NEXT: [[SUB368:%.*]] = sub i32 [[SUB367]], 1
-// CHECK2-NEXT: [[ADD369:%.*]] = add i32 [[SUB368]], 1
-// CHECK2-NEXT: [[DIV370:%.*]] = udiv i32 [[ADD369]], 1
-// CHECK2-NEXT: [[MUL371:%.*]] = mul i32 [[MUL366]], [[DIV370]]
-// CHECK2-NEXT: [[CONV372:%.*]] = zext i32 [[MUL371]] to i64
-// CHECK2-NEXT: [[DIV373:%.*]] = sdiv i64 [[SUB363]], [[CONV372]]
-// CHECK2-NEXT: [[TMP195:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB374:%.*]] = sub i32 [[TMP195]], -31
-// CHECK2-NEXT: [[DIV375:%.*]] = udiv i32 [[SUB374]], 32
-// CHECK2-NEXT: [[MUL376:%.*]] = mul i32 1, [[DIV375]]
-// CHECK2-NEXT: [[TMP196:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP197:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB377:%.*]] = sub i32 [[TMP196]], [[TMP197]]
-// CHECK2-NEXT: [[SUB378:%.*]] = sub i32 [[SUB377]], 1
-// CHECK2-NEXT: [[ADD379:%.*]] = add i32 [[SUB378]], 1
-// CHECK2-NEXT: [[DIV380:%.*]] = udiv i32 [[ADD379]], 1
-// CHECK2-NEXT: [[MUL381:%.*]] = mul i32 [[MUL376]], [[DIV380]]
-// CHECK2-NEXT: [[CONV382:%.*]] = zext i32 [[MUL381]] to i64
-// CHECK2-NEXT: [[MUL383:%.*]] = mul nsw i64 [[DIV373]], [[CONV382]]
-// CHECK2-NEXT: [[SUB384:%.*]] = sub nsw i64 [[SUB332]], [[MUL383]]
-// CHECK2-NEXT: [[TMP198:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP199:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB385:%.*]] = sub i32 [[TMP198]], [[TMP199]]
-// CHECK2-NEXT: [[SUB386:%.*]] = sub i32 [[SUB385]], 1
-// CHECK2-NEXT: [[ADD387:%.*]] = add i32 [[SUB386]], 1
-// CHECK2-NEXT: [[DIV388:%.*]] = udiv i32 [[ADD387]], 1
-// CHECK2-NEXT: [[MUL389:%.*]] = mul i32 1, [[DIV388]]
-// CHECK2-NEXT: [[CONV390:%.*]] = zext i32 [[MUL389]] to i64
-// CHECK2-NEXT: [[DIV391:%.*]] = sdiv i64 [[SUB384]], [[CONV390]]
-// CHECK2-NEXT: [[TMP200:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP201:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB392:%.*]] = sub i32 [[TMP200]], [[TMP201]]
-// CHECK2-NEXT: [[SUB393:%.*]] = sub i32 [[SUB392]], 1
-// CHECK2-NEXT: [[ADD394:%.*]] = add i32 [[SUB393]], 1
-// CHECK2-NEXT: [[DIV395:%.*]] = udiv i32 [[ADD394]], 1
-// CHECK2-NEXT: [[MUL396:%.*]] = mul i32 1, [[DIV395]]
-// CHECK2-NEXT: [[CONV397:%.*]] = zext i32 [[MUL396]] to i64
-// CHECK2-NEXT: [[MUL398:%.*]] = mul nsw i64 [[DIV391]], [[CONV397]]
-// CHECK2-NEXT: [[SUB399:%.*]] = sub nsw i64 [[SUB301]], [[MUL398]]
-// CHECK2-NEXT: [[MUL400:%.*]] = mul nsw i64 [[SUB399]], 1
-// CHECK2-NEXT: [[ADD401:%.*]] = add nsw i64 [[CONV218]], [[MUL400]]
-// CHECK2-NEXT: [[CONV402:%.*]] = trunc i64 [[ADD401]] to i32
-// CHECK2-NEXT: store i32 [[CONV402]], ptr [[DOTTILE_0_IV_K52]], align 4
-// CHECK2-NEXT: [[TMP202:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4
-// CHECK2-NEXT: [[TMP203:%.*]] = load i32, ptr [[DOTTILE_0_IV_K52]], align 4
-// CHECK2-NEXT: [[TMP204:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4
-// CHECK2-NEXT: [[MUL403:%.*]] = mul i32 [[TMP203]], [[TMP204]]
-// CHECK2-NEXT: [[ADD404:%.*]] = add i32 [[TMP202]], [[MUL403]]
-// CHECK2-NEXT: store i32 [[ADD404]], ptr [[K]], align 4
-// CHECK2-NEXT: [[TMP205:%.*]] = load i32, ptr [[I49]], align 4
-// CHECK2-NEXT: [[TMP206:%.*]] = load i32, ptr [[J50]], align 4
-// CHECK2-NEXT: [[TMP207:%.*]] = load i32, ptr [[K]], align 4
-// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP205]], i32 noundef [[TMP206]], i32 noundef [[TMP207]])
-// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK2-NEXT: [[MUL272:%.*]] = mul i32 1, [[DIV271]]
+// CHECK2-NEXT: [[MUL273:%.*]] = mul i32 [[MUL272]], 32
+// CHECK2-NEXT: [[CONV274:%.*]] = zext i32 [[MUL273]] to i64
+// CHECK2-NEXT: [[MUL275:%.*]] = mul nsw i64 [[DIV269]], [[CONV274]]
+// CHECK2-NEXT: [[SUB276:%.*]] = sub nsw i64 [[SUB240]], [[MUL275]]
+// CHECK2-NEXT: [[DIV277:%.*]] = sdiv i64 [[SUB276]], 32
+// CHECK2-NEXT: [[MUL278:%.*]] = mul nsw i64 [[DIV277]], 32
+// CHECK2-NEXT: [[SUB279:%.*]] = sub nsw i64 [[SUB217]], [[MUL278]]
+// CHECK2-NEXT: [[MUL280:%.*]] = mul nsw i64 [[SUB279]], 1
+// CHECK2-NEXT: [[ADD281:%.*]] = add nsw i64 [[CONV158]], [[MUL280]]
+// CHECK2-NEXT: [[CONV282:%.*]] = trunc i64 [[ADD281]] to i32
+// CHECK2-NEXT: store i32 [[CONV282]], ptr [[DOTTILE_0_IV_K42]], align 4
+// CHECK2-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTTILE_0_IV_K42]], align 4
+// CHECK2-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
+// CHECK2-NEXT: [[ADD283:%.*]] = add i32 [[TMP146]], 1
+// CHECK2-NEXT: [[CMP284:%.*]] = icmp ult i32 [[TMP145]], [[ADD283]]
+// CHECK2-NEXT: br i1 [[CMP284]], label [[OMP_BODY_NEXT:%.*]], label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK2: omp.body.next:
+// CHECK2-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4
+// CHECK2-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTTILE_0_IV_K42]], align 4
+// CHECK2-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4
+// CHECK2-NEXT: [[MUL285:%.*]] = mul i32 [[TMP148]], [[TMP149]]
+// CHECK2-NEXT: [[ADD286:%.*]] = add i32 [[TMP147]], [[MUL285]]
+// CHECK2-NEXT: store i32 [[ADD286]], ptr [[K]], align 4
+// CHECK2-NEXT: [[TMP150:%.*]] = load i32, ptr [[I39]], align 4
+// CHECK2-NEXT: [[TMP151:%.*]] = load i32, ptr [[J40]], align 4
+// CHECK2-NEXT: [[TMP152:%.*]] = load i32, ptr [[K]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP150]], i32 noundef [[TMP151]], i32 noundef [[TMP152]])
+// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP208:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[ADD405:%.*]] = add nsw i64 [[TMP208]], 1
-// CHECK2-NEXT: store i64 [[ADD405]], ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP153:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[ADD287:%.*]] = add nsw i64 [[TMP153]], 1
+// CHECK2-NEXT: store i64 [[ADD287]], ptr [[DOTOMP_IV]], align 8
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK2: omp.inner.for.end:
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
@@ -4638,19 +4117,20 @@ extern "C" void foo10() {
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTFLOOR_0_IV_K:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[_TMP35:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[I49:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[J50:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTFLOOR_0_IV_K51:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTTILE_0_IV_K52:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[I39:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[J40:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTFLOOR_0_IV_K41:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTTILE_0_IV_K42:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
// CHECK2-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4
// CHECK2-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4
@@ -4690,628 +4170,453 @@ extern "C" void foo10() {
// CHECK2-NEXT: store i32 [[ADD15]], ptr [[DOTCAPTURE_EXPR_14]], align 4
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[_TMP2]], align 4
// CHECK2-NEXT: store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
-// CHECK2-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 1
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[_TMP2]], align 4
-// CHECK2-NEXT: [[ADD19:%.*]] = add i32 [[TMP18]], 64
-// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD18]], [[ADD19]]
-// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK2: cond.true:
-// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
-// CHECK2-NEXT: [[ADD20:%.*]] = add i32 [[TMP19]], 1
-// CHECK2-NEXT: br label [[COND_END:%.*]]
-// CHECK2: cond.false:
-// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[_TMP2]], align 4
-// CHECK2-NEXT: [[ADD21:%.*]] = add i32 [[TMP20]], 64
-// CHECK2-NEXT: br label [[COND_END]]
-// CHECK2: cond.end:
-// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[ADD20]], [[COND_TRUE]] ], [ [[ADD21]], [[COND_FALSE]] ]
-// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
-// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[SUB23:%.*]] = sub i32 [[TMP21]], [[TMP22]]
-// CHECK2-NEXT: [[SUB24:%.*]] = sub i32 [[SUB23]], 1
-// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
-// CHECK2-NEXT: [[ADD25:%.*]] = add i32 [[SUB24]], [[TMP23]]
-// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
-// CHECK2-NEXT: [[DIV26:%.*]] = udiv i32 [[ADD25]], [[TMP24]]
-// CHECK2-NEXT: [[CONV:%.*]] = zext i32 [[DIV26]] to i64
-// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB27:%.*]] = sub i32 [[TMP25]], [[TMP26]]
-// CHECK2-NEXT: [[SUB28:%.*]] = sub i32 [[SUB27]], 1
-// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD29:%.*]] = add i32 [[SUB28]], [[TMP27]]
-// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV30:%.*]] = udiv i32 [[ADD29]], [[TMP28]]
+// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[_TMP2]], align 4
+// CHECK2-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 64
+// CHECK2-NEXT: store i32 [[ADD18]], ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
+// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[SUB20:%.*]] = sub i32 [[TMP18]], [[TMP19]]
+// CHECK2-NEXT: [[SUB21:%.*]] = sub i32 [[SUB20]], 1
+// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK2-NEXT: [[ADD22:%.*]] = add i32 [[SUB21]], [[TMP20]]
+// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK2-NEXT: [[DIV23:%.*]] = udiv i32 [[ADD22]], [[TMP21]]
+// CHECK2-NEXT: [[CONV:%.*]] = zext i32 [[DIV23]] to i64
+// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB24:%.*]] = sub i32 [[TMP22]], [[TMP23]]
+// CHECK2-NEXT: [[SUB25:%.*]] = sub i32 [[SUB24]], 1
+// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD26:%.*]] = add i32 [[SUB25]], [[TMP24]]
+// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV27:%.*]] = udiv i32 [[ADD26]], [[TMP25]]
+// CHECK2-NEXT: [[CONV28:%.*]] = zext i32 [[DIV27]] to i64
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV28]]
+// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB29:%.*]] = sub i32 [[TMP26]], -63
+// CHECK2-NEXT: [[DIV30:%.*]] = udiv i32 [[SUB29]], 64
// CHECK2-NEXT: [[CONV31:%.*]] = zext i32 [[DIV30]] to i64
-// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV31]]
-// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB32:%.*]] = sub i32 [[TMP29]], -63
-// CHECK2-NEXT: [[DIV33:%.*]] = udiv i32 [[SUB32]], 64
-// CHECK2-NEXT: [[CONV34:%.*]] = zext i32 [[DIV33]] to i64
-// CHECK2-NEXT: [[MUL35:%.*]] = mul nsw i64 [[MUL]], [[CONV34]]
-// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB36:%.*]] = sub i32 [[TMP30]], [[TMP31]]
-// CHECK2-NEXT: [[SUB37:%.*]] = sub i32 [[SUB36]], 1
-// CHECK2-NEXT: [[ADD38:%.*]] = add i32 [[SUB37]], 1
-// CHECK2-NEXT: [[DIV39:%.*]] = udiv i32 [[ADD38]], 1
-// CHECK2-NEXT: [[CONV40:%.*]] = zext i32 [[DIV39]] to i64
-// CHECK2-NEXT: [[MUL41:%.*]] = mul nsw i64 [[MUL35]], [[CONV40]]
-// CHECK2-NEXT: [[SUB42:%.*]] = sub nsw i64 [[MUL41]], 1
-// CHECK2-NEXT: store i64 [[SUB42]], ptr [[DOTCAPTURE_EXPR_22]], align 8
-// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: store i32 [[TMP32]], ptr [[I]], align 4
-// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: store i32 [[TMP33]], ptr [[J]], align 4
+// CHECK2-NEXT: [[MUL32:%.*]] = mul nsw i64 [[MUL]], [[CONV31]]
+// CHECK2-NEXT: [[MUL33:%.*]] = mul nsw i64 [[MUL32]], 64
+// CHECK2-NEXT: [[SUB34:%.*]] = sub nsw i64 [[MUL33]], 1
+// CHECK2-NEXT: store i64 [[SUB34]], ptr [[DOTCAPTURE_EXPR_19]], align 8
+// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: store i32 [[TMP27]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: store i32 [[TMP28]], ptr [[J]], align 4
// CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_K]], align 4
-// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: store i32 [[TMP34]], ptr [[DOTTILE_0_IV_K]], align 4
-// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
-// CHECK2-NEXT: [[CMP43:%.*]] = icmp slt i32 [[TMP35]], [[TMP36]]
-// CHECK2-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
+// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_K]], align 4
+// CHECK2-NEXT: store i32 [[TMP29]], ptr [[DOTTILE_0_IV_K]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[_TMP35]], align 4
+// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
+// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP30]], [[TMP31]]
+// CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK2: land.lhs.true:
-// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]]
-// CHECK2-NEXT: br i1 [[CMP44]], label [[LAND_LHS_TRUE45:%.*]], label [[OMP_PRECOND_END]]
-// CHECK2: land.lhs.true45:
-// CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[CMP46:%.*]] = icmp ult i32 0, [[TMP39]]
-// CHECK2-NEXT: br i1 [[CMP46]], label [[LAND_LHS_TRUE47:%.*]], label [[OMP_PRECOND_END]]
-// CHECK2: land.lhs.true47:
-// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[CMP48:%.*]] = icmp ult i32 [[TMP40]], [[TMP41]]
-// CHECK2-NEXT: br i1 [[CMP48]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
+// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[CMP36:%.*]] = icmp slt i32 [[TMP32]], [[TMP33]]
+// CHECK2-NEXT: br i1 [[CMP36]], label [[LAND_LHS_TRUE37:%.*]], label [[OMP_PRECOND_END]]
+// CHECK2: land.lhs.true37:
+// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[CMP38:%.*]] = icmp ult i32 0, [[TMP34]]
+// CHECK2-NEXT: br i1 [[CMP38]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
// CHECK2: omp.precond.then:
// CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
-// CHECK2-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
-// CHECK2-NEXT: store i64 [[TMP42]], ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: [[TMP35:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_19]], align 8
+// CHECK2-NEXT: store i64 [[TMP35]], ptr [[DOTOMP_UB]], align 8
// CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
-// CHECK2-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK2-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
-// CHECK2-NEXT: [[CMP53:%.*]] = icmp sgt i64 [[TMP43]], [[TMP44]]
-// CHECK2-NEXT: br i1 [[CMP53]], label [[COND_TRUE54:%.*]], label [[COND_FALSE55:%.*]]
-// CHECK2: cond.true54:
-// CHECK2-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
-// CHECK2-NEXT: br label [[COND_END56:%.*]]
-// CHECK2: cond.false55:
-// CHECK2-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK2-NEXT: br label [[COND_END56]]
-// CHECK2: cond.end56:
-// CHECK2-NEXT: [[COND57:%.*]] = phi i64 [ [[TMP45]], [[COND_TRUE54]] ], [ [[TMP46]], [[COND_FALSE55]] ]
-// CHECK2-NEXT: store i64 [[COND57]], ptr [[DOTOMP_UB]], align 8
-// CHECK2-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
-// CHECK2-NEXT: store i64 [[TMP47]], ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP36:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_19]], align 8
+// CHECK2-NEXT: [[CMP43:%.*]] = icmp sgt i64 [[TMP36]], [[TMP37]]
+// CHECK2-NEXT: br i1 [[CMP43]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK2: cond.true:
+// CHECK2-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_19]], align 8
+// CHECK2-NEXT: br label [[COND_END:%.*]]
+// CHECK2: cond.false:
+// CHECK2-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: br label [[COND_END]]
+// CHECK2: cond.end:
+// CHECK2-NEXT: [[COND:%.*]] = phi i64 [ [[TMP38]], [[COND_TRUE]] ], [ [[TMP39]], [[COND_FALSE]] ]
+// CHECK2-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: [[TMP40:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
+// CHECK2-NEXT: store i64 [[TMP40]], ptr [[DOTOMP_IV]], align 8
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK2-NEXT: [[CMP58:%.*]] = icmp sle i64 [[TMP48]], [[TMP49]]
-// CHECK2-NEXT: br i1 [[CMP58]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK2-NEXT: [[TMP41:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: [[CMP44:%.*]] = icmp sle i64 [[TMP41]], [[TMP42]]
+// CHECK2-NEXT: br i1 [[CMP44]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[CONV59:%.*]] = sext i32 [[TMP50]] to i64
-// CHECK2-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB60:%.*]] = sub i32 [[TMP52]], [[TMP53]]
-// CHECK2-NEXT: [[SUB61:%.*]] = sub i32 [[SUB60]], 1
-// CHECK2-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD62:%.*]] = add i32 [[SUB61]], [[TMP54]]
-// CHECK2-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV63:%.*]] = udiv i32 [[ADD62]], [[TMP55]]
-// CHECK2-NEXT: [[MUL64:%.*]] = mul i32 1, [[DIV63]]
-// CHECK2-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB65:%.*]] = sub i32 [[TMP56]], -63
-// CHECK2-NEXT: [[DIV66:%.*]] = udiv i32 [[SUB65]], 64
-// CHECK2-NEXT: [[MUL67:%.*]] = mul i32 [[MUL64]], [[DIV66]]
-// CHECK2-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB68:%.*]] = sub i32 [[TMP57]], [[TMP58]]
-// CHECK2-NEXT: [[SUB69:%.*]] = sub i32 [[SUB68]], 1
-// CHECK2-NEXT: [[ADD70:%.*]] = add i32 [[SUB69]], 1
-// CHECK2-NEXT: [[DIV71:%.*]] = udiv i32 [[ADD70]], 1
-// CHECK2-NEXT: [[MUL72:%.*]] = mul i32 [[MUL67]], [[DIV71]]
-// CHECK2-NEXT: [[CONV73:%.*]] = zext i32 [[MUL72]] to i64
-// CHECK2-NEXT: [[DIV74:%.*]] = sdiv i64 [[TMP51]], [[CONV73]]
-// CHECK2-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
-// CHECK2-NEXT: [[CONV75:%.*]] = sext i32 [[TMP59]] to i64
-// CHECK2-NEXT: [[MUL76:%.*]] = mul nsw i64 [[DIV74]], [[CONV75]]
-// CHECK2-NEXT: [[ADD77:%.*]] = add nsw i64 [[CONV59]], [[MUL76]]
-// CHECK2-NEXT: [[CONV78:%.*]] = trunc i64 [[ADD77]] to i32
-// CHECK2-NEXT: store i32 [[CONV78]], ptr [[I49]], align 4
+// CHECK2-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[CONV45:%.*]] = sext i32 [[TMP43]] to i64
+// CHECK2-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB46:%.*]] = sub i32 [[TMP45]], [[TMP46]]
+// CHECK2-NEXT: [[SUB47:%.*]] = sub i32 [[SUB46]], 1
+// CHECK2-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD48:%.*]] = add i32 [[SUB47]], [[TMP47]]
+// CHECK2-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV49:%.*]] = udiv i32 [[ADD48]], [[TMP48]]
+// CHECK2-NEXT: [[MUL50:%.*]] = mul i32 1, [[DIV49]]
+// CHECK2-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB51:%.*]] = sub i32 [[TMP49]], -63
+// CHECK2-NEXT: [[DIV52:%.*]] = udiv i32 [[SUB51]], 64
+// CHECK2-NEXT: [[MUL53:%.*]] = mul i32 [[MUL50]], [[DIV52]]
+// CHECK2-NEXT: [[MUL54:%.*]] = mul i32 [[MUL53]], 64
+// CHECK2-NEXT: [[CONV55:%.*]] = zext i32 [[MUL54]] to i64
+// CHECK2-NEXT: [[DIV56:%.*]] = sdiv i64 [[TMP44]], [[CONV55]]
+// CHECK2-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK2-NEXT: [[CONV57:%.*]] = sext i32 [[TMP50]] to i64
+// CHECK2-NEXT: [[MUL58:%.*]] = mul nsw i64 [[DIV56]], [[CONV57]]
+// CHECK2-NEXT: [[ADD59:%.*]] = add nsw i64 [[CONV45]], [[MUL58]]
+// CHECK2-NEXT: [[CONV60:%.*]] = trunc i64 [[ADD59]] to i32
+// CHECK2-NEXT: store i32 [[CONV60]], ptr [[I39]], align 4
+// CHECK2-NEXT: [[TMP51:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[CONV61:%.*]] = sext i32 [[TMP51]] to i64
+// CHECK2-NEXT: [[TMP52:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP53:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB62:%.*]] = sub i32 [[TMP54]], [[TMP55]]
+// CHECK2-NEXT: [[SUB63:%.*]] = sub i32 [[SUB62]], 1
+// CHECK2-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD64:%.*]] = add i32 [[SUB63]], [[TMP56]]
+// CHECK2-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV65:%.*]] = udiv i32 [[ADD64]], [[TMP57]]
+// CHECK2-NEXT: [[MUL66:%.*]] = mul i32 1, [[DIV65]]
+// CHECK2-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB67:%.*]] = sub i32 [[TMP58]], -63
+// CHECK2-NEXT: [[DIV68:%.*]] = udiv i32 [[SUB67]], 64
+// CHECK2-NEXT: [[MUL69:%.*]] = mul i32 [[MUL66]], [[DIV68]]
+// CHECK2-NEXT: [[MUL70:%.*]] = mul i32 [[MUL69]], 64
+// CHECK2-NEXT: [[CONV71:%.*]] = zext i32 [[MUL70]] to i64
+// CHECK2-NEXT: [[DIV72:%.*]] = sdiv i64 [[TMP53]], [[CONV71]]
+// CHECK2-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
// CHECK2-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[CONV79:%.*]] = sext i32 [[TMP60]] to i64
-// CHECK2-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB80:%.*]] = sub i32 [[TMP63]], [[TMP64]]
-// CHECK2-NEXT: [[SUB81:%.*]] = sub i32 [[SUB80]], 1
-// CHECK2-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD82:%.*]] = add i32 [[SUB81]], [[TMP65]]
-// CHECK2-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV83:%.*]] = udiv i32 [[ADD82]], [[TMP66]]
-// CHECK2-NEXT: [[MUL84:%.*]] = mul i32 1, [[DIV83]]
-// CHECK2-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB85:%.*]] = sub i32 [[TMP67]], -63
+// CHECK2-NEXT: [[SUB73:%.*]] = sub i32 [[TMP59]], [[TMP60]]
+// CHECK2-NEXT: [[SUB74:%.*]] = sub i32 [[SUB73]], 1
+// CHECK2-NEXT: [[TMP61:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD75:%.*]] = add i32 [[SUB74]], [[TMP61]]
+// CHECK2-NEXT: [[TMP62:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV76:%.*]] = udiv i32 [[ADD75]], [[TMP62]]
+// CHECK2-NEXT: [[MUL77:%.*]] = mul i32 1, [[DIV76]]
+// CHECK2-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB78:%.*]] = sub i32 [[TMP63]], -63
+// CHECK2-NEXT: [[DIV79:%.*]] = udiv i32 [[SUB78]], 64
+// CHECK2-NEXT: [[MUL80:%.*]] = mul i32 [[MUL77]], [[DIV79]]
+// CHECK2-NEXT: [[MUL81:%.*]] = mul i32 [[MUL80]], 64
+// CHECK2-NEXT: [[CONV82:%.*]] = zext i32 [[MUL81]] to i64
+// CHECK2-NEXT: [[MUL83:%.*]] = mul nsw i64 [[DIV72]], [[CONV82]]
+// CHECK2-NEXT: [[SUB84:%.*]] = sub nsw i64 [[TMP52]], [[MUL83]]
+// CHECK2-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB85:%.*]] = sub i32 [[TMP64]], -63
// CHECK2-NEXT: [[DIV86:%.*]] = udiv i32 [[SUB85]], 64
-// CHECK2-NEXT: [[MUL87:%.*]] = mul i32 [[MUL84]], [[DIV86]]
-// CHECK2-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB88:%.*]] = sub i32 [[TMP68]], [[TMP69]]
-// CHECK2-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 1
-// CHECK2-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 1
-// CHECK2-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 1
-// CHECK2-NEXT: [[MUL92:%.*]] = mul i32 [[MUL87]], [[DIV91]]
-// CHECK2-NEXT: [[CONV93:%.*]] = zext i32 [[MUL92]] to i64
-// CHECK2-NEXT: [[DIV94:%.*]] = sdiv i64 [[TMP62]], [[CONV93]]
-// CHECK2-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB95:%.*]] = sub i32 [[TMP70]], [[TMP71]]
+// CHECK2-NEXT: [[MUL87:%.*]] = mul i32 1, [[DIV86]]
+// CHECK2-NEXT: [[MUL88:%.*]] = mul i32 [[MUL87]], 64
+// CHECK2-NEXT: [[CONV89:%.*]] = zext i32 [[MUL88]] to i64
+// CHECK2-NEXT: [[DIV90:%.*]] = sdiv i64 [[SUB84]], [[CONV89]]
+// CHECK2-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[CONV91:%.*]] = sext i32 [[TMP65]] to i64
+// CHECK2-NEXT: [[MUL92:%.*]] = mul nsw i64 [[DIV90]], [[CONV91]]
+// CHECK2-NEXT: [[ADD93:%.*]] = add nsw i64 [[CONV61]], [[MUL92]]
+// CHECK2-NEXT: [[CONV94:%.*]] = trunc i64 [[ADD93]] to i32
+// CHECK2-NEXT: store i32 [[CONV94]], ptr [[J40]], align 4
+// CHECK2-NEXT: [[TMP66:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP67:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB95:%.*]] = sub i32 [[TMP68]], [[TMP69]]
// CHECK2-NEXT: [[SUB96:%.*]] = sub i32 [[SUB95]], 1
-// CHECK2-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP72]]
-// CHECK2-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP73]]
+// CHECK2-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP70]]
+// CHECK2-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP71]]
// CHECK2-NEXT: [[MUL99:%.*]] = mul i32 1, [[DIV98]]
-// CHECK2-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB100:%.*]] = sub i32 [[TMP74]], -63
+// CHECK2-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB100:%.*]] = sub i32 [[TMP72]], -63
// CHECK2-NEXT: [[DIV101:%.*]] = udiv i32 [[SUB100]], 64
// CHECK2-NEXT: [[MUL102:%.*]] = mul i32 [[MUL99]], [[DIV101]]
-// CHECK2-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB103:%.*]] = sub i32 [[TMP75]], [[TMP76]]
-// CHECK2-NEXT: [[SUB104:%.*]] = sub i32 [[SUB103]], 1
-// CHECK2-NEXT: [[ADD105:%.*]] = add i32 [[SUB104]], 1
-// CHECK2-NEXT: [[DIV106:%.*]] = udiv i32 [[ADD105]], 1
-// CHECK2-NEXT: [[MUL107:%.*]] = mul i32 [[MUL102]], [[DIV106]]
-// CHECK2-NEXT: [[CONV108:%.*]] = zext i32 [[MUL107]] to i64
-// CHECK2-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV94]], [[CONV108]]
-// CHECK2-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP61]], [[MUL109]]
+// CHECK2-NEXT: [[MUL103:%.*]] = mul i32 [[MUL102]], 64
+// CHECK2-NEXT: [[CONV104:%.*]] = zext i32 [[MUL103]] to i64
+// CHECK2-NEXT: [[DIV105:%.*]] = sdiv i64 [[TMP67]], [[CONV104]]
+// CHECK2-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB106:%.*]] = sub i32 [[TMP73]], [[TMP74]]
+// CHECK2-NEXT: [[SUB107:%.*]] = sub i32 [[SUB106]], 1
+// CHECK2-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD108:%.*]] = add i32 [[SUB107]], [[TMP75]]
+// CHECK2-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV109:%.*]] = udiv i32 [[ADD108]], [[TMP76]]
+// CHECK2-NEXT: [[MUL110:%.*]] = mul i32 1, [[DIV109]]
// CHECK2-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
// CHECK2-NEXT: [[SUB111:%.*]] = sub i32 [[TMP77]], -63
// CHECK2-NEXT: [[DIV112:%.*]] = udiv i32 [[SUB111]], 64
-// CHECK2-NEXT: [[MUL113:%.*]] = mul i32 1, [[DIV112]]
-// CHECK2-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB114:%.*]] = sub i32 [[TMP78]], [[TMP79]]
-// CHECK2-NEXT: [[SUB115:%.*]] = sub i32 [[SUB114]], 1
-// CHECK2-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], 1
-// CHECK2-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], 1
-// CHECK2-NEXT: [[MUL118:%.*]] = mul i32 [[MUL113]], [[DIV117]]
-// CHECK2-NEXT: [[CONV119:%.*]] = zext i32 [[MUL118]] to i64
-// CHECK2-NEXT: [[DIV120:%.*]] = sdiv i64 [[SUB110]], [[CONV119]]
-// CHECK2-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[CONV121:%.*]] = sext i32 [[TMP80]] to i64
-// CHECK2-NEXT: [[MUL122:%.*]] = mul nsw i64 [[DIV120]], [[CONV121]]
-// CHECK2-NEXT: [[ADD123:%.*]] = add nsw i64 [[CONV79]], [[MUL122]]
-// CHECK2-NEXT: [[CONV124:%.*]] = trunc i64 [[ADD123]] to i32
-// CHECK2-NEXT: store i32 [[CONV124]], ptr [[J50]], align 4
-// CHECK2-NEXT: [[TMP81:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP82:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB125:%.*]] = sub i32 [[TMP83]], [[TMP84]]
-// CHECK2-NEXT: [[SUB126:%.*]] = sub i32 [[SUB125]], 1
-// CHECK2-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP85]]
-// CHECK2-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP86]]
-// CHECK2-NEXT: [[MUL129:%.*]] = mul i32 1, [[DIV128]]
-// CHECK2-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB130:%.*]] = sub i32 [[TMP87]], -63
-// CHECK2-NEXT: [[DIV131:%.*]] = udiv i32 [[SUB130]], 64
-// CHECK2-NEXT: [[MUL132:%.*]] = mul i32 [[MUL129]], [[DIV131]]
-// CHECK2-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB133:%.*]] = sub i32 [[TMP88]], [[TMP89]]
-// CHECK2-NEXT: [[SUB134:%.*]] = sub i32 [[SUB133]], 1
-// CHECK2-NEXT: [[ADD135:%.*]] = add i32 [[SUB134]], 1
-// CHECK2-NEXT: [[DIV136:%.*]] = udiv i32 [[ADD135]], 1
-// CHECK2-NEXT: [[MUL137:%.*]] = mul i32 [[MUL132]], [[DIV136]]
+// CHECK2-NEXT: [[MUL113:%.*]] = mul i32 [[MUL110]], [[DIV112]]
+// CHECK2-NEXT: [[MUL114:%.*]] = mul i32 [[MUL113]], 64
+// CHECK2-NEXT: [[CONV115:%.*]] = zext i32 [[MUL114]] to i64
+// CHECK2-NEXT: [[MUL116:%.*]] = mul nsw i64 [[DIV105]], [[CONV115]]
+// CHECK2-NEXT: [[SUB117:%.*]] = sub nsw i64 [[TMP66]], [[MUL116]]
+// CHECK2-NEXT: [[TMP78:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP79:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP81:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB118:%.*]] = sub i32 [[TMP80]], [[TMP81]]
+// CHECK2-NEXT: [[SUB119:%.*]] = sub i32 [[SUB118]], 1
+// CHECK2-NEXT: [[TMP82:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD120:%.*]] = add i32 [[SUB119]], [[TMP82]]
+// CHECK2-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV121:%.*]] = udiv i32 [[ADD120]], [[TMP83]]
+// CHECK2-NEXT: [[MUL122:%.*]] = mul i32 1, [[DIV121]]
+// CHECK2-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB123:%.*]] = sub i32 [[TMP84]], -63
+// CHECK2-NEXT: [[DIV124:%.*]] = udiv i32 [[SUB123]], 64
+// CHECK2-NEXT: [[MUL125:%.*]] = mul i32 [[MUL122]], [[DIV124]]
+// CHECK2-NEXT: [[MUL126:%.*]] = mul i32 [[MUL125]], 64
+// CHECK2-NEXT: [[CONV127:%.*]] = zext i32 [[MUL126]] to i64
+// CHECK2-NEXT: [[DIV128:%.*]] = sdiv i64 [[TMP79]], [[CONV127]]
+// CHECK2-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB129:%.*]] = sub i32 [[TMP85]], [[TMP86]]
+// CHECK2-NEXT: [[SUB130:%.*]] = sub i32 [[SUB129]], 1
+// CHECK2-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD131:%.*]] = add i32 [[SUB130]], [[TMP87]]
+// CHECK2-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV132:%.*]] = udiv i32 [[ADD131]], [[TMP88]]
+// CHECK2-NEXT: [[MUL133:%.*]] = mul i32 1, [[DIV132]]
+// CHECK2-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB134:%.*]] = sub i32 [[TMP89]], -63
+// CHECK2-NEXT: [[DIV135:%.*]] = udiv i32 [[SUB134]], 64
+// CHECK2-NEXT: [[MUL136:%.*]] = mul i32 [[MUL133]], [[DIV135]]
+// CHECK2-NEXT: [[MUL137:%.*]] = mul i32 [[MUL136]], 64
// CHECK2-NEXT: [[CONV138:%.*]] = zext i32 [[MUL137]] to i64
-// CHECK2-NEXT: [[DIV139:%.*]] = sdiv i64 [[TMP82]], [[CONV138]]
-// CHECK2-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB140:%.*]] = sub i32 [[TMP90]], [[TMP91]]
-// CHECK2-NEXT: [[SUB141:%.*]] = sub i32 [[SUB140]], 1
-// CHECK2-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD142:%.*]] = add i32 [[SUB141]], [[TMP92]]
-// CHECK2-NEXT: [[TMP93:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV143:%.*]] = udiv i32 [[ADD142]], [[TMP93]]
-// CHECK2-NEXT: [[MUL144:%.*]] = mul i32 1, [[DIV143]]
-// CHECK2-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB145:%.*]] = sub i32 [[TMP94]], -63
-// CHECK2-NEXT: [[DIV146:%.*]] = udiv i32 [[SUB145]], 64
-// CHECK2-NEXT: [[MUL147:%.*]] = mul i32 [[MUL144]], [[DIV146]]
-// CHECK2-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB148:%.*]] = sub i32 [[TMP95]], [[TMP96]]
-// CHECK2-NEXT: [[SUB149:%.*]] = sub i32 [[SUB148]], 1
-// CHECK2-NEXT: [[ADD150:%.*]] = add i32 [[SUB149]], 1
-// CHECK2-NEXT: [[DIV151:%.*]] = udiv i32 [[ADD150]], 1
-// CHECK2-NEXT: [[MUL152:%.*]] = mul i32 [[MUL147]], [[DIV151]]
-// CHECK2-NEXT: [[CONV153:%.*]] = zext i32 [[MUL152]] to i64
-// CHECK2-NEXT: [[MUL154:%.*]] = mul nsw i64 [[DIV139]], [[CONV153]]
-// CHECK2-NEXT: [[SUB155:%.*]] = sub nsw i64 [[TMP81]], [[MUL154]]
-// CHECK2-NEXT: [[TMP97:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP98:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB156:%.*]] = sub i32 [[TMP99]], [[TMP100]]
-// CHECK2-NEXT: [[SUB157:%.*]] = sub i32 [[SUB156]], 1
-// CHECK2-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD158:%.*]] = add i32 [[SUB157]], [[TMP101]]
+// CHECK2-NEXT: [[MUL139:%.*]] = mul nsw i64 [[DIV128]], [[CONV138]]
+// CHECK2-NEXT: [[SUB140:%.*]] = sub nsw i64 [[TMP78]], [[MUL139]]
+// CHECK2-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB141:%.*]] = sub i32 [[TMP90]], -63
+// CHECK2-NEXT: [[DIV142:%.*]] = udiv i32 [[SUB141]], 64
+// CHECK2-NEXT: [[MUL143:%.*]] = mul i32 1, [[DIV142]]
+// CHECK2-NEXT: [[MUL144:%.*]] = mul i32 [[MUL143]], 64
+// CHECK2-NEXT: [[CONV145:%.*]] = zext i32 [[MUL144]] to i64
+// CHECK2-NEXT: [[DIV146:%.*]] = sdiv i64 [[SUB140]], [[CONV145]]
+// CHECK2-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB147:%.*]] = sub i32 [[TMP91]], -63
+// CHECK2-NEXT: [[DIV148:%.*]] = udiv i32 [[SUB147]], 64
+// CHECK2-NEXT: [[MUL149:%.*]] = mul i32 1, [[DIV148]]
+// CHECK2-NEXT: [[MUL150:%.*]] = mul i32 [[MUL149]], 64
+// CHECK2-NEXT: [[CONV151:%.*]] = zext i32 [[MUL150]] to i64
+// CHECK2-NEXT: [[MUL152:%.*]] = mul nsw i64 [[DIV146]], [[CONV151]]
+// CHECK2-NEXT: [[SUB153:%.*]] = sub nsw i64 [[SUB117]], [[MUL152]]
+// CHECK2-NEXT: [[DIV154:%.*]] = sdiv i64 [[SUB153]], 64
+// CHECK2-NEXT: [[MUL155:%.*]] = mul nsw i64 [[DIV154]], 64
+// CHECK2-NEXT: [[ADD156:%.*]] = add nsw i64 0, [[MUL155]]
+// CHECK2-NEXT: [[CONV157:%.*]] = trunc i64 [[ADD156]] to i32
+// CHECK2-NEXT: store i32 [[CONV157]], ptr [[DOTFLOOR_0_IV_K41]], align 4
+// CHECK2-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_K41]], align 4
+// CHECK2-NEXT: [[CONV158:%.*]] = zext i32 [[TMP92]] to i64
+// CHECK2-NEXT: [[TMP93:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP94:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB159:%.*]] = sub i32 [[TMP95]], [[TMP96]]
+// CHECK2-NEXT: [[SUB160:%.*]] = sub i32 [[SUB159]], 1
+// CHECK2-NEXT: [[TMP97:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD161:%.*]] = add i32 [[SUB160]], [[TMP97]]
+// CHECK2-NEXT: [[TMP98:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV162:%.*]] = udiv i32 [[ADD161]], [[TMP98]]
+// CHECK2-NEXT: [[MUL163:%.*]] = mul i32 1, [[DIV162]]
+// CHECK2-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB164:%.*]] = sub i32 [[TMP99]], -63
+// CHECK2-NEXT: [[DIV165:%.*]] = udiv i32 [[SUB164]], 64
+// CHECK2-NEXT: [[MUL166:%.*]] = mul i32 [[MUL163]], [[DIV165]]
+// CHECK2-NEXT: [[MUL167:%.*]] = mul i32 [[MUL166]], 64
+// CHECK2-NEXT: [[CONV168:%.*]] = zext i32 [[MUL167]] to i64
+// CHECK2-NEXT: [[DIV169:%.*]] = sdiv i64 [[TMP94]], [[CONV168]]
+// CHECK2-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB170:%.*]] = sub i32 [[TMP100]], [[TMP101]]
+// CHECK2-NEXT: [[SUB171:%.*]] = sub i32 [[SUB170]], 1
// CHECK2-NEXT: [[TMP102:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV159:%.*]] = udiv i32 [[ADD158]], [[TMP102]]
-// CHECK2-NEXT: [[MUL160:%.*]] = mul i32 1, [[DIV159]]
-// CHECK2-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB161:%.*]] = sub i32 [[TMP103]], -63
-// CHECK2-NEXT: [[DIV162:%.*]] = udiv i32 [[SUB161]], 64
-// CHECK2-NEXT: [[MUL163:%.*]] = mul i32 [[MUL160]], [[DIV162]]
-// CHECK2-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB164:%.*]] = sub i32 [[TMP104]], [[TMP105]]
-// CHECK2-NEXT: [[SUB165:%.*]] = sub i32 [[SUB164]], 1
-// CHECK2-NEXT: [[ADD166:%.*]] = add i32 [[SUB165]], 1
-// CHECK2-NEXT: [[DIV167:%.*]] = udiv i32 [[ADD166]], 1
-// CHECK2-NEXT: [[MUL168:%.*]] = mul i32 [[MUL163]], [[DIV167]]
-// CHECK2-NEXT: [[CONV169:%.*]] = zext i32 [[MUL168]] to i64
-// CHECK2-NEXT: [[DIV170:%.*]] = sdiv i64 [[TMP98]], [[CONV169]]
-// CHECK2-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB171:%.*]] = sub i32 [[TMP106]], [[TMP107]]
-// CHECK2-NEXT: [[SUB172:%.*]] = sub i32 [[SUB171]], 1
-// CHECK2-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD173:%.*]] = add i32 [[SUB172]], [[TMP108]]
+// CHECK2-NEXT: [[ADD172:%.*]] = add i32 [[SUB171]], [[TMP102]]
+// CHECK2-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV173:%.*]] = udiv i32 [[ADD172]], [[TMP103]]
+// CHECK2-NEXT: [[MUL174:%.*]] = mul i32 1, [[DIV173]]
+// CHECK2-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB175:%.*]] = sub i32 [[TMP104]], -63
+// CHECK2-NEXT: [[DIV176:%.*]] = udiv i32 [[SUB175]], 64
+// CHECK2-NEXT: [[MUL177:%.*]] = mul i32 [[MUL174]], [[DIV176]]
+// CHECK2-NEXT: [[MUL178:%.*]] = mul i32 [[MUL177]], 64
+// CHECK2-NEXT: [[CONV179:%.*]] = zext i32 [[MUL178]] to i64
+// CHECK2-NEXT: [[MUL180:%.*]] = mul nsw i64 [[DIV169]], [[CONV179]]
+// CHECK2-NEXT: [[SUB181:%.*]] = sub nsw i64 [[TMP93]], [[MUL180]]
+// CHECK2-NEXT: [[TMP105:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP106:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB182:%.*]] = sub i32 [[TMP107]], [[TMP108]]
+// CHECK2-NEXT: [[SUB183:%.*]] = sub i32 [[SUB182]], 1
// CHECK2-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV174:%.*]] = udiv i32 [[ADD173]], [[TMP109]]
-// CHECK2-NEXT: [[MUL175:%.*]] = mul i32 1, [[DIV174]]
-// CHECK2-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB176:%.*]] = sub i32 [[TMP110]], -63
-// CHECK2-NEXT: [[DIV177:%.*]] = udiv i32 [[SUB176]], 64
-// CHECK2-NEXT: [[MUL178:%.*]] = mul i32 [[MUL175]], [[DIV177]]
-// CHECK2-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB179:%.*]] = sub i32 [[TMP111]], [[TMP112]]
-// CHECK2-NEXT: [[SUB180:%.*]] = sub i32 [[SUB179]], 1
-// CHECK2-NEXT: [[ADD181:%.*]] = add i32 [[SUB180]], 1
-// CHECK2-NEXT: [[DIV182:%.*]] = udiv i32 [[ADD181]], 1
-// CHECK2-NEXT: [[MUL183:%.*]] = mul i32 [[MUL178]], [[DIV182]]
-// CHECK2-NEXT: [[CONV184:%.*]] = zext i32 [[MUL183]] to i64
-// CHECK2-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV170]], [[CONV184]]
-// CHECK2-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP97]], [[MUL185]]
-// CHECK2-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB187:%.*]] = sub i32 [[TMP113]], -63
+// CHECK2-NEXT: [[ADD184:%.*]] = add i32 [[SUB183]], [[TMP109]]
+// CHECK2-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV185:%.*]] = udiv i32 [[ADD184]], [[TMP110]]
+// CHECK2-NEXT: [[MUL186:%.*]] = mul i32 1, [[DIV185]]
+// CHECK2-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB187:%.*]] = sub i32 [[TMP111]], -63
// CHECK2-NEXT: [[DIV188:%.*]] = udiv i32 [[SUB187]], 64
-// CHECK2-NEXT: [[MUL189:%.*]] = mul i32 1, [[DIV188]]
-// CHECK2-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB190:%.*]] = sub i32 [[TMP114]], [[TMP115]]
-// CHECK2-NEXT: [[SUB191:%.*]] = sub i32 [[SUB190]], 1
-// CHECK2-NEXT: [[ADD192:%.*]] = add i32 [[SUB191]], 1
-// CHECK2-NEXT: [[DIV193:%.*]] = udiv i32 [[ADD192]], 1
-// CHECK2-NEXT: [[MUL194:%.*]] = mul i32 [[MUL189]], [[DIV193]]
-// CHECK2-NEXT: [[CONV195:%.*]] = zext i32 [[MUL194]] to i64
-// CHECK2-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB186]], [[CONV195]]
+// CHECK2-NEXT: [[MUL189:%.*]] = mul i32 [[MUL186]], [[DIV188]]
+// CHECK2-NEXT: [[MUL190:%.*]] = mul i32 [[MUL189]], 64
+// CHECK2-NEXT: [[CONV191:%.*]] = zext i32 [[MUL190]] to i64
+// CHECK2-NEXT: [[DIV192:%.*]] = sdiv i64 [[TMP106]], [[CONV191]]
+// CHECK2-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB193:%.*]] = sub i32 [[TMP112]], [[TMP113]]
+// CHECK2-NEXT: [[SUB194:%.*]] = sub i32 [[SUB193]], 1
+// CHECK2-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD195:%.*]] = add i32 [[SUB194]], [[TMP114]]
+// CHECK2-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV196:%.*]] = udiv i32 [[ADD195]], [[TMP115]]
+// CHECK2-NEXT: [[MUL197:%.*]] = mul i32 1, [[DIV196]]
// CHECK2-NEXT: [[TMP116:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB197:%.*]] = sub i32 [[TMP116]], -63
-// CHECK2-NEXT: [[DIV198:%.*]] = udiv i32 [[SUB197]], 64
-// CHECK2-NEXT: [[MUL199:%.*]] = mul i32 1, [[DIV198]]
-// CHECK2-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB200:%.*]] = sub i32 [[TMP117]], [[TMP118]]
-// CHECK2-NEXT: [[SUB201:%.*]] = sub i32 [[SUB200]], 1
-// CHECK2-NEXT: [[ADD202:%.*]] = add i32 [[SUB201]], 1
-// CHECK2-NEXT: [[DIV203:%.*]] = udiv i32 [[ADD202]], 1
-// CHECK2-NEXT: [[MUL204:%.*]] = mul i32 [[MUL199]], [[DIV203]]
-// CHECK2-NEXT: [[CONV205:%.*]] = zext i32 [[MUL204]] to i64
-// CHECK2-NEXT: [[MUL206:%.*]] = mul nsw i64 [[DIV196]], [[CONV205]]
-// CHECK2-NEXT: [[SUB207:%.*]] = sub nsw i64 [[SUB155]], [[MUL206]]
-// CHECK2-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB208:%.*]] = sub i32 [[TMP119]], [[TMP120]]
-// CHECK2-NEXT: [[SUB209:%.*]] = sub i32 [[SUB208]], 1
-// CHECK2-NEXT: [[ADD210:%.*]] = add i32 [[SUB209]], 1
-// CHECK2-NEXT: [[DIV211:%.*]] = udiv i32 [[ADD210]], 1
-// CHECK2-NEXT: [[MUL212:%.*]] = mul i32 1, [[DIV211]]
-// CHECK2-NEXT: [[CONV213:%.*]] = zext i32 [[MUL212]] to i64
-// CHECK2-NEXT: [[DIV214:%.*]] = sdiv i64 [[SUB207]], [[CONV213]]
-// CHECK2-NEXT: [[MUL215:%.*]] = mul nsw i64 [[DIV214]], 64
-// CHECK2-NEXT: [[ADD216:%.*]] = add nsw i64 0, [[MUL215]]
-// CHECK2-NEXT: [[CONV217:%.*]] = trunc i64 [[ADD216]] to i32
-// CHECK2-NEXT: store i32 [[CONV217]], ptr [[DOTFLOOR_0_IV_K51]], align 4
-// CHECK2-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[CONV218:%.*]] = zext i32 [[TMP121]] to i64
-// CHECK2-NEXT: [[TMP122:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP123:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB219:%.*]] = sub i32 [[TMP124]], [[TMP125]]
-// CHECK2-NEXT: [[SUB220:%.*]] = sub i32 [[SUB219]], 1
-// CHECK2-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD221:%.*]] = add i32 [[SUB220]], [[TMP126]]
-// CHECK2-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV222:%.*]] = udiv i32 [[ADD221]], [[TMP127]]
-// CHECK2-NEXT: [[MUL223:%.*]] = mul i32 1, [[DIV222]]
-// CHECK2-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB224:%.*]] = sub i32 [[TMP128]], -63
-// CHECK2-NEXT: [[DIV225:%.*]] = udiv i32 [[SUB224]], 64
-// CHECK2-NEXT: [[MUL226:%.*]] = mul i32 [[MUL223]], [[DIV225]]
-// CHECK2-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB227:%.*]] = sub i32 [[TMP129]], [[TMP130]]
-// CHECK2-NEXT: [[SUB228:%.*]] = sub i32 [[SUB227]], 1
-// CHECK2-NEXT: [[ADD229:%.*]] = add i32 [[SUB228]], 1
-// CHECK2-NEXT: [[DIV230:%.*]] = udiv i32 [[ADD229]], 1
-// CHECK2-NEXT: [[MUL231:%.*]] = mul i32 [[MUL226]], [[DIV230]]
-// CHECK2-NEXT: [[CONV232:%.*]] = zext i32 [[MUL231]] to i64
-// CHECK2-NEXT: [[DIV233:%.*]] = sdiv i64 [[TMP123]], [[CONV232]]
-// CHECK2-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB234:%.*]] = sub i32 [[TMP131]], [[TMP132]]
-// CHECK2-NEXT: [[SUB235:%.*]] = sub i32 [[SUB234]], 1
-// CHECK2-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD236:%.*]] = add i32 [[SUB235]], [[TMP133]]
-// CHECK2-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV237:%.*]] = udiv i32 [[ADD236]], [[TMP134]]
-// CHECK2-NEXT: [[MUL238:%.*]] = mul i32 1, [[DIV237]]
-// CHECK2-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB239:%.*]] = sub i32 [[TMP135]], -63
-// CHECK2-NEXT: [[DIV240:%.*]] = udiv i32 [[SUB239]], 64
-// CHECK2-NEXT: [[MUL241:%.*]] = mul i32 [[MUL238]], [[DIV240]]
-// CHECK2-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB242:%.*]] = sub i32 [[TMP136]], [[TMP137]]
-// CHECK2-NEXT: [[SUB243:%.*]] = sub i32 [[SUB242]], 1
-// CHECK2-NEXT: [[ADD244:%.*]] = add i32 [[SUB243]], 1
-// CHECK2-NEXT: [[DIV245:%.*]] = udiv i32 [[ADD244]], 1
-// CHECK2-NEXT: [[MUL246:%.*]] = mul i32 [[MUL241]], [[DIV245]]
-// CHECK2-NEXT: [[CONV247:%.*]] = zext i32 [[MUL246]] to i64
-// CHECK2-NEXT: [[MUL248:%.*]] = mul nsw i64 [[DIV233]], [[CONV247]]
-// CHECK2-NEXT: [[SUB249:%.*]] = sub nsw i64 [[TMP122]], [[MUL248]]
-// CHECK2-NEXT: [[TMP138:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP139:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB250:%.*]] = sub i32 [[TMP140]], [[TMP141]]
-// CHECK2-NEXT: [[SUB251:%.*]] = sub i32 [[SUB250]], 1
-// CHECK2-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD252:%.*]] = add i32 [[SUB251]], [[TMP142]]
-// CHECK2-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV253:%.*]] = udiv i32 [[ADD252]], [[TMP143]]
-// CHECK2-NEXT: [[MUL254:%.*]] = mul i32 1, [[DIV253]]
+// CHECK2-NEXT: [[SUB198:%.*]] = sub i32 [[TMP116]], -63
+// CHECK2-NEXT: [[DIV199:%.*]] = udiv i32 [[SUB198]], 64
+// CHECK2-NEXT: [[MUL200:%.*]] = mul i32 [[MUL197]], [[DIV199]]
+// CHECK2-NEXT: [[MUL201:%.*]] = mul i32 [[MUL200]], 64
+// CHECK2-NEXT: [[CONV202:%.*]] = zext i32 [[MUL201]] to i64
+// CHECK2-NEXT: [[MUL203:%.*]] = mul nsw i64 [[DIV192]], [[CONV202]]
+// CHECK2-NEXT: [[SUB204:%.*]] = sub nsw i64 [[TMP105]], [[MUL203]]
+// CHECK2-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB205:%.*]] = sub i32 [[TMP117]], -63
+// CHECK2-NEXT: [[DIV206:%.*]] = udiv i32 [[SUB205]], 64
+// CHECK2-NEXT: [[MUL207:%.*]] = mul i32 1, [[DIV206]]
+// CHECK2-NEXT: [[MUL208:%.*]] = mul i32 [[MUL207]], 64
+// CHECK2-NEXT: [[CONV209:%.*]] = zext i32 [[MUL208]] to i64
+// CHECK2-NEXT: [[DIV210:%.*]] = sdiv i64 [[SUB204]], [[CONV209]]
+// CHECK2-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB211:%.*]] = sub i32 [[TMP118]], -63
+// CHECK2-NEXT: [[DIV212:%.*]] = udiv i32 [[SUB211]], 64
+// CHECK2-NEXT: [[MUL213:%.*]] = mul i32 1, [[DIV212]]
+// CHECK2-NEXT: [[MUL214:%.*]] = mul i32 [[MUL213]], 64
+// CHECK2-NEXT: [[CONV215:%.*]] = zext i32 [[MUL214]] to i64
+// CHECK2-NEXT: [[MUL216:%.*]] = mul nsw i64 [[DIV210]], [[CONV215]]
+// CHECK2-NEXT: [[SUB217:%.*]] = sub nsw i64 [[SUB181]], [[MUL216]]
+// CHECK2-NEXT: [[TMP119:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP120:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP122:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB218:%.*]] = sub i32 [[TMP121]], [[TMP122]]
+// CHECK2-NEXT: [[SUB219:%.*]] = sub i32 [[SUB218]], 1
+// CHECK2-NEXT: [[TMP123:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD220:%.*]] = add i32 [[SUB219]], [[TMP123]]
+// CHECK2-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV221:%.*]] = udiv i32 [[ADD220]], [[TMP124]]
+// CHECK2-NEXT: [[MUL222:%.*]] = mul i32 1, [[DIV221]]
+// CHECK2-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB223:%.*]] = sub i32 [[TMP125]], -63
+// CHECK2-NEXT: [[DIV224:%.*]] = udiv i32 [[SUB223]], 64
+// CHECK2-NEXT: [[MUL225:%.*]] = mul i32 [[MUL222]], [[DIV224]]
+// CHECK2-NEXT: [[MUL226:%.*]] = mul i32 [[MUL225]], 64
+// CHECK2-NEXT: [[CONV227:%.*]] = zext i32 [[MUL226]] to i64
+// CHECK2-NEXT: [[DIV228:%.*]] = sdiv i64 [[TMP120]], [[CONV227]]
+// CHECK2-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB229:%.*]] = sub i32 [[TMP126]], [[TMP127]]
+// CHECK2-NEXT: [[SUB230:%.*]] = sub i32 [[SUB229]], 1
+// CHECK2-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD231:%.*]] = add i32 [[SUB230]], [[TMP128]]
+// CHECK2-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV232:%.*]] = udiv i32 [[ADD231]], [[TMP129]]
+// CHECK2-NEXT: [[MUL233:%.*]] = mul i32 1, [[DIV232]]
+// CHECK2-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB234:%.*]] = sub i32 [[TMP130]], -63
+// CHECK2-NEXT: [[DIV235:%.*]] = udiv i32 [[SUB234]], 64
+// CHECK2-NEXT: [[MUL236:%.*]] = mul i32 [[MUL233]], [[DIV235]]
+// CHECK2-NEXT: [[MUL237:%.*]] = mul i32 [[MUL236]], 64
+// CHECK2-NEXT: [[CONV238:%.*]] = zext i32 [[MUL237]] to i64
+// CHECK2-NEXT: [[MUL239:%.*]] = mul nsw i64 [[DIV228]], [[CONV238]]
+// CHECK2-NEXT: [[SUB240:%.*]] = sub nsw i64 [[TMP119]], [[MUL239]]
+// CHECK2-NEXT: [[TMP131:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP132:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB241:%.*]] = sub i32 [[TMP133]], [[TMP134]]
+// CHECK2-NEXT: [[SUB242:%.*]] = sub i32 [[SUB241]], 1
+// CHECK2-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD243:%.*]] = add i32 [[SUB242]], [[TMP135]]
+// CHECK2-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV244:%.*]] = udiv i32 [[ADD243]], [[TMP136]]
+// CHECK2-NEXT: [[MUL245:%.*]] = mul i32 1, [[DIV244]]
+// CHECK2-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB246:%.*]] = sub i32 [[TMP137]], -63
+// CHECK2-NEXT: [[DIV247:%.*]] = udiv i32 [[SUB246]], 64
+// CHECK2-NEXT: [[MUL248:%.*]] = mul i32 [[MUL245]], [[DIV247]]
+// CHECK2-NEXT: [[MUL249:%.*]] = mul i32 [[MUL248]], 64
+// CHECK2-NEXT: [[CONV250:%.*]] = zext i32 [[MUL249]] to i64
+// CHECK2-NEXT: [[DIV251:%.*]] = sdiv i64 [[TMP132]], [[CONV250]]
+// CHECK2-NEXT: [[TMP138:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP139:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB252:%.*]] = sub i32 [[TMP138]], [[TMP139]]
+// CHECK2-NEXT: [[SUB253:%.*]] = sub i32 [[SUB252]], 1
+// CHECK2-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD254:%.*]] = add i32 [[SUB253]], [[TMP140]]
+// CHECK2-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV255:%.*]] = udiv i32 [[ADD254]], [[TMP141]]
+// CHECK2-NEXT: [[MUL256:%.*]] = mul i32 1, [[DIV255]]
+// CHECK2-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB257:%.*]] = sub i32 [[TMP142]], -63
+// CHECK2-NEXT: [[DIV258:%.*]] = udiv i32 [[SUB257]], 64
+// CHECK2-NEXT: [[MUL259:%.*]] = mul i32 [[MUL256]], [[DIV258]]
+// CHECK2-NEXT: [[MUL260:%.*]] = mul i32 [[MUL259]], 64
+// CHECK2-NEXT: [[CONV261:%.*]] = zext i32 [[MUL260]] to i64
+// CHECK2-NEXT: [[MUL262:%.*]] = mul nsw i64 [[DIV251]], [[CONV261]]
+// CHECK2-NEXT: [[SUB263:%.*]] = sub nsw i64 [[TMP131]], [[MUL262]]
+// CHECK2-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB264:%.*]] = sub i32 [[TMP143]], -63
+// CHECK2-NEXT: [[DIV265:%.*]] = udiv i32 [[SUB264]], 64
+// CHECK2-NEXT: [[MUL266:%.*]] = mul i32 1, [[DIV265]]
+// CHECK2-NEXT: [[MUL267:%.*]] = mul i32 [[MUL266]], 64
+// CHECK2-NEXT: [[CONV268:%.*]] = zext i32 [[MUL267]] to i64
+// CHECK2-NEXT: [[DIV269:%.*]] = sdiv i64 [[SUB263]], [[CONV268]]
// CHECK2-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB255:%.*]] = sub i32 [[TMP144]], -63
-// CHECK2-NEXT: [[DIV256:%.*]] = udiv i32 [[SUB255]], 64
-// CHECK2-NEXT: [[MUL257:%.*]] = mul i32 [[MUL254]], [[DIV256]]
-// CHECK2-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB258:%.*]] = sub i32 [[TMP145]], [[TMP146]]
-// CHECK2-NEXT: [[SUB259:%.*]] = sub i32 [[SUB258]], 1
-// CHECK2-NEXT: [[ADD260:%.*]] = add i32 [[SUB259]], 1
-// CHECK2-NEXT: [[DIV261:%.*]] = udiv i32 [[ADD260]], 1
-// CHECK2-NEXT: [[MUL262:%.*]] = mul i32 [[MUL257]], [[DIV261]]
-// CHECK2-NEXT: [[CONV263:%.*]] = zext i32 [[MUL262]] to i64
-// CHECK2-NEXT: [[DIV264:%.*]] = sdiv i64 [[TMP139]], [[CONV263]]
-// CHECK2-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB265:%.*]] = sub i32 [[TMP147]], [[TMP148]]
-// CHECK2-NEXT: [[SUB266:%.*]] = sub i32 [[SUB265]], 1
-// CHECK2-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD267:%.*]] = add i32 [[SUB266]], [[TMP149]]
-// CHECK2-NEXT: [[TMP150:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV268:%.*]] = udiv i32 [[ADD267]], [[TMP150]]
-// CHECK2-NEXT: [[MUL269:%.*]] = mul i32 1, [[DIV268]]
-// CHECK2-NEXT: [[TMP151:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB270:%.*]] = sub i32 [[TMP151]], -63
+// CHECK2-NEXT: [[SUB270:%.*]] = sub i32 [[TMP144]], -63
// CHECK2-NEXT: [[DIV271:%.*]] = udiv i32 [[SUB270]], 64
-// CHECK2-NEXT: [[MUL272:%.*]] = mul i32 [[MUL269]], [[DIV271]]
-// CHECK2-NEXT: [[TMP152:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP153:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB273:%.*]] = sub i32 [[TMP152]], [[TMP153]]
-// CHECK2-NEXT: [[SUB274:%.*]] = sub i32 [[SUB273]], 1
-// CHECK2-NEXT: [[ADD275:%.*]] = add i32 [[SUB274]], 1
-// CHECK2-NEXT: [[DIV276:%.*]] = udiv i32 [[ADD275]], 1
-// CHECK2-NEXT: [[MUL277:%.*]] = mul i32 [[MUL272]], [[DIV276]]
-// CHECK2-NEXT: [[CONV278:%.*]] = zext i32 [[MUL277]] to i64
-// CHECK2-NEXT: [[MUL279:%.*]] = mul nsw i64 [[DIV264]], [[CONV278]]
-// CHECK2-NEXT: [[SUB280:%.*]] = sub nsw i64 [[TMP138]], [[MUL279]]
-// CHECK2-NEXT: [[TMP154:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB281:%.*]] = sub i32 [[TMP154]], -63
-// CHECK2-NEXT: [[DIV282:%.*]] = udiv i32 [[SUB281]], 64
-// CHECK2-NEXT: [[MUL283:%.*]] = mul i32 1, [[DIV282]]
-// CHECK2-NEXT: [[TMP155:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP156:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB284:%.*]] = sub i32 [[TMP155]], [[TMP156]]
-// CHECK2-NEXT: [[SUB285:%.*]] = sub i32 [[SUB284]], 1
-// CHECK2-NEXT: [[ADD286:%.*]] = add i32 [[SUB285]], 1
-// CHECK2-NEXT: [[DIV287:%.*]] = udiv i32 [[ADD286]], 1
-// CHECK2-NEXT: [[MUL288:%.*]] = mul i32 [[MUL283]], [[DIV287]]
-// CHECK2-NEXT: [[CONV289:%.*]] = zext i32 [[MUL288]] to i64
-// CHECK2-NEXT: [[DIV290:%.*]] = sdiv i64 [[SUB280]], [[CONV289]]
-// CHECK2-NEXT: [[TMP157:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB291:%.*]] = sub i32 [[TMP157]], -63
-// CHECK2-NEXT: [[DIV292:%.*]] = udiv i32 [[SUB291]], 64
-// CHECK2-NEXT: [[MUL293:%.*]] = mul i32 1, [[DIV292]]
-// CHECK2-NEXT: [[TMP158:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP159:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB294:%.*]] = sub i32 [[TMP158]], [[TMP159]]
-// CHECK2-NEXT: [[SUB295:%.*]] = sub i32 [[SUB294]], 1
-// CHECK2-NEXT: [[ADD296:%.*]] = add i32 [[SUB295]], 1
-// CHECK2-NEXT: [[DIV297:%.*]] = udiv i32 [[ADD296]], 1
-// CHECK2-NEXT: [[MUL298:%.*]] = mul i32 [[MUL293]], [[DIV297]]
-// CHECK2-NEXT: [[CONV299:%.*]] = zext i32 [[MUL298]] to i64
-// CHECK2-NEXT: [[MUL300:%.*]] = mul nsw i64 [[DIV290]], [[CONV299]]
-// CHECK2-NEXT: [[SUB301:%.*]] = sub nsw i64 [[SUB249]], [[MUL300]]
-// CHECK2-NEXT: [[TMP160:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP161:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP162:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP163:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB302:%.*]] = sub i32 [[TMP162]], [[TMP163]]
-// CHECK2-NEXT: [[SUB303:%.*]] = sub i32 [[SUB302]], 1
-// CHECK2-NEXT: [[TMP164:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD304:%.*]] = add i32 [[SUB303]], [[TMP164]]
-// CHECK2-NEXT: [[TMP165:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV305:%.*]] = udiv i32 [[ADD304]], [[TMP165]]
-// CHECK2-NEXT: [[MUL306:%.*]] = mul i32 1, [[DIV305]]
-// CHECK2-NEXT: [[TMP166:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB307:%.*]] = sub i32 [[TMP166]], -63
-// CHECK2-NEXT: [[DIV308:%.*]] = udiv i32 [[SUB307]], 64
-// CHECK2-NEXT: [[MUL309:%.*]] = mul i32 [[MUL306]], [[DIV308]]
-// CHECK2-NEXT: [[TMP167:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP168:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB310:%.*]] = sub i32 [[TMP167]], [[TMP168]]
-// CHECK2-NEXT: [[SUB311:%.*]] = sub i32 [[SUB310]], 1
-// CHECK2-NEXT: [[ADD312:%.*]] = add i32 [[SUB311]], 1
-// CHECK2-NEXT: [[DIV313:%.*]] = udiv i32 [[ADD312]], 1
-// CHECK2-NEXT: [[MUL314:%.*]] = mul i32 [[MUL309]], [[DIV313]]
-// CHECK2-NEXT: [[CONV315:%.*]] = zext i32 [[MUL314]] to i64
-// CHECK2-NEXT: [[DIV316:%.*]] = sdiv i64 [[TMP161]], [[CONV315]]
-// CHECK2-NEXT: [[TMP169:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP170:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB317:%.*]] = sub i32 [[TMP169]], [[TMP170]]
-// CHECK2-NEXT: [[SUB318:%.*]] = sub i32 [[SUB317]], 1
-// CHECK2-NEXT: [[TMP171:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD319:%.*]] = add i32 [[SUB318]], [[TMP171]]
-// CHECK2-NEXT: [[TMP172:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV320:%.*]] = udiv i32 [[ADD319]], [[TMP172]]
-// CHECK2-NEXT: [[MUL321:%.*]] = mul i32 1, [[DIV320]]
-// CHECK2-NEXT: [[TMP173:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB322:%.*]] = sub i32 [[TMP173]], -63
-// CHECK2-NEXT: [[DIV323:%.*]] = udiv i32 [[SUB322]], 64
-// CHECK2-NEXT: [[MUL324:%.*]] = mul i32 [[MUL321]], [[DIV323]]
-// CHECK2-NEXT: [[TMP174:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP175:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB325:%.*]] = sub i32 [[TMP174]], [[TMP175]]
-// CHECK2-NEXT: [[SUB326:%.*]] = sub i32 [[SUB325]], 1
-// CHECK2-NEXT: [[ADD327:%.*]] = add i32 [[SUB326]], 1
-// CHECK2-NEXT: [[DIV328:%.*]] = udiv i32 [[ADD327]], 1
-// CHECK2-NEXT: [[MUL329:%.*]] = mul i32 [[MUL324]], [[DIV328]]
-// CHECK2-NEXT: [[CONV330:%.*]] = zext i32 [[MUL329]] to i64
-// CHECK2-NEXT: [[MUL331:%.*]] = mul nsw i64 [[DIV316]], [[CONV330]]
-// CHECK2-NEXT: [[SUB332:%.*]] = sub nsw i64 [[TMP160]], [[MUL331]]
-// CHECK2-NEXT: [[TMP176:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP177:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP178:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP179:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB333:%.*]] = sub i32 [[TMP178]], [[TMP179]]
-// CHECK2-NEXT: [[SUB334:%.*]] = sub i32 [[SUB333]], 1
-// CHECK2-NEXT: [[TMP180:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD335:%.*]] = add i32 [[SUB334]], [[TMP180]]
-// CHECK2-NEXT: [[TMP181:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV336:%.*]] = udiv i32 [[ADD335]], [[TMP181]]
-// CHECK2-NEXT: [[MUL337:%.*]] = mul i32 1, [[DIV336]]
-// CHECK2-NEXT: [[TMP182:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB338:%.*]] = sub i32 [[TMP182]], -63
-// CHECK2-NEXT: [[DIV339:%.*]] = udiv i32 [[SUB338]], 64
-// CHECK2-NEXT: [[MUL340:%.*]] = mul i32 [[MUL337]], [[DIV339]]
-// CHECK2-NEXT: [[TMP183:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP184:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB341:%.*]] = sub i32 [[TMP183]], [[TMP184]]
-// CHECK2-NEXT: [[SUB342:%.*]] = sub i32 [[SUB341]], 1
-// CHECK2-NEXT: [[ADD343:%.*]] = add i32 [[SUB342]], 1
-// CHECK2-NEXT: [[DIV344:%.*]] = udiv i32 [[ADD343]], 1
-// CHECK2-NEXT: [[MUL345:%.*]] = mul i32 [[MUL340]], [[DIV344]]
-// CHECK2-NEXT: [[CONV346:%.*]] = zext i32 [[MUL345]] to i64
-// CHECK2-NEXT: [[DIV347:%.*]] = sdiv i64 [[TMP177]], [[CONV346]]
-// CHECK2-NEXT: [[TMP185:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
-// CHECK2-NEXT: [[TMP186:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
-// CHECK2-NEXT: [[SUB348:%.*]] = sub i32 [[TMP185]], [[TMP186]]
-// CHECK2-NEXT: [[SUB349:%.*]] = sub i32 [[SUB348]], 1
-// CHECK2-NEXT: [[TMP187:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[ADD350:%.*]] = add i32 [[SUB349]], [[TMP187]]
-// CHECK2-NEXT: [[TMP188:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
-// CHECK2-NEXT: [[DIV351:%.*]] = udiv i32 [[ADD350]], [[TMP188]]
-// CHECK2-NEXT: [[MUL352:%.*]] = mul i32 1, [[DIV351]]
-// CHECK2-NEXT: [[TMP189:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB353:%.*]] = sub i32 [[TMP189]], -63
-// CHECK2-NEXT: [[DIV354:%.*]] = udiv i32 [[SUB353]], 64
-// CHECK2-NEXT: [[MUL355:%.*]] = mul i32 [[MUL352]], [[DIV354]]
-// CHECK2-NEXT: [[TMP190:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP191:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB356:%.*]] = sub i32 [[TMP190]], [[TMP191]]
-// CHECK2-NEXT: [[SUB357:%.*]] = sub i32 [[SUB356]], 1
-// CHECK2-NEXT: [[ADD358:%.*]] = add i32 [[SUB357]], 1
-// CHECK2-NEXT: [[DIV359:%.*]] = udiv i32 [[ADD358]], 1
-// CHECK2-NEXT: [[MUL360:%.*]] = mul i32 [[MUL355]], [[DIV359]]
-// CHECK2-NEXT: [[CONV361:%.*]] = zext i32 [[MUL360]] to i64
-// CHECK2-NEXT: [[MUL362:%.*]] = mul nsw i64 [[DIV347]], [[CONV361]]
-// CHECK2-NEXT: [[SUB363:%.*]] = sub nsw i64 [[TMP176]], [[MUL362]]
-// CHECK2-NEXT: [[TMP192:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB364:%.*]] = sub i32 [[TMP192]], -63
-// CHECK2-NEXT: [[DIV365:%.*]] = udiv i32 [[SUB364]], 64
-// CHECK2-NEXT: [[MUL366:%.*]] = mul i32 1, [[DIV365]]
-// CHECK2-NEXT: [[TMP193:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP194:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB367:%.*]] = sub i32 [[TMP193]], [[TMP194]]
-// CHECK2-NEXT: [[SUB368:%.*]] = sub i32 [[SUB367]], 1
-// CHECK2-NEXT: [[ADD369:%.*]] = add i32 [[SUB368]], 1
-// CHECK2-NEXT: [[DIV370:%.*]] = udiv i32 [[ADD369]], 1
-// CHECK2-NEXT: [[MUL371:%.*]] = mul i32 [[MUL366]], [[DIV370]]
-// CHECK2-NEXT: [[CONV372:%.*]] = zext i32 [[MUL371]] to i64
-// CHECK2-NEXT: [[DIV373:%.*]] = sdiv i64 [[SUB363]], [[CONV372]]
-// CHECK2-NEXT: [[TMP195:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
-// CHECK2-NEXT: [[SUB374:%.*]] = sub i32 [[TMP195]], -63
-// CHECK2-NEXT: [[DIV375:%.*]] = udiv i32 [[SUB374]], 64
-// CHECK2-NEXT: [[MUL376:%.*]] = mul i32 1, [[DIV375]]
-// CHECK2-NEXT: [[TMP196:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP197:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB377:%.*]] = sub i32 [[TMP196]], [[TMP197]]
-// CHECK2-NEXT: [[SUB378:%.*]] = sub i32 [[SUB377]], 1
-// CHECK2-NEXT: [[ADD379:%.*]] = add i32 [[SUB378]], 1
-// CHECK2-NEXT: [[DIV380:%.*]] = udiv i32 [[ADD379]], 1
-// CHECK2-NEXT: [[MUL381:%.*]] = mul i32 [[MUL376]], [[DIV380]]
-// CHECK2-NEXT: [[CONV382:%.*]] = zext i32 [[MUL381]] to i64
-// CHECK2-NEXT: [[MUL383:%.*]] = mul nsw i64 [[DIV373]], [[CONV382]]
-// CHECK2-NEXT: [[SUB384:%.*]] = sub nsw i64 [[SUB332]], [[MUL383]]
-// CHECK2-NEXT: [[TMP198:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP199:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB385:%.*]] = sub i32 [[TMP198]], [[TMP199]]
-// CHECK2-NEXT: [[SUB386:%.*]] = sub i32 [[SUB385]], 1
-// CHECK2-NEXT: [[ADD387:%.*]] = add i32 [[SUB386]], 1
-// CHECK2-NEXT: [[DIV388:%.*]] = udiv i32 [[ADD387]], 1
-// CHECK2-NEXT: [[MUL389:%.*]] = mul i32 1, [[DIV388]]
-// CHECK2-NEXT: [[CONV390:%.*]] = zext i32 [[MUL389]] to i64
-// CHECK2-NEXT: [[DIV391:%.*]] = sdiv i64 [[SUB384]], [[CONV390]]
-// CHECK2-NEXT: [[TMP200:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
-// CHECK2-NEXT: [[TMP201:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
-// CHECK2-NEXT: [[SUB392:%.*]] = sub i32 [[TMP200]], [[TMP201]]
-// CHECK2-NEXT: [[SUB393:%.*]] = sub i32 [[SUB392]], 1
-// CHECK2-NEXT: [[ADD394:%.*]] = add i32 [[SUB393]], 1
-// CHECK2-NEXT: [[DIV395:%.*]] = udiv i32 [[ADD394]], 1
-// CHECK2-NEXT: [[MUL396:%.*]] = mul i32 1, [[DIV395]]
-// CHECK2-NEXT: [[CONV397:%.*]] = zext i32 [[MUL396]] to i64
-// CHECK2-NEXT: [[MUL398:%.*]] = mul nsw i64 [[DIV391]], [[CONV397]]
-// CHECK2-NEXT: [[SUB399:%.*]] = sub nsw i64 [[SUB301]], [[MUL398]]
-// CHECK2-NEXT: [[MUL400:%.*]] = mul nsw i64 [[SUB399]], 1
-// CHECK2-NEXT: [[ADD401:%.*]] = add nsw i64 [[CONV218]], [[MUL400]]
-// CHECK2-NEXT: [[CONV402:%.*]] = trunc i64 [[ADD401]] to i32
-// CHECK2-NEXT: store i32 [[CONV402]], ptr [[DOTTILE_0_IV_K52]], align 4
-// CHECK2-NEXT: [[TMP202:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4
-// CHECK2-NEXT: [[TMP203:%.*]] = load i32, ptr [[DOTTILE_0_IV_K52]], align 4
-// CHECK2-NEXT: [[TMP204:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4
-// CHECK2-NEXT: [[MUL403:%.*]] = mul i32 [[TMP203]], [[TMP204]]
-// CHECK2-NEXT: [[ADD404:%.*]] = add i32 [[TMP202]], [[MUL403]]
-// CHECK2-NEXT: store i32 [[ADD404]], ptr [[K]], align 4
-// CHECK2-NEXT: [[TMP205:%.*]] = load i32, ptr [[I49]], align 4
-// CHECK2-NEXT: [[TMP206:%.*]] = load i32, ptr [[J50]], align 4
-// CHECK2-NEXT: [[TMP207:%.*]] = load i32, ptr [[K]], align 4
-// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP205]], i32 noundef [[TMP206]], i32 noundef [[TMP207]])
-// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK2-NEXT: [[MUL272:%.*]] = mul i32 1, [[DIV271]]
+// CHECK2-NEXT: [[MUL273:%.*]] = mul i32 [[MUL272]], 64
+// CHECK2-NEXT: [[CONV274:%.*]] = zext i32 [[MUL273]] to i64
+// CHECK2-NEXT: [[MUL275:%.*]] = mul nsw i64 [[DIV269]], [[CONV274]]
+// CHECK2-NEXT: [[SUB276:%.*]] = sub nsw i64 [[SUB240]], [[MUL275]]
+// CHECK2-NEXT: [[DIV277:%.*]] = sdiv i64 [[SUB276]], 64
+// CHECK2-NEXT: [[MUL278:%.*]] = mul nsw i64 [[DIV277]], 64
+// CHECK2-NEXT: [[SUB279:%.*]] = sub nsw i64 [[SUB217]], [[MUL278]]
+// CHECK2-NEXT: [[MUL280:%.*]] = mul nsw i64 [[SUB279]], 1
+// CHECK2-NEXT: [[ADD281:%.*]] = add nsw i64 [[CONV158]], [[MUL280]]
+// CHECK2-NEXT: [[CONV282:%.*]] = trunc i64 [[ADD281]] to i32
+// CHECK2-NEXT: store i32 [[CONV282]], ptr [[DOTTILE_0_IV_K42]], align 4
+// CHECK2-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTTILE_0_IV_K42]], align 4
+// CHECK2-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
+// CHECK2-NEXT: [[ADD283:%.*]] = add i32 [[TMP146]], 1
+// CHECK2-NEXT: [[CMP284:%.*]] = icmp ult i32 [[TMP145]], [[ADD283]]
+// CHECK2-NEXT: br i1 [[CMP284]], label [[OMP_BODY_NEXT:%.*]], label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK2: omp.body.next:
+// CHECK2-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4
+// CHECK2-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTTILE_0_IV_K42]], align 4
+// CHECK2-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4
+// CHECK2-NEXT: [[MUL285:%.*]] = mul i32 [[TMP148]], [[TMP149]]
+// CHECK2-NEXT: [[ADD286:%.*]] = add i32 [[TMP147]], [[MUL285]]
+// CHECK2-NEXT: store i32 [[ADD286]], ptr [[K]], align 4
+// CHECK2-NEXT: [[TMP150:%.*]] = load i32, ptr [[I39]], align 4
+// CHECK2-NEXT: [[TMP151:%.*]] = load i32, ptr [[J40]], align 4
+// CHECK2-NEXT: [[TMP152:%.*]] = load i32, ptr [[K]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP150]], i32 noundef [[TMP151]], i32 noundef [[TMP152]])
+// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP208:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[ADD405:%.*]] = add nsw i64 [[TMP208]], 1
-// CHECK2-NEXT: store i64 [[ADD405]], ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP153:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[ADD287:%.*]] = add nsw i64 [[TMP153]], 1
+// CHECK2-NEXT: store i64 [[ADD287]], ptr [[DOTOMP_IV]], align 8
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK2: omp.inner.for.end:
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
@@ -5321,4 +4626,4 @@ extern "C" void foo10() {
// CHECK2: omp.precond.end:
// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
// CHECK2-NEXT: ret void
-
+//
diff --git a/clang/test/OpenMP/tile_codegen.cpp b/clang/test/OpenMP/tile_codegen.cpp
index 85b004dc73f4f..6ec808d67e389 100644
--- a/clang/test/OpenMP/tile_codegen.cpp
+++ b/clang/test/OpenMP/tile_codegen.cpp
@@ -174,9 +174,9 @@ extern "C" void foo10(data_t data) {
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 3
// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 7, [[MUL]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[I2]], align 8
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[I2]], align 8, !nonnull [[META2:![0-9]+]], !align [[META3:![0-9]+]]
// CHECK1-NEXT: store i32 [[ADD9]], ptr [[TMP6]], align 4
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[I2]], align 8
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[I2]], align 8, !nonnull [[META2]], !align [[META3]]
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP8]])
// CHECK1-NEXT: br label [[FOR_INC:%.*]]
@@ -184,14 +184,14 @@ extern "C" void foo10(data_t data) {
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP3:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]]
// CHECK1: for.end:
// CHECK1-NEXT: br label [[FOR_INC10:%.*]]
// CHECK1: for.inc10:
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP10]], 5
// CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTFLOOR_0_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
// CHECK1: for.end12:
// CHECK1-NEXT: ret void
//
@@ -276,14 +276,14 @@ extern "C" void foo10(data_t data) {
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
// CHECK1-NEXT: [[INC:%.*]] = add i32 [[TMP20]], 1
// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP6:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP7:![0-9]+]]
// CHECK1: for.end:
// CHECK1-NEXT: br label [[FOR_INC15:%.*]]
// CHECK1: for.inc15:
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
// CHECK1-NEXT: [[ADD16:%.*]] = add i32 [[TMP21]], 5
// CHECK1-NEXT: store i32 [[ADD16]], ptr [[DOTFLOOR_0_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
// CHECK1: for.end17:
// CHECK1-NEXT: ret void
//
@@ -375,28 +375,28 @@ extern "C" void foo10(data_t data) {
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1
// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTTILE_1_IV_J]], align 4
-// CHECK1-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]]
// CHECK1: for.end:
// CHECK1-NEXT: br label [[FOR_INC22:%.*]]
// CHECK1: for.inc22:
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
// CHECK1-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1
// CHECK1-NEXT: store i32 [[INC23]], ptr [[DOTTILE_0_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP9:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP10:![0-9]+]]
// CHECK1: for.end24:
// CHECK1-NEXT: br label [[FOR_INC25:%.*]]
// CHECK1: for.inc25:
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4
// CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP16]], 5
// CHECK1-NEXT: store i32 [[ADD26]], ptr [[DOTFLOOR_1_IV_J]], align 4
-// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP10:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP11:![0-9]+]]
// CHECK1: for.end27:
// CHECK1-NEXT: br label [[FOR_INC28:%.*]]
// CHECK1: for.inc28:
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP17]], 5
// CHECK1-NEXT: store i32 [[ADD29]], ptr [[DOTFLOOR_0_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
// CHECK1: for.end30:
// CHECK1-NEXT: ret void
//
@@ -511,21 +511,21 @@ extern "C" void foo10(data_t data) {
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTTILE_1_IV_J]], align 4
-// CHECK1-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP12:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP13:![0-9]+]]
// CHECK1: for.end:
// CHECK1-NEXT: br label [[FOR_INC27:%.*]]
// CHECK1: for.inc27:
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
// CHECK1-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP21]], 1
// CHECK1-NEXT: store i32 [[INC28]], ptr [[DOTTILE_0_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP13:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP14:![0-9]+]]
// CHECK1: for.end29:
// CHECK1-NEXT: br label [[FOR_INC30:%.*]]
// CHECK1: for.inc30:
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4
// CHECK1-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP22]], 5
// CHECK1-NEXT: store i32 [[ADD31]], ptr [[DOTFLOOR_1_IV_J]], align 4
-// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
// CHECK1: for.end32:
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
@@ -664,21 +664,21 @@ extern "C" void foo10(data_t data) {
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP22]], 1
// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTTILE_1_IV_J]], align 4
-// CHECK1-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP15:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP16:![0-9]+]]
// CHECK1: for.end:
// CHECK1-NEXT: br label [[FOR_INC32:%.*]]
// CHECK1: for.inc32:
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
// CHECK1-NEXT: [[INC33:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK1-NEXT: store i32 [[INC33]], ptr [[DOTTILE_0_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP16:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP17:![0-9]+]]
// CHECK1: for.end34:
// CHECK1-NEXT: br label [[FOR_INC35:%.*]]
// CHECK1: for.inc35:
// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4
// CHECK1-NEXT: [[ADD36:%.*]] = add nsw i32 [[TMP24]], 5
// CHECK1-NEXT: store i32 [[ADD36]], ptr [[DOTFLOOR_1_IV_J]], align 4
-// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
// CHECK1: for.end37:
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
@@ -699,208 +699,106 @@ extern "C" void foo10(data_t data) {
// CHECK1-LABEL: define dso_local void @foo5(
// CHECK1-SAME: ) #[[ATTR0]] {
// CHECK1-NEXT: entry:
-// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
-// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
-// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
-// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTFLOOR_0_IV_I11:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTTILE_0_IV_I12:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[J13:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
// CHECK1-NEXT: store i32 7, ptr [[I]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 5
-// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 4, [[ADD]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTCAPTURE_EXPR_3]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
+// CHECK1-NEXT: store i32 19, ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK1: cond.true:
// CHECK1-NEXT: br label [[COND_END:%.*]]
// CHECK1: cond.false:
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP]], align 4
-// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 5
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// CHECK1-NEXT: br label [[COND_END]]
// CHECK1: cond.end:
-// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[ADD4]], [[COND_FALSE]] ]
-// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_3]], align 4
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP4]], [[TMP5]]
-// CHECK1-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1
-// CHECK1-NEXT: [[ADD7:%.*]] = add i32 [[SUB6]], 1
-// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD7]], 1
-// CHECK1-NEXT: [[CONV:%.*]] = zext i32 [[DIV]] to i64
-// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 1, [[CONV]]
-// CHECK1-NEXT: [[MUL8:%.*]] = mul nsw i64 [[MUL]], 4
-// CHECK1-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL8]], 1
-// CHECK1-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8
-// CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 4
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTTILE_0_IV_I]], align 4
-// CHECK1-NEXT: store i32 7, ptr [[J]], align 4
-// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
-// CHECK1-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]]
-// CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// CHECK1: omp.precond.then:
-// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
-// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8
-// CHECK1-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 8
-// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
-// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8
-// CHECK1-NEXT: [[CMP14:%.*]] = icmp sgt i64 [[TMP10]], [[TMP11]]
-// CHECK1-NEXT: br i1 [[CMP14]], label [[COND_TRUE15:%.*]], label [[COND_FALSE16:%.*]]
-// CHECK1: cond.true15:
-// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8
-// CHECK1-NEXT: br label [[COND_END17:%.*]]
-// CHECK1: cond.false16:
-// CHECK1-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK1-NEXT: br label [[COND_END17]]
-// CHECK1: cond.end17:
-// CHECK1-NEXT: [[COND18:%.*]] = phi i64 [ [[TMP12]], [[COND_TRUE15]] ], [ [[TMP13]], [[COND_FALSE16]] ]
-// CHECK1-NEXT: store i64 [[COND18]], ptr [[DOTOMP_UB]], align 8
-// CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
-// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
+// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK1-NEXT: [[CMP19:%.*]] = icmp sle i64 [[TMP15]], [[TMP16]]
-// CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
+// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[SUB20:%.*]] = sub i32 [[TMP18]], [[TMP19]]
-// CHECK1-NEXT: [[SUB21:%.*]] = sub i32 [[SUB20]], 1
-// CHECK1-NEXT: [[ADD22:%.*]] = add i32 [[SUB21]], 1
-// CHECK1-NEXT: [[DIV23:%.*]] = udiv i32 [[ADD22]], 1
-// CHECK1-NEXT: [[MUL24:%.*]] = mul i32 1, [[DIV23]]
-// CHECK1-NEXT: [[MUL25:%.*]] = mul i32 [[MUL24]], 4
-// CHECK1-NEXT: [[CONV26:%.*]] = zext i32 [[MUL25]] to i64
-// CHECK1-NEXT: [[DIV27:%.*]] = sdiv i64 [[TMP17]], [[CONV26]]
-// CHECK1-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV27]], 5
-// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i64 0, [[MUL28]]
-// CHECK1-NEXT: [[CONV30:%.*]] = trunc i64 [[ADD29]] to i32
-// CHECK1-NEXT: store i32 [[CONV30]], ptr [[DOTFLOOR_0_IV_I11]], align 4
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[CONV31:%.*]] = sext i32 [[TMP20]] to i64
-// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
-// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[SUB32:%.*]] = sub i32 [[TMP23]], [[TMP24]]
-// CHECK1-NEXT: [[SUB33:%.*]] = sub i32 [[SUB32]], 1
-// CHECK1-NEXT: [[ADD34:%.*]] = add i32 [[SUB33]], 1
-// CHECK1-NEXT: [[DIV35:%.*]] = udiv i32 [[ADD34]], 1
-// CHECK1-NEXT: [[MUL36:%.*]] = mul i32 1, [[DIV35]]
-// CHECK1-NEXT: [[MUL37:%.*]] = mul i32 [[MUL36]], 4
-// CHECK1-NEXT: [[CONV38:%.*]] = zext i32 [[MUL37]] to i64
-// CHECK1-NEXT: [[DIV39:%.*]] = sdiv i64 [[TMP22]], [[CONV38]]
-// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
-// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[SUB40:%.*]] = sub i32 [[TMP25]], [[TMP26]]
-// CHECK1-NEXT: [[SUB41:%.*]] = sub i32 [[SUB40]], 1
-// CHECK1-NEXT: [[ADD42:%.*]] = add i32 [[SUB41]], 1
-// CHECK1-NEXT: [[DIV43:%.*]] = udiv i32 [[ADD42]], 1
-// CHECK1-NEXT: [[MUL44:%.*]] = mul i32 1, [[DIV43]]
-// CHECK1-NEXT: [[MUL45:%.*]] = mul i32 [[MUL44]], 4
-// CHECK1-NEXT: [[CONV46:%.*]] = zext i32 [[MUL45]] to i64
-// CHECK1-NEXT: [[MUL47:%.*]] = mul nsw i64 [[DIV39]], [[CONV46]]
-// CHECK1-NEXT: [[SUB48:%.*]] = sub nsw i64 [[TMP21]], [[MUL47]]
-// CHECK1-NEXT: [[DIV49:%.*]] = sdiv i64 [[SUB48]], 4
-// CHECK1-NEXT: [[MUL50:%.*]] = mul nsw i64 [[DIV49]], 1
-// CHECK1-NEXT: [[ADD51:%.*]] = add nsw i64 [[CONV31]], [[MUL50]]
-// CHECK1-NEXT: [[CONV52:%.*]] = trunc i64 [[ADD51]] to i32
-// CHECK1-NEXT: store i32 [[CONV52]], ptr [[DOTTILE_0_IV_I12]], align 4
-// CHECK1-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
-// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[SUB53:%.*]] = sub i32 [[TMP29]], [[TMP30]]
-// CHECK1-NEXT: [[SUB54:%.*]] = sub i32 [[SUB53]], 1
-// CHECK1-NEXT: [[ADD55:%.*]] = add i32 [[SUB54]], 1
-// CHECK1-NEXT: [[DIV56:%.*]] = udiv i32 [[ADD55]], 1
-// CHECK1-NEXT: [[MUL57:%.*]] = mul i32 1, [[DIV56]]
-// CHECK1-NEXT: [[MUL58:%.*]] = mul i32 [[MUL57]], 4
-// CHECK1-NEXT: [[CONV59:%.*]] = zext i32 [[MUL58]] to i64
-// CHECK1-NEXT: [[DIV60:%.*]] = sdiv i64 [[TMP28]], [[CONV59]]
-// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
-// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[SUB61:%.*]] = sub i32 [[TMP31]], [[TMP32]]
-// CHECK1-NEXT: [[SUB62:%.*]] = sub i32 [[SUB61]], 1
-// CHECK1-NEXT: [[ADD63:%.*]] = add i32 [[SUB62]], 1
-// CHECK1-NEXT: [[DIV64:%.*]] = udiv i32 [[ADD63]], 1
-// CHECK1-NEXT: [[MUL65:%.*]] = mul i32 1, [[DIV64]]
-// CHECK1-NEXT: [[MUL66:%.*]] = mul i32 [[MUL65]], 4
-// CHECK1-NEXT: [[CONV67:%.*]] = zext i32 [[MUL66]] to i64
-// CHECK1-NEXT: [[MUL68:%.*]] = mul nsw i64 [[DIV60]], [[CONV67]]
-// CHECK1-NEXT: [[SUB69:%.*]] = sub nsw i64 [[TMP27]], [[MUL68]]
-// CHECK1-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
-// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[SUB70:%.*]] = sub i32 [[TMP35]], [[TMP36]]
-// CHECK1-NEXT: [[SUB71:%.*]] = sub i32 [[SUB70]], 1
-// CHECK1-NEXT: [[ADD72:%.*]] = add i32 [[SUB71]], 1
-// CHECK1-NEXT: [[DIV73:%.*]] = udiv i32 [[ADD72]], 1
-// CHECK1-NEXT: [[MUL74:%.*]] = mul i32 1, [[DIV73]]
-// CHECK1-NEXT: [[MUL75:%.*]] = mul i32 [[MUL74]], 4
-// CHECK1-NEXT: [[CONV76:%.*]] = zext i32 [[MUL75]] to i64
-// CHECK1-NEXT: [[DIV77:%.*]] = sdiv i64 [[TMP34]], [[CONV76]]
-// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
-// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[SUB78:%.*]] = sub i32 [[TMP37]], [[TMP38]]
-// CHECK1-NEXT: [[SUB79:%.*]] = sub i32 [[SUB78]], 1
-// CHECK1-NEXT: [[ADD80:%.*]] = add i32 [[SUB79]], 1
-// CHECK1-NEXT: [[DIV81:%.*]] = udiv i32 [[ADD80]], 1
-// CHECK1-NEXT: [[MUL82:%.*]] = mul i32 1, [[DIV81]]
-// CHECK1-NEXT: [[MUL83:%.*]] = mul i32 [[MUL82]], 4
-// CHECK1-NEXT: [[CONV84:%.*]] = zext i32 [[MUL83]] to i64
-// CHECK1-NEXT: [[MUL85:%.*]] = mul nsw i64 [[DIV77]], [[CONV84]]
-// CHECK1-NEXT: [[SUB86:%.*]] = sub nsw i64 [[TMP33]], [[MUL85]]
-// CHECK1-NEXT: [[DIV87:%.*]] = sdiv i64 [[SUB86]], 4
-// CHECK1-NEXT: [[MUL88:%.*]] = mul nsw i64 [[DIV87]], 4
-// CHECK1-NEXT: [[SUB89:%.*]] = sub nsw i64 [[SUB69]], [[MUL88]]
-// CHECK1-NEXT: [[MUL90:%.*]] = mul nsw i64 [[SUB89]], 3
-// CHECK1-NEXT: [[ADD91:%.*]] = add nsw i64 7, [[MUL90]]
-// CHECK1-NEXT: [[CONV92:%.*]] = trunc i64 [[ADD91]] to i32
-// CHECK1-NEXT: store i32 [[CONV92]], ptr [[J13]], align 4
-// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTTILE_0_IV_I12]], align 4
-// CHECK1-NEXT: [[MUL93:%.*]] = mul nsw i32 [[TMP39]], 3
-// CHECK1-NEXT: [[ADD94:%.*]] = add nsw i32 7, [[MUL93]]
-// CHECK1-NEXT: store i32 [[ADD94]], ptr [[I]], align 4
-// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[I]], align 4
-// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[J13]], align 4
-// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP40]], i32 noundef [[TMP41]])
-// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 20
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 5
+// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTFLOOR_0_IV_I]], align 4
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[DIV6:%.*]] = sdiv i32 [[TMP11]], 20
+// CHECK1-NEXT: [[MUL7:%.*]] = mul nsw i32 [[DIV6]], 20
+// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP10]], [[MUL7]]
+// CHECK1-NEXT: [[DIV8:%.*]] = sdiv i32 [[SUB]], 4
+// CHECK1-NEXT: [[MUL9:%.*]] = mul nsw i32 [[DIV8]], 1
+// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP9]], [[MUL9]]
+// CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTTILE_0_IV_I]], align 4
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[DIV11:%.*]] = sdiv i32 [[TMP13]], 20
+// CHECK1-NEXT: [[MUL12:%.*]] = mul nsw i32 [[DIV11]], 20
+// CHECK1-NEXT: [[SUB13:%.*]] = sub nsw i32 [[TMP12]], [[MUL12]]
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[DIV14:%.*]] = sdiv i32 [[TMP15]], 20
+// CHECK1-NEXT: [[MUL15:%.*]] = mul nsw i32 [[DIV14]], 20
+// CHECK1-NEXT: [[SUB16:%.*]] = sub nsw i32 [[TMP14]], [[MUL15]]
+// CHECK1-NEXT: [[DIV17:%.*]] = sdiv i32 [[SUB16]], 4
+// CHECK1-NEXT: [[MUL18:%.*]] = mul nsw i32 [[DIV17]], 4
+// CHECK1-NEXT: [[SUB19:%.*]] = sub nsw i32 [[SUB13]], [[MUL18]]
+// CHECK1-NEXT: [[MUL20:%.*]] = mul nsw i32 [[SUB19]], 3
+// CHECK1-NEXT: [[ADD21:%.*]] = add nsw i32 7, [[MUL20]]
+// CHECK1-NEXT: store i32 [[ADD21]], ptr [[J]], align 4
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
+// CHECK1-NEXT: [[CMP22:%.*]] = icmp slt i32 [[TMP16]], 4
+// CHECK1-NEXT: br i1 [[CMP22]], label [[OMP_BODY_NEXT:%.*]], label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK1: omp.body.next:
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
+// CHECK1-NEXT: [[MUL23:%.*]] = mul nsw i32 [[TMP17]], 3
+// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 7, [[MUL23]]
+// CHECK1-NEXT: store i32 [[ADD24]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[J]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP18]], i32 noundef [[TMP19]])
+// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK1-NEXT: [[ADD95:%.*]] = add nsw i64 [[TMP42]], 1
-// CHECK1-NEXT: store i64 [[ADD95]], ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP20]], 1
+// CHECK1-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])
-// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
-// CHECK1: omp.precond.end:
// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
// CHECK1-NEXT: ret void
//
@@ -991,7 +889,7 @@ extern "C" void foo10(data_t data) {
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1
// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
// CHECK1: for.end:
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
@@ -1087,14 +985,14 @@ extern "C" void foo10(data_t data) {
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
// CHECK1-NEXT: [[INC:%.*]] = add i32 [[TMP16]], 1
// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP21:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP22:![0-9]+]]
// CHECK1: for.end:
// CHECK1-NEXT: br label [[FOR_INC15:%.*]]
// CHECK1: for.inc15:
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
// CHECK1-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 5
// CHECK1-NEXT: store i32 [[ADD16]], ptr [[DOTFLOOR_0_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
// CHECK1: for.end17:
// CHECK1-NEXT: ret void
//
@@ -1166,7 +1064,7 @@ extern "C" void foo10(data_t data) {
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP23:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP24:![0-9]+]]
// CHECK1: for.end:
// CHECK1-NEXT: br label [[FOR_INC17:%.*]]
// CHECK1: for.inc17:
@@ -1183,7 +1081,7 @@ extern "C" void foo10(data_t data) {
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
// CHECK1-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP14]], [[COND22]]
// CHECK1-NEXT: store i32 [[ADD23]], ptr [[DOTFLOOR_0_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
// CHECK1: for.end24:
// CHECK1-NEXT: ret void
//
@@ -1202,14 +1100,14 @@ extern "C" void foo10(data_t data) {
// CHECK1-NEXT: [[V:%.*]] = alloca double, align 8
// CHECK1-NEXT: [[ARRAY:%.*]] = getelementptr inbounds nuw [[STRUCT_DATA_T]], ptr [[DATA]], i32 0, i32 0
// CHECK1-NEXT: store ptr [[ARRAY]], ptr [[__RANGE2]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META26:![0-9]+]]
// CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP0]], i64 0, i64 0
// CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 12
// CHECK1-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META26]]
// CHECK1-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP1]], i64 0, i64 0
// CHECK1-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META26]]
// CHECK1-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP2]], i64 0, i64 0
// CHECK1-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 8
@@ -1273,14 +1171,14 @@ extern "C" void foo10(data_t data) {
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTTILE_0_IV___BEGIN2]], align 8
// CHECK1-NEXT: [[INC:%.*]] = add nsw i64 [[TMP19]], 1
// CHECK1-NEXT: store i64 [[INC]], ptr [[DOTTILE_0_IV___BEGIN2]], align 8
-// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP25:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP27:![0-9]+]]
// CHECK1: for.end:
// CHECK1-NEXT: br label [[FOR_INC16:%.*]]
// CHECK1: for.inc16:
// CHECK1-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 8
// CHECK1-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP20]], 5
// CHECK1-NEXT: store i64 [[ADD17]], ptr [[DOTFLOOR_0_IV___BEGIN2]], align 8
-// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
// CHECK1: for.end18:
// CHECK1-NEXT: ret void
//
@@ -1301,14 +1199,14 @@ extern "C" void foo10(data_t data) {
// CHECK1-NEXT: store double 4.200000e+01, ptr [[C]], align 8
// CHECK1-NEXT: [[ARRAY:%.*]] = getelementptr inbounds nuw [[STRUCT_DATA_T]], ptr [[DATA]], i32 0, i32 0
// CHECK1-NEXT: store ptr [[ARRAY]], ptr [[__RANGE2]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META26]]
// CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP0]], i64 0, i64 0
// CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 12
// CHECK1-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META26]]
// CHECK1-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP1]], i64 0, i64 0
// CHECK1-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META26]]
// CHECK1-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP2]], i64 0, i64 0
// CHECK1-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 8
@@ -1373,14 +1271,14 @@ extern "C" void foo10(data_t data) {
// CHECK1-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTTILE_0_IV___BEGIN2]], align 8
// CHECK1-NEXT: [[INC:%.*]] = add nsw i64 [[TMP20]], 1
// CHECK1-NEXT: store i64 [[INC]], ptr [[DOTTILE_0_IV___BEGIN2]], align 8
-// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP27:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP29:![0-9]+]]
// CHECK1: for.end:
// CHECK1-NEXT: br label [[FOR_INC16:%.*]]
// CHECK1: for.inc16:
// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 8
// CHECK1-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP21]], 5
// CHECK1-NEXT: store i64 [[ADD17]], ptr [[DOTFLOOR_0_IV___BEGIN2]], align 8
-// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
// CHECK1: for.end18:
// CHECK1-NEXT: ret void
//
@@ -1452,9 +1350,9 @@ extern "C" void foo10(data_t data) {
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 3
// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 7, [[MUL]]
-// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[I2]], align 8
+// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[I2]], align 8, !nonnull [[META2:![0-9]+]], !align [[META3:![0-9]+]]
// CHECK2-NEXT: store i32 [[ADD9]], ptr [[TMP6]], align 4
-// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[I2]], align 8
+// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[I2]], align 8, !nonnull [[META2]], !align [[META3]]
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP8]])
// CHECK2-NEXT: br label [[FOR_INC:%.*]]
@@ -1462,14 +1360,14 @@ extern "C" void foo10(data_t data) {
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP3:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]]
// CHECK2: for.end:
// CHECK2-NEXT: br label [[FOR_INC10:%.*]]
// CHECK2: for.inc10:
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP10]], 5
// CHECK2-NEXT: store i32 [[ADD11]], ptr [[DOTFLOOR_0_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
// CHECK2: for.end12:
// CHECK2-NEXT: ret void
//
@@ -1560,14 +1458,14 @@ extern "C" void foo10(data_t data) {
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
// CHECK2-NEXT: [[INC:%.*]] = add i32 [[TMP20]], 1
// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP6:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP7:![0-9]+]]
// CHECK2: for.end:
// CHECK2-NEXT: br label [[FOR_INC15:%.*]]
// CHECK2: for.inc15:
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
// CHECK2-NEXT: [[ADD16:%.*]] = add i32 [[TMP21]], 5
// CHECK2-NEXT: store i32 [[ADD16]], ptr [[DOTFLOOR_0_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
// CHECK2: for.end17:
// CHECK2-NEXT: ret void
//
@@ -1588,14 +1486,14 @@ extern "C" void foo10(data_t data) {
// CHECK2-NEXT: store double 4.200000e+01, ptr [[C]], align 8
// CHECK2-NEXT: [[ARRAY:%.*]] = getelementptr inbounds nuw [[STRUCT_DATA_T]], ptr [[DATA]], i32 0, i32 0
// CHECK2-NEXT: store ptr [[ARRAY]], ptr [[__RANGE2]], align 8
-// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META9:![0-9]+]]
// CHECK2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP0]], i64 0, i64 0
// CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 12
// CHECK2-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META9]]
// CHECK2-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP1]], i64 0, i64 0
// CHECK2-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META9]]
// CHECK2-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP2]], i64 0, i64 0
// CHECK2-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 8
@@ -1660,14 +1558,14 @@ extern "C" void foo10(data_t data) {
// CHECK2-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTTILE_0_IV___BEGIN2]], align 8
// CHECK2-NEXT: [[INC:%.*]] = add nsw i64 [[TMP20]], 1
// CHECK2-NEXT: store i64 [[INC]], ptr [[DOTTILE_0_IV___BEGIN2]], align 8
-// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP8:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP10:![0-9]+]]
// CHECK2: for.end:
// CHECK2-NEXT: br label [[FOR_INC16:%.*]]
// CHECK2: for.inc16:
// CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 8
// CHECK2-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP21]], 5
// CHECK2-NEXT: store i64 [[ADD17]], ptr [[DOTFLOOR_0_IV___BEGIN2]], align 8
-// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
// CHECK2: for.end18:
// CHECK2-NEXT: ret void
//
@@ -1759,28 +1657,28 @@ extern "C" void foo10(data_t data) {
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1
// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTTILE_1_IV_J]], align 4
-// CHECK2-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP10:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP12:![0-9]+]]
// CHECK2: for.end:
// CHECK2-NEXT: br label [[FOR_INC22:%.*]]
// CHECK2: for.inc22:
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
// CHECK2-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1
// CHECK2-NEXT: store i32 [[INC23]], ptr [[DOTTILE_0_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP11:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP13:![0-9]+]]
// CHECK2: for.end24:
// CHECK2-NEXT: br label [[FOR_INC25:%.*]]
// CHECK2: for.inc25:
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4
// CHECK2-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP16]], 5
// CHECK2-NEXT: store i32 [[ADD26]], ptr [[DOTFLOOR_1_IV_J]], align 4
-// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP12:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP14:![0-9]+]]
// CHECK2: for.end27:
// CHECK2-NEXT: br label [[FOR_INC28:%.*]]
// CHECK2: for.inc28:
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
// CHECK2-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP17]], 5
// CHECK2-NEXT: store i32 [[ADD29]], ptr [[DOTFLOOR_0_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
// CHECK2: for.end30:
// CHECK2-NEXT: ret void
//
@@ -1895,21 +1793,21 @@ extern "C" void foo10(data_t data) {
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTTILE_1_IV_J]], align 4
-// CHECK2-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP14:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP16:![0-9]+]]
// CHECK2: for.end:
// CHECK2-NEXT: br label [[FOR_INC27:%.*]]
// CHECK2: for.inc27:
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
// CHECK2-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP21]], 1
// CHECK2-NEXT: store i32 [[INC28]], ptr [[DOTTILE_0_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP15:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP17:![0-9]+]]
// CHECK2: for.end29:
// CHECK2-NEXT: br label [[FOR_INC30:%.*]]
// CHECK2: for.inc30:
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4
// CHECK2-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP22]], 5
// CHECK2-NEXT: store i32 [[ADD31]], ptr [[DOTFLOOR_1_IV_J]], align 4
-// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
// CHECK2: for.end32:
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
@@ -2048,21 +1946,21 @@ extern "C" void foo10(data_t data) {
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP22]], 1
// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTTILE_1_IV_J]], align 4
-// CHECK2-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP17:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP19:![0-9]+]]
// CHECK2: for.end:
// CHECK2-NEXT: br label [[FOR_INC32:%.*]]
// CHECK2: for.inc32:
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
// CHECK2-NEXT: [[INC33:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK2-NEXT: store i32 [[INC33]], ptr [[DOTTILE_0_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP18:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP20:![0-9]+]]
// CHECK2: for.end34:
// CHECK2-NEXT: br label [[FOR_INC35:%.*]]
// CHECK2: for.inc35:
// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4
// CHECK2-NEXT: [[ADD36:%.*]] = add nsw i32 [[TMP24]], 5
// CHECK2-NEXT: store i32 [[ADD36]], ptr [[DOTFLOOR_1_IV_J]], align 4
-// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
// CHECK2: for.end37:
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
@@ -2083,208 +1981,106 @@ extern "C" void foo10(data_t data) {
// CHECK2-LABEL: define dso_local void @foo5(
// CHECK2-SAME: ) #[[ATTR1]] {
// CHECK2-NEXT: entry:
-// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
-// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
-// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
-// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTFLOOR_0_IV_I11:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTTILE_0_IV_I12:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[J13:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
// CHECK2-NEXT: store i32 7, ptr [[I]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 5
-// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 4, [[ADD]]
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[DOTCAPTURE_EXPR_3]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
+// CHECK2-NEXT: store i32 19, ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK2: cond.true:
// CHECK2-NEXT: br label [[COND_END:%.*]]
// CHECK2: cond.false:
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP]], align 4
-// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 5
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// CHECK2-NEXT: br label [[COND_END]]
// CHECK2: cond.end:
-// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[ADD4]], [[COND_FALSE]] ]
-// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_3]], align 4
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
-// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP4]], [[TMP5]]
-// CHECK2-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1
-// CHECK2-NEXT: [[ADD7:%.*]] = add i32 [[SUB6]], 1
-// CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD7]], 1
-// CHECK2-NEXT: [[CONV:%.*]] = zext i32 [[DIV]] to i64
-// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 1, [[CONV]]
-// CHECK2-NEXT: [[MUL8:%.*]] = mul nsw i64 [[MUL]], 4
-// CHECK2-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL8]], 1
-// CHECK2-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8
-// CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 4
-// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: store i32 [[TMP6]], ptr [[DOTTILE_0_IV_I]], align 4
-// CHECK2-NEXT: store i32 7, ptr [[J]], align 4
-// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
-// CHECK2-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]]
-// CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// CHECK2: omp.precond.then:
-// CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
-// CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8
-// CHECK2-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 8
-// CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
-// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
-// CHECK2-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK2-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8
-// CHECK2-NEXT: [[CMP14:%.*]] = icmp sgt i64 [[TMP10]], [[TMP11]]
-// CHECK2-NEXT: br i1 [[CMP14]], label [[COND_TRUE15:%.*]], label [[COND_FALSE16:%.*]]
-// CHECK2: cond.true15:
-// CHECK2-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8
-// CHECK2-NEXT: br label [[COND_END17:%.*]]
-// CHECK2: cond.false16:
-// CHECK2-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK2-NEXT: br label [[COND_END17]]
-// CHECK2: cond.end17:
-// CHECK2-NEXT: [[COND18:%.*]] = phi i64 [ [[TMP12]], [[COND_TRUE15]] ], [ [[TMP13]], [[COND_FALSE16]] ]
-// CHECK2-NEXT: store i64 [[COND18]], ptr [[DOTOMP_UB]], align 8
-// CHECK2-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
-// CHECK2-NEXT: store i64 [[TMP14]], ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
+// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK2-NEXT: [[CMP19:%.*]] = icmp sle i64 [[TMP15]], [[TMP16]]
-// CHECK2-NEXT: br i1 [[CMP19]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
+// CHECK2-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
-// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[SUB20:%.*]] = sub i32 [[TMP18]], [[TMP19]]
-// CHECK2-NEXT: [[SUB21:%.*]] = sub i32 [[SUB20]], 1
-// CHECK2-NEXT: [[ADD22:%.*]] = add i32 [[SUB21]], 1
-// CHECK2-NEXT: [[DIV23:%.*]] = udiv i32 [[ADD22]], 1
-// CHECK2-NEXT: [[MUL24:%.*]] = mul i32 1, [[DIV23]]
-// CHECK2-NEXT: [[MUL25:%.*]] = mul i32 [[MUL24]], 4
-// CHECK2-NEXT: [[CONV26:%.*]] = zext i32 [[MUL25]] to i64
-// CHECK2-NEXT: [[DIV27:%.*]] = sdiv i64 [[TMP17]], [[CONV26]]
-// CHECK2-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV27]], 5
-// CHECK2-NEXT: [[ADD29:%.*]] = add nsw i64 0, [[MUL28]]
-// CHECK2-NEXT: [[CONV30:%.*]] = trunc i64 [[ADD29]] to i32
-// CHECK2-NEXT: store i32 [[CONV30]], ptr [[DOTFLOOR_0_IV_I11]], align 4
-// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[CONV31:%.*]] = sext i32 [[TMP20]] to i64
-// CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
-// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[SUB32:%.*]] = sub i32 [[TMP23]], [[TMP24]]
-// CHECK2-NEXT: [[SUB33:%.*]] = sub i32 [[SUB32]], 1
-// CHECK2-NEXT: [[ADD34:%.*]] = add i32 [[SUB33]], 1
-// CHECK2-NEXT: [[DIV35:%.*]] = udiv i32 [[ADD34]], 1
-// CHECK2-NEXT: [[MUL36:%.*]] = mul i32 1, [[DIV35]]
-// CHECK2-NEXT: [[MUL37:%.*]] = mul i32 [[MUL36]], 4
-// CHECK2-NEXT: [[CONV38:%.*]] = zext i32 [[MUL37]] to i64
-// CHECK2-NEXT: [[DIV39:%.*]] = sdiv i64 [[TMP22]], [[CONV38]]
-// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
-// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[SUB40:%.*]] = sub i32 [[TMP25]], [[TMP26]]
-// CHECK2-NEXT: [[SUB41:%.*]] = sub i32 [[SUB40]], 1
-// CHECK2-NEXT: [[ADD42:%.*]] = add i32 [[SUB41]], 1
-// CHECK2-NEXT: [[DIV43:%.*]] = udiv i32 [[ADD42]], 1
-// CHECK2-NEXT: [[MUL44:%.*]] = mul i32 1, [[DIV43]]
-// CHECK2-NEXT: [[MUL45:%.*]] = mul i32 [[MUL44]], 4
-// CHECK2-NEXT: [[CONV46:%.*]] = zext i32 [[MUL45]] to i64
-// CHECK2-NEXT: [[MUL47:%.*]] = mul nsw i64 [[DIV39]], [[CONV46]]
-// CHECK2-NEXT: [[SUB48:%.*]] = sub nsw i64 [[TMP21]], [[MUL47]]
-// CHECK2-NEXT: [[DIV49:%.*]] = sdiv i64 [[SUB48]], 4
-// CHECK2-NEXT: [[MUL50:%.*]] = mul nsw i64 [[DIV49]], 1
-// CHECK2-NEXT: [[ADD51:%.*]] = add nsw i64 [[CONV31]], [[MUL50]]
-// CHECK2-NEXT: [[CONV52:%.*]] = trunc i64 [[ADD51]] to i32
-// CHECK2-NEXT: store i32 [[CONV52]], ptr [[DOTTILE_0_IV_I12]], align 4
-// CHECK2-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
-// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[SUB53:%.*]] = sub i32 [[TMP29]], [[TMP30]]
-// CHECK2-NEXT: [[SUB54:%.*]] = sub i32 [[SUB53]], 1
-// CHECK2-NEXT: [[ADD55:%.*]] = add i32 [[SUB54]], 1
-// CHECK2-NEXT: [[DIV56:%.*]] = udiv i32 [[ADD55]], 1
-// CHECK2-NEXT: [[MUL57:%.*]] = mul i32 1, [[DIV56]]
-// CHECK2-NEXT: [[MUL58:%.*]] = mul i32 [[MUL57]], 4
-// CHECK2-NEXT: [[CONV59:%.*]] = zext i32 [[MUL58]] to i64
-// CHECK2-NEXT: [[DIV60:%.*]] = sdiv i64 [[TMP28]], [[CONV59]]
-// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
-// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[SUB61:%.*]] = sub i32 [[TMP31]], [[TMP32]]
-// CHECK2-NEXT: [[SUB62:%.*]] = sub i32 [[SUB61]], 1
-// CHECK2-NEXT: [[ADD63:%.*]] = add i32 [[SUB62]], 1
-// CHECK2-NEXT: [[DIV64:%.*]] = udiv i32 [[ADD63]], 1
-// CHECK2-NEXT: [[MUL65:%.*]] = mul i32 1, [[DIV64]]
-// CHECK2-NEXT: [[MUL66:%.*]] = mul i32 [[MUL65]], 4
-// CHECK2-NEXT: [[CONV67:%.*]] = zext i32 [[MUL66]] to i64
-// CHECK2-NEXT: [[MUL68:%.*]] = mul nsw i64 [[DIV60]], [[CONV67]]
-// CHECK2-NEXT: [[SUB69:%.*]] = sub nsw i64 [[TMP27]], [[MUL68]]
-// CHECK2-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
-// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[SUB70:%.*]] = sub i32 [[TMP35]], [[TMP36]]
-// CHECK2-NEXT: [[SUB71:%.*]] = sub i32 [[SUB70]], 1
-// CHECK2-NEXT: [[ADD72:%.*]] = add i32 [[SUB71]], 1
-// CHECK2-NEXT: [[DIV73:%.*]] = udiv i32 [[ADD72]], 1
-// CHECK2-NEXT: [[MUL74:%.*]] = mul i32 1, [[DIV73]]
-// CHECK2-NEXT: [[MUL75:%.*]] = mul i32 [[MUL74]], 4
-// CHECK2-NEXT: [[CONV76:%.*]] = zext i32 [[MUL75]] to i64
-// CHECK2-NEXT: [[DIV77:%.*]] = sdiv i64 [[TMP34]], [[CONV76]]
-// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
-// CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[SUB78:%.*]] = sub i32 [[TMP37]], [[TMP38]]
-// CHECK2-NEXT: [[SUB79:%.*]] = sub i32 [[SUB78]], 1
-// CHECK2-NEXT: [[ADD80:%.*]] = add i32 [[SUB79]], 1
-// CHECK2-NEXT: [[DIV81:%.*]] = udiv i32 [[ADD80]], 1
-// CHECK2-NEXT: [[MUL82:%.*]] = mul i32 1, [[DIV81]]
-// CHECK2-NEXT: [[MUL83:%.*]] = mul i32 [[MUL82]], 4
-// CHECK2-NEXT: [[CONV84:%.*]] = zext i32 [[MUL83]] to i64
-// CHECK2-NEXT: [[MUL85:%.*]] = mul nsw i64 [[DIV77]], [[CONV84]]
-// CHECK2-NEXT: [[SUB86:%.*]] = sub nsw i64 [[TMP33]], [[MUL85]]
-// CHECK2-NEXT: [[DIV87:%.*]] = sdiv i64 [[SUB86]], 4
-// CHECK2-NEXT: [[MUL88:%.*]] = mul nsw i64 [[DIV87]], 4
-// CHECK2-NEXT: [[SUB89:%.*]] = sub nsw i64 [[SUB69]], [[MUL88]]
-// CHECK2-NEXT: [[MUL90:%.*]] = mul nsw i64 [[SUB89]], 3
-// CHECK2-NEXT: [[ADD91:%.*]] = add nsw i64 7, [[MUL90]]
-// CHECK2-NEXT: [[CONV92:%.*]] = trunc i64 [[ADD91]] to i32
-// CHECK2-NEXT: store i32 [[CONV92]], ptr [[J13]], align 4
-// CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTTILE_0_IV_I12]], align 4
-// CHECK2-NEXT: [[MUL93:%.*]] = mul nsw i32 [[TMP39]], 3
-// CHECK2-NEXT: [[ADD94:%.*]] = add nsw i32 7, [[MUL93]]
-// CHECK2-NEXT: store i32 [[ADD94]], ptr [[I]], align 4
-// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[I]], align 4
-// CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[J13]], align 4
-// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP40]], i32 noundef [[TMP41]])
-// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 20
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 5
+// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD5]], ptr [[DOTFLOOR_0_IV_I]], align 4
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[DIV6:%.*]] = sdiv i32 [[TMP11]], 20
+// CHECK2-NEXT: [[MUL7:%.*]] = mul nsw i32 [[DIV6]], 20
+// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP10]], [[MUL7]]
+// CHECK2-NEXT: [[DIV8:%.*]] = sdiv i32 [[SUB]], 4
+// CHECK2-NEXT: [[MUL9:%.*]] = mul nsw i32 [[DIV8]], 1
+// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP9]], [[MUL9]]
+// CHECK2-NEXT: store i32 [[ADD10]], ptr [[DOTTILE_0_IV_I]], align 4
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[DIV11:%.*]] = sdiv i32 [[TMP13]], 20
+// CHECK2-NEXT: [[MUL12:%.*]] = mul nsw i32 [[DIV11]], 20
+// CHECK2-NEXT: [[SUB13:%.*]] = sub nsw i32 [[TMP12]], [[MUL12]]
+// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[DIV14:%.*]] = sdiv i32 [[TMP15]], 20
+// CHECK2-NEXT: [[MUL15:%.*]] = mul nsw i32 [[DIV14]], 20
+// CHECK2-NEXT: [[SUB16:%.*]] = sub nsw i32 [[TMP14]], [[MUL15]]
+// CHECK2-NEXT: [[DIV17:%.*]] = sdiv i32 [[SUB16]], 4
+// CHECK2-NEXT: [[MUL18:%.*]] = mul nsw i32 [[DIV17]], 4
+// CHECK2-NEXT: [[SUB19:%.*]] = sub nsw i32 [[SUB13]], [[MUL18]]
+// CHECK2-NEXT: [[MUL20:%.*]] = mul nsw i32 [[SUB19]], 3
+// CHECK2-NEXT: [[ADD21:%.*]] = add nsw i32 7, [[MUL20]]
+// CHECK2-NEXT: store i32 [[ADD21]], ptr [[J]], align 4
+// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
+// CHECK2-NEXT: [[CMP22:%.*]] = icmp slt i32 [[TMP16]], 4
+// CHECK2-NEXT: br i1 [[CMP22]], label [[OMP_BODY_NEXT:%.*]], label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK2: omp.body.next:
+// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
+// CHECK2-NEXT: [[MUL23:%.*]] = mul nsw i32 [[TMP17]], 3
+// CHECK2-NEXT: [[ADD24:%.*]] = add nsw i32 7, [[MUL23]]
+// CHECK2-NEXT: store i32 [[ADD24]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[J]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP18]], i32 noundef [[TMP19]])
+// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK2-NEXT: [[ADD95:%.*]] = add nsw i64 [[TMP42]], 1
-// CHECK2-NEXT: store i64 [[ADD95]], ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP20]], 1
+// CHECK2-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_IV]], align 4
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK2: omp.inner.for.end:
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK2: omp.loop.exit:
// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])
-// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
-// CHECK2: omp.precond.end:
// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
// CHECK2-NEXT: ret void
//
@@ -2375,7 +2171,7 @@ extern "C" void foo10(data_t data) {
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1
// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
// CHECK2: for.end:
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
@@ -2459,7 +2255,7 @@ extern "C" void foo10(data_t data) {
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP23:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP25:![0-9]+]]
// CHECK2: for.end:
// CHECK2-NEXT: br label [[FOR_INC17:%.*]]
// CHECK2: for.inc17:
@@ -2476,7 +2272,7 @@ extern "C" void foo10(data_t data) {
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
// CHECK2-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP14]], [[COND22]]
// CHECK2-NEXT: store i32 [[ADD23]], ptr [[DOTFLOOR_0_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
// CHECK2: for.end24:
// CHECK2-NEXT: ret void
//
@@ -2495,14 +2291,14 @@ extern "C" void foo10(data_t data) {
// CHECK2-NEXT: [[V:%.*]] = alloca double, align 8
// CHECK2-NEXT: [[ARRAY:%.*]] = getelementptr inbounds nuw [[STRUCT_DATA_T]], ptr [[DATA]], i32 0, i32 0
// CHECK2-NEXT: store ptr [[ARRAY]], ptr [[__RANGE2]], align 8
-// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META9]]
// CHECK2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP0]], i64 0, i64 0
// CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 12
// CHECK2-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META9]]
// CHECK2-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP1]], i64 0, i64 0
// CHECK2-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META9]]
// CHECK2-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP2]], i64 0, i64 0
// CHECK2-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 8
@@ -2566,14 +2362,14 @@ extern "C" void foo10(data_t data) {
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTTILE_0_IV___BEGIN2]], align 8
// CHECK2-NEXT: [[INC:%.*]] = add nsw i64 [[TMP19]], 1
// CHECK2-NEXT: store i64 [[INC]], ptr [[DOTTILE_0_IV___BEGIN2]], align 8
-// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP25:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP27:![0-9]+]]
// CHECK2: for.end:
// CHECK2-NEXT: br label [[FOR_INC16:%.*]]
// CHECK2: for.inc16:
// CHECK2-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 8
// CHECK2-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP20]], 5
// CHECK2-NEXT: store i64 [[ADD17]], ptr [[DOTFLOOR_0_IV___BEGIN2]], align 8
-// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
// CHECK2: for.end18:
// CHECK2-NEXT: ret void
//
@@ -2657,14 +2453,14 @@ extern "C" void foo10(data_t data) {
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
// CHECK2-NEXT: [[INC:%.*]] = add i32 [[TMP16]], 1
// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP27:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP29:![0-9]+]]
// CHECK2: for.end:
// CHECK2-NEXT: br label [[FOR_INC15:%.*]]
// CHECK2: for.inc15:
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
// CHECK2-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 5
// CHECK2-NEXT: store i32 [[ADD16]], ptr [[DOTFLOOR_0_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
// CHECK2: for.end17:
// CHECK2-NEXT: ret void
//
@@ -2676,53 +2472,59 @@ extern "C" void foo10(data_t data) {
// CHECK2-NEXT: ret void
//
//.
-// CHECK1: [[LOOP3]] = distinct !{[[LOOP3]], [[META4:![0-9]+]]}
-// CHECK1: [[META4]] = !{!"llvm.loop.mustprogress"}
-// CHECK1: [[LOOP5]] = distinct !{[[LOOP5]], [[META4]]}
-// CHECK1: [[LOOP6]] = distinct !{[[LOOP6]], [[META4]]}
-// CHECK1: [[LOOP7]] = distinct !{[[LOOP7]], [[META4]]}
-// CHECK1: [[LOOP8]] = distinct !{[[LOOP8]], [[META4]]}
-// CHECK1: [[LOOP9]] = distinct !{[[LOOP9]], [[META4]]}
-// CHECK1: [[LOOP10]] = distinct !{[[LOOP10]], [[META4]]}
-// CHECK1: [[LOOP11]] = distinct !{[[LOOP11]], [[META4]]}
-// CHECK1: [[LOOP12]] = distinct !{[[LOOP12]], [[META4]]}
-// CHECK1: [[LOOP13]] = distinct !{[[LOOP13]], [[META4]]}
-// CHECK1: [[LOOP14]] = distinct !{[[LOOP14]], [[META4]]}
-// CHECK1: [[LOOP15]] = distinct !{[[LOOP15]], [[META4]]}
-// CHECK1: [[LOOP16]] = distinct !{[[LOOP16]], [[META4]]}
-// CHECK1: [[LOOP17]] = distinct !{[[LOOP17]], [[META4]]}
-// CHECK1: [[LOOP18]] = distinct !{[[LOOP18]], [[META4]]}
-// CHECK1: [[LOOP21]] = distinct !{[[LOOP21]], [[META4]]}
-// CHECK1: [[LOOP22]] = distinct !{[[LOOP22]], [[META4]]}
-// CHECK1: [[LOOP23]] = distinct !{[[LOOP23]], [[META4]]}
-// CHECK1: [[LOOP24]] = distinct !{[[LOOP24]], [[META4]]}
-// CHECK1: [[LOOP25]] = distinct !{[[LOOP25]], [[META4]]}
-// CHECK1: [[LOOP26]] = distinct !{[[LOOP26]], [[META4]]}
-// CHECK1: [[LOOP27]] = distinct !{[[LOOP27]], [[META4]]}
-// CHECK1: [[LOOP28]] = distinct !{[[LOOP28]], [[META4]]}
+// CHECK1: [[META2]] = !{}
+// CHECK1: [[META3]] = !{i64 4}
+// CHECK1: [[LOOP4]] = distinct !{[[LOOP4]], [[META5:![0-9]+]]}
+// CHECK1: [[META5]] = !{!"llvm.loop.mustprogress"}
+// CHECK1: [[LOOP6]] = distinct !{[[LOOP6]], [[META5]]}
+// CHECK1: [[LOOP7]] = distinct !{[[LOOP7]], [[META5]]}
+// CHECK1: [[LOOP8]] = distinct !{[[LOOP8]], [[META5]]}
+// CHECK1: [[LOOP9]] = distinct !{[[LOOP9]], [[META5]]}
+// CHECK1: [[LOOP10]] = distinct !{[[LOOP10]], [[META5]]}
+// CHECK1: [[LOOP11]] = distinct !{[[LOOP11]], [[META5]]}
+// CHECK1: [[LOOP12]] = distinct !{[[LOOP12]], [[META5]]}
+// CHECK1: [[LOOP13]] = distinct !{[[LOOP13]], [[META5]]}
+// CHECK1: [[LOOP14]] = distinct !{[[LOOP14]], [[META5]]}
+// CHECK1: [[LOOP15]] = distinct !{[[LOOP15]], [[META5]]}
+// CHECK1: [[LOOP16]] = distinct !{[[LOOP16]], [[META5]]}
+// CHECK1: [[LOOP17]] = distinct !{[[LOOP17]], [[META5]]}
+// CHECK1: [[LOOP18]] = distinct !{[[LOOP18]], [[META5]]}
+// CHECK1: [[LOOP19]] = distinct !{[[LOOP19]], [[META5]]}
+// CHECK1: [[LOOP22]] = distinct !{[[LOOP22]], [[META5]]}
+// CHECK1: [[LOOP23]] = distinct !{[[LOOP23]], [[META5]]}
+// CHECK1: [[LOOP24]] = distinct !{[[LOOP24]], [[META5]]}
+// CHECK1: [[LOOP25]] = distinct !{[[LOOP25]], [[META5]]}
+// CHECK1: [[META26]] = !{i64 8}
+// CHECK1: [[LOOP27]] = distinct !{[[LOOP27]], [[META5]]}
+// CHECK1: [[LOOP28]] = distinct !{[[LOOP28]], [[META5]]}
+// CHECK1: [[LOOP29]] = distinct !{[[LOOP29]], [[META5]]}
+// CHECK1: [[LOOP30]] = distinct !{[[LOOP30]], [[META5]]}
//.
-// CHECK2: [[LOOP3]] = distinct !{[[LOOP3]], [[META4:![0-9]+]]}
-// CHECK2: [[META4]] = !{!"llvm.loop.mustprogress"}
-// CHECK2: [[LOOP5]] = distinct !{[[LOOP5]], [[META4]]}
-// CHECK2: [[LOOP6]] = distinct !{[[LOOP6]], [[META4]]}
-// CHECK2: [[LOOP7]] = distinct !{[[LOOP7]], [[META4]]}
-// CHECK2: [[LOOP8]] = distinct !{[[LOOP8]], [[META4]]}
-// CHECK2: [[LOOP9]] = distinct !{[[LOOP9]], [[META4]]}
-// CHECK2: [[LOOP10]] = distinct !{[[LOOP10]], [[META4]]}
-// CHECK2: [[LOOP11]] = distinct !{[[LOOP11]], [[META4]]}
-// CHECK2: [[LOOP12]] = distinct !{[[LOOP12]], [[META4]]}
-// CHECK2: [[LOOP13]] = distinct !{[[LOOP13]], [[META4]]}
-// CHECK2: [[LOOP14]] = distinct !{[[LOOP14]], [[META4]]}
-// CHECK2: [[LOOP15]] = distinct !{[[LOOP15]], [[META4]]}
-// CHECK2: [[LOOP16]] = distinct !{[[LOOP16]], [[META4]]}
-// CHECK2: [[LOOP17]] = distinct !{[[LOOP17]], [[META4]]}
-// CHECK2: [[LOOP18]] = distinct !{[[LOOP18]], [[META4]]}
-// CHECK2: [[LOOP19]] = distinct !{[[LOOP19]], [[META4]]}
-// CHECK2: [[LOOP20]] = distinct !{[[LOOP20]], [[META4]]}
-// CHECK2: [[LOOP23]] = distinct !{[[LOOP23]], [[META4]]}
-// CHECK2: [[LOOP24]] = distinct !{[[LOOP24]], [[META4]]}
-// CHECK2: [[LOOP25]] = distinct !{[[LOOP25]], [[META4]]}
-// CHECK2: [[LOOP26]] = distinct !{[[LOOP26]], [[META4]]}
-// CHECK2: [[LOOP27]] = distinct !{[[LOOP27]], [[META4]]}
-// CHECK2: [[LOOP28]] = distinct !{[[LOOP28]], [[META4]]}
+// CHECK2: [[META2]] = !{}
+// CHECK2: [[META3]] = !{i64 4}
+// CHECK2: [[LOOP4]] = distinct !{[[LOOP4]], [[META5:![0-9]+]]}
+// CHECK2: [[META5]] = !{!"llvm.loop.mustprogress"}
+// CHECK2: [[LOOP6]] = distinct !{[[LOOP6]], [[META5]]}
+// CHECK2: [[LOOP7]] = distinct !{[[LOOP7]], [[META5]]}
+// CHECK2: [[LOOP8]] = distinct !{[[LOOP8]], [[META5]]}
+// CHECK2: [[META9]] = !{i64 8}
+// CHECK2: [[LOOP10]] = distinct !{[[LOOP10]], [[META5]]}
+// CHECK2: [[LOOP11]] = distinct !{[[LOOP11]], [[META5]]}
+// CHECK2: [[LOOP12]] = distinct !{[[LOOP12]], [[META5]]}
+// CHECK2: [[LOOP13]] = distinct !{[[LOOP13]], [[META5]]}
+// CHECK2: [[LOOP14]] = distinct !{[[LOOP14]], [[META5]]}
+// CHECK2: [[LOOP15]] = distinct !{[[LOOP15]], [[META5]]}
+// CHECK2: [[LOOP16]] = distinct !{[[LOOP16]], [[META5]]}
+// CHECK2: [[LOOP17]] = distinct !{[[LOOP17]], [[META5]]}
+// CHECK2: [[LOOP18]] = distinct !{[[LOOP18]], [[META5]]}
+// CHECK2: [[LOOP19]] = distinct !{[[LOOP19]], [[META5]]}
+// CHECK2: [[LOOP20]] = distinct !{[[LOOP20]], [[META5]]}
+// CHECK2: [[LOOP21]] = distinct !{[[LOOP21]], [[META5]]}
+// CHECK2: [[LOOP22]] = distinct !{[[LOOP22]], [[META5]]}
+// CHECK2: [[LOOP25]] = distinct !{[[LOOP25]], [[META5]]}
+// CHECK2: [[LOOP26]] = distinct !{[[LOOP26]], [[META5]]}
+// CHECK2: [[LOOP27]] = distinct !{[[LOOP27]], [[META5]]}
+// CHECK2: [[LOOP28]] = distinct !{[[LOOP28]], [[META5]]}
+// CHECK2: [[LOOP29]] = distinct !{[[LOOP29]], [[META5]]}
+// CHECK2: [[LOOP30]] = distinct !{[[LOOP30]], [[META5]]}
//.
diff --git a/clang/test/OpenMP/tile_collapse_messages.cpp b/clang/test/OpenMP/tile_collapse_messages.cpp
new file mode 100644
index 0000000000000..2c9cc57d35105
--- /dev/null
+++ b/clang/test/OpenMP/tile_collapse_messages.cpp
@@ -0,0 +1,75 @@
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -std=c++17 -fopenmp -fsyntax-only -Wuninitialized -verify %s
+
+// A collapsed intra-tile loop starts from the floor counter of an outer loop
+// in the same nest, so that floor must itself be one of the collapsed loops.
+// Inside another loop transformation it is assigned in an enclosing loop's
+// body and the nest would read a stale value, which is diagnosed rather than
+// silently miscomputed.
+
+extern void body(int);
+
+void collapse_through_single_tile() {
+#pragma omp for collapse(2)
+#pragma omp tile sizes(4)
+ for (int i = 0; i < 6; ++i)
+ body(i);
+}
+
+void collapse_through_tile_2d() {
+#pragma omp for collapse(4)
+#pragma omp tile sizes(2, 3)
+ for (int i = 0; i < 6; ++i)
+ for (int j = 0; j < 7; ++j)
+ body(i + j);
+}
+
+void collapse_outer_of_stacked_tiles() {
+ // Only the outer tile's floor and intra-tile loops are collapsed, and that
+ // floor is a collapsed counter, so this is fine.
+#pragma omp for collapse(2)
+#pragma omp tile sizes(2)
+#pragma omp tile sizes(4)
+ for (int i = 0; i < 6; ++i)
+ body(i);
+}
+
+void collapse_into_stacked_tiles() {
+ // The third loop is the inner tile's intra-tile loop, whose floor is computed
+ // inside the outer intra-tile loop's body.
+#pragma omp for collapse(3)
+#pragma omp tile sizes(2)
+#pragma omp tile sizes(4)
+ // expected-error at +1 {{cannot collapse the intra-tile loop of a '#pragma omp tile' that is nested inside another loop-transforming directive; OpenMP permits this construct, but it is not yet supported}}
+ for (int i = 0; i < 6; ++i)
+ body(i);
+}
+
+void collapse_simd_over_tile() {
+ // Rejected by the pre-existing restriction on nesting inside a 'simd' region.
+#pragma omp simd collapse(2)
+ // expected-error at +1 {{OpenMP constructs may not be nested inside a simd region except for ordered simd, simd, scan, or atomic directive}}
+#pragma omp tile sizes(4)
+ for (int i = 0; i < 6; ++i)
+ body(i);
+}
+
+void collapse_outer_of_stacked_tiles_2d() {
+ // Outer tile sizes(2, 3) needs two loops, so it reaches the inner
+ // intra-tile loop. Same limitation as tile_of_tile_two_sizes.
+#pragma omp for collapse(4)
+#pragma omp tile sizes(2, 3)
+#pragma omp tile sizes(4)
+ // expected-error at +1 {{cannot apply a loop transformation to the intra-tile loop of a '#pragma omp tile' that is nested inside another loop-transforming directive; OpenMP permits this construct, but it is not yet supported}}
+ for (int i = 0; i < 6; ++i)
+ body(i);
+}
+
+void tile_of_tile_two_sizes() {
+ // Outer tile sizes(3, 5) needs two loops, so it reaches the inner
+ // intra-tile loop. That nest would run the wrong iterations.
+#pragma omp tile sizes(3, 5)
+#pragma omp tile sizes(2)
+ // expected-error at +1 {{cannot apply a loop transformation to the intra-tile loop of a '#pragma omp tile' that is nested inside another loop-transforming directive; OpenMP permits this construct, but it is not yet supported}}
+ for (int i = 0; i < 6; ++i)
+ body(i);
+}
diff --git a/clang/test/OpenMP/tile_collapse_reinterpret_codegen.cpp b/clang/test/OpenMP/tile_collapse_reinterpret_codegen.cpp
new file mode 100644
index 0000000000000..477c86b4ead44
--- /dev/null
+++ b/clang/test/OpenMP/tile_collapse_reinterpret_codegen.cpp
@@ -0,0 +1,174 @@
+// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fclang-abi-compat=latest -std=c++20 -fopenmp -ast-print %s | FileCheck %s --check-prefix=PRINT
+// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fclang-abi-compat=latest -std=c++20 -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=IR
+
+// Check same results after serialization round-trip, which exercises reading
+// and writing OMPInvariantPredicateBoundAttr including its optional predicate.
+// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fclang-abi-compat=latest -std=c++20 -fopenmp -emit-pch -o %t %s
+// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fclang-abi-compat=latest -std=c++20 -fopenmp -include-pch %t -ast-print %s | FileCheck %s --check-prefix=PRINT
+
+// expected-no-diagnostics
+
+// How a loop-associated directive consumes a '#pragma omp tile': the stored
+// min-bounded intra-tile loop is reinterpreted as a rectangular one with a
+// constant trip count (the tile size), and a partial last tile is handled by a
+// body guard. Worksharing, 'distribute' and 'ordered(n)' consumers each read
+// the iteration space
diff erently, so all three are covered. The hint is
+// internal and never dumped, so it is observed through the guard it produces
+// ('omp.body.next') and through the PCH round-trip above.
+
+#ifndef HEADER
+#define HEADER
+
+extern "C" void body(...) {}
+
+// PRINT-LABEL: void collapse2_tile1d(
+// PRINT: #pragma omp parallel for collapse(2)
+// PRINT-NEXT: #pragma omp tile sizes(2)
+// IR-LABEL: define internal void @collapse2_tile1d.omp_outlined
+// IR: %.floor_0.iv{{[0-9a-z.]*}} = alloca i32
+// IR: %.tile_0.iv{{[0-9a-z.]*}} = alloca i32
+// IR: omp.inner.for.body:
+// IR: store i32 %{{.*}}, ptr %.tile_0.iv
+// IR: %[[PRED:.*]] = icmp slt i32 %{{.*}}, %{{.*}}
+// IR-NEXT: br i1 %[[PRED]], label %omp.body.next, label %omp.body.continue
+// IR: omp.body.next:
+// IR: call void (...) @body
+// IR-NEXT: br label %omp.body.continue
+// IR: omp.body.continue:
+extern "C" void collapse2_tile1d(int n) {
+#pragma omp parallel for collapse(2)
+#pragma omp tile sizes(2)
+ for (int i = 0; i < n; ++i)
+ body(i);
+}
+
+// A non-tiled inner loop joins the collapsed nest as a third counter, and the
+// guard still applies to the tile counter alone.
+// PRINT-LABEL: void collapse3_tile1d_nested(
+// PRINT: #pragma omp parallel for collapse(3)
+// PRINT-NEXT: #pragma omp tile sizes(5)
+// IR-LABEL: define internal void @collapse3_tile1d_nested.omp_outlined
+// IR: omp.inner.for.body:
+// IR: store i32 %{{.*}}, ptr %.tile_0.iv
+// IR: store i32 %{{.*}}, ptr %j
+// IR: %[[TILEIV:.*]] = load i32, ptr %.tile_0.iv
+// IR: %[[PRED:.*]] = icmp slt i32 %[[TILEIV]], %{{.*}}
+// IR-NEXT: br i1 %[[PRED]], label %omp.body.next, label %omp.body.continue
+extern "C" void collapse3_tile1d_nested(int n) {
+#pragma omp parallel for collapse(3)
+#pragma omp tile sizes(5)
+ for (int i = 0; i < n; ++i)
+ for (int j = 0; j < n; ++j)
+ body(i, j);
+}
+
+// An enclosing 'tile' is another loop transformation rather than a consumer, so
+// the inner intra-tile loop stays min-bounded and gets no guard.
+// PRINT-LABEL: void tile2d_inside_tile1d(
+// PRINT: #pragma omp tile sizes(3)
+// PRINT-NEXT: #pragma omp tile sizes(2)
+// IR-LABEL: define {{.*}} @tile2d_inside_tile1d(
+// IR: %.tile_0.iv{{[0-9a-z.]*}} = alloca i32
+// IR: cond.true:
+// IR: cond.false:
+// IR: cond.end:
+// IR: %{{.*}} = phi i32
+// IR-NOT: omp.body.next
+extern "C" void tile2d_inside_tile1d(int n) {
+#pragma omp tile sizes(3)
+#pragma omp tile sizes(2)
+ for (int i = 0; i < n; ++i)
+ body(i);
+}
+
+// PRINT-LABEL: void collapse3_tile2d(
+// PRINT: #pragma omp parallel for collapse(3)
+// PRINT-NEXT: #pragma omp tile sizes(2, 3)
+// IR-LABEL: define internal void @collapse3_tile2d.omp_outlined
+// IR: omp.inner.for.body:
+// IR: store i32 %{{.*}}, ptr %.tile_0.iv
+// IR: br i1 %{{.*}}, label %omp.body.next, label %omp.body.continue
+// IR: omp.body.next:
+// IR: call void (...) @body
+extern "C" void collapse3_tile2d(int n) {
+#pragma omp parallel for collapse(3)
+#pragma omp tile sizes(2, 3)
+ for (int i = 0; i < n; ++i)
+ for (int j = 0; j < n; ++j)
+ body(i, j);
+}
+
+// Trip count 10 is a multiple of the tile size 5, so no tile is partial, the
+// hint carries no predicate, and the body is emitted with no guard.
+// PRINT-LABEL: void collapse2_tile1d_no_partial_tile(
+// PRINT: #pragma omp parallel for collapse(2)
+// PRINT-NEXT: #pragma omp tile sizes(5)
+// IR-LABEL: define internal void @collapse2_tile1d_no_partial_tile.omp_outlined
+// IR: omp.inner.for.body:
+// IR-NOT: omp.body.next
+// IR: call void (...) @body
+// IR: omp.body.continue:
+extern "C" void collapse2_tile1d_no_partial_tile() {
+#pragma omp parallel for collapse(2)
+#pragma omp tile sizes(5)
+ for (int i = 0; i < 10; ++i)
+ body(i);
+}
+
+// Trip count 11 is not a multiple of the tile size 5, so the predicate is kept
+// even though both values are compile-time constants.
+// PRINT-LABEL: void collapse2_tile1d_constant_partial_tile(
+// PRINT: #pragma omp parallel for collapse(2)
+// PRINT-NEXT: #pragma omp tile sizes(5)
+// IR-LABEL: define internal void @collapse2_tile1d_constant_partial_tile.omp_outlined
+// IR: omp.inner.for.body:
+// IR: br i1 %{{.*}}, label %omp.body.next, label %omp.body.continue
+// IR: omp.body.next:
+// IR: call void (...) @body
+extern "C" void collapse2_tile1d_constant_partial_tile() {
+#pragma omp parallel for collapse(2)
+#pragma omp tile sizes(5)
+ for (int i = 0; i < 11; ++i)
+ body(i);
+}
+
+// 'distribute' computes bounds through its own LB/UB/EUB/DistCond fields, so
+// check that the reinterpretation and its guard survive that path too.
+// PRINT-LABEL: void dist_collapse2_tile1d(
+// PRINT: #pragma omp teams distribute collapse(2)
+// PRINT-NEXT: #pragma omp tile sizes(5)
+// IR-LABEL: define internal void @dist_collapse2_tile1d.omp_outlined
+// IR: omp.inner.for.body:
+// IR: store i32 %{{.*}}, ptr %.tile_0.iv
+// IR: br i1 %{{.*}}, label %omp.body.next, label %omp.body.continue
+// IR: omp.body.next:
+// IR: call void (...) @body
+extern "C" void dist_collapse2_tile1d(int n) {
+#pragma omp teams distribute collapse(2)
+#pragma omp tile sizes(5)
+ for (int i = 0; i < n; ++i)
+ body(i);
+}
+
+// 'ordered(n)' feeds each collapsed loop's trip count to __kmpc_doacross_init,
+// so the intra-tile dimension must report the constant tile size, matching the
+// space 'collapse' linearizes.
+// PRINT-LABEL: void ordered_collapse2_tile1d(
+// PRINT: #pragma omp for collapse(2) ordered(2)
+// PRINT-NEXT: #pragma omp tile sizes(5)
+// IR-LABEL: define {{.*}} @ordered_collapse2_tile1d(
+// IR: %[[DIM1:.*]] = getelementptr inbounds [2 x %struct.kmp_dim], ptr %dims, i64 0, i64 1
+// IR: %[[UP1:.*]] = getelementptr inbounds nuw %struct.kmp_dim, ptr %[[DIM1]], i32 0, i32 1
+// IR-NEXT: store i64 5, ptr %[[UP1]]
+// IR: call void @__kmpc_doacross_init(ptr @{{[0-9]+}}, i32 %{{.*}}, i32 2, ptr %{{.*}})
+// IR: omp.inner.for.body:
+// IR: br i1 %{{.*}}, label %omp.body.next, label %omp.body.continue
+// IR: call void @__kmpc_doacross_fini(
+extern "C" void ordered_collapse2_tile1d(int n) {
+#pragma omp for collapse(2) ordered(2)
+#pragma omp tile sizes(5)
+ for (int i = 0; i < n; ++i)
+ body(i);
+}
+
+#endif /* HEADER */
diff --git a/clang/test/OpenMP/tile_messages.cpp b/clang/test/OpenMP/tile_messages.cpp
index e1f5155c924e5..021262ac9a54a 100644
--- a/clang/test/OpenMP/tile_messages.cpp
+++ b/clang/test/OpenMP/tile_messages.cpp
@@ -170,3 +170,43 @@ void f(void) {
;
}
} // namespace GH139073
+
+// A loop transformation that consumes an inner tile's intra-tile loop would
+// miscompute the nest; that is diagnosed. Consuming only the generated floor
+// (one size, or unroll) is still accepted.
+namespace consumed_by_transformation {
+// Codegen: tile_codegen_tile_for.cpp;
+// run time: libomp transform/tile/parallel-wsloop-collapse-stacked-tile.cpp.
+void tile_of_tile() {
+#pragma omp tile sizes(3, 5)
+#pragma omp tile sizes(2)
+ // expected-error at +1 {{cannot apply a loop transformation to the intra-tile loop of a '#pragma omp tile' that is nested inside another loop-transforming directive; OpenMP permits this construct, but it is not yet supported}}
+ for (int i = 0; i < 100; ++i)
+ ;
+}
+
+// Same, for a range-based for loop.
+void tile_of_tile_range_for(int (&A)[100]) {
+#pragma omp tile sizes(3, 5)
+#pragma omp tile sizes(2)
+ // expected-error at +1 {{cannot apply a loop transformation to the intra-tile loop of a '#pragma omp tile' that is nested inside another loop-transforming directive; OpenMP permits this construct, but it is not yet supported}}
+ for (int &v : A)
+ (void)v;
+}
+
+// Outer tile takes only the inner floor, not the intra-tile loop.
+void tile_of_tile_one_size() {
+#pragma omp tile sizes(3)
+#pragma omp tile sizes(2)
+ for (int i = 0; i < 100; ++i)
+ ;
+}
+
+// 'unroll' only consumes the generated floor.
+void unroll_of_tile() {
+#pragma omp unroll partial(4)
+#pragma omp tile sizes(2)
+ for (int i = 0; i < 100; ++i)
+ ;
+}
+} // namespace consumed_by_transformation
diff --git a/clang/test/OpenMP/tile_rect_codegen_ir.cpp b/clang/test/OpenMP/tile_rect_codegen_ir.cpp
new file mode 100644
index 0000000000000..33b3415d36b6d
--- /dev/null
+++ b/clang/test/OpenMP/tile_rect_codegen_ir.cpp
@@ -0,0 +1,168 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6
+// A standalone `#pragma omp tile` keeps the intra-tile loop min-bounded: the
+// upper bound `min(.floor.iv + tilesize, N)` is materialized as a
+// cond.true/cond.false/phi and there is no body guard. The guarded rectangular
+// form appears only once a directive consumes the tile, see
+// tile_collapse_reinterpret_codegen.cpp.
+//
+// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-llvm -o - %s | FileCheck %s --check-prefix=IR
+// expected-no-diagnostics
+
+extern "C" void body(int);
+
+// Trip count 6, tile 4: the last tile is partial, and the min() bound alone
+// stops it at the trip count.
+// IR-LABEL: define dso_local void @_Z18remainder_6_tile_4v(
+// IR-SAME: ) #[[ATTR0:[0-9]+]] {
+// IR-NEXT: [[ENTRY:.*:]]
+// IR-NEXT: [[I:%.*]] = alloca i32, align 4
+// IR-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4
+// IR-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4
+// IR-NEXT: store i32 0, ptr [[I]], align 4
+// IR-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 4
+// IR-NEXT: br label %[[FOR_COND:.*]]
+// IR: [[FOR_COND]]:
+// IR-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
+// IR-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 6
+// IR-NEXT: br i1 [[CMP]], label %[[FOR_BODY:.*]], label %[[FOR_END9:.*]]
+// IR: [[FOR_BODY]]:
+// IR-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
+// IR-NEXT: store i32 [[TMP1]], ptr [[DOTTILE_0_IV_I]], align 4
+// IR-NEXT: br label %[[FOR_COND1:.*]]
+// IR: [[FOR_COND1]]:
+// IR-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
+// IR-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
+// IR-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 4
+// IR-NEXT: [[CMP2:%.*]] = icmp slt i32 6, [[ADD]]
+// IR-NEXT: br i1 [[CMP2]], label %[[COND_TRUE:.*]], label %[[COND_FALSE:.*]]
+// IR: [[COND_TRUE]]:
+// IR-NEXT: br label %[[COND_END:.*]]
+// IR: [[COND_FALSE]]:
+// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
+// IR-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP4]], 4
+// IR-NEXT: br label %[[COND_END]]
+// IR: [[COND_END]]:
+// IR-NEXT: [[COND:%.*]] = phi i32 [ 6, %[[COND_TRUE]] ], [ [[ADD3]], %[[COND_FALSE]] ]
+// IR-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP2]], [[COND]]
+// IR-NEXT: br i1 [[CMP4]], label %[[FOR_BODY5:.*]], label %[[FOR_END:.*]]
+// IR: [[FOR_BODY5]]:
+// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
+// IR-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 1
+// IR-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL]]
+// IR-NEXT: store i32 [[ADD6]], ptr [[I]], align 4
+// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4
+// IR-NEXT: call void @body(i32 noundef [[TMP6]])
+// IR-NEXT: br label %[[FOR_INC:.*]]
+// IR: [[FOR_INC]]:
+// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
+// IR-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1
+// IR-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4
+// IR-NEXT: br label %[[FOR_COND1]], !llvm.loop [[LOOP2:![0-9]+]]
+// IR: [[FOR_END]]:
+// IR-NEXT: br label %[[FOR_INC7:.*]]
+// IR: [[FOR_INC7]]:
+// IR-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
+// IR-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 4
+// IR-NEXT: store i32 [[ADD8]], ptr [[DOTFLOOR_0_IV_I]], align 4
+// IR-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
+// IR: [[FOR_END9]]:
+// IR-NEXT: ret void
+//
+void remainder_6_tile_4(void) {
+#pragma omp tile sizes(4)
+ for (int i = 0; i < 6; ++i)
+ body(i);
+}
+
+// The inner `j` loop is not one of the tiled loops, so it is emitted untouched
+// inside the intra-tile loop.
+// IR-LABEL: define dso_local void @_Z14nested_inner_ji(
+// IR-SAME: i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// IR-NEXT: [[ENTRY:.*:]]
+// IR-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// IR-NEXT: [[I:%.*]] = alloca i32, align 4
+// IR-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4
+// IR-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4
+// IR-NEXT: [[J:%.*]] = alloca i32, align 4
+// IR-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
+// IR-NEXT: store i32 0, ptr [[I]], align 4
+// IR-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 4
+// IR-NEXT: br label %[[FOR_COND:.*]]
+// IR: [[FOR_COND]]:
+// IR-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
+// IR-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 6
+// IR-NEXT: br i1 [[CMP]], label %[[FOR_BODY:.*]], label %[[FOR_END16:.*]]
+// IR: [[FOR_BODY]]:
+// IR-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
+// IR-NEXT: store i32 [[TMP1]], ptr [[DOTTILE_0_IV_I]], align 4
+// IR-NEXT: br label %[[FOR_COND1:.*]]
+// IR: [[FOR_COND1]]:
+// IR-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
+// IR-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
+// IR-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 4
+// IR-NEXT: [[CMP2:%.*]] = icmp slt i32 6, [[ADD]]
+// IR-NEXT: br i1 [[CMP2]], label %[[COND_TRUE:.*]], label %[[COND_FALSE:.*]]
+// IR: [[COND_TRUE]]:
+// IR-NEXT: br label %[[COND_END:.*]]
+// IR: [[COND_FALSE]]:
+// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
+// IR-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP4]], 4
+// IR-NEXT: br label %[[COND_END]]
+// IR: [[COND_END]]:
+// IR-NEXT: [[COND:%.*]] = phi i32 [ 6, %[[COND_TRUE]] ], [ [[ADD3]], %[[COND_FALSE]] ]
+// IR-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP2]], [[COND]]
+// IR-NEXT: br i1 [[CMP4]], label %[[FOR_BODY5:.*]], label %[[FOR_END13:.*]]
+// IR: [[FOR_BODY5]]:
+// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
+// IR-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 1
+// IR-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL]]
+// IR-NEXT: store i32 [[ADD6]], ptr [[I]], align 4
+// IR-NEXT: store i32 0, ptr [[J]], align 4
+// IR-NEXT: br label %[[FOR_COND7:.*]]
+// IR: [[FOR_COND7]]:
+// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[J]], align 4
+// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// IR-NEXT: [[CMP8:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
+// IR-NEXT: br i1 [[CMP8]], label %[[FOR_BODY9:.*]], label %[[FOR_END:.*]]
+// IR: [[FOR_BODY9]]:
+// IR-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4
+// IR-NEXT: [[TMP9:%.*]] = load i32, ptr [[J]], align 4
+// IR-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
+// IR-NEXT: call void @body(i32 noundef [[ADD10]])
+// IR-NEXT: br label %[[FOR_INC:.*]]
+// IR: [[FOR_INC]]:
+// IR-NEXT: [[TMP10:%.*]] = load i32, ptr [[J]], align 4
+// IR-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1
+// IR-NEXT: store i32 [[INC]], ptr [[J]], align 4
+// IR-NEXT: br label %[[FOR_COND7]], !llvm.loop [[LOOP5:![0-9]+]]
+// IR: [[FOR_END]]:
+// IR-NEXT: br label %[[FOR_INC11:.*]]
+// IR: [[FOR_INC11]]:
+// IR-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4
+// IR-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP11]], 1
+// IR-NEXT: store i32 [[INC12]], ptr [[DOTTILE_0_IV_I]], align 4
+// IR-NEXT: br label %[[FOR_COND1]], !llvm.loop [[LOOP6:![0-9]+]]
+// IR: [[FOR_END13]]:
+// IR-NEXT: br label %[[FOR_INC14:.*]]
+// IR: [[FOR_INC14]]:
+// IR-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4
+// IR-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP12]], 4
+// IR-NEXT: store i32 [[ADD15]], ptr [[DOTFLOOR_0_IV_I]], align 4
+// IR-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
+// IR: [[FOR_END16]]:
+// IR-NEXT: ret void
+//
+void nested_inner_j(int n) {
+#pragma omp tile sizes(4)
+ for (int i = 0; i < 6; ++i)
+ for (int j = 0; j < n; ++j)
+ body(i + j);
+}
+//.
+// IR: [[LOOP2]] = distinct !{[[LOOP2]], [[META3:![0-9]+]]}
+// IR: [[META3]] = !{!"llvm.loop.mustprogress"}
+// IR: [[LOOP4]] = distinct !{[[LOOP4]], [[META3]]}
+// IR: [[LOOP5]] = distinct !{[[LOOP5]], [[META3]]}
+// IR: [[LOOP6]] = distinct !{[[LOOP6]], [[META3]]}
+// IR: [[LOOP7]] = distinct !{[[LOOP7]], [[META3]]}
+//.
diff --git a/clang/test/OpenMP/tile_vectorize_codegen.cpp b/clang/test/OpenMP/tile_vectorize_codegen.cpp
new file mode 100644
index 0000000000000..f2f110c0372c4
--- /dev/null
+++ b/clang/test/OpenMP/tile_vectorize_codegen.cpp
@@ -0,0 +1,28 @@
+// RUN: %clang_cc1 -verify -triple x86_64-unknown-linux-gnu -fclang-abi-compat=latest -std=c++17 -fopenmp -O2 -vectorize-loops -vectorize-slp -emit-llvm %s -o - | FileCheck %s
+// REQUIRES: x86-registered-target
+// expected-no-diagnostics
+
+// Why the intra-tile loop is stored min-bounded: that form carries its trip
+// count in the loop bound and vectorizes, while the rectangular form a
+// 'collapse' consumer needs adds a body guard that blocks the vectorizer. Both
+// sides are checked here so the tradeoff is visible in one place.
+
+// CHECK-LABEL: define {{.*}} @vec_tile(
+// CHECK: fadd <4 x float>
+extern "C" void vec_tile(float *a, float *b, int n) {
+#pragma omp tile sizes(64)
+ for (int i = 0; i < n; ++i)
+ a[i] = a[i] + b[i];
+}
+
+// CHECK-LABEL: define internal void @vec_tile_collapsed.omp_outlined(
+// CHECK-NOT: fadd <4 x float>
+// CHECK: br i1 %{{.*}}, label %omp.body.next, label %omp.inner.for.inc
+// CHECK-NOT: fadd <4 x float>
+// CHECK: ret void
+extern "C" void vec_tile_collapsed(float *a, float *b, int n) {
+#pragma omp parallel for collapse(2)
+#pragma omp tile sizes(64)
+ for (int i = 0; i < n; ++i)
+ a[i] = a[i] + b[i];
+}
diff --git a/clang/unittests/AST/AttrTest.cpp b/clang/unittests/AST/AttrTest.cpp
index cbdc3a1cc59a9..56096054dd267 100644
--- a/clang/unittests/AST/AttrTest.cpp
+++ b/clang/unittests/AST/AttrTest.cpp
@@ -8,6 +8,7 @@
#include "clang/AST/Attr.h"
#include "clang/AST/ASTContext.h"
+#include "clang/AST/StmtOpenMP.h"
#include "clang/ASTMatchers/ASTMatchFinder.h"
#include "clang/ASTMatchers/ASTMatchers.h"
#include "clang/Basic/AttrKinds.h"
@@ -272,4 +273,69 @@ TEST(Attr, UnknownScopedAttributeSpellingIndex) {
EXPECT_EQ(CI.getAttributeSpellingListIndex(), 0u);
}
+template <typename NodeT> const NodeT *findFirst(const Stmt *S) {
+ if (!S)
+ return nullptr;
+ if (const auto *N = dyn_cast<NodeT>(S))
+ return N;
+ for (const Stmt *C : S->children())
+ if (const NodeT *N = findFirst<NodeT>(C))
+ return N;
+ return nullptr;
+}
+
+const OMPInvariantPredicateBoundAttr *findIntraTileHint(const Stmt *S) {
+ if (const auto *AS = findFirst<AttributedStmt>(S))
+ for (const Attr *A : AS->getAttrs())
+ if (const auto *Hint = dyn_cast<OMPInvariantPredicateBoundAttr>(A))
+ return Hint;
+ return nullptr;
+}
+
+// The intra-tile loop generated by '#pragma omp tile' carries an internal
+// OMPInvariantPredicateBoundAttr; that marker is what lets a consuming
+// directive such as 'collapse' reinterpret the min-bounded loop as a
+// rectangular one with a constant trip count.
+//
+// Assert on the attribute directly here,
+// including the fact that the overshoot predicate is dropped when the trip
+// count is a compile-time multiple of the tile size.
+TEST(Attr, OMPInvariantPredicateBoundOnIntraTileLoop) {
+ auto AST = buildASTFromCodeWithArgs(
+ R"cpp(
+ void body(int);
+ void partial_last_tile() {
+ #pragma omp tile sizes(5)
+ for (int i = 0; i < 11; ++i)
+ body(i);
+ }
+ void full_tiles_only() {
+ #pragma omp tile sizes(5)
+ for (int i = 0; i < 10; ++i)
+ body(i);
+ }
+ )cpp",
+ {"-fopenmp"});
+ ASSERT_TRUE(AST);
+
+ auto GetHint = [&AST](const char *FuncName) {
+ const FunctionDecl *Func = getFunctionNode(AST.get(), FuncName);
+ const auto *Tile = findFirst<OMPTileDirective>(Func->getBody());
+ EXPECT_TRUE(Tile);
+ return Tile ? findIntraTileHint(Tile->getTransformedStmt()) : nullptr;
+ };
+
+ const OMPInvariantPredicateBoundAttr *Partial = GetHint("partial_last_tile");
+ ASSERT_TRUE(Partial);
+ EXPECT_TRUE(Partial->getRectCond());
+ EXPECT_TRUE(Partial->getTileSize());
+ EXPECT_TRUE(Partial->getPredicate());
+
+ const OMPInvariantPredicateBoundAttr *Full = GetHint("full_tiles_only");
+ ASSERT_TRUE(Full);
+ EXPECT_TRUE(Full->getRectCond());
+ EXPECT_TRUE(Full->getTileSize());
+ EXPECT_FALSE(Full->getPredicate());
+}
+
} // namespace
diff --git a/openmp/runtime/test/transform/tile/parallel-wsloop-collapse-stacked-tile.cpp b/openmp/runtime/test/transform/tile/parallel-wsloop-collapse-stacked-tile.cpp
new file mode 100644
index 0000000000000..feb780e8d3aec
--- /dev/null
+++ b/openmp/runtime/test/transform/tile/parallel-wsloop-collapse-stacked-tile.cpp
@@ -0,0 +1,31 @@
+// RUN: %libomp-cxx-compile-and-run | FileCheck %s --match-full-lines
+
+// collapse(2) on stacked tiles: only outer floor+tile consumed (works).
+
+#ifndef HEADER
+#define HEADER
+
+#include <cstdlib>
+#include <cstdio>
+
+int main() {
+ printf("do\n");
+#pragma omp parallel for collapse(2) num_threads(1)
+#pragma omp tile sizes(2)
+#pragma omp tile sizes(4)
+ for (int i = 0; i < 6; ++i)
+ printf("i=%d\n", i);
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+#endif /* HEADER */
+
+// CHECK: do
+// CHECK-NEXT: i=0
+// CHECK-NEXT: i=1
+// CHECK-NEXT: i=2
+// CHECK-NEXT: i=3
+// CHECK-NEXT: i=4
+// CHECK-NEXT: i=5
+// CHECK-NEXT: done
diff --git a/openmp/runtime/test/transform/tile/parallel-wsloop-collapse-through-tile-2d.cpp b/openmp/runtime/test/transform/tile/parallel-wsloop-collapse-through-tile-2d.cpp
new file mode 100644
index 0000000000000..64c31fd9470a5
--- /dev/null
+++ b/openmp/runtime/test/transform/tile/parallel-wsloop-collapse-through-tile-2d.cpp
@@ -0,0 +1,56 @@
+// RUN: %libomp-cxx-compile-and-run | FileCheck %s --match-full-lines
+// RUN: %libomp-cxx-compile -O2 && %libomp-run | FileCheck %s --match-full-lines
+
+// 2-D tile consumed by collapse(4) (full) and collapse(3) (partial).
+
+#ifndef HEADER
+#define HEADER
+
+#include <cstdlib>
+#include <cstdio>
+
+int main() {
+ printf("full4\n");
+#pragma omp parallel for collapse(4) num_threads(1)
+#pragma omp tile sizes(2, 2)
+ for (int i = 0; i < 3; ++i)
+ for (int j = 0; j < 3; ++j)
+ printf("i=%d j=%d\n", i, j);
+
+ printf("part3\n");
+#pragma omp parallel for collapse(3) num_threads(1)
+#pragma omp tile sizes(2, 2)
+ for (int i = 0; i < 3; ++i)
+ for (int j = 0; j < 4; ++j)
+ printf("i=%d j=%d\n", i, j);
+
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+#endif /* HEADER */
+
+// CHECK: full4
+// CHECK-NEXT: i=0 j=0
+// CHECK-NEXT: i=0 j=1
+// CHECK-NEXT: i=1 j=0
+// CHECK-NEXT: i=1 j=1
+// CHECK-NEXT: i=0 j=2
+// CHECK-NEXT: i=1 j=2
+// CHECK-NEXT: i=2 j=0
+// CHECK-NEXT: i=2 j=1
+// CHECK-NEXT: i=2 j=2
+// CHECK-NEXT: part3
+// CHECK-NEXT: i=0 j=0
+// CHECK-NEXT: i=0 j=1
+// CHECK-NEXT: i=1 j=0
+// CHECK-NEXT: i=1 j=1
+// CHECK-NEXT: i=0 j=2
+// CHECK-NEXT: i=0 j=3
+// CHECK-NEXT: i=1 j=2
+// CHECK-NEXT: i=1 j=3
+// CHECK-NEXT: i=2 j=0
+// CHECK-NEXT: i=2 j=1
+// CHECK-NEXT: i=2 j=2
+// CHECK-NEXT: i=2 j=3
+// CHECK-NEXT: done
diff --git a/openmp/runtime/test/transform/tile/parallel-wsloop-collapse-through-tile-compose.cpp b/openmp/runtime/test/transform/tile/parallel-wsloop-collapse-through-tile-compose.cpp
new file mode 100644
index 0000000000000..15fe9e72564fc
--- /dev/null
+++ b/openmp/runtime/test/transform/tile/parallel-wsloop-collapse-through-tile-compose.cpp
@@ -0,0 +1,51 @@
+// RUN: %libomp-cxx-compile-and-run | FileCheck %s --match-full-lines
+// RUN: %libomp-cxx-compile -O2 && %libomp-run | FileCheck %s --match-full-lines
+
+// collapse consuming a tile composed with reverse.
+
+#ifndef HEADER
+#define HEADER
+
+#include <cstdlib>
+#include <cstdio>
+
+int main() {
+ printf("rev2\n");
+#pragma omp parallel for collapse(2) num_threads(1)
+#pragma omp tile sizes(2)
+#pragma omp reverse
+ for (int i = 0; i < 5; ++i)
+ printf("i=%d\n", i);
+
+ printf("rev3\n");
+#pragma omp parallel for collapse(3) num_threads(1)
+#pragma omp tile sizes(2)
+#pragma omp reverse
+ for (int i = 0; i < 5; ++i)
+ for (int j = 0; j < 2; ++j)
+ printf("i=%d j=%d\n", i, j);
+
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+#endif /* HEADER */
+
+// CHECK: rev2
+// CHECK-NEXT: i=4
+// CHECK-NEXT: i=3
+// CHECK-NEXT: i=2
+// CHECK-NEXT: i=1
+// CHECK-NEXT: i=0
+// CHECK-NEXT: rev3
+// CHECK-NEXT: i=4 j=0
+// CHECK-NEXT: i=4 j=1
+// CHECK-NEXT: i=3 j=0
+// CHECK-NEXT: i=3 j=1
+// CHECK-NEXT: i=2 j=0
+// CHECK-NEXT: i=2 j=1
+// CHECK-NEXT: i=1 j=0
+// CHECK-NEXT: i=1 j=1
+// CHECK-NEXT: i=0 j=0
+// CHECK-NEXT: i=0 j=1
+// CHECK-NEXT: done
diff --git a/openmp/runtime/test/transform/tile/parallel-wsloop-collapse-through-tile-iterator.cpp b/openmp/runtime/test/transform/tile/parallel-wsloop-collapse-through-tile-iterator.cpp
new file mode 100644
index 0000000000000..94f3399aef9e9
--- /dev/null
+++ b/openmp/runtime/test/transform/tile/parallel-wsloop-collapse-through-tile-iterator.cpp
@@ -0,0 +1,74 @@
+// RUN: %libomp-cxx-compile-and-run | FileCheck %s --match-full-lines
+// RUN: %libomp-cxx-compile -O2 && %libomp-run | FileCheck %s --match-full-lines
+
+// collapse consuming a tiled range-based-for loop.
+
+#ifndef HEADER
+#define HEADER
+
+#include <cstdlib>
+#include <cstdio>
+
+struct Range {
+ int lo, hi;
+ struct It {
+ int v;
+ int operator*() const { return v; }
+ It &operator++() {
+ ++v;
+ return *this;
+ }
+ It operator++(int) {
+ It t = *this;
+ ++v;
+ return t;
+ }
+ bool operator==(const It &o) const { return v == o.v; }
+ bool operator!=(const It &o) const { return v != o.v; }
+ int operator-(const It &o) const { return v - o.v; }
+ It operator+(int n) const { return It{v + n}; }
+ };
+ It begin() const { return It{lo}; }
+ It end() const { return It{hi}; }
+};
+
+int main() {
+ Range r{0, 5};
+
+ printf("iter2\n");
+#pragma omp parallel for collapse(2) num_threads(1)
+#pragma omp tile sizes(2)
+ for (int v : r)
+ printf("v=%d\n", v);
+
+ printf("iter3\n");
+#pragma omp parallel for collapse(3) num_threads(1)
+#pragma omp tile sizes(2)
+ for (int v : r)
+ for (int j = 0; j < 2; ++j)
+ printf("v=%d j=%d\n", v, j);
+
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+#endif /* HEADER */
+
+// CHECK: iter2
+// CHECK-NEXT: v=0
+// CHECK-NEXT: v=1
+// CHECK-NEXT: v=2
+// CHECK-NEXT: v=3
+// CHECK-NEXT: v=4
+// CHECK-NEXT: iter3
+// CHECK-NEXT: v=0 j=0
+// CHECK-NEXT: v=0 j=1
+// CHECK-NEXT: v=1 j=0
+// CHECK-NEXT: v=1 j=1
+// CHECK-NEXT: v=2 j=0
+// CHECK-NEXT: v=2 j=1
+// CHECK-NEXT: v=3 j=0
+// CHECK-NEXT: v=3 j=1
+// CHECK-NEXT: v=4 j=0
+// CHECK-NEXT: v=4 j=1
+// CHECK-NEXT: done
diff --git a/openmp/runtime/test/transform/tile/parallel-wsloop-collapse-through-tile.cpp b/openmp/runtime/test/transform/tile/parallel-wsloop-collapse-through-tile.cpp
new file mode 100644
index 0000000000000..2cdd3ea33703f
--- /dev/null
+++ b/openmp/runtime/test/transform/tile/parallel-wsloop-collapse-through-tile.cpp
@@ -0,0 +1,38 @@
+// RUN: %libomp-cxx-compile-and-run | FileCheck %s --match-full-lines
+// RUN: %libomp-cxx-compile -O2 && %libomp-run | FileCheck %s --match-full-lines
+
+// collapse(3) reaches through a tiled loop to include the inner `j` loop.
+
+#ifndef HEADER
+#define HEADER
+
+#include <cstdlib>
+#include <cstdio>
+
+int main() {
+ printf("do\n");
+#pragma omp parallel for collapse(3) num_threads(1)
+#pragma omp tile sizes(4)
+ for (int i = 0; i < 6; ++i)
+ for (int j = 0; j < 2; ++j)
+ printf("i=%d j=%d\n", i, j);
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+#endif /* HEADER */
+
+// CHECK: do
+// CHECK-NEXT: i=0 j=0
+// CHECK-NEXT: i=0 j=1
+// CHECK-NEXT: i=1 j=0
+// CHECK-NEXT: i=1 j=1
+// CHECK-NEXT: i=2 j=0
+// CHECK-NEXT: i=2 j=1
+// CHECK-NEXT: i=3 j=0
+// CHECK-NEXT: i=3 j=1
+// CHECK-NEXT: i=4 j=0
+// CHECK-NEXT: i=4 j=1
+// CHECK-NEXT: i=5 j=0
+// CHECK-NEXT: i=5 j=1
+// CHECK-NEXT: done
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