[clang] [clang-format] Recognize the signed modifier for Verilog struct (PR #219694)

[via cfe-commits]

https://github.com/sstwcw created https://github.com/llvm/llvm-project/pull/219694

after

```SystemVerilog
struct packed signed {
  int a;
} pack1;
```

before

```SystemVerilog
struct packed signed { int a; }
pack1;
```

>From 4ba0547d94c50e6099eaffaa223ac2ae91b58e3d Mon Sep 17 00:00:00 2001
From: sstwcw <su3e8a96kzlver at posteo.net>
Date: Sat, 29 Aug 2026 15:43:44 +0000
Subject: [PATCH] [clang-format] Recognize the signed modifier for Verilog
 struct

after

```SystemVerilog
struct packed signed {
  int a;
} pack1;
```

before

```SystemVerilog
struct packed signed { int a; }
pack1;
```
---
 clang/lib/Format/UnwrappedLineParser.cpp     |  4 +++-
 clang/unittests/Format/FormatTestVerilog.cpp | 21 ++++++++++++++++++++
 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp
index 3def19d0a9c89..f3b84e83a61be 100644
--- a/clang/lib/Format/UnwrappedLineParser.cpp
+++ b/clang/lib/Format/UnwrappedLineParser.cpp
@@ -4150,7 +4150,9 @@ void UnwrappedLineParser::parseRecord(bool ParseAsExpr, bool IsJavaRecord) {
                             tok::kw_alignas, tok::l_square) ||
          FormatTok->isAttribute() ||
          ((Style.isJava() || Style.isJavaScript()) &&
-          FormatTok->isOneOf(tok::period, tok::comma))) {
+          FormatTok->isOneOf(tok::period, tok::comma)) ||
+         (Style.isVerilog() &&
+          FormatTok->isOneOf(tok::kw_signed, tok::kw_unsigned))) {
     if (Style.isJavaScript() &&
         FormatTok->isOneOf(Keywords.kw_extends, Keywords.kw_implements)) {
       JSPastExtendsOrImplements = true;
diff --git a/clang/unittests/Format/FormatTestVerilog.cpp b/clang/unittests/Format/FormatTestVerilog.cpp
index 9b92d3e19204d..9baa3210dbd82 100644
--- a/clang/unittests/Format/FormatTestVerilog.cpp
+++ b/clang/unittests/Format/FormatTestVerilog.cpp
@@ -1412,6 +1412,27 @@ TEST_F(FormatTestVerilog, StringLiteral) {
                  getStyleWithColumns(getDefaultStyle(), 29));
 }
 
+TEST_F(FormatTestVerilog, Struct) {
+  verifyFormat("struct packed signed {\n"
+               "  int a;\n"
+               "} pack1;");
+  verifyFormat("struct packed {\n"
+               "  int a;\n"
+               "} pack1;");
+  verifyFormat("struct {\n"
+               "  int a;\n"
+               "} pack1;");
+  verifyFormat("typedef struct packed signed {\n"
+               "  bit [3 : 0] GFC;\n"
+               "} s_atmcell;");
+  verifyFormat("typedef struct {\n"
+               "  bit [3 : 0] GFC;\n"
+               "} s_atmcell;");
+  verifyFormat("typedef struct packed {\n"
+               "  bit [3 : 0] GFC;\n"
+               "} s_atmcell;");
+}
+
 TEST_F(FormatTestVerilog, StructLiteral) {
   verifyFormat("c = '{0, 0.0};");
   verifyFormat("c = '{'{1, 1.0}, '{2, 2.0}};");