[clang] [llvm] [mlir] [clang][NVPTX][MLIR][NVVM] Add overloaded fadd intrinsics (PR #217336)

[Durgadoss R via cfe-commits]

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@@ -7048,24 +7071,65 @@ static SDValue combineF16AddWithNeg(SDNode *N, SelectionDAG &DAG,
     return SDValue();
   }
 
-  SDLoc DL(N);
-  return DAG.getNode(getF16SubOpc(AddIntrinsicID), DL, N->getValueType(0),
-                     SubOp1, SubOp2);
+  return DAG.getNode(Opc, SDLoc(N), VT, SubOp1, SubOp2);
+}
+
+static bool isSupportedFAdd(EVT VT, Intrinsic::ID IID, APFloat::roundingMode RM,
+                            const NVPTXSubtarget &STI) {
+  if (VT.isVector() && VT.getVectorElementCount() != ElementCount::getFixed(2))
+    return false;
+
+  const bool IsSat = nvvm::FAddShouldSaturate(IID);
+  switch (VT.getScalarType().getSimpleVT().SimpleTy) {
+  case MVT::f16:
+    return RM == APFloat::rmNearestTiesToEven;
+  case MVT::bf16:
+    return RM == APFloat::rmNearestTiesToEven && !IsSat &&
+           !nvvm::FAddShouldFTZ(IID) && STI.hasNativeBF16Support(ISD::FADD);
+  case MVT::f32:
+    return !VT.isVector() || (!IsSat && STI.hasF32x2Instructions());
+  case MVT::f64:
+    return !VT.isVector() && !IsSat && !nvvm::FAddShouldFTZ(IID);
+  default:
+    return false;
+  }
+}
+
+static SDValue diagnoseInvalidFAdd(SDNode *N, SelectionDAG &DAG,
+                                   Intrinsic::ID IID, APFloat::roundingMode RM,
+                                   const NVPTXSubtarget &STI) {
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durga4github wrote:

let us have the STI as the third argument .. and then IID, RM can follow

https://github.com/llvm/llvm-project/pull/217336