[clang] [llvm] [AArch64] Implement the atomic store with hint intrinsic (PR #198316)

[via cfe-commits]

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@@ -0,0 +1,470 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel=1 -global-isel-abort=0 -verify-machineinstrs < %s | FileCheck %s
+
+;
+; W register offset
+;
+
+; Int
+
+define void @relaxed_store_hint_roW_i8(ptr %ptr, i32 %offset, i8 %val) nounwind {
+; CHECK-LABEL: relaxed_store_hint_roW_i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    stshh keep
+; CHECK-NEXT:    strb w2, [x0, w1, sxtw]
+; CHECK-NEXT:    ret
+  %addr = getelementptr i8, ptr %ptr, i32 %offset
+  store atomic i8 %val, ptr %addr monotonic, align 8, !mem.cache_hint !0
+  ret void
+}
+
+define void @relaxed_store_hint_roW_i16(ptr %ptr, i32 %offset, i16 %val) nounwind {
+; CHECK-LABEL: relaxed_store_hint_roW_i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    stshh keep
+; CHECK-NEXT:    strh w2, [x0, w1, sxtw #1]
+; CHECK-NEXT:    ret
+  %addr = getelementptr i16, ptr %ptr, i32 %offset
+  store atomic i16 %val, ptr %addr monotonic, align 8, !mem.cache_hint !0
+  ret void
+}
+
+define void @relaxed_store_hint_roW_i32(ptr %ptr, i32 %offset, i32 %val) nounwind {
+; CHECK-LABEL: relaxed_store_hint_roW_i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    stshh keep
+; CHECK-NEXT:    str w2, [x0, w1, sxtw #2]
+; CHECK-NEXT:    ret
+  %addr = getelementptr i32, ptr %ptr, i32 %offset
+  store atomic i32 %val, ptr %addr monotonic, align 8, !mem.cache_hint !0
+  ret void
+}
+
+define void @relaxed_store_hint_roW_i64(ptr %ptr, i32 %offset, i64 %val) nounwind {
+; CHECK-LABEL: relaxed_store_hint_roW_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    stshh keep
+; CHECK-NEXT:    str x2, [x0, w1, sxtw #3]
+; CHECK-NEXT:    ret
+  %addr = getelementptr i64, ptr %ptr, i32 %offset
+  store atomic i64 %val, ptr %addr monotonic, align 8, !mem.cache_hint !0
+  ret void
+}
+
+; FP
+
+define void @relaxed_store_hint_roW_mfloat(ptr %ptr, i32 %offset, <1 x i8> %val) nounwind {
+; CHECK-LABEL: relaxed_store_hint_roW_mfloat:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    umov w8, v0.b[0]
+; CHECK-NEXT:    stshh strm
+; CHECK-NEXT:    strb w8, [x0, w1, sxtw]
+; CHECK-NEXT:    ret
+  %addr = getelementptr <1 x i8>, ptr %ptr, i32 %offset
+  store atomic <1 x i8> %val, ptr %addr monotonic, align 8, !mem.cache_hint !2
+  ret void
+}
+
+define void @relaxed_store_hint_roW_bfloat(ptr %ptr, i32 %offset, bfloat %val) nounwind {
+; CHECK-LABEL: relaxed_store_hint_roW_bfloat:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $h0 killed $h0 def $s0
+; CHECK-NEXT:    fmov w8, s0
+; CHECK-NEXT:    stshh strm
+; CHECK-NEXT:    strh w8, [x0, w1, sxtw #1]
----------------
Lukacma wrote:

I think you are missing patterns for floating point values. We have equivalent SIMD instructions in [ISA](https://support.arm.com/documentation/ddi0602/2026-06/SIMD-FP-Instructions/STR--register--SIMD-FP---Store-SIMD-FP-register--register-offset--?lang=en) we could lower to, so the mov is unnecessary here. Similarly for other variants.

https://github.com/llvm/llvm-project/pull/198316