[clang] 3f22626 - [RISCV] Remove experimental from Zicfiss. (#217794)
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cfe-commits at lists.llvm.org
Thu Aug 20 21:57:27 PDT 2026
Author: Craig Topper
Date: 2026-08-21T04:57:21Z
New Revision: 3f226265c84026cbe6965b317757c96989cb6ff8
URL: https://github.com/llvm/llvm-project/commit/3f226265c84026cbe6965b317757c96989cb6ff8
DIFF: https://github.com/llvm/llvm-project/commit/3f226265c84026cbe6965b317757c96989cb6ff8.diff
LOG: [RISCV] Remove experimental from Zicfiss. (#217794)
Use zimop in test command lines were possible.
At this point9, no code checks Zicfiss being enabled. Everything is
based on Zimop. I don't know for sure if shadow stack support is
complete at this point, but the extension being marked experimental
isn't enough to warn users.
Added:
Modified:
clang/test/Driver/print-enabled-extensions/riscv-sifive-x390.c
clang/test/Driver/print-supported-extensions-riscv.c
llvm/docs/ReleaseNotes.md
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/test/CodeGen/RISCV/features-info.ll
llvm/test/CodeGen/RISCV/option-arch-experimental.ll
llvm/test/CodeGen/RISCV/shadow-stack-zcmp.ll
llvm/test/CodeGen/RISCV/shadowcallstack-frame-flags.ll
llvm/test/CodeGen/RISCV/shadowcallstack.ll
llvm/test/MC/RISCV/compressed-zicfiss.s
llvm/test/MC/RISCV/zicfiss-invalid.s
llvm/test/MC/RISCV/zicfiss-valid.s
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Removed:
################################################################################
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-sifive-x390.c b/clang/test/Driver/print-enabled-extensions/riscv-sifive-x390.c
index aa038a18693e0..efe2a20900fbb 100644
--- a/clang/test/Driver/print-enabled-extensions/riscv-sifive-x390.c
+++ b/clang/test/Driver/print-enabled-extensions/riscv-sifive-x390.c
@@ -17,6 +17,7 @@
// CHECK-NEXT: ziccamoa 1.0 'Ziccamoa' (Main Memory Supports All Atomics in A)
// CHECK-NEXT: ziccif 1.0 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)
// CHECK-NEXT: ziccrse 1.0 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)
+// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack)
// CHECK-NEXT: zicntr 2.0 'Zicntr' (Base Counters and Timers)
// CHECK-NEXT: zicond 1.0 'Zicond' (Integer Conditional Operations)
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
@@ -66,6 +67,5 @@
// CHECK-EMPTY:
// CHECK-NEXT: Experimental extensions
// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad)
-// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack)
// CHECK-EMPTY:
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_ziccrse1p0_zicfilp1p0_zicfiss1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkr1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfbfwma1p0_zvfh1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_xsifivecdiscarddlone1p0_xsifivecflushdlone1p0
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index f90a5fc581baa..16bdda144fba9 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -25,6 +25,7 @@
// CHECK-NEXT: ziccif 1.0 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)
// CHECK-NEXT: zicclsm 1.0 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)
// CHECK-NEXT: ziccrse 1.0 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)
+// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack)
// CHECK-NEXT: zicntr 2.0 'Zicntr' (Base Counters and Timers)
// CHECK-NEXT: zicond 1.0 'Zicond' (Integer Conditional Operations)
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
@@ -248,7 +249,6 @@
// CHECK-NEXT: y 0.98 'Y' ('Base Y' (CHERI))
// CHECK-NEXT: zibi 0.1 'Zibi' (Branch with Immediate)
// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad)
-// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack)
// CHECK-NEXT: zilx 0.1 'Zilx' (Indexed Integer Load Instructions)
// CHECK-NEXT: zvabd 0.7 'Zvabd' (Vector Absolute Difference)
// CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 9e4811067aa4d..1f13119292c6c 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -115,15 +115,13 @@ Makes programs 10x faster by doing Special New Thing.
* Added experimental MC support for the `Smcsps` and `Sscsps`
conditional stack pointer swap extensions.
-
* Adds experimental assembler/CodeGen support for the `Zilx` (Indexed Integer
Load) extension.
-
* Added experimental MC support for the `Smijt` and `Ssijt` interrupt jump
table extensions and the `Smehv` and `Ssehv` synchronous exception hardware
vectoring extensions.
-
* Bump Svukte extension to 1.0.
+* Remove experimental from Zicfiss.
### Changes to the WebAssembly Backend
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 2abc78ff874c2..5c4f274b515c2 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -185,8 +185,8 @@ def FeatureStdExtZicfilp
[FeatureStdExtZicsr]>;
def FeatureStdExtZicfiss
- : RISCVExperimentalExtension<1, 0, "Shadow stack",
- [FeatureStdExtZicsr, FeatureStdExtZimop]>,
+ : RISCVExtension<1, 0, "Shadow stack",
+ [FeatureStdExtZicsr, FeatureStdExtZimop]>,
RISCVExtensionBitmask<1, 27>;
def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">,
AssemblerPredicate<(all_of FeatureStdExtZicfiss),
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index 08cf62f61296c..ba271f9087aff 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -38,7 +38,6 @@
; CHECK-NEXT: experimental-y - 'Y' ('Base Y' (CHERI)).
; CHECK-NEXT: experimental-zibi - 'Zibi' (Branch with Immediate).
; CHECK-NEXT: experimental-zicfilp - 'Zicfilp' (Landing pad).
-; CHECK-NEXT: experimental-zicfiss - 'Zicfiss' (Shadow stack).
; CHECK-NEXT: experimental-zilx - 'Zilx' (Indexed Integer Load Instructions).
; CHECK-NEXT: experimental-zvabd - 'Zvabd' (Vector Absolute Difference).
; CHECK-NEXT: experimental-zvbc32e - 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements).
@@ -335,6 +334,7 @@
; CHECK-NEXT: ziccif - 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement).
; CHECK-NEXT: zicclsm - 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores).
; CHECK-NEXT: ziccrse - 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences).
+; CHECK-NEXT: zicfiss - 'Zicfiss' (Shadow stack).
; CHECK-NEXT: zicntr - 'Zicntr' (Base Counters and Timers).
; CHECK-NEXT: zicond - 'Zicond' (Integer Conditional Operations).
; CHECK-NEXT: zicsr - 'Zicsr' (CSRs).
diff --git a/llvm/test/CodeGen/RISCV/option-arch-experimental.ll b/llvm/test/CodeGen/RISCV/option-arch-experimental.ll
index b40e16acc735c..c83af6147fffa 100644
--- a/llvm/test/CodeGen/RISCV/option-arch-experimental.ll
+++ b/llvm/test/CodeGen/RISCV/option-arch-experimental.ll
@@ -3,9 +3,9 @@
; RUN: | llvm-mc -triple=riscv64 -mattr=+experimental -filetype=obj -o /dev/null
; CHECK: .option push
-; CHECK-NEXT: .option arch, +zicfiss, +zicsr, +zimop
+; CHECK-NEXT: .option arch, +zilx
; CHECK-NOT: experimental-
-define void @f() "target-features"="+experimental-zicfiss" {
+define void @f() "target-features"="+experimental-zilx" {
; CHECK-LABEL: f:
; CHECK: .option pop
entry:
diff --git a/llvm/test/CodeGen/RISCV/shadow-stack-zcmp.ll b/llvm/test/CodeGen/RISCV/shadow-stack-zcmp.ll
index 77feb85036981..60dcc09604315 100644
--- a/llvm/test/CodeGen/RISCV/shadow-stack-zcmp.ll
+++ b/llvm/test/CodeGen/RISCV/shadow-stack-zcmp.ll
@@ -54,4 +54,4 @@ for.body: ; preds = %entry, %for.body
; Function Attrs: nofree nounwind
declare dso_local noundef i32 @printf(ptr noundef readonly captures(none), ...) local_unnamed_addr #0
-attributes #0 = { "hw-shadow-stack" "target-features"="+experimental-zicfiss,+zcmop,+zcmp" }
+attributes #0 = { "hw-shadow-stack" "target-features"="+zimop,+zcmop,+zcmp" }
diff --git a/llvm/test/CodeGen/RISCV/shadowcallstack-frame-flags.ll b/llvm/test/CodeGen/RISCV/shadowcallstack-frame-flags.ll
index 1a0008d625cf5..21eb6bb74fe85 100644
--- a/llvm/test/CodeGen/RISCV/shadowcallstack-frame-flags.ll
+++ b/llvm/test/CodeGen/RISCV/shadowcallstack-frame-flags.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -mtriple=riscv32 -mattr=+experimental-zicfiss \
+; RUN: llc < %s -mtriple=riscv32 -mattr=+zimop \
; RUN: -verify-machineinstrs -stop-after=prolog-epilog \
; RUN: | FileCheck %s --check-prefix=RV32
-; RUN: llc < %s -mtriple=riscv64 -mattr=+experimental-zicfiss \
+; RUN: llc < %s -mtriple=riscv64 -mattr=+zimop \
; RUN: -verify-machineinstrs -stop-after=prolog-epilog \
; RUN: | FileCheck %s --check-prefix=RV64
diff --git a/llvm/test/CodeGen/RISCV/shadowcallstack.ll b/llvm/test/CodeGen/RISCV/shadowcallstack.ll
index 82a5e70e2977d..24fa8037f3502 100644
--- a/llvm/test/CodeGen/RISCV/shadowcallstack.ll
+++ b/llvm/test/CodeGen/RISCV/shadowcallstack.ll
@@ -4,16 +4,16 @@
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefix=RV64
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
-; RUN: -mattr=+zcmp,+experimental-zicfiss,+zcmop | FileCheck %s --check-prefix=RV64-ZCMP
+; RUN: -mattr=+zcmp,+zimop,+zcmop | FileCheck %s --check-prefix=RV64-ZCMP
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN: -mattr=+zcmp,+experimental-zicfiss | FileCheck %s --check-prefix=RV32-ZCMP-NOZCMOP
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfiss < %s \
+; RUN: -mattr=+zcmp,+zimop | FileCheck %s --check-prefix=RV32-ZCMP-NOZCMOP
+; RUN: llc -mtriple=riscv32 -mattr=+zimop < %s \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=RV32-ZICFISS,RV32-NOZCMOP
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfiss < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+zimop < %s \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=RV64-ZICFISS,RV64-NOZCMOP
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfiss,+zcmop < %s -M no-aliases \
+; RUN: llc -mtriple=riscv32 -mattr=+zimop,+zcmop < %s -M no-aliases \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=RV32-ZICFISS,RV32-ZCMOP
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfiss,+zcmop < %s -M no-aliases \
+; RUN: llc -mtriple=riscv64 -mattr=+zimop,+zcmop < %s -M no-aliases \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=RV64-ZICFISS,RV64-ZCMOP
define void @f1() shadowcallstack {
diff --git a/llvm/test/MC/RISCV/compressed-zicfiss.s b/llvm/test/MC/RISCV/compressed-zicfiss.s
index bd4bf1858b6dc..aa5bf2df8d800 100644
--- a/llvm/test/MC/RISCV/compressed-zicfiss.s
+++ b/llvm/test/MC/RISCV/compressed-zicfiss.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+zcmop -M no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicfiss,+zcmop -M no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+zcmop < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zicfiss,+zcmop -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zicfiss,+zcmop < %s \
+# RUN: | llvm-objdump --mattr=+zicfiss,+zcmop -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+zcmop -M no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicfiss,+zcmop -M no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+zcmop < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zicfiss,+zcmop -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zicfiss,+zcmop < %s \
+# RUN: | llvm-objdump --mattr=+zicfiss,+zcmop -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
#
# Compressed Zicfiss instructions only require Zcmop (and Zimop for
diff --git a/llvm/test/MC/RISCV/zicfiss-invalid.s b/llvm/test/MC/RISCV/zicfiss-invalid.s
index f978d8c2c5ce8..559c8c6afc411 100644
--- a/llvm/test/MC/RISCV/zicfiss-invalid.s
+++ b/llvm/test/MC/RISCV/zicfiss-invalid.s
@@ -1,6 +1,6 @@
-# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+zcmop,+c -M no-aliases -show-encoding \
+# RUN: not llvm-mc %s -triple=riscv32 -mattr=+zicfiss,+zcmop,+c -M no-aliases -show-encoding \
# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
-# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+zcmop,+c -M no-aliases -show-encoding \
+# RUN: not llvm-mc %s -triple=riscv64 -mattr=+zicfiss,+zcmop,+c -M no-aliases -show-encoding \
# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
# CHECK-ERR: error: register must be ra or t0 (x1 or x5)
diff --git a/llvm/test/MC/RISCV/zicfiss-valid.s b/llvm/test/MC/RISCV/zicfiss-valid.s
index 5f6d70dedcf25..4ab4665d69552 100644
--- a/llvm/test/MC/RISCV/zicfiss-valid.s
+++ b/llvm/test/MC/RISCV/zicfiss-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+a,+experimental-zicfiss -M no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+a,+zicfiss -M no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a,+experimental-zicfiss < %s \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a,+zicfiss < %s \
# RUN: | llvm-objdump --mattr=+a,+experimental-zicfiss -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -defsym=RV64=1 -mattr=+a,+experimental-zicfiss -M no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -defsym=RV64=1 -mattr=+a,+zicfiss -M no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM-RV64,CHECK-ASM,CHECK-ASM-AND-OBJ-RV64,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -defsym=RV64=1 -mattr=+a,+experimental-zicfiss < %s \
-# RUN: | llvm-objdump --mattr=+a,+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -defsym=RV64=1 -mattr=+a,+zicfiss < %s \
+# RUN: | llvm-objdump --mattr=+a,+zicfiss -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ-RV64,CHECK-ASM-AND-OBJ %s
#
# Zicfiss MOP-based instructions (sspopchk, ssrdp, sspush) only require Zimop,
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 94261564e8043..4411127da160d 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1415,6 +1415,7 @@ R"(All available -march extensions for RISC-V
ziccif 1.0
zicclsm 1.0
ziccrse 1.0
+ zicfiss 1.0
zicntr 2.0
zicond 1.0
zicsr 2.0
@@ -1638,7 +1639,6 @@ Experimental extensions
y 0.98
zibi 0.1
zicfilp 1.0 This is a long dummy description
- zicfiss 1.0
zilx 0.1
zvabd 0.7
zvbc32e 0.7
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