[clang] 0c29000 - [clang][CIR][AArch64] Add lowering for conversion intrinsics (#217017)
via cfe-commits
cfe-commits at lists.llvm.org
Wed Aug 19 00:06:33 PDT 2026
Author: Andrzej Warzyński
Date: 2026-08-19T08:06:26+01:00
New Revision: 0c290008e752f31dee8704c21705552f46e2ee88
URL: https://github.com/llvm/llvm-project/commit/0c290008e752f31dee8704c21705552f46e2ee88
DIFF: https://github.com/llvm/llvm-project/commit/0c290008e752f31dee8704c21705552f46e2ee88.diff
LOG: [clang][CIR][AArch64] Add lowering for conversion intrinsics (#217017)
This PR adds lowering for intrinsic from the following groups:
* https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions
It continues the work started in #190961, #193273, #199990, #209252,
#211609 and #216757.
This PR implements the conversions for the following "truncating to
nearest" intrinsics:
* vcvtnd_s32_f64
* vcvtnd_s64_f64
* vcvtnd_u32_f64
* vcvtnd_u64_f64
This PR implements the conversions for the following
1) "round towards minus inf" intrinsics:
* vcvtm_s32_f32
* vcvtmq_s32_f32
* vcvtm_u32_f32
* vcvtmq_u32_f32
* vcvtms_s32_f32
* vcvtms_s64_f32
* vcvtms_u32_f32
* vcvtms_u64_f32
* vcvtm_s64_f64
* vcvtmq_s64_f64
* vcvtm_u64_f64
* vcvtmq_u64_f64
* vcvtmd_s32_f64
* vcvtmd_s64_f64
* vcvtmd_u32_f64
* vcvtmd_u64_f64
2) "round towards plus inf" intrinsics:
* vcvtp_s32_f32
* vcvtpq_s32_f32
* vcvtp_u32_f32
* vcvtpq_u32_f32
* vcvtps_s32_f32
* vcvtps_s64_f32
* vcvtps_u32_f32
* vcvtps_u64_f32
* vcvtp_s64_f64
* vcvtpq_s64_f64
* vcvtp_u64_f64
* vcvtpq_u64_f64
* vcvtpd_s32_f64
* vcvtpd_s64_f64
* vcvtpd_u32_f64
* vcvtpd_u64_f64
3) "round towards away nearest" intrinsics:
* vcvta_s32_f32
* vcvtaq_s32_f32
* vcvta_u32_f32
* vcvtaq_u32_f32
* vcvtas_s32_f32
* vcvtas_s64_f32
* vcvtas_u32_f32
* vcvtas_u64_f32
* vcvta_s64_f64
* vcvtaq_s64_f64
* vcvta_u64_f64
* vcvtaq_u64_f64
* vcvtad_s32_f64
* vcvtad_s64_f64
* vcvtad_u32_f64
* vcvtad_u64_f64
The corresponding tests are moved from:
* clang/test/CodeGen/AArch64/
to:
* clang/test/CodeGen/AArch64/neon/
The lowering follows the existing implementation in
CodeGen/TargetBuiltins/ARM.cpp.
Added:
Modified:
clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
clang/lib/CodeGen/TargetBuiltins/ARM.cpp
clang/test/CodeGen/AArch64/neon-fcvt-intrinsics.c
clang/test/CodeGen/AArch64/neon-intrinsics.c
clang/test/CodeGen/AArch64/neon-misc.c
clang/test/CodeGen/AArch64/neon/intrinsics.c
Removed:
################################################################################
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index bb20e8f3ed73d..f2bc4141f433e 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -455,6 +455,34 @@ emitCommonNeonSISDBuiltinExpr(CIRGenFunction &cgf,
case NEON::BI__builtin_neon_vcvtns_s64_f32:
case NEON::BI__builtin_neon_vcvtns_u32_f32:
case NEON::BI__builtin_neon_vcvtns_u64_f32:
+ case NEON::BI__builtin_neon_vcvtnd_s32_f64:
+ case NEON::BI__builtin_neon_vcvtnd_s64_f64:
+ case NEON::BI__builtin_neon_vcvtnd_u32_f64:
+ case NEON::BI__builtin_neon_vcvtnd_u64_f64:
+ case NEON::BI__builtin_neon_vcvtms_s32_f32:
+ case NEON::BI__builtin_neon_vcvtms_s64_f32:
+ case NEON::BI__builtin_neon_vcvtms_u32_f32:
+ case NEON::BI__builtin_neon_vcvtms_u64_f32:
+ case NEON::BI__builtin_neon_vcvtmd_s32_f64:
+ case NEON::BI__builtin_neon_vcvtmd_u32_f64:
+ case NEON::BI__builtin_neon_vcvtmd_s64_f64:
+ case NEON::BI__builtin_neon_vcvtmd_u64_f64:
+ case NEON::BI__builtin_neon_vcvtps_s32_f32:
+ case NEON::BI__builtin_neon_vcvtps_s64_f32:
+ case NEON::BI__builtin_neon_vcvtps_u32_f32:
+ case NEON::BI__builtin_neon_vcvtps_u64_f32:
+ case NEON::BI__builtin_neon_vcvtpd_s32_f64:
+ case NEON::BI__builtin_neon_vcvtpd_u32_f64:
+ case NEON::BI__builtin_neon_vcvtpd_s64_f64:
+ case NEON::BI__builtin_neon_vcvtpd_u64_f64:
+ case NEON::BI__builtin_neon_vcvtas_s32_f32:
+ case NEON::BI__builtin_neon_vcvtas_s64_f32:
+ case NEON::BI__builtin_neon_vcvtas_u32_f32:
+ case NEON::BI__builtin_neon_vcvtas_u64_f32:
+ case NEON::BI__builtin_neon_vcvtad_s32_f64:
+ case NEON::BI__builtin_neon_vcvtad_u32_f64:
+ case NEON::BI__builtin_neon_vcvtad_s64_f64:
+ case NEON::BI__builtin_neon_vcvtad_u64_f64:
case NEON::BI__builtin_neon_vaddlv_s32:
case NEON::BI__builtin_neon_vaddlv_u32:
case NEON::BI__builtin_neon_vaddlvq_s32:
@@ -3245,30 +3273,51 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
case NEON::BI__builtin_neon_vcvtq_u64_v:
case NEON::BI__builtin_neon_vcvtq_s16_f16:
case NEON::BI__builtin_neon_vcvtq_u16_f16:
+
case NEON::BI__builtin_neon_vcvta_s16_f16:
case NEON::BI__builtin_neon_vcvta_u16_f16:
- case NEON::BI__builtin_neon_vcvta_s32_v:
case NEON::BI__builtin_neon_vcvtaq_s16_f16:
+ case NEON::BI__builtin_neon_vcvtaq_u16_f16:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
+ case NEON::BI__builtin_neon_vcvta_s32_v:
case NEON::BI__builtin_neon_vcvtaq_s32_v:
case NEON::BI__builtin_neon_vcvta_u32_v:
- case NEON::BI__builtin_neon_vcvtaq_u16_f16:
case NEON::BI__builtin_neon_vcvtaq_u32_v:
case NEON::BI__builtin_neon_vcvta_s64_v:
case NEON::BI__builtin_neon_vcvtaq_s64_v:
case NEON::BI__builtin_neon_vcvta_u64_v:
- case NEON::BI__builtin_neon_vcvtaq_u64_v:
+ case NEON::BI__builtin_neon_vcvtaq_u64_v: {
+ auto argTy = getFloatNeonType(*this, type);
+ llvm::StringRef intrName =
+ usgn ? "aarch64.neon.fcvtau" : "aarch64.neon.fcvtas";
+ return emitNeonCall(cgm, builder, {argTy}, ops, intrName, ty, loc);
+ }
+
case NEON::BI__builtin_neon_vcvtm_s16_f16:
- case NEON::BI__builtin_neon_vcvtm_s32_v:
case NEON::BI__builtin_neon_vcvtmq_s16_f16:
- case NEON::BI__builtin_neon_vcvtmq_s32_v:
case NEON::BI__builtin_neon_vcvtm_u16_f16:
- case NEON::BI__builtin_neon_vcvtm_u32_v:
case NEON::BI__builtin_neon_vcvtmq_u16_f16:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
+ case NEON::BI__builtin_neon_vcvtm_s32_v:
+ case NEON::BI__builtin_neon_vcvtmq_s32_v:
+ case NEON::BI__builtin_neon_vcvtm_u32_v:
case NEON::BI__builtin_neon_vcvtmq_u32_v:
case NEON::BI__builtin_neon_vcvtm_s64_v:
case NEON::BI__builtin_neon_vcvtmq_s64_v:
case NEON::BI__builtin_neon_vcvtm_u64_v:
- case NEON::BI__builtin_neon_vcvtmq_u64_v:
+ case NEON::BI__builtin_neon_vcvtmq_u64_v: {
+ auto argTy = getFloatNeonType(*this, type);
+ llvm::StringRef intrName =
+ usgn ? "aarch64.neon.fcvtmu" : "aarch64.neon.fcvtms";
+ return emitNeonCall(cgm, builder, {argTy}, ops, intrName, ty, loc);
+ }
+
case NEON::BI__builtin_neon_vcvtn_s16_f16:
case NEON::BI__builtin_neon_vcvtnq_s16_f16:
case NEON::BI__builtin_neon_vcvtn_u16_f16:
@@ -3293,17 +3342,27 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
}
case NEON::BI__builtin_neon_vcvtp_s16_f16:
- case NEON::BI__builtin_neon_vcvtp_s32_v:
case NEON::BI__builtin_neon_vcvtpq_s16_f16:
- case NEON::BI__builtin_neon_vcvtpq_s32_v:
case NEON::BI__builtin_neon_vcvtp_u16_f16:
- case NEON::BI__builtin_neon_vcvtp_u32_v:
case NEON::BI__builtin_neon_vcvtpq_u16_f16:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
+ case NEON::BI__builtin_neon_vcvtp_s32_v:
+ case NEON::BI__builtin_neon_vcvtpq_s32_v:
+ case NEON::BI__builtin_neon_vcvtp_u32_v:
case NEON::BI__builtin_neon_vcvtpq_u32_v:
case NEON::BI__builtin_neon_vcvtp_s64_v:
case NEON::BI__builtin_neon_vcvtpq_s64_v:
case NEON::BI__builtin_neon_vcvtp_u64_v:
- case NEON::BI__builtin_neon_vcvtpq_u64_v:
+ case NEON::BI__builtin_neon_vcvtpq_u64_v: {
+ auto argTy = getFloatNeonType(*this, type);
+ llvm::StringRef intrName =
+ usgn ? "aarch64.neon.fcvtpu" : "aarch64.neon.fcvtps";
+ return emitNeonCall(cgm, builder, {argTy}, ops, intrName, ty, loc);
+ }
+
case NEON::BI__builtin_neon_vmulx_v:
case NEON::BI__builtin_neon_vmulxq_v:
case NEON::BI__builtin_neon_vmulxh_lane_f16:
diff --git a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
index bc322ae5c8b17..22e0dfc55157f 100644
--- a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
@@ -6403,12 +6403,12 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
return EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vcvta");
}
case NEON::BI__builtin_neon_vcvtm_s16_f16:
- case NEON::BI__builtin_neon_vcvtm_s32_v:
case NEON::BI__builtin_neon_vcvtmq_s16_f16:
- case NEON::BI__builtin_neon_vcvtmq_s32_v:
case NEON::BI__builtin_neon_vcvtm_u16_f16:
- case NEON::BI__builtin_neon_vcvtm_u32_v:
case NEON::BI__builtin_neon_vcvtmq_u16_f16:
+ case NEON::BI__builtin_neon_vcvtm_s32_v:
+ case NEON::BI__builtin_neon_vcvtmq_s32_v:
+ case NEON::BI__builtin_neon_vcvtm_u32_v:
case NEON::BI__builtin_neon_vcvtmq_u32_v:
case NEON::BI__builtin_neon_vcvtm_s64_v:
case NEON::BI__builtin_neon_vcvtmq_s64_v:
@@ -6435,12 +6435,12 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
return EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vcvtn");
}
case NEON::BI__builtin_neon_vcvtp_s16_f16:
- case NEON::BI__builtin_neon_vcvtp_s32_v:
case NEON::BI__builtin_neon_vcvtpq_s16_f16:
- case NEON::BI__builtin_neon_vcvtpq_s32_v:
case NEON::BI__builtin_neon_vcvtp_u16_f16:
- case NEON::BI__builtin_neon_vcvtp_u32_v:
case NEON::BI__builtin_neon_vcvtpq_u16_f16:
+ case NEON::BI__builtin_neon_vcvtp_s32_v:
+ case NEON::BI__builtin_neon_vcvtpq_s32_v:
+ case NEON::BI__builtin_neon_vcvtp_u32_v:
case NEON::BI__builtin_neon_vcvtpq_u32_v:
case NEON::BI__builtin_neon_vcvtp_s64_v:
case NEON::BI__builtin_neon_vcvtpq_s64_v:
diff --git a/clang/test/CodeGen/AArch64/neon-fcvt-intrinsics.c b/clang/test/CodeGen/AArch64/neon-fcvt-intrinsics.c
index d1c76e0250549..f460065112444 100644
--- a/clang/test/CodeGen/AArch64/neon-fcvt-intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon-fcvt-intrinsics.c
@@ -15,283 +15,3 @@
float32_t test_vcvtxd_f32_f64(float64_t a) {
return (float32_t)vcvtxd_f32_f64(a);
}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtas_s32_f32
-// CHECK-SAME: (float noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTAS_S32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtas.i32.f32(float [[A]])
-// CHECK-NEXT: ret i32 [[VCVTAS_S32_F32_I]]
-//
-int32_t test_vcvtas_s32_f32(float32_t a) {
- return (int32_t)vcvtas_s32_f32(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtad_s64_f64
-// CHECK-SAME: (double noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTAD_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtas.i64.f64(double [[A]])
-// CHECK-NEXT: ret i64 [[VCVTAD_S64_F64_I]]
-//
-int64_t test_vcvtad_s64_f64(float64_t a) {
- return (int64_t)vcvtad_s64_f64(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtas_s64_f32
-// CHECK-SAME: (float noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTAS_S64_F32_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtas.i64.f32(float [[A]])
-// CHECK-NEXT: ret i64 [[VCVTAS_S64_F32_I]]
-//
-int64_t test_vcvtas_s64_f32(float32_t a) {
- return (int64_t)vcvtas_s64_f32(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtad_s32_f64
-// CHECK-SAME: (double noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTAD_S32_F64_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtas.i32.f64(double [[A]])
-// CHECK-NEXT: ret i32 [[VCVTAD_S32_F64_I]]
-//
-int32_t test_vcvtad_s32_f64(float64_t a) {
- return (int32_t)vcvtad_s32_f64(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtas_u32_f32
-// CHECK-SAME: (float noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTAS_U32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float [[A]])
-// CHECK-NEXT: ret i32 [[VCVTAS_U32_F32_I]]
-//
-uint32_t test_vcvtas_u32_f32(float32_t a) {
- return (uint32_t)vcvtas_u32_f32(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtad_u64_f64
-// CHECK-SAME: (double noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTAD_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtau.i64.f64(double [[A]])
-// CHECK-NEXT: ret i64 [[VCVTAD_U64_F64_I]]
-//
-uint64_t test_vcvtad_u64_f64(float64_t a) {
- return (uint64_t)vcvtad_u64_f64(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtas_u64_f32
-// CHECK-SAME: (float noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTAS_U64_F32_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtau.i64.f32(float [[A]])
-// CHECK-NEXT: ret i64 [[VCVTAS_U64_F32_I]]
-//
-uint64_t test_vcvtas_u64_f32(float32_t a) {
- return (uint64_t)vcvtas_u64_f32(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtad_u32_f64
-// CHECK-SAME: (double noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTAD_U32_F64_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtau.i32.f64(double [[A]])
-// CHECK-NEXT: ret i32 [[VCVTAD_U32_F64_I]]
-//
-uint32_t test_vcvtad_u32_f64(float64_t a) {
- return (uint32_t)vcvtad_u32_f64(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtms_s32_f32
-// CHECK-SAME: (float noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTMS_S32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtms.i32.f32(float [[A]])
-// CHECK-NEXT: ret i32 [[VCVTMS_S32_F32_I]]
-//
-int32_t test_vcvtms_s32_f32(float32_t a) {
- return (int32_t)vcvtms_s32_f32(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtmd_s64_f64
-// CHECK-SAME: (double noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTMD_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtms.i64.f64(double [[A]])
-// CHECK-NEXT: ret i64 [[VCVTMD_S64_F64_I]]
-//
-int64_t test_vcvtmd_s64_f64(float64_t a) {
- return (int64_t)vcvtmd_s64_f64(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtms_s64_f32
-// CHECK-SAME: (float noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTMS_S64_F32_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtms.i64.f32(float [[A]])
-// CHECK-NEXT: ret i64 [[VCVTMS_S64_F32_I]]
-//
-int64_t test_vcvtms_s64_f32(float32_t a) {
- return (int64_t)vcvtms_s64_f32(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtmd_s32_f64
-// CHECK-SAME: (double noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTMD_S32_F64_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtms.i32.f64(double [[A]])
-// CHECK-NEXT: ret i32 [[VCVTMD_S32_F64_I]]
-//
-int32_t test_vcvtmd_s32_f64(float64_t a) {
- return (int32_t)vcvtmd_s32_f64(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtms_u32_f32
-// CHECK-SAME: (float noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTMS_U32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtmu.i32.f32(float [[A]])
-// CHECK-NEXT: ret i32 [[VCVTMS_U32_F32_I]]
-//
-uint32_t test_vcvtms_u32_f32(float32_t a) {
- return (uint32_t)vcvtms_u32_f32(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtmd_u64_f64
-// CHECK-SAME: (double noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTMD_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtmu.i64.f64(double [[A]])
-// CHECK-NEXT: ret i64 [[VCVTMD_U64_F64_I]]
-//
-uint64_t test_vcvtmd_u64_f64(float64_t a) {
- return (uint64_t)vcvtmd_u64_f64(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtms_u64_f32
-// CHECK-SAME: (float noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTMS_U64_F32_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtmu.i64.f32(float [[A]])
-// CHECK-NEXT: ret i64 [[VCVTMS_U64_F32_I]]
-//
-uint64_t test_vcvtms_u64_f32(float32_t a) {
- return (uint64_t)vcvtms_u64_f32(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtmd_u32_f64
-// CHECK-SAME: (double noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTMD_U32_F64_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtmu.i32.f64(double [[A]])
-// CHECK-NEXT: ret i32 [[VCVTMD_U32_F64_I]]
-//
-uint32_t test_vcvtmd_u32_f64(float64_t a) {
- return (uint32_t)vcvtmd_u32_f64(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtnd_s64_f64
-// CHECK-SAME: (double noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTND_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtns.i64.f64(double [[A]])
-// CHECK-NEXT: ret i64 [[VCVTND_S64_F64_I]]
-//
-int64_t test_vcvtnd_s64_f64(float64_t a) {
- return (int64_t)vcvtnd_s64_f64(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtnd_s32_f64
-// CHECK-SAME: (double noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTND_S32_F64_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtns.i32.f64(double [[A]])
-// CHECK-NEXT: ret i32 [[VCVTND_S32_F64_I]]
-//
-int32_t test_vcvtnd_s32_f64(float64_t a) {
- return (int32_t)vcvtnd_s32_f64(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtnd_u64_f64
-// CHECK-SAME: (double noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTND_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtnu.i64.f64(double [[A]])
-// CHECK-NEXT: ret i64 [[VCVTND_U64_F64_I]]
-//
-uint64_t test_vcvtnd_u64_f64(float64_t a) {
- return (uint64_t)vcvtnd_u64_f64(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtnd_u32_f64
-// CHECK-SAME: (double noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTND_U32_F64_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtnu.i32.f64(double [[A]])
-// CHECK-NEXT: ret i32 [[VCVTND_U32_F64_I]]
-//
-uint32_t test_vcvtnd_u32_f64(float64_t a) {
- return (uint32_t)vcvtnd_u32_f64(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtps_s32_f32
-// CHECK-SAME: (float noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTPS_S32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtps.i32.f32(float [[A]])
-// CHECK-NEXT: ret i32 [[VCVTPS_S32_F32_I]]
-//
-int32_t test_vcvtps_s32_f32(float32_t a) {
- return (int32_t)vcvtps_s32_f32(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtpd_s64_f64
-// CHECK-SAME: (double noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTPD_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtps.i64.f64(double [[A]])
-// CHECK-NEXT: ret i64 [[VCVTPD_S64_F64_I]]
-//
-int64_t test_vcvtpd_s64_f64(float64_t a) {
- return (int64_t)vcvtpd_s64_f64(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtps_s64_f32
-// CHECK-SAME: (float noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTPS_S64_F32_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtps.i64.f32(float [[A]])
-// CHECK-NEXT: ret i64 [[VCVTPS_S64_F32_I]]
-//
-int64_t test_vcvtps_s64_f32(float32_t a) {
- return (int64_t)vcvtps_s64_f32(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtpd_s32_f64
-// CHECK-SAME: (double noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTPD_S32_F64_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtps.i32.f64(double [[A]])
-// CHECK-NEXT: ret i32 [[VCVTPD_S32_F64_I]]
-//
-int32_t test_vcvtpd_s32_f64(float64_t a) {
- return (int32_t)vcvtpd_s32_f64(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtps_u32_f32
-// CHECK-SAME: (float noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTPS_U32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtpu.i32.f32(float [[A]])
-// CHECK-NEXT: ret i32 [[VCVTPS_U32_F32_I]]
-//
-uint32_t test_vcvtps_u32_f32(float32_t a) {
- return (uint32_t)vcvtps_u32_f32(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtpd_u64_f64
-// CHECK-SAME: (double noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTPD_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtpu.i64.f64(double [[A]])
-// CHECK-NEXT: ret i64 [[VCVTPD_U64_F64_I]]
-//
-uint64_t test_vcvtpd_u64_f64(float64_t a) {
- return (uint64_t)vcvtpd_u64_f64(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtps_u64_f32
-// CHECK-SAME: (float noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTPS_U64_F32_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtpu.i64.f32(float [[A]])
-// CHECK-NEXT: ret i64 [[VCVTPS_U64_F32_I]]
-//
-uint64_t test_vcvtps_u64_f32(float32_t a) {
- return (uint64_t)vcvtps_u64_f32(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vcvtpd_u32_f64
-// CHECK-SAME: (double noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VCVTPD_U32_F64_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtpu.i32.f64(double [[A]])
-// CHECK-NEXT: ret i32 [[VCVTPD_U32_F64_I]]
-//
-uint32_t test_vcvtpd_u32_f64(float64_t a) {
- return (uint32_t)vcvtpd_u32_f64(a);
-}
diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c
index ca38406a1ed45..79cb1c42cd5af 100644
--- a/clang/test/CodeGen/AArch64/neon-intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c
@@ -12440,90 +12440,6 @@ float64x1_t test_vneg_f64(float64x1_t a) {
return vneg_f64(a);
}
-// CHECK-LABEL: define dso_local <1 x i64> @test_vcvtp_s64_f64(
-// CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
-// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[VCVTP_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
-// CHECK-NEXT: [[VCVTP1_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.v1f64(<1 x double> [[VCVTP_I]])
-// CHECK-NEXT: ret <1 x i64> [[VCVTP1_I]]
-//
-int64x1_t test_vcvtp_s64_f64(float64x1_t a) {
- return vcvtp_s64_f64(a);
-}
-
-// CHECK-LABEL: define dso_local <1 x i64> @test_vcvtp_u64_f64(
-// CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
-// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[VCVTP_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
-// CHECK-NEXT: [[VCVTP1_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtpu.v1i64.v1f64(<1 x double> [[VCVTP_I]])
-// CHECK-NEXT: ret <1 x i64> [[VCVTP1_I]]
-//
-uint64x1_t test_vcvtp_u64_f64(float64x1_t a) {
- return vcvtp_u64_f64(a);
-}
-
-// CHECK-LABEL: define dso_local <1 x i64> @test_vcvtm_s64_f64(
-// CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
-// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[VCVTM_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
-// CHECK-NEXT: [[VCVTM1_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.v1f64(<1 x double> [[VCVTM_I]])
-// CHECK-NEXT: ret <1 x i64> [[VCVTM1_I]]
-//
-int64x1_t test_vcvtm_s64_f64(float64x1_t a) {
- return vcvtm_s64_f64(a);
-}
-
-// CHECK-LABEL: define dso_local <1 x i64> @test_vcvtm_u64_f64(
-// CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
-// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[VCVTM_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
-// CHECK-NEXT: [[VCVTM1_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.v1f64(<1 x double> [[VCVTM_I]])
-// CHECK-NEXT: ret <1 x i64> [[VCVTM1_I]]
-//
-uint64x1_t test_vcvtm_u64_f64(float64x1_t a) {
- return vcvtm_u64_f64(a);
-}
-
-// CHECK-LABEL: define dso_local <1 x i64> @test_vcvta_s64_f64(
-// CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
-// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[VCVTA_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
-// CHECK-NEXT: [[VCVTA1_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.v1f64(<1 x double> [[VCVTA_I]])
-// CHECK-NEXT: ret <1 x i64> [[VCVTA1_I]]
-//
-int64x1_t test_vcvta_s64_f64(float64x1_t a) {
- return vcvta_s64_f64(a);
-}
-
-// CHECK-LABEL: define dso_local <1 x i64> @test_vcvta_u64_f64(
-// CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
-// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[VCVTA_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
-// CHECK-NEXT: [[VCVTA1_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.v1f64(<1 x double> [[VCVTA_I]])
-// CHECK-NEXT: ret <1 x i64> [[VCVTA1_I]]
-//
-uint64x1_t test_vcvta_u64_f64(float64x1_t a) {
- return vcvta_u64_f64(a);
-}
-
// CHECK-LABEL: define dso_local <1 x double> @test_vcvt_f64_s64(
// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
diff --git a/clang/test/CodeGen/AArch64/neon-misc.c b/clang/test/CodeGen/AArch64/neon-misc.c
index 9ce457d0121c1..cfc85c7bd3c52 100644
--- a/clang/test/CodeGen/AArch64/neon-misc.c
+++ b/clang/test/CodeGen/AArch64/neon-misc.c
@@ -2827,240 +2827,6 @@ float64x2_t test_vrndiq_f64(float64x2_t a) {
return vrndiq_f64(a);
}
-// CHECK-LABEL: define dso_local <2 x i32> @test_vcvtp_s32_f32(
-// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[VCVTP_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
-// CHECK-NEXT: [[VCVTP1_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtps.v2i32.v2f32(<2 x float> [[VCVTP_I]])
-// CHECK-NEXT: ret <2 x i32> [[VCVTP1_I]]
-//
-int32x2_t test_vcvtp_s32_f32(float32x2_t a) {
- return vcvtp_s32_f32(a);
-}
-
-// CHECK-LABEL: define dso_local <4 x i32> @test_vcvtpq_s32_f32(
-// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[VCVTP_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
-// CHECK-NEXT: [[VCVTP1_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtps.v4i32.v4f32(<4 x float> [[VCVTP_I]])
-// CHECK-NEXT: ret <4 x i32> [[VCVTP1_I]]
-//
-int32x4_t test_vcvtpq_s32_f32(float32x4_t a) {
- return vcvtpq_s32_f32(a);
-}
-
-// CHECK-LABEL: define dso_local <2 x i64> @test_vcvtpq_s64_f64(
-// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[VCVTP_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
-// CHECK-NEXT: [[VCVTP1_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double> [[VCVTP_I]])
-// CHECK-NEXT: ret <2 x i64> [[VCVTP1_I]]
-//
-int64x2_t test_vcvtpq_s64_f64(float64x2_t a) {
- return vcvtpq_s64_f64(a);
-}
-
-// CHECK-LABEL: define dso_local <2 x i32> @test_vcvtp_u32_f32(
-// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[VCVTP_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
-// CHECK-NEXT: [[VCVTP1_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtpu.v2i32.v2f32(<2 x float> [[VCVTP_I]])
-// CHECK-NEXT: ret <2 x i32> [[VCVTP1_I]]
-//
-uint32x2_t test_vcvtp_u32_f32(float32x2_t a) {
- return vcvtp_u32_f32(a);
-}
-
-// CHECK-LABEL: define dso_local <4 x i32> @test_vcvtpq_u32_f32(
-// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[VCVTP_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
-// CHECK-NEXT: [[VCVTP1_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtpu.v4i32.v4f32(<4 x float> [[VCVTP_I]])
-// CHECK-NEXT: ret <4 x i32> [[VCVTP1_I]]
-//
-uint32x4_t test_vcvtpq_u32_f32(float32x4_t a) {
- return vcvtpq_u32_f32(a);
-}
-
-// CHECK-LABEL: define dso_local <2 x i64> @test_vcvtpq_u64_f64(
-// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[VCVTP_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
-// CHECK-NEXT: [[VCVTP1_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtpu.v2i64.v2f64(<2 x double> [[VCVTP_I]])
-// CHECK-NEXT: ret <2 x i64> [[VCVTP1_I]]
-//
-uint64x2_t test_vcvtpq_u64_f64(float64x2_t a) {
- return vcvtpq_u64_f64(a);
-}
-
-// CHECK-LABEL: define dso_local <2 x i32> @test_vcvtm_s32_f32(
-// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[VCVTM_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
-// CHECK-NEXT: [[VCVTM1_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtms.v2i32.v2f32(<2 x float> [[VCVTM_I]])
-// CHECK-NEXT: ret <2 x i32> [[VCVTM1_I]]
-//
-int32x2_t test_vcvtm_s32_f32(float32x2_t a) {
- return vcvtm_s32_f32(a);
-}
-
-// CHECK-LABEL: define dso_local <4 x i32> @test_vcvtmq_s32_f32(
-// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[VCVTM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
-// CHECK-NEXT: [[VCVTM1_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtms.v4i32.v4f32(<4 x float> [[VCVTM_I]])
-// CHECK-NEXT: ret <4 x i32> [[VCVTM1_I]]
-//
-int32x4_t test_vcvtmq_s32_f32(float32x4_t a) {
- return vcvtmq_s32_f32(a);
-}
-
-// CHECK-LABEL: define dso_local <2 x i64> @test_vcvtmq_s64_f64(
-// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[VCVTM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
-// CHECK-NEXT: [[VCVTM1_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double> [[VCVTM_I]])
-// CHECK-NEXT: ret <2 x i64> [[VCVTM1_I]]
-//
-int64x2_t test_vcvtmq_s64_f64(float64x2_t a) {
- return vcvtmq_s64_f64(a);
-}
-
-// CHECK-LABEL: define dso_local <2 x i32> @test_vcvtm_u32_f32(
-// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[VCVTM_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
-// CHECK-NEXT: [[VCVTM1_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtmu.v2i32.v2f32(<2 x float> [[VCVTM_I]])
-// CHECK-NEXT: ret <2 x i32> [[VCVTM1_I]]
-//
-uint32x2_t test_vcvtm_u32_f32(float32x2_t a) {
- return vcvtm_u32_f32(a);
-}
-
-// CHECK-LABEL: define dso_local <4 x i32> @test_vcvtmq_u32_f32(
-// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[VCVTM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
-// CHECK-NEXT: [[VCVTM1_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtmu.v4i32.v4f32(<4 x float> [[VCVTM_I]])
-// CHECK-NEXT: ret <4 x i32> [[VCVTM1_I]]
-//
-uint32x4_t test_vcvtmq_u32_f32(float32x4_t a) {
- return vcvtmq_u32_f32(a);
-}
-
-// CHECK-LABEL: define dso_local <2 x i64> @test_vcvtmq_u64_f64(
-// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[VCVTM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
-// CHECK-NEXT: [[VCVTM1_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double> [[VCVTM_I]])
-// CHECK-NEXT: ret <2 x i64> [[VCVTM1_I]]
-//
-uint64x2_t test_vcvtmq_u64_f64(float64x2_t a) {
- return vcvtmq_u64_f64(a);
-}
-
-// CHECK-LABEL: define dso_local <2 x i32> @test_vcvta_s32_f32(
-// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[VCVTA_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
-// CHECK-NEXT: [[VCVTA1_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float> [[VCVTA_I]])
-// CHECK-NEXT: ret <2 x i32> [[VCVTA1_I]]
-//
-int32x2_t test_vcvta_s32_f32(float32x2_t a) {
- return vcvta_s32_f32(a);
-}
-
-// CHECK-LABEL: define dso_local <4 x i32> @test_vcvtaq_s32_f32(
-// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[VCVTA_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
-// CHECK-NEXT: [[VCVTA1_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtas.v4i32.v4f32(<4 x float> [[VCVTA_I]])
-// CHECK-NEXT: ret <4 x i32> [[VCVTA1_I]]
-//
-int32x4_t test_vcvtaq_s32_f32(float32x4_t a) {
- return vcvtaq_s32_f32(a);
-}
-
-// CHECK-LABEL: define dso_local <2 x i64> @test_vcvtaq_s64_f64(
-// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[VCVTA_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
-// CHECK-NEXT: [[VCVTA1_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double> [[VCVTA_I]])
-// CHECK-NEXT: ret <2 x i64> [[VCVTA1_I]]
-//
-int64x2_t test_vcvtaq_s64_f64(float64x2_t a) {
- return vcvtaq_s64_f64(a);
-}
-
-// CHECK-LABEL: define dso_local <2 x i32> @test_vcvta_u32_f32(
-// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[VCVTA_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
-// CHECK-NEXT: [[VCVTA1_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float> [[VCVTA_I]])
-// CHECK-NEXT: ret <2 x i32> [[VCVTA1_I]]
-//
-uint32x2_t test_vcvta_u32_f32(float32x2_t a) {
- return vcvta_u32_f32(a);
-}
-
-// CHECK-LABEL: define dso_local <4 x i32> @test_vcvtaq_u32_f32(
-// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[VCVTA_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
-// CHECK-NEXT: [[VCVTA1_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float> [[VCVTA_I]])
-// CHECK-NEXT: ret <4 x i32> [[VCVTA1_I]]
-//
-uint32x4_t test_vcvtaq_u32_f32(float32x4_t a) {
- return vcvtaq_u32_f32(a);
-}
-
-// CHECK-LABEL: define dso_local <2 x i64> @test_vcvtaq_u64_f64(
-// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[VCVTA_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
-// CHECK-NEXT: [[VCVTA1_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double> [[VCVTA_I]])
-// CHECK-NEXT: ret <2 x i64> [[VCVTA1_I]]
-//
-uint64x2_t test_vcvtaq_u64_f64(float64x2_t a) {
- return vcvtaq_u64_f64(a);
-}
-
// CHECK-LABEL: define dso_local <2 x float> @test_vrsqrte_f32(
// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index 31eb0205389c6..12b181a4ee917 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -4842,6 +4842,616 @@ uint64x2_t test_vcvtnq_u64_f64(float64x2_t a) {
return vcvtnq_u64_f64(a);
}
+// LLVM-LABEL: @test_vcvtnd_s64_f64
+int64_t test_vcvtnd_s64_f64(float64_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtns"
+
+// LLVM-SAME: double {{.*}} [[A:%.*]])
+// LLVM: [[VCVTND_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtns.i64.f64(double [[A]])
+// LLVM: ret i64 [[VCVTND_S64_F64_I]]
+ return (int64_t)vcvtnd_s64_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtnd_s32_f64
+int32_t test_vcvtnd_s32_f64(float64_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtns"
+
+// LLVM-SAME: double {{.*}} [[A:%.*]])
+// LLVM: [[VCVTND_S32_F64_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtns.i32.f64(double [[A]])
+// LLVM: ret i32 [[VCVTND_S32_F64_I]]
+ return (int32_t)vcvtnd_s32_f64(a);
+}
+
+// LLVM-LABEL: define {{[^@]+}}@test_vcvtnd_u64_f64
+uint64_t test_vcvtnd_u64_f64(float64_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtnu"
+
+ return (uint64_t)vcvtnd_u64_f64(a);
+// LLVM-SAME: double {{.*}} [[A:%.*]])
+// LLVM: [[VCVTND_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtnu.i64.f64(double [[A]])
+// LLVM: ret i64 [[VCVTND_U64_F64_I]]
+}
+
+// LLVM-LABEL: @test_vcvtnd_u32_f64
+uint32_t test_vcvtnd_u32_f64(float64_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtnu"
+
+// LLVM-SAME: double {{.*}} [[A:%.*]])
+// LLVM: [[VCVTND_U32_F64_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtnu.i32.f64(double [[A]])
+// LLVM: ret i32 [[VCVTND_U32_F64_I]]
+ return (uint32_t)vcvtnd_u32_f64(a);
+}
+
+//===------------------------------------------------------===//
+// 2.1.4.1 Convearions (round towards minus inf)
+// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions
+//===------------------------------------------------------===//
+// LLVM-LABEL: @test_vcvtm_s32_f32
+int32x2_t test_vcvtm_s32_f32(float32x2_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtms"
+
+// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
+// LLVM: [[VCVTM1_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtms.v2i32.v2f32(<2 x float> [[VCVTM_I]])
+// LLVM: ret <2 x i32> [[VCVTM1_I]]
+ return vcvtm_s32_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtmq_s32_f32(
+int32x4_t test_vcvtmq_s32_f32(float32x4_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtms"
+
+// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
+// LLVM: [[VCVTM1_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtms.v4i32.v4f32(<4 x float> [[VCVTM_I]])
+// LLVM: ret <4 x i32> [[VCVTM1_I]]
+ return vcvtmq_s32_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtm_u32_f32(
+uint32x2_t test_vcvtm_u32_f32(float32x2_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtmu"
+
+// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]]) #[[ATTR0]] {
+// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
+// LLVM: [[VCVTM1_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtmu.v2i32.v2f32(<2 x float> [[VCVTM_I]])
+// LLVM: ret <2 x i32> [[VCVTM1_I]]
+ return vcvtm_u32_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtmq_u32_f32(
+uint32x4_t test_vcvtmq_u32_f32(float32x4_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtmu"
+
+// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
+// LLVM: [[VCVTM1_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtmu.v4i32.v4f32(<4 x float> [[VCVTM_I]])
+// LLVM: ret <4 x i32> [[VCVTM1_I]]
+ return vcvtmq_u32_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtms_s32_f32
+int32_t test_vcvtms_s32_f32(float32_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtms"
+
+// LLVM-SAME: float {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMS_S32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtms.i32.f32(float [[A]])
+// LLVM: ret i32 [[VCVTMS_S32_F32_I]]
+ return (int32_t)vcvtms_s32_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtms_s64_f32
+int64_t test_vcvtms_s64_f32(float32_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtms"
+
+// LLVM-SAME: float {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMS_S64_F32_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtms.i64.f32(float [[A]])
+// LLVM: ret i64 [[VCVTMS_S64_F32_I]]
+ return (int64_t)vcvtms_s64_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtms_u32_f32
+uint32_t test_vcvtms_u32_f32(float32_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtmu"
+
+// LLVM-SAME: float {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMS_U32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtmu.i32.f32(float [[A]])
+// LLVM: ret i32 [[VCVTMS_U32_F32_I]]
+ return (uint32_t)vcvtms_u32_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtms_u64_f32
+uint64_t test_vcvtms_u64_f32(float32_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtmu"
+
+// LLVM-SAME: float {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMS_U64_F32_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtmu.i64.f32(float [[A]])
+// LLVM: ret i64 [[VCVTMS_U64_F32_I]]
+ return (uint64_t)vcvtms_u64_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtm_s64_f64(
+int64x1_t test_vcvtm_s64_f64(float64x1_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtms"
+
+// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
+// LLVM: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
+// LLVM: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
+// LLVM: [[VCVTM1_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.v1f64(<1 x double> [[VCVTM_I]])
+// LLVM: ret <1 x i64> [[VCVTM1_I]]
+ return vcvtm_s64_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtmq_s64_f64(
+int64x2_t test_vcvtmq_s64_f64(float64x2_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtms"
+
+// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
+// LLVM: [[VCVTM1_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double> [[VCVTM_I]])
+// LLVM: ret <2 x i64> [[VCVTM1_I]]
+ return vcvtmq_s64_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtm_u64_f64(
+uint64x1_t test_vcvtm_u64_f64(float64x1_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtmu"
+
+// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]]) #[[ATTR0]] {
+// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
+// LLVM: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
+// LLVM: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
+// LLVM: [[VCVTM1_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.v1f64(<1 x double> [[VCVTM_I]])
+// LLVM: ret <1 x i64> [[VCVTM1_I]]
+ return vcvtm_u64_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtmq_u64_f64(
+uint64x2_t test_vcvtmq_u64_f64(float64x2_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtmu"
+
+// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
+// LLVM: [[VCVTM1_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double> [[VCVTM_I]])
+// LLVM: ret <2 x i64> [[VCVTM1_I]]
+ return vcvtmq_u64_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtmd_s32_f64
+int32_t test_vcvtmd_s32_f64(float64_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtms"
+
+// LLVM-SAME: double {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMD_S32_F64_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtms.i32.f64(double [[A]])
+// LLVM: ret i32 [[VCVTMD_S32_F64_I]]
+ return (int32_t)vcvtmd_s32_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtmd_s64_f64
+int64_t test_vcvtmd_s64_f64(float64_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtms"
+
+// LLVM-SAME: double {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMD_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtms.i64.f64(double [[A]])
+// LLVM: ret i64 [[VCVTMD_S64_F64_I]]
+ return (int64_t)vcvtmd_s64_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtmd_u64_f64
+uint64_t test_vcvtmd_u64_f64(float64_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtmu"
+
+// LLVM-SAME: double {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMD_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtmu.i64.f64(double [[A]])
+// LLVM: ret i64 [[VCVTMD_U64_F64_I]]
+ return (uint64_t)vcvtmd_u64_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtmd_u32_f64
+uint32_t test_vcvtmd_u32_f64(float64_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtmu"
+
+// LLVM-SAME: double {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMD_U32_F64_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtmu.i32.f64(double [[A]])
+// LLVM: ret i32 [[VCVTMD_U32_F64_I]]
+ return (uint32_t)vcvtmd_u32_f64(a);
+}
+
+//===------------------------------------------------------===//
+// 2.1.4.1 Convearions (round towards plus inf)
+// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions
+//===------------------------------------------------------===//
+// LLVM-LABEL: @test_vcvtp_s32_f32
+int32x2_t test_vcvtp_s32_f32(float32x2_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtps"
+
+// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
+// LLVM: [[VCVTM1_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtps.v2i32.v2f32(<2 x float> [[VCVTM_I]])
+// LLVM: ret <2 x i32> [[VCVTM1_I]]
+ return vcvtp_s32_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtpq_s32_f32(
+int32x4_t test_vcvtpq_s32_f32(float32x4_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtps"
+
+// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
+// LLVM: [[VCVTM1_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtps.v4i32.v4f32(<4 x float> [[VCVTM_I]])
+// LLVM: ret <4 x i32> [[VCVTM1_I]]
+ return vcvtpq_s32_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtp_u32_f32(
+uint32x2_t test_vcvtp_u32_f32(float32x2_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtpu"
+
+// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]]) #[[ATTR0]] {
+// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
+// LLVM: [[VCVTM1_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtpu.v2i32.v2f32(<2 x float> [[VCVTM_I]])
+// LLVM: ret <2 x i32> [[VCVTM1_I]]
+ return vcvtp_u32_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtpq_u32_f32(
+uint32x4_t test_vcvtpq_u32_f32(float32x4_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtpu"
+
+// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
+// LLVM: [[VCVTM1_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtpu.v4i32.v4f32(<4 x float> [[VCVTM_I]])
+// LLVM: ret <4 x i32> [[VCVTM1_I]]
+ return vcvtpq_u32_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtps_s32_f32
+int32_t test_vcvtps_s32_f32(float32_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtps"
+
+// LLVM-SAME: float {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMS_S32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtps.i32.f32(float [[A]])
+// LLVM: ret i32 [[VCVTMS_S32_F32_I]]
+ return (int32_t)vcvtps_s32_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtps_s64_f32
+int64_t test_vcvtps_s64_f32(float32_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtps"
+
+// LLVM-SAME: float {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMS_S64_F32_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtps.i64.f32(float [[A]])
+// LLVM: ret i64 [[VCVTMS_S64_F32_I]]
+ return (int64_t)vcvtps_s64_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtps_u32_f32
+uint32_t test_vcvtps_u32_f32(float32_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtpu"
+
+// LLVM-SAME: float {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMS_U32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtpu.i32.f32(float [[A]])
+// LLVM: ret i32 [[VCVTMS_U32_F32_I]]
+ return (uint32_t)vcvtps_u32_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtps_u64_f32
+uint64_t test_vcvtps_u64_f32(float32_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtpu"
+
+// LLVM-SAME: float {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMS_U64_F32_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtpu.i64.f32(float [[A]])
+// LLVM: ret i64 [[VCVTMS_U64_F32_I]]
+ return (uint64_t)vcvtps_u64_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtp_s64_f64(
+int64x1_t test_vcvtp_s64_f64(float64x1_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtps"
+
+// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
+// LLVM: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
+// LLVM: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
+// LLVM: [[VCVTM1_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.v1f64(<1 x double> [[VCVTM_I]])
+// LLVM: ret <1 x i64> [[VCVTM1_I]]
+ return vcvtp_s64_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtpq_s64_f64(
+int64x2_t test_vcvtpq_s64_f64(float64x2_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtps"
+
+// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
+// LLVM: [[VCVTM1_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double> [[VCVTM_I]])
+// LLVM: ret <2 x i64> [[VCVTM1_I]]
+ return vcvtpq_s64_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtp_u64_f64(
+uint64x1_t test_vcvtp_u64_f64(float64x1_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtpu"
+
+// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]]) #[[ATTR0]] {
+// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
+// LLVM: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
+// LLVM: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
+// LLVM: [[VCVTM1_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtpu.v1i64.v1f64(<1 x double> [[VCVTM_I]])
+// LLVM: ret <1 x i64> [[VCVTM1_I]]
+ return vcvtp_u64_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtpq_u64_f64(
+uint64x2_t test_vcvtpq_u64_f64(float64x2_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtpu"
+
+// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
+// LLVM: [[VCVTM1_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtpu.v2i64.v2f64(<2 x double> [[VCVTM_I]])
+// LLVM: ret <2 x i64> [[VCVTM1_I]]
+ return vcvtpq_u64_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtpd_s32_f64
+int32_t test_vcvtpd_s32_f64(float64_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtps"
+
+// LLVM-SAME: double {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMD_S32_F64_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtps.i32.f64(double [[A]])
+// LLVM: ret i32 [[VCVTMD_S32_F64_I]]
+ return (int32_t)vcvtpd_s32_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtpd_s64_f64
+int64_t test_vcvtpd_s64_f64(float64_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtps"
+
+// LLVM-SAME: double {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMD_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtps.i64.f64(double [[A]])
+// LLVM: ret i64 [[VCVTMD_S64_F64_I]]
+ return (int64_t)vcvtpd_s64_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtpd_u64_f64
+uint64_t test_vcvtpd_u64_f64(float64_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtpu"
+
+// LLVM-SAME: double {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMD_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtpu.i64.f64(double [[A]])
+// LLVM: ret i64 [[VCVTMD_U64_F64_I]]
+ return (uint64_t)vcvtpd_u64_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtpd_u32_f64
+uint32_t test_vcvtpd_u32_f64(float64_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtpu"
+
+// LLVM-SAME: double {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMD_U32_F64_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtpu.i32.f64(double [[A]])
+// LLVM: ret i32 [[VCVTMD_U32_F64_I]]
+ return (uint32_t)vcvtpd_u32_f64(a);
+}
+
+//===------------------------------------------------------===//
+// 2.1.4.1 Convearions (nearest away)
+// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions
+//===------------------------------------------------------===//
+// LLVM-LABEL: @test_vcvta_s32_f32
+int32x2_t test_vcvta_s32_f32(float32x2_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtas"
+
+// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
+// LLVM: [[VCVTM1_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float> [[VCVTM_I]])
+// LLVM: ret <2 x i32> [[VCVTM1_I]]
+ return vcvta_s32_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtaq_s32_f32(
+int32x4_t test_vcvtaq_s32_f32(float32x4_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtas"
+
+// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
+// LLVM: [[VCVTM1_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtas.v4i32.v4f32(<4 x float> [[VCVTM_I]])
+// LLVM: ret <4 x i32> [[VCVTM1_I]]
+ return vcvtaq_s32_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvta_u32_f32(
+uint32x2_t test_vcvta_u32_f32(float32x2_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtau"
+
+// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]]) #[[ATTR0]] {
+// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
+// LLVM: [[VCVTM1_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float> [[VCVTM_I]])
+// LLVM: ret <2 x i32> [[VCVTM1_I]]
+ return vcvta_u32_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtaq_u32_f32(
+uint32x4_t test_vcvtaq_u32_f32(float32x4_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtau"
+
+// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
+// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
+// LLVM: [[VCVTM1_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float> [[VCVTM_I]])
+// LLVM: ret <4 x i32> [[VCVTM1_I]]
+ return vcvtaq_u32_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtas_s32_f32
+int32_t test_vcvtas_s32_f32(float32_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtas"
+
+// LLVM-SAME: float {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMS_S32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtas.i32.f32(float [[A]])
+// LLVM: ret i32 [[VCVTMS_S32_F32_I]]
+ return (int32_t)vcvtas_s32_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtas_s64_f32
+int64_t test_vcvtas_s64_f32(float32_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtas"
+
+// LLVM-SAME: float {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMS_S64_F32_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtas.i64.f32(float [[A]])
+// LLVM: ret i64 [[VCVTMS_S64_F32_I]]
+ return (int64_t)vcvtas_s64_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtas_u32_f32
+uint32_t test_vcvtas_u32_f32(float32_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtau"
+
+// LLVM-SAME: float {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMS_U32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float [[A]])
+// LLVM: ret i32 [[VCVTMS_U32_F32_I]]
+ return (uint32_t)vcvtas_u32_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvtas_u64_f32
+uint64_t test_vcvtas_u64_f32(float32_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtau"
+
+// LLVM-SAME: float {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMS_U64_F32_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtau.i64.f32(float [[A]])
+// LLVM: ret i64 [[VCVTMS_U64_F32_I]]
+ return (uint64_t)vcvtas_u64_f32(a);
+}
+
+// LLVM-LABEL: @test_vcvta_s64_f64(
+int64x1_t test_vcvta_s64_f64(float64x1_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtas"
+
+// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
+// LLVM: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
+// LLVM: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
+// LLVM: [[VCVTM1_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.v1f64(<1 x double> [[VCVTM_I]])
+// LLVM: ret <1 x i64> [[VCVTM1_I]]
+ return vcvta_s64_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtaq_s64_f64(
+int64x2_t test_vcvtaq_s64_f64(float64x2_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtas"
+
+// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
+// LLVM: [[VCVTM1_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double> [[VCVTM_I]])
+// LLVM: ret <2 x i64> [[VCVTM1_I]]
+ return vcvtaq_s64_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvta_u64_f64(
+uint64x1_t test_vcvta_u64_f64(float64x1_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtau"
+
+// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]]) #[[ATTR0]] {
+// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
+// LLVM: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
+// LLVM: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
+// LLVM: [[VCVTM1_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.v1f64(<1 x double> [[VCVTM_I]])
+// LLVM: ret <1 x i64> [[VCVTM1_I]]
+ return vcvta_u64_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtaq_u64_f64(
+uint64x2_t test_vcvtaq_u64_f64(float64x2_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtau"
+
+// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// LLVM: [[VCVTM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
+// LLVM: [[VCVTM1_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double> [[VCVTM_I]])
+// LLVM: ret <2 x i64> [[VCVTM1_I]]
+ return vcvtaq_u64_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtad_s32_f64
+int32_t test_vcvtad_s32_f64(float64_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtas"
+
+// LLVM-SAME: double {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMD_S32_F64_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtas.i32.f64(double [[A]])
+// LLVM: ret i32 [[VCVTMD_S32_F64_I]]
+ return (int32_t)vcvtad_s32_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtad_s64_f64
+int64_t test_vcvtad_s64_f64(float64_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtas"
+
+// LLVM-SAME: double {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMD_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtas.i64.f64(double [[A]])
+// LLVM: ret i64 [[VCVTMD_S64_F64_I]]
+ return (int64_t)vcvtad_s64_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtad_u64_f64
+uint64_t test_vcvtad_u64_f64(float64_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtau"
+
+// LLVM-SAME: double {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMD_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtau.i64.f64(double [[A]])
+// LLVM: ret i64 [[VCVTMD_U64_F64_I]]
+ return (uint64_t)vcvtad_u64_f64(a);
+}
+
+// LLVM-LABEL: @test_vcvtad_u32_f64
+uint32_t test_vcvtad_u32_f64(float64_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtau"
+
+// LLVM-SAME: double {{.*}} [[A:%.*]])
+// LLVM: [[VCVTMD_U32_F64_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtau.i32.f64(double [[A]])
+// LLVM: ret i32 [[VCVTMD_U32_F64_I]]
+ return (uint32_t)vcvtad_u32_f64(a);
+}
+
//===------------------------------------------------------===//
// 2.1.3.2.3 Vector shift right and accumulate
// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-right-and-accumulate
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