[clang] [llvm] [ARM] Emit an error when the hard-float ABI is enabled but can't be used (PR #111334)
Chris Copeland via cfe-commits
cfe-commits at lists.llvm.org
Thu Aug 13 08:49:24 PDT 2026
https://github.com/chrisnc updated https://github.com/llvm/llvm-project/pull/111334
>From 89ee673b90a259d6ca140e1759a8f4c17e112664 Mon Sep 17 00:00:00 2001
From: Chris Copeland <chris at chrisnc.net>
Date: Wed, 22 Jul 2026 11:55:38 -0700
Subject: [PATCH] [ARM] Emit an error when the hard-float PCS is enabled but
can't be used
Prior to this, compiling for an eabihf target with a CPU lacking
floating-point registers would silently use the soft-float ABI instead,
even though the Arm attributes section would still have
"Tag_ABI_VFP_args: VFP registers", which leads to silent ABI mismatches
at link time.
Update various tests that were using inconsistent ABI/PCS and features.
Change ARMTargetLowering::getEffectiveCallingConv from private to public
and modify it to pass through unrecognized calling conventions. Now that
ARMBaseTargetMachine::createMachineFunctionInfo calls it, leaving a
fatal error would change the behavior of IR passes that do not need to
lower calling conventions. Unrecognized calling conventions are still
treated as errors in lowering.
Fixes #110383.
---
clang/test/CodeGenCXX/arm-pcs.cpp | 13 +-
llvm/docs/ReleaseNotes.md | 4 +
llvm/lib/Target/ARM/ARMISelLowering.cpp | 5 +-
llvm/lib/Target/ARM/ARMISelLowering.h | 4 +-
llvm/lib/Target/ARM/ARMTargetMachine.cpp | 40 +++++-
.../2013-04-05-Small-ByVal-Structs-PR15293.ll | 2 +-
.../ARM/2013-05-13-AAPCS-byval-padding.ll | 2 +-
.../ARM/2013-05-13-AAPCS-byval-padding2.ll | 2 +-
.../2014-02-21-byval-reg-split-alignment.ll | 2 +-
llvm/test/CodeGen/ARM/arm-eabi.ll | 24 ++--
llvm/test/CodeGen/ARM/arm-storebytesmerge.ll | 4 +-
llvm/test/CodeGen/ARM/block-order.mir | 4 +-
.../CodeGen/ARM/byval_struct_copy_tailcall.ll | 118 +++++++++---------
.../CodeGen/ARM/constant-islands-split-IT.mir | 2 +-
llvm/test/CodeGen/ARM/constantfp.ll | 42 +++----
llvm/test/CodeGen/ARM/constantpool-promote.ll | 8 +-
llvm/test/CodeGen/ARM/eabihf-no-fpregs.ll | 39 ++++++
llvm/test/CodeGen/ARM/fold-stack-adjust.ll | 2 +-
llvm/test/CodeGen/ARM/fp16-promote.ll | 2 +-
.../ARM/machine-outliner-thunk-tcgpr.mir | 2 +-
llvm/test/CodeGen/ARM/macho-extern-hidden.ll | 2 +-
llvm/test/CodeGen/ARM/memfunc.ll | 6 +-
.../ARM/no-expand-memcpy-no-builtins.ll | 2 +-
llvm/test/CodeGen/ARM/pei-swiftself.mir | 2 +-
llvm/test/CodeGen/ARM/readtp.ll | 8 +-
llvm/test/CodeGen/ARM/ssat-with-shift.ll | 10 +-
llvm/test/CodeGen/ARM/subtarget-align.ll | 2 +-
.../CodeGen/ARM/unsupported-calling-conv.ll | 6 +
.../CodeGen/ARM/unsupported-calling-conv.mir | 12 ++
llvm/test/CodeGen/ARM/usat-with-shift.ll | 8 +-
.../Thumb2/LowOverheadLoops/sibling-loops.ll | 2 +-
llvm/test/CodeGen/Thumb2/cde-gpr.ll | 24 ++--
llvm/test/CodeGen/Thumb2/emit-unwinding.ll | 2 +-
.../CodeGen/Thumb2/mve-gather-scatter-opt.ll | 8 +-
.../CodeGen/Thumb2/pacbti-m-outliner-1.ll | 4 +-
llvm/test/CodeGen/Thumb2/shift_parts.ll | 2 +-
llvm/test/DebugInfo/COFF/jump-table.ll | 4 +-
.../MIR/ARM/dbgcall-site-propagated-value.mir | 10 +-
38 files changed, 271 insertions(+), 164 deletions(-)
create mode 100644 llvm/test/CodeGen/ARM/eabihf-no-fpregs.ll
create mode 100644 llvm/test/CodeGen/ARM/unsupported-calling-conv.ll
create mode 100644 llvm/test/CodeGen/ARM/unsupported-calling-conv.mir
diff --git a/clang/test/CodeGenCXX/arm-pcs.cpp b/clang/test/CodeGenCXX/arm-pcs.cpp
index 1d327d794b721..f6b646a756224 100644
--- a/clang/test/CodeGenCXX/arm-pcs.cpp
+++ b/clang/test/CodeGenCXX/arm-pcs.cpp
@@ -6,6 +6,13 @@
// RUN: %clang -mfloat-abi=softfp --target=armv7-unknown-linux-gnueabi -O3 -S -o - %s | FileCheck %s -check-prefixes=SOFTFP,CHECK
// RUN: %clang -mfloat-abi=soft --target=armv7-unknown-linux-gnueabi -O3 -S -o - %s | FileCheck %s -check-prefixes=SOFT,CHECK
+// aapcs-vfp is only supported when fpregs is available.
+#ifdef __ARM_FP
+#define PCS_VFP __attribute__((pcs("aapcs-vfp")))
+#else
+#define PCS_VFP
+#endif
+
struct S {
float f;
float d;
@@ -15,7 +22,7 @@ struct S {
// Variadic functions should always marshal for the base standard.
// See section 5.5 (Parameter Passing) of the AAPCS.
-float __attribute__((pcs("aapcs-vfp"))) variadic(S s, ...) {
+float PCS_VFP variadic(S s, ...) {
// CHECK-NOT: vmov s{{[0-9]+}}, s{{[0-9]+}}
// CHECK: mov r{{[0-9]+}}, r{{[0-9]+}}
return s.d;
@@ -28,7 +35,7 @@ float no_attribute(S s) {
return s.d;
}
-float __attribute__((pcs("aapcs-vfp"))) baz(float x, float y) {
+float PCS_VFP baz(float x, float y) {
// CHECK-NOT: mov s{{[0-9]+}}, r{{[0-9]+}}
// SOFT: mov r{{[0-9]+}}, r{{[0-9]+}}
// SOFTFP: vmov.f32 s{{[0-9]+}}, s{{[0-9]+}}
@@ -36,7 +43,7 @@ float __attribute__((pcs("aapcs-vfp"))) baz(float x, float y) {
return y;
}
-float __attribute__((pcs("aapcs-vfp"))) foo(S s) {
+float PCS_VFP foo(S s) {
// CHECK-NOT: mov s{{[0-9]+}}, r{{[0-9]+}}
// SOFT: mov r{{[0-9]+}}, r{{[0-9]+}}
// SOFTFP: vmov.f32 s{{[0-9]+}}, s{{[0-9]+}}
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 785be1f827426..fa0ee49558255 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -87,6 +87,10 @@ Makes programs 10x faster by doing Special New Thing.
### Changes to the ARM Backend
+* Using the hard-float procedure call standard without floating-point registers
+ is now an error. Previously this would fall back to the soft-float PCS while
+ still emitting the hard-float ABI attribute tag.
+
### Changes to the AVR Backend
### Changes to the DirectX Backend
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 3a31e072831aa..7d1e89cc5ae73 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -1690,7 +1690,7 @@ ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
bool isVarArg) const {
switch (CC) {
default:
- report_fatal_error("Unsupported calling convention");
+ // Unknown CCs are rejected when calling convention lowering is required.
case CallingConv::ARM_AAPCS:
case CallingConv::ARM_APCS:
case CallingConv::GHC:
@@ -1708,8 +1708,7 @@ ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
case CallingConv::Tail:
if (!getTM().isAAPCS_ABI())
return CallingConv::ARM_APCS;
- else if (Subtarget->hasFPRegs() && !Subtarget->isThumb1Only() &&
- Subtarget->isTargetHardFloat() && !isVarArg)
+ else if (Subtarget->isTargetHardFloat() && !isVarArg)
return CallingConv::ARM_AAPCS_VFP;
else
return CallingConv::ARM_AAPCS;
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index 2bbb91a8758e2..30d9c4ea63054 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -439,6 +439,8 @@ class VectorType;
preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N,
unsigned ExpansionFactor) const override;
+ CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
+ bool isVarArg) const;
CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
@@ -539,8 +541,6 @@ class VectorType;
SDValue &Root, SelectionDAG &DAG,
const SDLoc &dl) const;
- CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
- bool isVarArg) const;
CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
bool isVarArg) const;
std::pair<SDValue, MachinePointerInfo>
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 3d388a7db6687..25b3b64d2cde2 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -35,8 +35,12 @@
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/Attributes.h"
+#include "llvm/IR/CallingConv.h"
#include "llvm/IR/DataLayout.h"
+#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/Function.h"
+#include "llvm/IR/InstIterator.h"
+#include "llvm/IR/InstrTypes.h"
#include "llvm/IR/Module.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Pass.h"
@@ -203,8 +207,40 @@ ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
MachineFunctionInfo *ARMBaseTargetMachine::createMachineFunctionInfo(
BumpPtrAllocator &Allocator, const Function &F,
const TargetSubtargetInfo *STI) const {
- return ARMFunctionInfo::create<ARMFunctionInfo>(
- Allocator, F, static_cast<const ARMSubtarget *>(STI));
+ const auto *ARMSTI = static_cast<const ARMSubtarget *>(STI);
+ bool FPRegsUnavailable = !ARMSTI->hasFPRegs() || ARMSTI->isThumb1Only();
+ if (FPRegsUnavailable) {
+ const StringRef FPRegsUnavailableMsg =
+ ", but floating-point registers are unavailable";
+ const ARMTargetLowering *TLI = ARMSTI->getTargetLowering();
+
+ if (TLI->getEffectiveCallingConv(F.getCallingConv(), F.isVarArg()) ==
+ CallingConv::ARM_AAPCS_VFP) {
+ F.getContext().diagnose(DiagnosticInfoUnsupported(
+ F, Twine("calling convention is hard-float") + FPRegsUnavailableMsg,
+ DiagnosticLocation(F.getSubprogram())));
+ } else {
+ for (const Instruction &I : instructions(F)) {
+ const auto *CB = dyn_cast<CallBase>(&I);
+ if (!CB || CB->isInlineAsm() ||
+ (CB->getCalledFunction() && CB->getCalledFunction()->isIntrinsic()))
+ continue;
+ if (TLI->getEffectiveCallingConv(CB->getCallingConv(),
+ CB->getFunctionType()->isVarArg()) ==
+ CallingConv::ARM_AAPCS_VFP) {
+ const Function *Callee = CB->getCalledFunction();
+ F.getContext().diagnose(DiagnosticInfoUnsupported(
+ F,
+ (Callee ? Twine("call to '") + Callee->getName() + "'"
+ : Twine("indirect call")) +
+ " expects a hard-float calling convention" +
+ FPRegsUnavailableMsg,
+ CB->getDebugLoc()));
+ }
+ }
+ }
+ }
+ return ARMFunctionInfo::create<ARMFunctionInfo>(Allocator, F, ARMSTI);
}
const ARMSubtarget *
diff --git a/llvm/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll b/llvm/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll
index 8669935bd95db..d1c4159b69dd1 100644
--- a/llvm/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll
+++ b/llvm/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll
@@ -1,5 +1,5 @@
;PR15293: ARM codegen ice - expected larger existing stack allocation
-;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s
+;RUN: llc -mtriple=arm-linux-gnueabi < %s | FileCheck %s
;CHECK-LABEL: foo:
;CHECK: sub sp, sp, #16
diff --git a/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll b/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll
index e186ae3a96150..56454bb1de525 100644
--- a/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll
+++ b/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll
@@ -1,5 +1,5 @@
;PR15293: ARM codegen ice - expected larger existing stack allocation
-;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s
+;RUN: llc -mtriple=arm-linux-gnueabi < %s | FileCheck %s
%struct.S227 = type { [49 x i32], i32 }
diff --git a/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll b/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll
index efdecce9ae723..1a24ccb98541e 100644
--- a/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll
+++ b/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll
@@ -1,5 +1,5 @@
;PR15293: ARM codegen ice - expected larger existing stack allocation
-;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s
+;RUN: llc -mtriple=arm-linux-gnueabi < %s | FileCheck %s
%struct4bytes = type { i32 }
%struct20bytes = type { i32, i32, i32, i32, i32 }
diff --git a/llvm/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll b/llvm/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll
index 4242343ae67bf..ff616c22463eb 100644
--- a/llvm/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll
+++ b/llvm/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s
+; RUN: llc -mtriple=arm-linux-gnueabi < %s | FileCheck %s
%struct4bytes = type { i32 }
%struct8bytes8align = type { i64 }
diff --git a/llvm/test/CodeGen/ARM/arm-eabi.ll b/llvm/test/CodeGen/ARM/arm-eabi.ll
index 9abdb81805bda..b2972ba97469e 100644
--- a/llvm/test/CodeGen/ARM/arm-eabi.ll
+++ b/llvm/test/CodeGen/ARM/arm-eabi.ll
@@ -1,31 +1,31 @@
; RUN: llc < %s -mtriple=arm-none-eabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
-; RUN: llc < %s -mtriple=arm-none-eabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
+; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp2 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
; RUN: llc < %s -mtriple=arm-none-androideabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
; RUN: llc < %s -mtriple=arm-none-gnueabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI
-; RUN: llc < %s -mtriple=arm-none-gnueabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI
+; RUN: llc < %s -mtriple=arm-none-gnueabihf -mattr=+vfp2 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI
; RUN: llc < %s -mtriple=arm-none-musleabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI
-; RUN: llc < %s -mtriple=arm-none-musleabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI
+; RUN: llc < %s -mtriple=arm-none-musleabihf -mattr=+vfp2 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI
; RUN: llc < %s -mtriple=arm-none-eabi -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI
-; RUN: llc < %s -mtriple=arm-none-eabihf -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI
+; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp2 -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI
; RUN: llc < %s -mtriple=arm-none-androideabi -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI
; RUN: llc < %s -mtriple=arm-none-gnueabi -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI
-; RUN: llc < %s -mtriple=arm-none-gnueabihf -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI
+; RUN: llc < %s -mtriple=arm-none-gnueabihf -mattr=+vfp2 -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI
; RUN: llc < %s -mtriple=arm-none-musleabi -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI
-; RUN: llc < %s -mtriple=arm-none-musleabihf -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI
+; RUN: llc < %s -mtriple=arm-none-musleabihf -mattr=+vfp2 -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI
; RUN: llc < %s -mtriple=arm-none-eabi -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
-; RUN: llc < %s -mtriple=arm-none-eabihf -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
+; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp2 -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
; RUN: llc < %s -mtriple=arm-none-androideabi -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
; RUN: llc < %s -mtriple=arm-none-gnueabi -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
-; RUN: llc < %s -mtriple=arm-none-gnueabihf -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
+; RUN: llc < %s -mtriple=arm-none-gnueabihf -mattr=+vfp2 -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
; RUN: llc < %s -mtriple=arm-none-musleabi -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
-; RUN: llc < %s -mtriple=arm-none-musleabihf -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
+; RUN: llc < %s -mtriple=arm-none-musleabihf -mattr=+vfp2 -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
; RUN: llc < %s -mtriple=arm-none-eabi -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
-; RUN: llc < %s -mtriple=arm-none-eabihf -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
+; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp2 -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
; RUN: llc < %s -mtriple=arm-none-androideabi -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
; RUN: llc < %s -mtriple=arm-none-gnueabi -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
-; RUN: llc < %s -mtriple=arm-none-gnueabihf -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
+; RUN: llc < %s -mtriple=arm-none-gnueabihf -mattr=+vfp2 -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
; RUN: llc < %s -mtriple=arm-none-musleabi -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
-; RUN: llc < %s -mtriple=arm-none-musleabihf -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
+; RUN: llc < %s -mtriple=arm-none-musleabihf -mattr=+vfp2 -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI
%struct.my_s = type { [18 x i32] }
diff --git a/llvm/test/CodeGen/ARM/arm-storebytesmerge.ll b/llvm/test/CodeGen/ARM/arm-storebytesmerge.ll
index 20448570502c0..1c79d10cd234a 100644
--- a/llvm/test/CodeGen/ARM/arm-storebytesmerge.ll
+++ b/llvm/test/CodeGen/ARM/arm-storebytesmerge.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=thumbv7em-arm-none-eabi %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv7em-none-eabi %s -o - | FileCheck %s
-define arm_aapcs_vfpcc void @test(ptr %v50) {
+define void @test(ptr %v50) {
; CHECK-LABEL: test:
; CHECK: @ %bb.0:
; CHECK-NEXT: movw r1, #65534
diff --git a/llvm/test/CodeGen/ARM/block-order.mir b/llvm/test/CodeGen/ARM/block-order.mir
index ecc749382f1f7..745655cf36e4b 100644
--- a/llvm/test/CodeGen/ARM/block-order.mir
+++ b/llvm/test/CodeGen/ARM/block-order.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -o - %s -mtriple=thumbv7em-arm-none-eabihf -run-pass=block-placement -verify-machineinstrs | FileCheck %s
-# RUN: llc -o - %s -mtriple=thumbv7em-arm-none-eabihf -run-pass=block-placement -force-loop-cold-block -verify-machineinstrs | FileCheck %s
+# RUN: llc -o - %s -mtriple=thumbv7em-none-eabi -run-pass=block-placement -verify-machineinstrs | FileCheck %s
+# RUN: llc -o - %s -mtriple=thumbv7em-none-eabi -run-pass=block-placement -force-loop-cold-block -verify-machineinstrs | FileCheck %s
---
name: fn
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/ARM/byval_struct_copy_tailcall.ll b/llvm/test/CodeGen/ARM/byval_struct_copy_tailcall.ll
index 50c676c425ce7..b0c62ad0f1ed6 100644
--- a/llvm/test/CodeGen/ARM/byval_struct_copy_tailcall.ll
+++ b/llvm/test/CodeGen/ARM/byval_struct_copy_tailcall.ll
@@ -1,65 +1,69 @@
-; RUN: llc -mtriple thumbv7em-apple-darwin -o - < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple thumbv7em-none-eabi -o - < %s | FileCheck %s
%"struct.s1" = type { [19 x i32] }
define void @f0(ptr byval(%"struct.s1") %0, ptr %1) #1 {
-; CHECK-LABEL: _f0: @ @f0
-; CHECK-NEXT: @ %bb.0:
-; CHECK-NEXT: sub sp, #16
-; CHECK-NEXT: push {r4, lr}
-; CHECK-NEXT: sub sp, #76
-; CHECK-NEXT: add.w r9, sp, #84
-; CHECK-NEXT: stm.w r9, {r0, r1, r2, r3}
-; CHECK-NEXT: mov r0, sp
-; CHECK-NEXT: add r1, sp, #84
-; CHECK-NEXT: movs r2, #76
-; CHECK-NEXT: mov r3, r0
-; CHECK-NEXT: LBB0_1: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ldr r4, [r1], #4
-; CHECK-NEXT: subs r2, #4
-; CHECK-NEXT: str r4, [r3], #4
-; CHECK-NEXT: bne LBB0_1
+; CHECK-LABEL: f0:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #16
+; CHECK-NEXT: sub sp, #16
+; CHECK-NEXT: .save {r4, lr}
+; CHECK-NEXT: push {r4, lr}
+; CHECK-NEXT: .pad #76
+; CHECK-NEXT: sub sp, #76
+; CHECK-NEXT: add.w r12, sp, #84
+; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: add r1, sp, #84
+; CHECK-NEXT: movs r2, #76
+; CHECK-NEXT: mov r3, r0
+; CHECK-NEXT: .LBB0_1: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ldr r4, [r1], #4
+; CHECK-NEXT: subs r2, #4
+; CHECK-NEXT: str r4, [r3], #4
+; CHECK-NEXT: bne .LBB0_1
; CHECK-NEXT: @ %bb.2:
-; CHECK-NEXT: add.w r1, r0, #12
-; CHECK-NEXT: add r2, sp, #100
-; CHECK-NEXT: ldr r0, [sp, #160]
-; CHECK-NEXT: ldr r3, [r1], #4
-; CHECK-NEXT: str r3, [r2], #4
-; CHECK-NEXT: ldr r3, [r1], #4
-; CHECK-NEXT: str r3, [r2], #4
-; CHECK-NEXT: ldr r3, [r1], #4
-; CHECK-NEXT: str r3, [r2], #4
-; CHECK-NEXT: ldr r3, [r1], #4
-; CHECK-NEXT: str r3, [r2], #4
-; CHECK-NEXT: ldr r3, [r1], #4
-; CHECK-NEXT: str r3, [r2], #4
-; CHECK-NEXT: ldr r3, [r1], #4
-; CHECK-NEXT: str r3, [r2], #4
-; CHECK-NEXT: ldr r3, [r1], #4
-; CHECK-NEXT: str r3, [r2], #4
-; CHECK-NEXT: ldr r3, [r1], #4
-; CHECK-NEXT: str r3, [r2], #4
-; CHECK-NEXT: ldr r3, [r1], #4
-; CHECK-NEXT: str r3, [r2], #4
-; CHECK-NEXT: ldr r3, [r1], #4
-; CHECK-NEXT: str r3, [r2], #4
-; CHECK-NEXT: ldr r3, [r1], #4
-; CHECK-NEXT: str r3, [r2], #4
-; CHECK-NEXT: ldr r3, [r1], #4
-; CHECK-NEXT: str r3, [r2], #4
-; CHECK-NEXT: ldr r3, [r1], #4
-; CHECK-NEXT: str r3, [r2], #4
-; CHECK-NEXT: ldr r3, [r1], #4
-; CHECK-NEXT: str r3, [r2], #4
-; CHECK-NEXT: ldr r3, [r1], #4
-; CHECK-NEXT: str r3, [r2], #4
-; CHECK-NEXT: ldr r3, [r1], #4
-; CHECK-NEXT: str r3, [r2], #4
-; CHECK-NEXT: ldm.w sp, {r1, r2, r3}
-; CHECK-NEXT: add sp, #76
-; CHECK-NEXT: pop.w {r4, lr}
-; CHECK-NEXT: add sp, #16
-; CHECK-NEXT: b.w _f1
+; CHECK-NEXT: add.w r1, r0, #12
+; CHECK-NEXT: add r2, sp, #100
+; CHECK-NEXT: ldr r0, [sp, #160]
+; CHECK-NEXT: ldr r3, [r1], #4
+; CHECK-NEXT: str r3, [r2], #4
+; CHECK-NEXT: ldr r3, [r1], #4
+; CHECK-NEXT: str r3, [r2], #4
+; CHECK-NEXT: ldr r3, [r1], #4
+; CHECK-NEXT: str r3, [r2], #4
+; CHECK-NEXT: ldr r3, [r1], #4
+; CHECK-NEXT: str r3, [r2], #4
+; CHECK-NEXT: ldr r3, [r1], #4
+; CHECK-NEXT: str r3, [r2], #4
+; CHECK-NEXT: ldr r3, [r1], #4
+; CHECK-NEXT: str r3, [r2], #4
+; CHECK-NEXT: ldr r3, [r1], #4
+; CHECK-NEXT: str r3, [r2], #4
+; CHECK-NEXT: ldr r3, [r1], #4
+; CHECK-NEXT: str r3, [r2], #4
+; CHECK-NEXT: ldr r3, [r1], #4
+; CHECK-NEXT: str r3, [r2], #4
+; CHECK-NEXT: ldr r3, [r1], #4
+; CHECK-NEXT: str r3, [r2], #4
+; CHECK-NEXT: ldr r3, [r1], #4
+; CHECK-NEXT: str r3, [r2], #4
+; CHECK-NEXT: ldr r3, [r1], #4
+; CHECK-NEXT: str r3, [r2], #4
+; CHECK-NEXT: ldr r3, [r1], #4
+; CHECK-NEXT: str r3, [r2], #4
+; CHECK-NEXT: ldr r3, [r1], #4
+; CHECK-NEXT: str r3, [r2], #4
+; CHECK-NEXT: ldr r3, [r1], #4
+; CHECK-NEXT: str r3, [r2], #4
+; CHECK-NEXT: ldr r3, [r1], #4
+; CHECK-NEXT: str r3, [r2], #4
+; CHECK-NEXT: ldm.w sp, {r1, r2, r3}
+; CHECK-NEXT: add sp, #76
+; CHECK-NEXT: pop.w {r4, lr}
+; CHECK-NEXT: add sp, #16
+; CHECK-NEXT: b f1
tail call void @f1(ptr %1, ptr byval(%"struct.s1") %0)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/constant-islands-split-IT.mir b/llvm/test/CodeGen/ARM/constant-islands-split-IT.mir
index 60f4ec612aaa3..e82e3e0cb72bd 100644
--- a/llvm/test/CodeGen/ARM/constant-islands-split-IT.mir
+++ b/llvm/test/CodeGen/ARM/constant-islands-split-IT.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -run-pass=arm-cp-islands %s -o - | FileCheck %s
+# RUN: llc -run-pass=arm-cp-islands -mattr=+fp-armv8 %s -o - | FileCheck %s
# This test make sure that the constant pool does not keep in the middle of an IT block
# when needs to split a block to place them.
diff --git a/llvm/test/CodeGen/ARM/constantfp.ll b/llvm/test/CodeGen/ARM/constantfp.ll
index 80bf74aa30ff1..1cd8ea879ab6b 100644
--- a/llvm/test/CodeGen/ARM/constantfp.ll
+++ b/llvm/test/CodeGen/ARM/constantfp.ll
@@ -1,35 +1,35 @@
-; RUN: llc -mtriple=armv7 -mattr=+neon -mcpu=swift %s -o - | FileCheck %s
-; RUN: llc -mtriple=armv7 -mattr=+neon -mcpu=cortex-a8 %s -o - | FileCheck --check-prefix=CHECK-NONEONFP %s
-; RUN: llc -mtriple=armv7 -mattr=-neon -mcpu=cortex-a8 %s -o - | FileCheck --check-prefix=CHECK-NONEON %s
+; RUN: llc -mtriple=armv7-none-eabihf -mattr=+neon -mcpu=swift %s -o - | FileCheck %s
+; RUN: llc -mtriple=armv7-none-eabihf -mattr=+neon -mcpu=cortex-a8 %s -o - | FileCheck --check-prefix=CHECK-NONEONFP %s
+; RUN: llc -mtriple=armv7-none-eabihf -mattr=-neon -mcpu=cortex-a8 %s -o - | FileCheck --check-prefix=CHECK-NONEON %s
-; RUN: llc -mtriple=thumbv7m -mcpu=cortex-m4 %s -o - \
+; RUN: llc -mtriple=thumbv7m-none-eabihf -mcpu=cortex-m4 %s -o - \
; RUN: | FileCheck --check-prefix=CHECK-NO-XO %s
-; RUN: llc -mtriple=thumbv7m -mattr=+execute-only -mcpu=cortex-m4 %s -o - \
+; RUN: llc -mtriple=thumbv7m-none-eabihf -mattr=+execute-only -mcpu=cortex-m4 %s -o - \
; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE %s
-; RUN: llc -mtriple=thumbv7meb -mattr=+execute-only -mcpu=cortex-m4 %s -o - \
+; RUN: llc -mtriple=thumbv7meb-none-eabihf -mattr=+execute-only -mcpu=cortex-m4 %s -o - \
; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE-BE --check-prefix=CHECK-XO-DOUBLE-BE-FPREGS %s
; RUN: llc -mtriple=thumbv7meb -mattr=+execute-only -mcpu=cortex-m3 %s -o - \
; RUN: | FileCheck --check-prefix=CHECK-XO-DOUBLE-BE %s
-; RUN: llc -mtriple=thumbv7m -mattr=+execute-only -mcpu=cortex-m4 -relocation-model=ropi %s -o - \
+; RUN: llc -mtriple=thumbv7m-none-eabihf -mattr=+execute-only -mcpu=cortex-m4 -relocation-model=ropi %s -o - \
; RUN: | FileCheck --check-prefix=CHECK-XO-ROPI %s
-; RUN: llc -mtriple=thumbv8m.main -mattr=fp-armv8 %s -o - \
+; RUN: llc -mtriple=thumbv8m.main-none-eabihf -mattr=fp-armv8 %s -o - \
; RUN: | FileCheck --check-prefix=CHECK-NO-XO %s
-; RUN: llc -mtriple=thumbv8m.main -mattr=+execute-only -mattr=fp-armv8 %s -o - \
+; RUN: llc -mtriple=thumbv8m.main-none-eabihf -mattr=+execute-only -mattr=fp-armv8 %s -o - \
; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE %s
-; RUN: llc -mtriple=thumbv8m.maineb -mattr=+execute-only -mattr=fp-armv8 %s -o - \
+; RUN: llc -mtriple=thumbv8m.maineb-none-eabihf -mattr=+execute-only -mattr=fp-armv8 %s -o - \
; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE-BE %s
-; RUN: llc -mtriple=thumbv8m.main -mattr=+execute-only -mattr=fp-armv8 -relocation-model=ropi %s -o - \
+; RUN: llc -mtriple=thumbv8m.main-none-eabihf -mattr=+execute-only -mattr=fp-armv8 -relocation-model=ropi %s -o - \
; RUN: | FileCheck --check-prefix=CHECK-XO-ROPI %s
-define arm_aapcs_vfpcc float @test_vmov_f32() {
+define float @test_vmov_f32() {
; CHECK-LABEL: test_vmov_f32:
; CHECK: vmov.f32 d0, #1.0
@@ -37,7 +37,7 @@ define arm_aapcs_vfpcc float @test_vmov_f32() {
ret float 1.0
}
-define arm_aapcs_vfpcc float @test_vmov_imm() {
+define float @test_vmov_imm() {
; CHECK-LABEL: test_vmov_imm:
; CHECK: vmov.i32 d0, #0
@@ -54,7 +54,7 @@ define arm_aapcs_vfpcc float @test_vmov_imm() {
ret float 0.0
}
-define arm_aapcs_vfpcc float @test_vmvn_imm() {
+define float @test_vmvn_imm() {
; CHECK-LABEL: test_vmvn_imm:
; CHECK: vmvn.i32 d0, #0xb0000000
@@ -71,7 +71,7 @@ define arm_aapcs_vfpcc float @test_vmvn_imm() {
ret float 8589934080.0
}
-define arm_aapcs_vfpcc double @test_vmov_f64() {
+define double @test_vmov_f64() {
; CHECK-LABEL: test_vmov_f64:
; CHECK: vmov.f64 d0, #1.0
@@ -81,7 +81,7 @@ define arm_aapcs_vfpcc double @test_vmov_f64() {
ret double 1.0
}
-define arm_aapcs_vfpcc double @test_vmov_double_imm() {
+define double @test_vmov_double_imm() {
; CHECK-LABEL: test_vmov_double_imm:
; CHECK: vmov.i32 d0, #0
@@ -103,7 +103,7 @@ define arm_aapcs_vfpcc double @test_vmov_double_imm() {
ret double 0.0
}
-define arm_aapcs_vfpcc double @test_vmvn_double_imm() {
+define double @test_vmvn_double_imm() {
; CHECK-LABEL: test_vmvn_double_imm:
; CHECK: vmvn.i32 d0, #0xb0000000
@@ -127,7 +127,7 @@ define arm_aapcs_vfpcc double @test_vmvn_double_imm() {
; Make sure we don't ignore the high half of 64-bit values when deciding whether
; a vmov/vmvn is possible.
-define arm_aapcs_vfpcc double @test_notvmvn_double_imm() {
+define double @test_notvmvn_double_imm() {
; CHECK-LABEL: test_notvmvn_double_imm:
; CHECK: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
@@ -151,7 +151,7 @@ define arm_aapcs_vfpcc double @test_notvmvn_double_imm() {
ret double 0x4fffffffffffffff
}
-define arm_aapcs_vfpcc float @lower_const_f32_xo() {
+define float @lower_const_f32_xo() {
; CHECK-NO-XO-LABEL: lower_const_f32_xo
; CHECK-NO-XO: vldr {{s[0-9]+}}, {{.?LCPI[0-9]+_[0-9]+}}
@@ -163,7 +163,7 @@ define arm_aapcs_vfpcc float @lower_const_f32_xo() {
ret float 0x3FDA6E9780000000
}
-define arm_aapcs_vfpcc double @lower_const_f64_xo() {
+define double @lower_const_f64_xo() {
; CHECK-NO-XO-LABEL: lower_const_f64_xo
; CHECK-NO-XO: vldr {{d[0-9]+}}, {{.?LCPI[0-9]+_[0-9]+}}
@@ -194,7 +194,7 @@ define arm_aapcs_vfpcc double @lower_const_f64_xo() {
; We need to make sure that the constant pools are placed in
; the data section when generating execute-only code:
-define arm_aapcs_vfpcc float @lower_fpconst_select(float %f) {
+define float @lower_fpconst_select(float %f) {
; CHECK-NO-XO-LABEL: lower_fpconst_select
; CHECK-NO-XO: adr [[REG:r[0-9]+]], [[LABEL:.?LCPI[0-9]+_[0-9]+]]
diff --git a/llvm/test/CodeGen/ARM/constantpool-promote.ll b/llvm/test/CodeGen/ARM/constantpool-promote.ll
index 87f14ebfe00b6..9bd7b7afe4bc6 100644
--- a/llvm/test/CodeGen/ARM/constantpool-promote.ll
+++ b/llvm/test/CodeGen/ARM/constantpool-promote.ll
@@ -6,10 +6,10 @@
; RUN: llc -mtriple thumbv7--linux-gnueabihf -relocation-model=pic -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V7,CHECK-V7THUMB
; RUN: llc -mtriple thumbv7--linux-gnueabihf -relocation-model=ropi -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V7,CHECK-V7THUMB
; RUN: llc -mtriple thumbv7--linux-gnueabihf -relocation-model=rwpi -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V7,CHECK-V7THUMB
-; RUN: llc -mtriple thumbv6m--linux-gnueabihf -relocation-model=static -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V6M
-; RUN: llc -mtriple thumbv6m--linux-gnueabihf -relocation-model=pic -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V6M
-; RUN: llc -mtriple thumbv6m--linux-gnueabihf -relocation-model=ropi -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V6M
-; RUN: llc -mtriple thumbv6m--linux-gnueabihf -relocation-model=rwpi -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V6M
+; RUN: llc -mtriple thumbv6m--linux-gnueabi -relocation-model=static -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V6M
+; RUN: llc -mtriple thumbv6m--linux-gnueabi -relocation-model=pic -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V6M
+; RUN: llc -mtriple thumbv6m--linux-gnueabi -relocation-model=ropi -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V6M
+; RUN: llc -mtriple thumbv6m--linux-gnueabi -relocation-model=rwpi -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V6M
@.str = private unnamed_addr constant [2 x i8] c"s\00", align 1
@.str1 = private unnamed_addr constant [69 x i8] c"this string is far too long to fit in a literal pool by far and away\00", align 1
diff --git a/llvm/test/CodeGen/ARM/eabihf-no-fpregs.ll b/llvm/test/CodeGen/ARM/eabihf-no-fpregs.ll
new file mode 100644
index 0000000000000..cdc70a249c760
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/eabihf-no-fpregs.ll
@@ -0,0 +1,39 @@
+; RUN: not llc --mtriple=armv7-none-eabi --mattr=-fpregs < %s -o /dev/null 2>&1 | FileCheck %s --implicit-check-not=error:
+; RUN: not llc --mtriple=armv7-none-eabihf --mattr=-fpregs < %s -o /dev/null 2>&1 | FileCheck %s --check-prefixes=CHECK,EABIHF --implicit-check-not=error:
+; RUN: not llc --mtriple=thumbv6-none-eabihf --mcpu=arm1176jzf-s < %s -o /dev/null 2>&1 | FileCheck %s --check-prefixes=CHECK,EABIHF --implicit-check-not=error:
+
+; EABIHF: error: <unknown>:0:0: in function default_pcs void (): calling convention is hard-float, but floating-point registers are unavailable
+define void @default_pcs() {
+ ret void
+}
+
+; CHECK: error: {{.*}} in function hard_pcs {{.*}}: calling convention is hard-float, but floating-point registers are unavailable
+define arm_aapcs_vfpcc void @hard_pcs() {
+ ret void
+}
+
+define arm_aapcscc void @soft_pcs() {
+ ret void
+}
+
+define void @variadic(...) {
+ ret void
+}
+
+; CHECK: error: {{.*}} in function soft_to_hard {{.*}}: call to 'hard_callee' expects a hard-float calling convention, but floating-point registers are unavailable
+; CHECK: error: {{.*}} call to 'hard_callee2' expects a hard-float calling convention, but floating-point registers are unavailable
+define arm_aapcscc void @soft_to_hard() {
+ call arm_aapcs_vfpcc void @hard_callee()
+ call arm_aapcs_vfpcc void @hard_callee2()
+ ret void
+}
+
+; EABIHF: error: {{.*}} in function soft_to_default_hard {{.*}}: call to 'default_callee' expects a hard-float calling convention, but floating-point registers are unavailable
+define arm_aapcscc void @soft_to_default_hard() {
+ call void @default_callee()
+ ret void
+}
+
+declare arm_aapcs_vfpcc void @hard_callee()
+declare arm_aapcs_vfpcc void @hard_callee2()
+declare void @default_callee()
diff --git a/llvm/test/CodeGen/ARM/fold-stack-adjust.ll b/llvm/test/CodeGen/ARM/fold-stack-adjust.ll
index 2a5666801f706..32f9dd33a425e 100644
--- a/llvm/test/CodeGen/ARM/fold-stack-adjust.ll
+++ b/llvm/test/CodeGen/ARM/fold-stack-adjust.ll
@@ -114,7 +114,7 @@ define i64 @check_no_return_clobber() minsize {
ret i64 0
}
-define arm_aapcs_vfpcc double @check_vfp_no_return_clobber() minsize {
+define arm_aapcs_vfpcc double @check_vfp_no_return_clobber() minsize "target-features"="+v6t2,+vfp2" {
; CHECK-FNSTART-LABEL: check_vfp_no_return_clobber:
; CHECK: push {r[[GLOBREG:[0-9]+]], lr}
; CHECK: vpush {d0, d1, d2, d3, d4, d5, d6, d7, d8, d9}
diff --git a/llvm/test/CodeGen/ARM/fp16-promote.ll b/llvm/test/CodeGen/ARM/fp16-promote.ll
index 5b3539def98a0..d126b79e2558b 100644
--- a/llvm/test/CodeGen/ARM/fp16-promote.ll
+++ b/llvm/test/CodeGen/ARM/fp16-promote.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -asm-verbose=false < %s -mattr=+vfp3,+fp16 | FileCheck %s --check-prefixes=CHECK-ALL,CHECK-VFP,CHECK-FP16
; RUN: llc -asm-verbose=false < %s | FileCheck %s --check-prefixes=CHECK-ALL,CHECK-LIBCALL,CHECK-VFP,CHECK-LIBCALL-VFP
-; RUN: llc -asm-verbose=false < %s -mattr=-fpregs | FileCheck %s --check-prefixes=CHECK-ALL,CHECK-LIBCALL,CHECK-NOVFP
+; RUN: llc -asm-verbose=false < %s -mattr=-fpregs -float-abi=soft | FileCheck %s --check-prefixes=CHECK-ALL,CHECK-LIBCALL,CHECK-NOVFP
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32"
target triple = "armv7---eabihf"
diff --git a/llvm/test/CodeGen/ARM/machine-outliner-thunk-tcgpr.mir b/llvm/test/CodeGen/ARM/machine-outliner-thunk-tcgpr.mir
index a64946b12357a..c3c93470cfd34 100644
--- a/llvm/test/CodeGen/ARM/machine-outliner-thunk-tcgpr.mir
+++ b/llvm/test/CodeGen/ARM/machine-outliner-thunk-tcgpr.mir
@@ -2,7 +2,7 @@
--- |
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
- target triple = "thumbv7m-unknown-none-eabihf"
+ target triple = "thumbv7m-unknown-none-eabi"
define void @callee_saved() #0 { ret void }
define void @caller_saved() #0 { ret void }
diff --git a/llvm/test/CodeGen/ARM/macho-extern-hidden.ll b/llvm/test/CodeGen/ARM/macho-extern-hidden.ll
index f0369e70fd183..68c0f4f7f4a85 100644
--- a/llvm/test/CodeGen/ARM/macho-extern-hidden.ll
+++ b/llvm/test/CodeGen/ARM/macho-extern-hidden.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=thumbv7em-apple-unknown-macho | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7em-apple-macho -mcpu=cortex-m4 | FileCheck %s
; CHECK: movw r0, :lower16:(L_bar$non_lazy_ptr-(LPC0_0+4))
; CHECK: movt r0, :upper16:(L_bar$non_lazy_ptr-(LPC0_0+4))
diff --git a/llvm/test/CodeGen/ARM/memfunc.ll b/llvm/test/CodeGen/ARM/memfunc.ll
index dfd86a2691cd5..555ebc61bbab1 100644
--- a/llvm/test/CodeGen/ARM/memfunc.ll
+++ b/llvm/test/CodeGen/ARM/memfunc.ll
@@ -1,12 +1,12 @@
; RUN: llc < %s -mtriple=armv7-apple-ios -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-IOS --check-prefix=CHECK
; RUN: llc < %s -mtriple=thumbv7m-none-macho -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-DARWIN --check-prefix=CHECK
; RUN: llc < %s -mtriple=arm-none-eabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI --check-prefix=CHECK
-; RUN: llc < %s -mtriple=arm-none-eabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI --check-prefix=CHECK
+; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp2 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI --check-prefix=CHECK
; RUN: llc < %s -mtriple=arm-none-androideabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI --check-prefix=CHECK
; RUN: llc < %s -mtriple=arm-none-gnueabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI --check-prefix=CHECK
-; RUN: llc < %s -mtriple=arm-none-gnueabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI --check-prefix=CHECK
+; RUN: llc < %s -mtriple=arm-none-gnueabihf -mattr=+vfp2 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI --check-prefix=CHECK
; RUN: llc < %s -mtriple=arm-none-musleabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI --check-prefix=CHECK
-; RUN: llc < %s -mtriple=arm-none-musleabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI --check-prefix=CHECK
+; RUN: llc < %s -mtriple=arm-none-musleabihf -mattr=+vfp2 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI --check-prefix=CHECK
define void @f1(ptr %dest, ptr %src) "frame-pointer"="all" {
entry:
diff --git a/llvm/test/CodeGen/ARM/no-expand-memcpy-no-builtins.ll b/llvm/test/CodeGen/ARM/no-expand-memcpy-no-builtins.ll
index 0b2c96d93ba43..0e2bb25f2e55f 100644
--- a/llvm/test/CodeGen/ARM/no-expand-memcpy-no-builtins.ll
+++ b/llvm/test/CodeGen/ARM/no-expand-memcpy-no-builtins.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -mtriple=thumbv7em-apple-unknown-macho < %s | FileCheck %s
+; RUN: llc -mtriple=thumbv7em-apple-macho -mcpu=cortex-m4 < %s | FileCheck %s
target datalayout = "e-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
diff --git a/llvm/test/CodeGen/ARM/pei-swiftself.mir b/llvm/test/CodeGen/ARM/pei-swiftself.mir
index 318c9938505d4..e7a15ef2b4ec0 100644
--- a/llvm/test/CodeGen/ARM/pei-swiftself.mir
+++ b/llvm/test/CodeGen/ARM/pei-swiftself.mir
@@ -1,4 +1,4 @@
-# RUN: llc -o - %s -mtriple=arm-- -run-pass prolog-epilog | FileCheck %s
+# RUN: llc -o - %s -mtriple=arm-- -mattr=+vfp2 -run-pass prolog-epilog | FileCheck %s
--- |
define swiftcc ptr @need_emergency_slot(ptr swiftself %v) {
; Just a dummy to add a swiftself bit. The real code is in the MI below.
diff --git a/llvm/test/CodeGen/ARM/readtp.ll b/llvm/test/CodeGen/ARM/readtp.ll
index dedd16cc49bf8..f14740ba17fa1 100644
--- a/llvm/test/CodeGen/ARM/readtp.ll
+++ b/llvm/test/CodeGen/ARM/readtp.ll
@@ -1,7 +1,7 @@
-; RUN: llc -mtriple=armeb-linux-gnueabihf -O2 -mattr=+read-tp-tpidrurw %s -o - | FileCheck %s -check-prefix=CHECK-TPIDRURW
-; RUN: llc -mtriple=armeb-linux-gnueabihf -O2 -mattr=+read-tp-tpidruro %s -o - | FileCheck %s -check-prefix=CHECK-TPIDRURO
-; RUN: llc -mtriple=armeb-linux-gnueabihf -O2 -mattr=+read-tp-tpidrprw %s -o - | FileCheck %s -check-prefix=CHECK-TPIDRPRW
-; RUN: llc -mtriple=armeb-linux-gnueabihf -O2 %s -o - | FileCheck %s -check-prefix=CHECK-SOFT
+; RUN: llc -mtriple=armebv7-linux-gnueabihf -O2 -mattr=+read-tp-tpidrurw %s -o - | FileCheck %s -check-prefix=CHECK-TPIDRURW
+; RUN: llc -mtriple=armebv7-linux-gnueabihf -O2 -mattr=+read-tp-tpidruro %s -o - | FileCheck %s -check-prefix=CHECK-TPIDRURO
+; RUN: llc -mtriple=armebv7-linux-gnueabihf -O2 -mattr=+read-tp-tpidrprw %s -o - | FileCheck %s -check-prefix=CHECK-TPIDRPRW
+; RUN: llc -mtriple=armebv7-linux-gnueabihf -O2 %s -o - | FileCheck %s -check-prefix=CHECK-SOFT
; RUN: llc -mtriple=thumbv7-linux-gnueabihf -O2 -mattr=+read-tp-tpidrurw %s -o - | FileCheck %s -check-prefix=CHECK-TPIDRURW
; RUN: llc -mtriple=thumbv7-linux-gnueabihf -O2 -mattr=+read-tp-tpidruro %s -o - | FileCheck %s -check-prefix=CHECK-TPIDRURO
; RUN: llc -mtriple=thumbv7-linux-gnueabihf -O2 -mattr=+read-tp-tpidrprw %s -o - | FileCheck %s -check-prefix=CHECK-TPIDRPRW
diff --git a/llvm/test/CodeGen/ARM/ssat-with-shift.ll b/llvm/test/CodeGen/ARM/ssat-with-shift.ll
index cbd792790b91a..9451bffc2e042 100644
--- a/llvm/test/CodeGen/ARM/ssat-with-shift.ll
+++ b/llvm/test/CodeGen/ARM/ssat-with-shift.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s
+; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+dsp %s -o - | FileCheck %s
-define arm_aapcs_vfpcc i32 @ssat_lsl(i32 %num){
+define i32 @ssat_lsl(i32 %num){
; CHECK-LABEL: ssat_lsl
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ssat r0, #8, r0, lsl #7
@@ -13,7 +13,7 @@ entry:
ret i32 %0
}
-define arm_aapcs_vfpcc i32 @ssat_asr(i32 %num){
+define i32 @ssat_asr(i32 %num){
; CHECK-LABEL: ssat_asr
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ssat r0, #8, r0, asr #7
@@ -24,7 +24,7 @@ entry:
ret i32 %0
}
-define arm_aapcs_vfpcc i32 @ssat_lsl2(i32 %num){
+define i32 @ssat_lsl2(i32 %num){
; CHECK-LABEL: ssat_lsl2:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ssat r0, #16, r0, lsl #15
@@ -38,7 +38,7 @@ entry:
ret i32 %3
}
-define arm_aapcs_vfpcc i32 @ssat_asr2(i32 %num){
+define i32 @ssat_asr2(i32 %num){
; CHECK-LABEL: ssat_asr2:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ssat r0, #16, r0, asr #15
diff --git a/llvm/test/CodeGen/ARM/subtarget-align.ll b/llvm/test/CodeGen/ARM/subtarget-align.ll
index f87e21f06d42c..98b05f81a1c07 100644
--- a/llvm/test/CodeGen/ARM/subtarget-align.ll
+++ b/llvm/test/CodeGen/ARM/subtarget-align.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=arm-linux-gnueabihf -filetype=obj <%s | llvm-objdump --triple=armv7 --no-show-raw-insn -d - | FileCheck %s
+; RUN: llc -mtriple=arm-linux-gnueabi -filetype=obj <%s | llvm-objdump --triple=armv7 --no-show-raw-insn -d - | FileCheck %s
;; Expect architectural nop to be used between func2 and func3 but not func1
;; and func2 due to lack of subtarget support in func2.
diff --git a/llvm/test/CodeGen/ARM/unsupported-calling-conv.ll b/llvm/test/CodeGen/ARM/unsupported-calling-conv.ll
new file mode 100644
index 0000000000000..e23c2309b62b3
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/unsupported-calling-conv.ll
@@ -0,0 +1,6 @@
+; RUN: not --crash llc -mtriple=armv7-none-eabi < %s 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Unsupported calling convention
+define coldcc void @f() {
+ ret void
+}
diff --git a/llvm/test/CodeGen/ARM/unsupported-calling-conv.mir b/llvm/test/CodeGen/ARM/unsupported-calling-conv.mir
new file mode 100644
index 0000000000000..51bdbf1bfd61d
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/unsupported-calling-conv.mir
@@ -0,0 +1,12 @@
+# RUN: llc -run-pass=machineverifier %s -o /dev/null
+
+--- |
+ target triple = "thumbv7m-none-eabi"
+ define coldcc void @f() { unreachable }
+...
+---
+name: f
+body: |
+ bb.0:
+ tBX_RET 14, $noreg
+...
diff --git a/llvm/test/CodeGen/ARM/usat-with-shift.ll b/llvm/test/CodeGen/ARM/usat-with-shift.ll
index b9c083e498c0c..134f0d2b763af 100644
--- a/llvm/test/CodeGen/ARM/usat-with-shift.ll
+++ b/llvm/test/CodeGen/ARM/usat-with-shift.ll
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s --check-prefixes=CHECK,ARMV6
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+dsp %s -o - | FileCheck %s --check-prefixes=CHECK,THUMB
-define arm_aapcs_vfpcc i32 @usat_lsl(i32 %num){
+define i32 @usat_lsl(i32 %num){
; CHECK-LABEL: usat_lsl:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: usat r0, #7, r0, lsl #2
@@ -13,7 +13,7 @@ entry:
ret i32 %0
}
-define arm_aapcs_vfpcc i32 @usat_asr(i32 %num){
+define i32 @usat_asr(i32 %num){
; CHECK-LABEL: usat_asr:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: usat r0, #7, r0, asr #2
@@ -24,7 +24,7 @@ entry:
ret i32 %0
}
-define arm_aapcs_vfpcc i32 @usat_lsl2(i32 %num){
+define i32 @usat_lsl2(i32 %num){
; ARMV6-LABEL: usat_lsl2:
; ARMV6: @ %bb.0: @ %entry
; ARMV6-NEXT: lsl r0, r0, #15
@@ -52,7 +52,7 @@ entry:
ret i32 %3
}
-define arm_aapcs_vfpcc i32 @usat_asr2(i32 %num){
+define i32 @usat_asr2(i32 %num){
; ARMV6-LABEL: usat_asr2:
; ARMV6: @ %bb.0: @ %entry
; ARMV6-NEXT: asr r1, r0, #15
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/sibling-loops.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/sibling-loops.ll
index c6158cb611a70..444714784930b 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/sibling-loops.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/sibling-loops.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob --verify-machineinstrs %s -o - | FileCheck %s
-define arm_aapcs_vfpcc void @test(ptr noalias nocapture readonly %off, ptr noalias nocapture %data, ptr noalias nocapture %dst, i32 %n) {
+define void @test(ptr noalias nocapture readonly %off, ptr noalias nocapture %data, ptr noalias nocapture %dst, i32 %n) {
; CHECK-LABEL: test:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r3, #1
diff --git a/llvm/test/CodeGen/Thumb2/cde-gpr.ll b/llvm/test/CodeGen/Thumb2/cde-gpr.ll
index 19052125c14be..6dc1fe7aef506 100644
--- a/llvm/test/CodeGen/Thumb2/cde-gpr.ll
+++ b/llvm/test/CodeGen/Thumb2/cde-gpr.ll
@@ -17,7 +17,7 @@ declare i32 @llvm.arm.cde.cx3a(i32 immarg, i32, i32, i32, i32 immarg)
declare { i32, i32 } @llvm.arm.cde.cx3d(i32 immarg, i32, i32, i32 immarg)
declare { i32, i32 } @llvm.arm.cde.cx3da(i32 immarg, i32, i32, i32, i32, i32 immarg)
-define arm_aapcs_vfpcc i32 @test_cx1() {
+define i32 @test_cx1() {
; CHECK-LABEL: test_cx1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cx1 p0, r0, #123
@@ -27,7 +27,7 @@ entry:
ret i32 %0
}
-define arm_aapcs_vfpcc i32 @test_cx1a(i32 %acc) {
+define i32 @test_cx1a(i32 %acc) {
; CHECK-LABEL: test_cx1a:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cx1a p0, r0, #345
@@ -37,7 +37,7 @@ entry:
ret i32 %0
}
-define arm_aapcs_vfpcc i64 @test_cx1d() {
+define i64 @test_cx1d() {
; CHECK-LABEL: test_cx1d:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cx1d p1, r0, r1, #567
@@ -53,7 +53,7 @@ entry:
ret i64 %6
}
-define arm_aapcs_vfpcc i64 @test_cx1da(i64 %acc) {
+define i64 @test_cx1da(i64 %acc) {
; CHECK-LABEL: test_cx1da:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $r1 killed $r1 killed $r0_r1 def $r0_r1
@@ -74,7 +74,7 @@ entry:
ret i64 %9
}
-define arm_aapcs_vfpcc i32 @test_cx2(i32 %n) {
+define i32 @test_cx2(i32 %n) {
; CHECK-LABEL: test_cx2:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cx2 p0, r0, r0, #11
@@ -84,7 +84,7 @@ entry:
ret i32 %0
}
-define arm_aapcs_vfpcc i32 @test_cx2a(i32 %acc, i32 %n) {
+define i32 @test_cx2a(i32 %acc, i32 %n) {
; CHECK-LABEL: test_cx2a:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cx2a p1, r0, r1, #22
@@ -94,7 +94,7 @@ entry:
ret i32 %0
}
-define arm_aapcs_vfpcc i64 @test_cx2d(i32 %n) #0 {
+define i64 @test_cx2d(i32 %n) #0 {
; CHECK-LABEL: test_cx2d:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cx2d p1, r0, r1, r0, #33
@@ -110,7 +110,7 @@ entry:
ret i64 %6
}
-define arm_aapcs_vfpcc i64 @test_cx2da(i64 %acc, i32 %n) {
+define i64 @test_cx2da(i64 %acc, i32 %n) {
; CHECK-LABEL: test_cx2da:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $r1 killed $r1 killed $r0_r1 def $r0_r1
@@ -131,7 +131,7 @@ entry:
ret i64 %9
}
-define arm_aapcs_vfpcc i32 @test_cx3(i32 %n, i32 %m) {
+define i32 @test_cx3(i32 %n, i32 %m) {
; CHECK-LABEL: test_cx3:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cx3 p0, r0, r0, r1, #1
@@ -141,7 +141,7 @@ entry:
ret i32 %0
}
-define arm_aapcs_vfpcc i32 @test_cx3a(i32 %acc, i32 %n, i32 %m) {
+define i32 @test_cx3a(i32 %acc, i32 %n, i32 %m) {
; CHECK-LABEL: test_cx3a:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cx3a p1, r0, r1, r2, #2
@@ -151,7 +151,7 @@ entry:
ret i32 %0
}
-define arm_aapcs_vfpcc i64 @test_cx3d(i32 %n, i32 %m) {
+define i64 @test_cx3d(i32 %n, i32 %m) {
; CHECK-LABEL: test_cx3d:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cx3d p1, r0, r1, r0, r1, #3
@@ -167,7 +167,7 @@ entry:
ret i64 %6
}
-define arm_aapcs_vfpcc i64 @test_cx3da(i64 %acc, i32 %n, i32 %m) {
+define i64 @test_cx3da(i64 %acc, i32 %n, i32 %m) {
; CHECK-LABEL: test_cx3da:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $r1 killed $r1 killed $r0_r1 def $r0_r1
diff --git a/llvm/test/CodeGen/Thumb2/emit-unwinding.ll b/llvm/test/CodeGen/Thumb2/emit-unwinding.ll
index 1931343de2457..ec7fec444afa7 100644
--- a/llvm/test/CodeGen/Thumb2/emit-unwinding.ll
+++ b/llvm/test/CodeGen/Thumb2/emit-unwinding.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple thumbv7em-apple-unknown-eabi-macho %s -o - -O0 | FileCheck %s
+; RUN: llc -mtriple thumbv7em-apple-macho -mcpu=cortex-m4 %s -o - -O0 | FileCheck %s
; CHECK: add r7, sp, #{{[1-9]+}}
diff --git a/llvm/test/CodeGen/Thumb2/mve-gather-scatter-opt.ll b/llvm/test/CodeGen/Thumb2/mve-gather-scatter-opt.ll
index 8013e1d639715..566c2bb7940af 100644
--- a/llvm/test/CodeGen/Thumb2/mve-gather-scatter-opt.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-gather-scatter-opt.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat=false %s -o - | FileCheck --check-prefix NOGATSCAT %s
-; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=-mve %s -o - | FileCheck --check-prefix NOMVE %s
+; RUN: llc -mtriple=thumbv8.1m.main-none-eabihf -mattr=+mve.fp -enable-arm-maskedgatscat=false %s -o - | FileCheck --check-prefix NOGATSCAT %s
+; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=-mve %s -o - | FileCheck --check-prefix NOMVE %s
-define arm_aapcs_vfpcc <4 x i32> @unscaled_i32_i32_gather(ptr %base, ptr %offptr) {
+define <4 x i32> @unscaled_i32_i32_gather(ptr %base, ptr %offptr) {
; NOGATSCAT-LABEL: unscaled_i32_i32_gather:
; NOGATSCAT: @ %bb.0: @ %entry
; NOGATSCAT-NEXT: vldrw.u32 q0, [r1]
@@ -41,7 +41,7 @@ entry:
declare <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr>, i32, <4 x i1>, <4 x i32>)
-define arm_aapcs_vfpcc void @unscaled_i32_i8_scatter(ptr %base, ptr %offptr, <4 x i32> %input) {
+define void @unscaled_i32_i8_scatter(ptr %base, ptr %offptr, <4 x i32> %input) {
; NOGATSCAT-LABEL: unscaled_i32_i8_scatter:
; NOGATSCAT: @ %bb.0: @ %entry
; NOGATSCAT-NEXT: .save {r4, r5, r7, lr}
diff --git a/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll b/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll
index dc06c268b0ef4..d7c2aa26309ca 100644
--- a/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll
+++ b/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll
@@ -1,5 +1,5 @@
-; RUN: llc --force-dwarf-frame-section --exception-model=arm %s -o - --target-abi=aapcs16 | FileCheck %s
-; RUN: llc --filetype=obj %s --exception-model=arm -o - --target-abi=aapcs16 | llvm-readelf -s --unwind - | FileCheck %s --check-prefix=UNWIND
+; RUN: llc --force-dwarf-frame-section --exception-model=arm %s -o - --target-abi=aapcs16 -mcpu=cortex-m4 | FileCheck %s
+; RUN: llc --filetype=obj %s --exception-model=arm -o - --target-abi=aapcs16 -mcpu=cortex-m4 | llvm-readelf -s --unwind - | FileCheck %s --check-prefix=UNWIND
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
; Triple tweaked so we get 16-byte stack alignment and better test coverage.
diff --git a/llvm/test/CodeGen/Thumb2/shift_parts.ll b/llvm/test/CodeGen/Thumb2/shift_parts.ll
index b4ac405d82ed5..22cf26f0b0d2e 100644
--- a/llvm/test/CodeGen/Thumb2/shift_parts.ll
+++ b/llvm/test/CodeGen/Thumb2/shift_parts.ll
@@ -195,7 +195,7 @@ entry:
%struct.bar = type { i16, i8, [5 x i8] }
-define arm_aapcs_vfpcc void @fn1(ptr nocapture %a) {
+define void @fn1(ptr nocapture %a) {
; CHECK-MVE-LABEL: fn1:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: ldr r2, [r0, #4]
diff --git a/llvm/test/DebugInfo/COFF/jump-table.ll b/llvm/test/DebugInfo/COFF/jump-table.ll
index be1de2be55788..9d1fe2998c17a 100644
--- a/llvm/test/DebugInfo/COFF/jump-table.ll
+++ b/llvm/test/DebugInfo/COFF/jump-table.ll
@@ -231,9 +231,9 @@ declare dso_local void @f4() #2
declare dso_local void @f5() #2
-attributes #0 = { mustprogress noinline optnone uwtable "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
+attributes #0 = { mustprogress noinline optnone uwtable "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
attributes #1 = { nocallback nofree nosync nounwind readnone speculatable willreturn }
-attributes #2 = { "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
+attributes #2 = { "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!2, !3, !4, !5, !6}
diff --git a/llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir b/llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir
index a2242acafebb9..ed62d019d2a8a 100644
--- a/llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir
+++ b/llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir
@@ -27,20 +27,20 @@
target triple = "armebv4t-unknown-unknown"
; Function Attrs: noinline nounwind optsize
- define arm_aapcs_vfpcc void @caller() #0 !dbg !20 {
+ define void @caller() #0 !dbg !20 {
entry:
unreachable
}
; Function Attrs: noinline nounwind optsize
- define internal arm_aapcs_vfpcc void @callee(ptr %p1) unnamed_addr #0 !dbg !29 {
+ define internal void @callee(ptr %p1) unnamed_addr #0 !dbg !29 {
entry:
unreachable
}
- declare !dbg !4 arm_aapcs_vfpcc ptr @value()
- declare !dbg !9 arm_aapcs_vfpcc i32 @interesting(ptr)
- declare !dbg !12 arm_aapcs_vfpcc void @ext(ptr)
+ declare !dbg !4 ptr @value()
+ declare !dbg !9 i32 @interesting(ptr)
+ declare !dbg !12 void @ext(ptr)
; Function Attrs: nounwind readnone speculatable willreturn
declare void @llvm.dbg.value(metadata, metadata, metadata) #1
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