[clang] [llvm] [RISCV][MC] Add experimental Smeihv, Sseihv, Smip, and Ssip support (PR #215095)
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Sun Aug 9 08:02:13 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clang-driver
Author: Zeyi Xu (zeyi2)
<details>
<summary>Changes</summary>
Add support for version 0.19 of the Smeihv, Sseihv, Smip, and Ssip extensions from the RISC-V fast interrupt specification.
---
Full diff: https://github.com/llvm/llvm-project/pull/215095.diff
14 Files Affected:
- (modified) clang/test/Driver/print-supported-extensions-riscv.c (+4)
- (modified) clang/test/Preprocessor/riscv-target-features.c (+36)
- (modified) llvm/docs/RISCVUsage.rst (+1-1)
- (modified) llvm/docs/ReleaseNotes.md (+4)
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+22)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+1)
- (added) llvm/lib/Target/RISCV/RISCVInstrInfoSmip.td (+24)
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+16)
- (modified) llvm/test/CodeGen/RISCV/features-info.ll (+4)
- (modified) llvm/test/MC/RISCV/attribute-arch.s (+12)
- (added) llvm/test/MC/RISCV/smip-ssip-invalid.s (+33)
- (added) llvm/test/MC/RISCV/smip-valid.s (+18)
- (added) llvm/test/MC/RISCV/ssip-valid.s (+18)
- (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+4)
``````````diff
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index f90a5fc581baa..7ab9adcb4b44a 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -272,11 +272,15 @@
// CHECK-NEXT: zvzip 0.1 'Zvzip' (Vector Reordering Structured Data)
// CHECK-NEXT: smcsps 0.19 'Smcsps' (Conditional Stack Pointer Swap at Machine Level)
// CHECK-NEXT: smehv 0.19 'Smehv' (Synchronous Exception Hardware Vectoring at Machine Level)
+// CHECK-NEXT: smeihv 0.19 'Smeihv' (External Interrupt Hardware Vectoring at Machine Level)
// CHECK-NEXT: smijt 0.19 'Smijt' (Interrupt Jump Table at Machine Level)
+// CHECK-NEXT: smip 0.19 'Smip' (Support for Interrupt Handler Push/Pop at Machine Level)
// CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension)
// CHECK-NEXT: sscsps 0.19 'Sscsps' (Conditional Stack Pointer Swap at Supervisor Level)
// CHECK-NEXT: ssehv 0.19 'Ssehv' (Synchronous Exception Hardware Vectoring at Supervisor Level)
+// CHECK-NEXT: sseihv 0.19 'Sseihv' (External Interrupt Hardware Vectoring at Supervisor Level)
// CHECK-NEXT: ssijt 0.19 'Ssijt' (Interrupt Jump Table at Supervisor Level)
+// CHECK-NEXT: ssip 0.19 'Ssip' (Support for Interrupt Handler Push/Pop at Supervisor Level)
// CHECK-NEXT: svukte 1.0 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
// CHECK-NEXT: xqccmt 0.1 'Xqccmt' (Qualcomm 16-bit Table Jump)
// CHECK-NEXT: xsfmclic 0.1 'XSfmclic' (SiFive CLIC Machine-mode CSRs)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 752e9702d9388..e95698c88734f 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -39,8 +39,10 @@
// CHECK-NOT: __riscv_smctr{{.*$}}
// CHECK-NOT: __riscv_smdbltrp {{.*$}}
// CHECK-NOT: __riscv_smehv {{.*$}}
+// CHECK-NOT: __riscv_smeihv {{.*$}}
// CHECK-NOT: __riscv_smepmp {{.*$}}
// CHECK-NOT: __riscv_smijt {{.*$}}
+// CHECK-NOT: __riscv_smip {{.*$}}
// CHECK-NOT: __riscv_smmpm{{.*$}}
// CHECK-NOT: __riscv_smnpm{{.*$}}
// CHECK-NOT: __riscv_smpmpmt {{.*$}}
@@ -56,7 +58,9 @@
// CHECK-NOT: __riscv_ssctr{{.*$}}
// CHECK-NOT: __riscv_ssdbltrp {{.*$}}
// CHECK-NOT: __riscv_ssehv {{.*$}}
+// CHECK-NOT: __riscv_sseihv {{.*$}}
// CHECK-NOT: __riscv_ssijt {{.*$}}
+// CHECK-NOT: __riscv_ssip {{.*$}}
// CHECK-NOT: __riscv_ssnpm{{.*$}}
// CHECK-NOT: __riscv_sspm{{.*$}}
// CHECK-NOT: __riscv_ssqosid{{.*$}}
@@ -1445,6 +1449,38 @@
// CHECK-SSEHV-EXT: __riscv_ssehv 19000{{$}}
// CHECK-SSEHV-EXT: __riscv_ssijt 19000{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_smeihv0p19 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMEIHV-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_smeihv0p19 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMEIHV-EXT %s
+// CHECK-SMEIHV-EXT: __riscv_smeihv 19000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_sseihv0p19 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SSEIHV-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_sseihv0p19 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SSEIHV-EXT %s
+// CHECK-SSEIHV-EXT: __riscv_sseihv 19000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_smip0p19 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMIP-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_smip0p19 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMIP-EXT %s
+// CHECK-SMIP-EXT: __riscv_smip 19000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_ssip0p19 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SSIP-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_ssip0p19 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SSIP-EXT %s
+// CHECK-SSIP-EXT: __riscv_ssip 19000{{$}}
+
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32ismpmpmt0p6 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMPMPMT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 8fbe60c55d64c..484cc1ef5a7aa 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -347,7 +347,7 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zicfilp``, ``experimental-zicfiss``
LLVM implements the `1.0 release specification <https://github.com/riscv/riscv-cfi/releases/tag/v1.0>`__.
-``experimental-smcsps``, ``experimental-sscsps``, ``experimental-smijt``, ``experimental-ssijt``, ``experimental-smehv``, ``experimental-ssehv``
+``experimental-smcsps``, ``experimental-sscsps``, ``experimental-smijt``, ``experimental-ssijt``, ``experimental-smehv``, ``experimental-ssehv``, ``experimental-smeihv``, ``experimental-sseihv``, ``experimental-smip``, ``experimental-ssip``
LLVM implements the `0.19 release specification <https://github.com/riscv/riscv-fast-interrupt/releases/tag/v0.19>`__.
``experimental-zvbc32e``, ``experimental-zvkgs``
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index efd33a907cfa7..e4d72d2234cbd 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -102,6 +102,10 @@ Makes programs 10x faster by doing Special New Thing.
table extensions and the `Smehv` and `Ssehv` synchronous exception hardware
vectoring extensions.
+* Added experimental MC support for the `Smeihv` and `Sseihv` external
+ interrupt hardware vectoring extensions and the `Smip` and `Ssip` interrupt
+ handler push/pop extensions.
+
* Bump Svukte extension to 1.0.
### Changes to the WebAssembly Backend
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 4e9710e2ecb7e..2221f23dda11f 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1115,6 +1115,28 @@ def FeatureStdExtSsehv
"Synchronous Exception Hardware Vectoring at Supervisor Level",
[FeatureStdExtSsijt]>;
+def FeatureStdExtSmeihv
+ : RISCVExperimentalExtension<0, 19,
+ "External Interrupt Hardware Vectoring at Machine Level">;
+def FeatureStdExtSseihv
+ : RISCVExperimentalExtension<0, 19,
+ "External Interrupt Hardware Vectoring at Supervisor Level">;
+
+def FeatureStdExtSmip
+ : RISCVExperimentalExtension<0, 19,
+ "Support for Interrupt Handler Push/Pop at Machine Level">;
+def HasStdExtSmip : Predicate<"Subtarget->hasStdExtSmip()">,
+ AssemblerPredicate<(all_of FeatureStdExtSmip),
+ "'Smip' (Support for Interrupt Handler Push/Pop at "
+ "Machine Level)">;
+def FeatureStdExtSsip
+ : RISCVExperimentalExtension<0, 19,
+ "Support for Interrupt Handler Push/Pop at Supervisor Level">;
+def HasStdExtSsip : Predicate<"Subtarget->hasStdExtSsip()">,
+ AssemblerPredicate<(all_of FeatureStdExtSsip),
+ "'Ssip' (Support for Interrupt Handler Push/Pop at "
+ "Supervisor Level)">;
+
def FeatureStdExtSmpmpmt
: RISCVExperimentalExtension<0, 6, "PMP-based Memory Types Extension">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 5d93509477102..b4b1bc9573b41 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2400,6 +2400,7 @@ include "RISCVInstrInfoZilx.td"
// Privileged
include "RISCVInstrInfoSmcsps.td"
+include "RISCVInstrInfoSmip.td"
// Scalar FP
include "RISCVInstrInfoF.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoSmip.td b/llvm/lib/Target/RISCV/RISCVInstrInfoSmip.td
new file mode 100644
index 0000000000000..29baca4848a53
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoSmip.td
@@ -0,0 +1,24 @@
+//===-- RISCVInstrInfoSmip.td ------------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+let mayLoad = 1, Uses = [X2], Defs = [X2, X10, X11, X12, X13, X14, X15],
+ isBarrier = 1, isReturn = 1, isTerminator = 1 in {
+let Predicates = [HasStdExtSmip] in
+def MIPOPRET : Priv<"mipopret", 0b0011000>, Sched<[]> {
+ let rd = 0;
+ let rs1 = 0;
+ let rs2 = 0b01000;
+}
+
+let Predicates = [HasStdExtSsip] in
+def SIPOPRET : Priv<"sipopret", 0b0001000>, Sched<[]> {
+ let rd = 0;
+ let rs1 = 0;
+ let rs2 = 0b01000;
+}
+} // isBarrier = 1, isReturn = 1, isTerminator = 1
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index df521014e3d16..363b78e1e46b8 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -135,6 +135,10 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssijt %s -o - | FileCheck --check-prefix=RV32SSIJT %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smehv %s -o - | FileCheck --check-prefix=RV32SMEHV %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssehv %s -o - | FileCheck --check-prefix=RV32SSEHV %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-smeihv %s -o - | FileCheck --check-prefix=RV32SMEIHV %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-sseihv %s -o - | FileCheck --check-prefix=RV32SSEIHV %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-smip %s -o - | FileCheck --check-prefix=RV32SMIP %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssip %s -o - | FileCheck --check-prefix=RV32SSIP %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smpmpmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SMPMPMT %s
; RUN: llc -mtriple=riscv32 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV32SMRNMI %s
; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
@@ -308,6 +312,10 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssijt %s -o - | FileCheck --check-prefix=RV64SSIJT %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smehv %s -o - | FileCheck --check-prefix=RV64SMEHV %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssehv %s -o - | FileCheck --check-prefix=RV64SSEHV %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-smeihv %s -o - | FileCheck --check-prefix=RV64SMEIHV %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-sseihv %s -o - | FileCheck --check-prefix=RV64SSEIHV %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-smip %s -o - | FileCheck --check-prefix=RV64SMIP %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssip %s -o - | FileCheck --check-prefix=RV64SSIP %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smpmpmt %s -o - | FileCheck --check-prefixes=CHECK,RV64SMPMPMT %s
; RUN: llc -mtriple=riscv64 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV64SMRNMI %s
; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
@@ -491,6 +499,10 @@
; RV32SSIJT: .attribute 5, "rv32i2p1_ssijt0p19"
; RV32SMEHV: .attribute 5, "rv32i2p1_smehv0p19_smijt0p19"
; RV32SSEHV: .attribute 5, "rv32i2p1_ssehv0p19_ssijt0p19"
+; RV32SMEIHV: .attribute 5, "rv32i2p1_smeihv0p19"
+; RV32SSEIHV: .attribute 5, "rv32i2p1_sseihv0p19"
+; RV32SMIP: .attribute 5, "rv32i2p1_smip0p19"
+; RV32SSIP: .attribute 5, "rv32i2p1_ssip0p19"
; RV32SMPMPMT: .attribute 5, "rv32i2p1_smpmpmt0p6"
; RV32SMRNMI: .attribute 5, "rv32i2p1_smrnmi1p0"
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
@@ -661,6 +673,10 @@
; RV64SSIJT: .attribute 5, "rv64i2p1_ssijt0p19"
; RV64SMEHV: .attribute 5, "rv64i2p1_smehv0p19_smijt0p19"
; RV64SSEHV: .attribute 5, "rv64i2p1_ssehv0p19_ssijt0p19"
+; RV64SMEIHV: .attribute 5, "rv64i2p1_smeihv0p19"
+; RV64SSEIHV: .attribute 5, "rv64i2p1_sseihv0p19"
+; RV64SMIP: .attribute 5, "rv64i2p1_smip0p19"
+; RV64SSIP: .attribute 5, "rv64i2p1_ssip0p19"
; RV64SMPMPMT: .attribute 5, "rv64i2p1_smpmpmt0p6"
; RV64SMRNMI: .attribute 5, "rv64i2p1_smrnmi1p0"
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index febe312db5836..c08d5db853853 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -26,11 +26,15 @@
; CHECK-NEXT: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile.
; CHECK-NEXT: experimental-smcsps - 'Smcsps' (Conditional Stack Pointer Swap at Machine Level).
; CHECK-NEXT: experimental-smehv - 'Smehv' (Synchronous Exception Hardware Vectoring at Machine Level).
+; CHECK-NEXT: experimental-smeihv - 'Smeihv' (External Interrupt Hardware Vectoring at Machine Level).
; CHECK-NEXT: experimental-smijt - 'Smijt' (Interrupt Jump Table at Machine Level).
+; CHECK-NEXT: experimental-smip - 'Smip' (Support for Interrupt Handler Push/Pop at Machine Level).
; CHECK-NEXT: experimental-smpmpmt - 'Smpmpmt' (PMP-based Memory Types Extension).
; CHECK-NEXT: experimental-sscsps - 'Sscsps' (Conditional Stack Pointer Swap at Supervisor Level).
; CHECK-NEXT: experimental-ssehv - 'Ssehv' (Synchronous Exception Hardware Vectoring at Supervisor Level).
+; CHECK-NEXT: experimental-sseihv - 'Sseihv' (External Interrupt Hardware Vectoring at Supervisor Level).
; CHECK-NEXT: experimental-ssijt - 'Ssijt' (Interrupt Jump Table at Supervisor Level).
+; CHECK-NEXT: experimental-ssip - 'Ssip' (Support for Interrupt Handler Push/Pop at Supervisor Level).
; CHECK-NEXT: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses).
; CHECK-NEXT: experimental-xqccmt - 'Xqccmt' (Qualcomm 16-bit Table Jump).
; CHECK-NEXT: experimental-xsfmclic - 'XSfmclic' (SiFive CLIC Machine-mode CSRs).
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index bf792bf4d2e54..5d39ee3c8ccd4 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -375,6 +375,18 @@
.attribute arch, "rv32i_ssehv0p19"
# CHECK: attribute 5, "rv32i2p1_ssehv0p19_ssijt0p19"
+.attribute arch, "rv32i_smeihv0p19"
+# CHECK: attribute 5, "rv32i2p1_smeihv0p19"
+
+.attribute arch, "rv32i_sseihv0p19"
+# CHECK: attribute 5, "rv32i2p1_sseihv0p19"
+
+.attribute arch, "rv32i_smip0p19"
+# CHECK: attribute 5, "rv32i2p1_smip0p19"
+
+.attribute arch, "rv32i_ssip0p19"
+# CHECK: attribute 5, "rv32i2p1_ssip0p19"
+
.attribute arch, "rv32i_smpmpmt0p6"
# CHECK: attribute 5, "rv32i2p1_smpmpmt0p6"
diff --git a/llvm/test/MC/RISCV/smip-ssip-invalid.s b/llvm/test/MC/RISCV/smip-ssip-invalid.s
new file mode 100644
index 0000000000000..0f2953cf93830
--- /dev/null
+++ b/llvm/test/MC/RISCV/smip-ssip-invalid.s
@@ -0,0 +1,33 @@
+# RUN: split-file %s %t
+# RUN: not llvm-mc -triple=riscv32 %t/no-features.s 2>&1 \
+# RUN: | FileCheck --check-prefix=NO-FEATURES %t/no-features.s
+# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-smip \
+# RUN: %t/no-ssip.s 2>&1 \
+# RUN: | FileCheck --check-prefix=NO-SSIP %t/no-ssip.s
+# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-ssip \
+# RUN: %t/no-smip.s 2>&1 \
+# RUN: | FileCheck --check-prefix=NO-SMIP %t/no-smip.s
+# RUN: not llvm-mc -triple=riscv32 \
+# RUN: -mattr=+experimental-smip,+experimental-ssip \
+# RUN: %t/invalid-operands.s 2>&1 \
+# RUN: | FileCheck --check-prefix=INVALID-OPERANDS %t/invalid-operands.s
+
+#--- no-features.s
+mipopret
+# NO-FEATURES: :[[#@LINE-1]]:1: error: instruction requires the following: 'Smip'
+sipopret
+# NO-FEATURES: :[[#@LINE-1]]:1: error: instruction requires the following: 'Ssip'
+
+#--- no-ssip.s
+sipopret
+# NO-SSIP: :[[#@LINE-1]]:1: error: instruction requires the following: 'Ssip'
+
+#--- no-smip.s
+mipopret
+# NO-SMIP: :[[#@LINE-1]]:1: error: instruction requires the following: 'Smip'
+
+#--- invalid-operands.s
+mipopret zero
+# INVALID-OPERANDS: :[[#@LINE-1]]:10: error: unexpected extra operand for instruction
+sipopret zero
+# INVALID-OPERANDS: :[[#@LINE-1]]:10: error: unexpected extra operand for instruction
diff --git a/llvm/test/MC/RISCV/smip-valid.s b/llvm/test/MC/RISCV/smip-valid.s
new file mode 100644
index 0000000000000..6a50ecc2f4e38
--- /dev/null
+++ b/llvm/test/MC/RISCV/smip-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-smip \
+# RUN: -M no-aliases -show-encoding \
+# RUN: | FileCheck --check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 \
+# RUN: -mattr=+experimental-smip < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-smip -M no-aliases - \
+# RUN: | FileCheck --check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-smip \
+# RUN: -M no-aliases -show-encoding \
+# RUN: | FileCheck --check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 \
+# RUN: -mattr=+experimental-smip < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-smip -M no-aliases - \
+# RUN: | FileCheck --check-prefix=CHECK-INST %s
+
+# CHECK-INST: mipopret
+# CHECK-ENC: encoding: [0x73,0x00,0x80,0x30]
+mipopret
diff --git a/llvm/test/MC/RISCV/ssip-valid.s b/llvm/test/MC/RISCV/ssip-valid.s
new file mode 100644
index 0000000000000..38a99f2312e0c
--- /dev/null
+++ b/llvm/test/MC/RISCV/ssip-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-ssip \
+# RUN: -M no-aliases -show-encoding \
+# RUN: | FileCheck --check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 \
+# RUN: -mattr=+experimental-ssip < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-ssip -M no-aliases - \
+# RUN: | FileCheck --check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-ssip \
+# RUN: -M no-aliases -show-encoding \
+# RUN: | FileCheck --check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 \
+# RUN: -mattr=+experimental-ssip < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-ssip -M no-aliases - \
+# RUN: | FileCheck --check-prefix=CHECK-INST %s
+
+# CHECK-INST: sipopret
+# CHECK-ENC: encoding: [0x73,0x00,0x80,0x10]
+sipopret
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 94261564e8043..0e5fbd7bbfdcd 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1662,11 +1662,15 @@ Experimental extensions
zvzip 0.1
smcsps 0.19
smehv 0.19
+ smeihv 0.19
smijt 0.19
+ smip 0.19
smpmpmt 0.6
sscsps 0.19
ssehv 0.19
+ sseihv 0.19
ssijt 0.19
+ ssip 0.19
svukte 1.0
xqccmt 0.1
xsfmclic 0.1
``````````
</details>
https://github.com/llvm/llvm-project/pull/215095
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