[clang] 3cce637 - Enforce single-operand form for llvm.loop.vectorize.predicate metadata (#213902)
via cfe-commits
cfe-commits at lists.llvm.org
Fri Aug 7 02:57:04 PDT 2026
Author: Madhur Amilkanthwar
Date: 2026-08-07T09:56:55Z
New Revision: 3cce637322a762daef7b50e4997c86af94d2d3c6
URL: https://github.com/llvm/llvm-project/commit/3cce637322a762daef7b50e4997c86af94d2d3c6
DIFF: https://github.com/llvm/llvm-project/commit/3cce637322a762daef7b50e4997c86af94d2d3c6.diff
LOG: Enforce single-operand form for llvm.loop.vectorize.predicate metadata (#213902)
Replace the two-operand boolean form
!{!"llvm.loop.vectorize.predicate.enable", i1 0/1} with a single-operand
enable/disable pair:
!{!"llvm.loop.vectorize.predicate.enable"}
!{!"llvm.loop.vectorize.predicate.disable"}
The Verifier rejects the two-operand form, AutoUpgrade rewrites old
bitcode, and the readers and producers in LLVM, Clang and MLIR are
updated.
Please refer to RFC:
https://discourse.llvm.org/t/rfc-enforce-single-operand-format-for-all-enable-metadata-nodes/90571/
Assisted by AI
Added:
llvm/test/Bitcode/upgrade-loop-vectorize-predicate-enable.ll
llvm/test/Bitcode/upgrade-loop-vectorize-predicate-enable.ll.bc
llvm/test/Verifier/llvm.loop.vectorize.predicate.ll
Modified:
clang/lib/CodeGen/CGLoopInfo.cpp
clang/test/CodeGenCXX/pragma-loop-predicate.cpp
llvm/docs/LangRef.md
llvm/include/llvm/IR/AutoUpgrade.h
llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
llvm/lib/IR/AutoUpgrade.cpp
llvm/lib/IR/Verifier.cpp
llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll
llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll
llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll
llvm/test/Transforms/LoopVectorize/AArch64/widen-gep-all-indices-invariant.ll
llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll
llvm/test/Transforms/LoopVectorize/ARM/tail-folding-loop-hint.ll
llvm/test/Transforms/LoopVectorize/ARM/tail-folding-prefer-flag.ll
llvm/test/Transforms/LoopVectorize/VPlan/AArch64/sve-tail-folding-forced.ll
llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing.ll
llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
llvm/test/Transforms/LoopVectorize/X86/tail_folding_and_assume_safety.ll
llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
llvm/test/Transforms/LoopVectorize/no-fold-tail-by-masking-iv-external-uses.ll
llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-predicated-early-exit.ll
llvm/test/Verifier/llvm.loop.distribute.ll
mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp
mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp
mlir/test/Target/LLVMIR/Import/metadata-loop.ll
mlir/test/Target/LLVMIR/loop-metadata.mlir
Removed:
################################################################################
diff --git a/clang/lib/CodeGen/CGLoopInfo.cpp b/clang/lib/CodeGen/CGLoopInfo.cpp
index 93857f9aaab8d..23eff005f7004 100644
--- a/clang/lib/CodeGen/CGLoopInfo.cpp
+++ b/clang/lib/CodeGen/CGLoopInfo.cpp
@@ -226,11 +226,11 @@ clang::CodeGen::LoopInfo::createLoopVectorizeMetadata(
IsVectorPredicateEnabled =
(Attrs.VectorizePredicateEnable == LoopAttributes::Enable);
- Metadata *Vals[] = {
- MDString::get(Ctx, "llvm.loop.vectorize.predicate.enable"),
- ConstantAsMetadata::get(ConstantInt::get(llvm::Type::getInt1Ty(Ctx),
- IsVectorPredicateEnabled))};
- Args.push_back(MDNode::get(Ctx, Vals));
+ Args.push_back(MDNode::get(
+ Ctx,
+ {MDString::get(Ctx, IsVectorPredicateEnabled
+ ? "llvm.loop.vectorize.predicate.enable"
+ : "llvm.loop.vectorize.predicate.disable")}));
}
// Setting vectorize.width
diff --git a/clang/test/CodeGenCXX/pragma-loop-predicate.cpp b/clang/test/CodeGenCXX/pragma-loop-predicate.cpp
index 421110fd9f867..cb7dfdb810215 100644
--- a/clang/test/CodeGenCXX/pragma-loop-predicate.cpp
+++ b/clang/test/CodeGenCXX/pragma-loop-predicate.cpp
@@ -106,10 +106,10 @@ void test9(int *List, int Length) {
// CHECK-NEXT: [[GEN3]] = !{!"llvm.loop.vectorize.enable"}
// CHECK-NEXT: ![[LOOP1]] = distinct !{![[LOOP1]], [[MP]], [[GEN6:![0-9]+]], [[GEN3]]}
-// CHECK-NEXT: [[GEN6]] = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+// CHECK-NEXT: [[GEN6]] = !{!"llvm.loop.vectorize.predicate.enable"}
// CHECK-NEXT: ![[LOOP2]] = distinct !{![[LOOP2]], [[MP]], [[GEN8:![0-9]+]], [[GEN3]]}
-// CHECK-NEXT: [[GEN8]] = !{!"llvm.loop.vectorize.predicate.enable", i1 false}
+// CHECK-NEXT: [[GEN8]] = !{!"llvm.loop.vectorize.predicate.disable"}
// CHECK-NEXT: ![[LOOP3]] = distinct !{![[LOOP3]], [[MP]], [[GEN6]], [[GEN3]]}
diff --git a/llvm/docs/LangRef.md b/llvm/docs/LangRef.md
index 6a3194271b838..d57f619042f22 100644
--- a/llvm/docs/LangRef.md
+++ b/llvm/docs/LangRef.md
@@ -8075,18 +8075,15 @@ node has a single operand containing the name string:
!1 = !{!"llvm.loop.vectorize.disable"}
```
-#### '`llvm.loop.vectorize.predicate.enable`' Metadata
+#### '`llvm.loop.vectorize.predicate.enable`' and '`llvm.loop.vectorize.predicate.disable`' Metadata
This metadata selectively enables or disables creating predicated instructions
for the loop, which can enable folding of the scalar epilogue loop into the
-main loop. The first operand is the string
-`llvm.loop.vectorize.predicate.enable` and the second operand is a bit. If
-the bit operand value is 1 predication is enabled. A value of 0 disables
-predication:
+main loop. Each node has a single operand containing the name string:
```llvm
-!0 = !{!"llvm.loop.vectorize.predicate.enable", i1 0}
-!1 = !{!"llvm.loop.vectorize.predicate.enable", i1 1}
+!0 = !{!"llvm.loop.vectorize.predicate.enable"}
+!1 = !{!"llvm.loop.vectorize.predicate.disable"}
```
Additionally, enabling predication implicitly enables vectorization.
diff --git a/llvm/include/llvm/IR/AutoUpgrade.h b/llvm/include/llvm/IR/AutoUpgrade.h
index 12aeb2793f705..1f1b3c4c27815 100644
--- a/llvm/include/llvm/IR/AutoUpgrade.h
+++ b/llvm/include/llvm/IR/AutoUpgrade.h
@@ -110,16 +110,34 @@ namespace llvm {
/// - sign-return-address-with-bkey
LLVM_ABI void copyModuleAttrToFunctions(Module &M);
+ /// Single-operand tags replacing a removed two-operand form
+ /// !{!"<Enable>", i1 X}: X = true selects Enable, X = false selects Disable.
+ struct BooleanLoopTags {
+ StringLiteral Enable;
+ StringLiteral Disable;
+ };
+
+ inline constexpr BooleanLoopTags OldBooleanLoopTags[] = {
+ {"llvm.loop.distribute.enable", "llvm.loop.distribute.disable"},
+ {"llvm.loop.vectorize.enable", "llvm.loop.vectorize.disable"},
+ {"llvm.loop.vectorize.predicate.enable",
+ "llvm.loop.vectorize.predicate.disable"}};
+
+ /// Return the replacement tags for the enable tag \p Name, or nullptr.
+ inline const BooleanLoopTags *findBooleanLoopTags(StringRef Name) {
+ for (const BooleanLoopTags &Tags : OldBooleanLoopTags)
+ if (Tags.Enable == Name)
+ return &Tags;
+ return nullptr;
+ }
+
/// Check whether a string looks like an old loop attachment tag.
inline bool mayBeOldLoopAttachmentTag(StringRef Name) {
- // "llvm.loop.distribute.enable" and "llvm.loop.vectorize.enable" are
- // intentionally included: the current single-operand form shares the tag
- // with the removed two-operand form (!{!"...", i1 X}), so we can only
- // decide by inspecting the operands, which happens in
+ // The enable tags are intentionally included: the current single-operand
+ // form shares the tag with the removed two-operand form (!{!"...", i1 X}),
+ // so we can only decide by inspecting the operands, which happens in
// upgradeLoopArgument().
- return Name.starts_with("llvm.vectorizer.") ||
- Name == "llvm.loop.distribute.enable" ||
- Name == "llvm.loop.vectorize.enable";
+ return Name.starts_with("llvm.vectorizer.") || findBooleanLoopTags(Name);
}
/// Upgrade the loop attachment metadata node.
diff --git a/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h b/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
index 3e8db73fd79d2..502fec920ece9 100644
--- a/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
+++ b/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
@@ -58,14 +58,7 @@ class Type;
/// for example 'force', means a decision has been made. So, we need to be
/// careful NOT to add them if the user hasn't specifically asked so.
class LoopVectorizeHints {
- enum HintKind {
- HK_WIDTH,
- HK_INTERLEAVE,
- HK_FORCE,
- HK_ISVECTORIZED,
- HK_PREDICATE,
- HK_SCALABLE
- };
+ enum HintKind { HK_WIDTH, HK_INTERLEAVE, HK_ISVECTORIZED, HK_SCALABLE };
/// Hint - associates name and validation with the hint value.
struct Hint {
@@ -85,14 +78,15 @@ class LoopVectorizeHints {
/// Vectorization interleave factor.
Hint Interleave;
- /// Vectorization forced
- Hint Force;
+ /// Vectorization forced; one of ForceKind. Carried as a plain value because
+ /// the enable/disable pair is a standalone tag with no operand to validate.
+ unsigned Force;
/// Already Vectorized
Hint IsVectorized;
- /// Vector Predicate
- Hint Predicate;
+ /// Vector Predicate; one of ForceKind, carried as a plain value like Force.
+ unsigned Predicate;
/// Says whether we should use fixed width or scalable vectorization.
Hint Scalable;
@@ -155,12 +149,12 @@ class LoopVectorizeHints {
return 0;
}
unsigned getIsVectorized() const { return IsVectorized.Value; }
- unsigned getPredicate() const { return Predicate.Value; }
+ unsigned getPredicate() const { return Predicate; }
enum ForceKind getForce() const {
- if ((ForceKind)Force.Value == FK_Undefined &&
+ if ((ForceKind)Force == FK_Undefined &&
hasDisableAllTransformsHint(TheLoop))
return FK_Disabled;
- return (ForceKind)Force.Value;
+ return (ForceKind)Force;
}
/// \return true if scalable vectorization has been explicitly disabled.
diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp
index d2216e4072337..5c4d38bd52bdb 100644
--- a/llvm/lib/IR/AutoUpgrade.cpp
+++ b/llvm/lib/IR/AutoUpgrade.cpp
@@ -7074,37 +7074,22 @@ void llvm::copyModuleAttrToFunctions(Module &M) {
}
}
-// Old two-operand form: !{!"llvm.loop.distribute.enable", i1 X}. The new
-// single-operand form uses "llvm.loop.distribute.enable" for X = true and
-// "llvm.loop.distribute.disable" for X = false.
-static bool isOldDistributeEnable(const MDTuple *T) {
- if (T->getNumOperands() != 2)
- return false;
- auto *Tag = dyn_cast_or_null<MDString>(T->getOperand(0));
- if (!Tag || Tag->getString() != "llvm.loop.distribute.enable")
- return false;
- return mdconst::hasa<ConstantInt>(T->getOperand(1));
-}
-
-/// Old two-operand form: !{!"llvm.loop.vectorize.enable", i1 X}. The new
-/// single-operand form uses "llvm.loop.vectorize.enable" for X = true and
-/// "llvm.loop.vectorize.disable" for X = false.
-static bool isOldVectorizeEnable(const MDTuple *T) {
- if (T->getNumOperands() != 2)
- return false;
+/// Return the replacement tags if \p T still uses a removed two-operand form.
+static const BooleanLoopTags *getOldBooleanLoopTags(const MDTuple *T) {
+ if (T->getNumOperands() != 2 || !mdconst::hasa<ConstantInt>(T->getOperand(1)))
+ return nullptr;
auto *Tag = dyn_cast_or_null<MDString>(T->getOperand(0));
- if (!Tag || Tag->getString() != "llvm.loop.vectorize.enable")
- return false;
- return mdconst::hasa<ConstantInt>(T->getOperand(1));
+ return Tag ? findBooleanLoopTags(Tag->getString()) : nullptr;
}
-/// Build the single-operand vectorize enable/disable node that replaces a
-/// boolean operand: nonzero -> enable, zero -> disable.
-static Metadata *makeVectorizeEnableNode(LLVMContext &C, const MDOperand &Op) {
+/// Build the single-operand node that replaces a boolean operand: nonzero
+/// selects the enable tag, zero the disable tag.
+static Metadata *makeBooleanLoopNode(LLVMContext &C,
+ const BooleanLoopTags &Tags,
+ const MDOperand &Op) {
bool Enable = !mdconst::extract<ConstantInt>(Op)->isZero();
- return MDTuple::get(
- C, {MDString::get(C, Enable ? "llvm.loop.vectorize.enable"
- : "llvm.loop.vectorize.disable")});
+ return MDTuple::get(C,
+ {MDString::get(C, Enable ? Tags.Enable : Tags.Disable)});
}
static bool isOldLoopArgument(Metadata *MD) {
@@ -7118,7 +7103,7 @@ static bool isOldLoopArgument(Metadata *MD) {
return false;
if (S->getString().starts_with("llvm.vectorizer."))
return true;
- return isOldDistributeEnable(T) || isOldVectorizeEnable(T);
+ return getOldBooleanLoopTags(T) != nullptr;
}
static MDString *upgradeLoopTag(LLVMContext &C, StringRef OldTag) {
@@ -7145,18 +7130,9 @@ static Metadata *upgradeLoopArgument(Metadata *MD) {
LLVMContext &C = T->getContext();
- // Rewrite the old two-operand distribute form to the single-operand pair.
- if (isOldDistributeEnable(T)) {
- bool Enable = !mdconst::extract<ConstantInt>(T->getOperand(1))->isZero();
- return MDTuple::get(
- C, {MDString::get(C, Enable ? "llvm.loop.distribute.enable"
- : "llvm.loop.distribute.disable")});
- }
-
- // Rewrite the modern two-operand vectorize.enable form to the single-operand
- // enable/disable pair.
- if (isOldVectorizeEnable(T))
- return makeVectorizeEnableNode(C, T->getOperand(1));
+ /// Rewrite a removed two-operand boolean form to the single-operand pair.
+ if (const BooleanLoopTags *Tags = getOldBooleanLoopTags(T))
+ return makeBooleanLoopNode(C, *Tags, T->getOperand(1));
if (!OldTag->getString().starts_with("llvm.vectorizer."))
return MD;
@@ -7166,9 +7142,9 @@ static Metadata *upgradeLoopArgument(Metadata *MD) {
// The legacy !{!"llvm.vectorizer.enable", i1 X} maps onto the single-operand
// vectorize.enable/disable pair, not a two-operand enable node.
- if (NewTag->getString() == "llvm.loop.vectorize.enable" &&
- T->getNumOperands() == 2 && mdconst::hasa<ConstantInt>(T->getOperand(1)))
- return makeVectorizeEnableNode(C, T->getOperand(1));
+ if (T->getNumOperands() == 2 && mdconst::hasa<ConstantInt>(T->getOperand(1)))
+ if (const BooleanLoopTags *Tags = findBooleanLoopTags(NewTag->getString()))
+ return makeBooleanLoopNode(C, *Tags, T->getOperand(1));
SmallVector<Metadata *, 8> Ops;
Ops.reserve(T->getNumOperands());
@@ -7187,14 +7163,14 @@ MDNode *llvm::upgradeInstructionLoopAttachment(MDNode &N) {
if (none_of(T->operands(), isOldLoopArgument))
return &N;
- // Fix the old two-operand distribute/vectorize.enable nodes in place: the
- // Verifier rejects any MDNode carrying those tags with more than one operand,
- // so a leftover reference (from the distinct loop-ID) would still trigger a
- // diagnostic. In-place mutation is safe on distinct MDNodes.
+ // Fix the removed two-operand boolean nodes in place: the Verifier rejects
+ // any MDNode carrying those tags with more than one operand, so a leftover
+ // reference (from the distinct loop-ID) would still trigger a diagnostic.
+ // In-place mutation is safe on distinct MDNodes.
if (T->isDistinct()) {
for (unsigned I = 0, E = T->getNumOperands(); I < E; ++I) {
auto *OpT = dyn_cast_or_null<MDTuple>(T->getOperand(I));
- if (OpT && (isOldDistributeEnable(OpT) || isOldVectorizeEnable(OpT)))
+ if (OpT && getOldBooleanLoopTags(OpT))
T->replaceOperandWith(I, upgradeLoopArgument(OpT));
}
if (none_of(T->operands(), isOldLoopArgument))
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 44d1843aa56a9..09429024e3ae8 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -64,6 +64,7 @@
#include "llvm/IR/Argument.h"
#include "llvm/IR/AttributeMask.h"
#include "llvm/IR/Attributes.h"
+#include "llvm/IR/AutoUpgrade.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/BundleAttributes.h"
#include "llvm/IR/CFG.h"
@@ -1009,18 +1010,12 @@ void Verifier::visitMDNode(const MDNode &BaseMD,
CurrentMD);
}
- // Enforce the single-operand form of llvm.loop.distribute metadata.
+ // Enforce the single-operand form of the loop enable/disable pairs.
if (CurrentMD->getNumOperands() > 0 &&
- (CurrentMD->getOperand(0).equalsStr("llvm.loop.distribute.enable") ||
- CurrentMD->getOperand(0).equalsStr("llvm.loop.distribute.disable")))
- Check(CurrentMD->getNumOperands() == 1,
- "Expected one operand for llvm.loop.distribute metadata",
- CurrentMD);
-
- // Enforce the single-operand form of llvm.loop.vectorize.enable metadata.
- if (CurrentMD->getNumOperands() > 0 &&
- (CurrentMD->getOperand(0).equalsStr("llvm.loop.vectorize.enable") ||
- CurrentMD->getOperand(0).equalsStr("llvm.loop.vectorize.disable")))
+ any_of(OldBooleanLoopTags, [CurrentMD](const BooleanLoopTags &Tags) {
+ return CurrentMD->getOperand(0).equalsStr(Tags.Enable) ||
+ CurrentMD->getOperand(0).equalsStr(Tags.Disable);
+ }))
Check(CurrentMD->getNumOperands() == 1,
"Expecting only the metadata name", CurrentMD);
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
index 9086880599231..c2c6ac7953d82 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
@@ -90,10 +90,7 @@ bool LoopVectorizeHints::Hint::validate(unsigned Val) {
return isPowerOf2_32(Val) && Val <= VectorizerParams::MaxVectorWidth;
case HK_INTERLEAVE:
return isPowerOf2_32(Val) && Val <= MaxInterleaveFactor;
- case HK_FORCE:
- return (Val <= 1);
case HK_ISVECTORIZED:
- case HK_PREDICATE:
case HK_SCALABLE:
return (Val == 0 || Val == 1);
}
@@ -107,9 +104,8 @@ LoopVectorizeHints::LoopVectorizeHints(const Loop *L,
: Width("vectorize.width",
VectorizerParams::VectorizationFactor.getKnownMinValue(), HK_WIDTH),
Interleave("interleave.count", InterleaveOnlyWhenForced, HK_INTERLEAVE),
- Force("vectorize.enable", FK_Undefined, HK_FORCE),
- IsVectorized("isvectorized", 0, HK_ISVECTORIZED),
- Predicate("vectorize.predicate.enable", FK_Undefined, HK_PREDICATE),
+ Force(FK_Undefined), IsVectorized("isvectorized", 0, HK_ISVECTORIZED),
+ Predicate(FK_Undefined),
Scalable("vectorize.scalable.enable", SK_Unspecified, HK_SCALABLE),
TheLoop(L), ORE(ORE) {
// Populate values with existing loop metadata.
@@ -182,7 +178,7 @@ void LoopVectorizeHints::reportDisallowedVectorization(
bool LoopVectorizeHints::allowVectorization(
Function *F, Loop *L, bool VectorizeOnlyWhenForced) const {
if (getForce() == LoopVectorizeHints::FK_Disabled) {
- if (Force.Value == LoopVectorizeHints::FK_Disabled) {
+ if (Force == LoopVectorizeHints::FK_Disabled) {
reportDisallowedVectorization("#pragma vectorize disable",
"MissedExplicitlyDisabled",
"vectorization is explicitly disabled", L);
@@ -226,7 +222,7 @@ void LoopVectorizeHints::emitRemarkWithHints() const {
using namespace ore;
ORE.emit([&]() {
- if (Force.Value == LoopVectorizeHints::FK_Disabled)
+ if (Force == LoopVectorizeHints::FK_Disabled)
return OptimizationRemarkMissed(LV_NAME, "MissedExplicitlyDisabled",
TheLoop->getStartLoc(),
TheLoop->getHeader())
@@ -235,7 +231,7 @@ void LoopVectorizeHints::emitRemarkWithHints() const {
OptimizationRemarkMissed R(LV_NAME, "MissedDetails", TheLoop->getStartLoc(),
TheLoop->getHeader());
R << "loop not vectorized";
- if (Force.Value == LoopVectorizeHints::FK_Enabled) {
+ if (Force == LoopVectorizeHints::FK_Enabled) {
R << " (Force=" << NV("Force", true);
if (Width.Value != 0)
R << ", Vector Width=" << NV("VectorWidth", getWidth());
@@ -290,9 +286,13 @@ void LoopVectorizeHints::getHintsFromMetadata() {
// The single-operand enable/disable pair carries no argument.
if (Args.empty()) {
if (Name == "llvm.loop.vectorize.enable")
- Force.Value = FK_Enabled;
+ Force = FK_Enabled;
else if (Name == "llvm.loop.vectorize.disable")
- Force.Value = FK_Disabled;
+ Force = FK_Disabled;
+ else if (Name == "llvm.loop.vectorize.predicate.enable")
+ Predicate = FK_Enabled;
+ else if (Name == "llvm.loop.vectorize.predicate.disable")
+ Predicate = FK_Disabled;
continue;
}
if (Args.size() == 1)
@@ -309,8 +309,9 @@ void LoopVectorizeHints::setHint(StringRef Name, Metadata *Arg) {
return;
unsigned Val = C->getZExtValue();
- Hint *Hints[] = {&Width, &Interleave, &Force,
- &IsVectorized, &Predicate, &Scalable};
+ // Force and Predicate are omitted: they are only spelled as single-operand
+ // enable/disable nodes, which never reach setHint().
+ Hint *Hints[] = {&Width, &Interleave, &IsVectorized, &Scalable};
for (auto *H : Hints) {
if (Name == H->Name) {
if (H->validate(Val))
diff --git a/llvm/test/Bitcode/upgrade-loop-vectorize-predicate-enable.ll b/llvm/test/Bitcode/upgrade-loop-vectorize-predicate-enable.ll
new file mode 100644
index 0000000000000..20e1f264e559c
--- /dev/null
+++ b/llvm/test/Bitcode/upgrade-loop-vectorize-predicate-enable.ll
@@ -0,0 +1,37 @@
+; Test that older bitcode carrying the two-operand form of
+; "llvm.loop.vectorize.predicate.enable" is auto-upgraded to the
+; single-operand enable/disable pair on load.
+;
+; RUN: llvm-dis < %s.bc | FileCheck %s
+; RUN: verify-uselistorder < %s.bc
+
+define void @enable_true() {
+entry:
+ br label %body
+body:
+ br i1 0, label %body, label %exit, !llvm.loop !0
+exit:
+ ret void
+}
+
+define void @enable_false() {
+entry:
+ br label %body
+body:
+ br i1 0, label %body, label %exit, !llvm.loop !2
+exit:
+ ret void
+}
+
+; i1 true -> single-operand enable.
+; i1 false -> disable.
+; CHECK: !{!"llvm.loop.vectorize.predicate.enable"}
+; CHECK: !{!"llvm.loop.vectorize.predicate.disable"}
+; The old two-operand nodes must be gone from the module.
+; CHECK-NOT: llvm.loop.vectorize.predicate.enable", i1
+; CHECK-NOT: llvm.loop.vectorize.predicate.disable", i1
+
+!0 = distinct !{!0, !1}
+!1 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!2 = distinct !{!2, !3}
+!3 = !{!"llvm.loop.vectorize.predicate.enable", i1 false}
diff --git a/llvm/test/Bitcode/upgrade-loop-vectorize-predicate-enable.ll.bc b/llvm/test/Bitcode/upgrade-loop-vectorize-predicate-enable.ll.bc
new file mode 100644
index 0000000000000..d8de6672e251b
Binary files /dev/null and b/llvm/test/Bitcode/upgrade-loop-vectorize-predicate-enable.ll.bc
diff er
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll b/llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
index 1138b19bd3471..c68421ac4a2a4 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
@@ -528,7 +528,7 @@ exit:
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.predicate.enable"}
!2 = !{!"branch_weights", i32 10, i32 30}
;.
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
index 0282a9cac5c8d..f493914d294a1 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
@@ -447,7 +447,7 @@ exit:
!7 = distinct !{!7, !8, !9, !10}
!8 = !{!"llvm.loop.mustprogress"}
-!9 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!9 = !{!"llvm.loop.vectorize.predicate.enable"}
!10 = !{!"llvm.loop.vectorize.enable"}
attributes #0 = { vscale_range(1,16) "target-features"="+sve" }
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
index 339aea4551d6b..97cc8e50b62c7 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
@@ -393,7 +393,7 @@ for.exit:
!7 = distinct !{!7, !8, !9, !10}
!8 = !{!"llvm.loop.mustprogress"}
-!9 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!9 = !{!"llvm.loop.vectorize.predicate.enable"}
!10 = !{!"llvm.loop.vectorize.enable"}
attributes #0 = { vscale_range(1,16) "target-features"="+sve" }
attributes #1 = { "target-features"="+neon" }
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
index 3ba46e2fd46d6..aa9ca9a265605 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
@@ -2394,5 +2394,5 @@ exit:
!7 = distinct !{!7, !8, !9, !10}
!8 = !{!"llvm.loop.mustprogress"}
-!9 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!9 = !{!"llvm.loop.vectorize.predicate.enable"}
!10 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
index 29cd49f425373..2e637e7752170 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
@@ -2691,7 +2691,7 @@ for.body:
!7 = distinct !{!7, !8, !9, !10}
!8 = !{!"llvm.loop.mustprogress"}
-!9 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!9 = !{!"llvm.loop.vectorize.predicate.enable"}
!10 = !{!"llvm.loop.vectorize.enable"}
attributes #0 = { vscale_range(1,16) "target-features"="+sve" }
attributes #1 = { vscale_range(1,16) "target-features"="+neon,+dotprod,+sve" "target-cpu"="neoverse-v2" }
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
index 641d6db59147d..61f4e4098a8bf 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
@@ -523,7 +523,7 @@ for.exit:
!7 = distinct !{!7, !8, !9, !10}
!8 = !{!"llvm.loop.mustprogress"}
-!9 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!9 = !{!"llvm.loop.vectorize.predicate.enable"}
!10 = !{!"llvm.loop.vectorize.enable"}
attributes #0 = { vscale_range(1,16) "target-features"="+sve" }
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll
index 03938490e465c..9aa27cee2ecb8 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll
@@ -1285,7 +1285,7 @@ exit:
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.predicate.enable"}
attributes #0 = { vscale_range(1,16) "target-features"="+sve" }
attributes #1 = { vscale_range(1,16) "target-features"="+neon,+dotprod,+sve" "target-cpu"="neoverse-v2" }
attributes #2 = { "target-features"="+neon,+dotprod" }
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll b/llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll
index 3c47627e5f45f..31f6e49c835b9 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll
@@ -370,7 +370,7 @@ attributes #1 = { "target-cpu"="neoverse-v2" }
!0 = distinct !{!0, !1, !2, !3}
!1 = !{!"llvm.loop.mustprogress"}
-!2 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.predicate.enable"}
!3 = !{!"llvm.loop.vectorize.enable"}
; BFI computes if is taken 20 times, and loop 32 times. Make sure we round the
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll b/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll
index b79cc7cf2bcee..b689914508b25 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll
@@ -1417,5 +1417,5 @@ for.cond.cleanup:
!9 = !{!"llvm.loop.interleave.count", i32 1}
!10 = !{!"llvm.loop.interleave.count", i32 4}
!11 = !{!"llvm.loop.vectorize.enable"}
-!12 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!12 = !{!"llvm.loop.vectorize.predicate.enable"}
!13 = distinct !{!13, !6, !9, !11}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
index e0a1b2bb6a03e..88a4ea2366d60 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
@@ -876,7 +876,7 @@ attributes #0 = { "target-features"="+sve2" vscale_range(1,16) }
!0 = distinct !{!0, !1}
!1 = !{!"llvm.loop.interleave.count", i32 2}
!2 = distinct !{!2, !3}
-!3 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.predicate.enable"}
!4 = distinct !{!4, !5}
!5 = !{!"llvm.loop.interleave.count", i32 1}
!6 = !{!7}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll b/llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll
index 0b783375a33e1..d323dce104e66 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll
@@ -150,7 +150,7 @@ while.end.loopexit:
}
!0 = distinct !{!0, !1, !2, !3, !4}
-!1 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.predicate.enable"}
!2 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
!3 = !{!"llvm.loop.interleave.count", i32 1}
!4 = !{!"llvm.loop.vectorize.width", i32 4}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/widen-gep-all-indices-invariant.ll b/llvm/test/Transforms/LoopVectorize/AArch64/widen-gep-all-indices-invariant.ll
index 3b29335c36301..18712ad5d1fba 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/widen-gep-all-indices-invariant.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/widen-gep-all-indices-invariant.ll
@@ -55,7 +55,7 @@ attributes #0 = { "target-cpu"="neoverse-v2" }
!0 = distinct !{!0, !1, !2}
!1 = !{!"llvm.loop.vectorize.enable"}
-!2 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.predicate.enable"}
;.
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll b/llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll
index 75862d9c72e00..46dbb741a1ee0 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll
@@ -425,7 +425,7 @@ attributes #0 = { nofree norecurse nounwind "target-features"="+armv8.1-m.main,+
!6 = !{!"llvm.loop.vectorize.enable"}
!7 = distinct !{!7, !8}
-!8 = !{!"llvm.loop.vectorize.predicate.enable", i1 false}
+!8 = !{!"llvm.loop.vectorize.predicate.disable"}
!10 = distinct !{!10, !11}
!11 = !{!"llvm.loop.vectorize.width", i32 4}
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-loop-hint.ll b/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-loop-hint.ll
index 3038b7fd935d3..e0bcaba596768 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-loop-hint.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-loop-hint.ll
@@ -80,5 +80,5 @@ for.body:
; CHECK-NEXT: [[VEC_LOOP2]] = distinct !{[[VEC_LOOP2]], [[MD_IS_VEC]], [[MD_RT_UNROLL_DIS]]}
!6 = distinct !{!6, !7, !8}
-!7 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!7 = !{!"llvm.loop.vectorize.predicate.enable"}
!8 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-prefer-flag.ll b/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-prefer-flag.ll
index a477fee265d59..8d4f990c09e84 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-prefer-flag.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-prefer-flag.ll
@@ -101,7 +101,7 @@ for.body:
}
!10 = distinct !{!10, !11, !12}
-!11 = !{!"llvm.loop.vectorize.predicate.enable", i1 false}
+!11 = !{!"llvm.loop.vectorize.predicate.disable"}
!12 = !{!"llvm.loop.vectorize.enable"}
!14 = distinct !{!14, !15}
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/sve-tail-folding-forced.ll b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/sve-tail-folding-forced.ll
index 592dbbb2b5c52..15e57eda91e0e 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/sve-tail-folding-forced.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/sve-tail-folding-forced.ll
@@ -85,4 +85,4 @@ while.end.loopexit:
attributes #0 = { "target-features"="+sve" }
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.predicate.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing.ll b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing.ll
index 5445a5e835fb6..91cb168e423ef 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing.ll
@@ -282,5 +282,5 @@ exit:
!0 = distinct !{!0, !2, !3}
!1 = distinct !{!1, !2, !4}
!2 = !{!"llvm.loop.interleave.count", i32 1}
-!3 = !{!"llvm.loop.vectorize.predicate.enable", i1 false}
-!4 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.predicate.disable"}
+!4 = !{!"llvm.loop.vectorize.predicate.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll b/llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
index 4ec0ec66d4321..cb00f39754036 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
@@ -319,4 +319,4 @@ exit:
!1 = distinct !{!1, !2, !3, !4}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
!3 = !{!"llvm.loop.vectorize.enable"}
-!4 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!4 = !{!"llvm.loop.vectorize.predicate.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll b/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
index 815d13351d15d..92b95f2256ebf 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
@@ -643,7 +643,7 @@ exit:
!1 = distinct !{!1, !2, !3, !4}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
!3 = !{!"llvm.loop.vectorize.enable"}
-!4 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!4 = !{!"llvm.loop.vectorize.predicate.enable"}
define void @wide_iv_trunc_reuse(ptr %dst) {
; CHECK-LABEL: define void @wide_iv_trunc_reuse(
diff --git a/llvm/test/Transforms/LoopVectorize/X86/tail_folding_and_assume_safety.ll b/llvm/test/Transforms/LoopVectorize/X86/tail_folding_and_assume_safety.ll
index a1def726e10ed..ca8b382556009 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/tail_folding_and_assume_safety.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/tail_folding_and_assume_safety.ll
@@ -146,9 +146,9 @@ attributes #0 = { "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float
!7 = !{!"llvm.loop.vectorize.enable"}
!8 = distinct !{!8, !9}
-!9 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!9 = !{!"llvm.loop.vectorize.predicate.enable"}
!10 = distinct !{}
!11 = distinct !{!11, !12, !13}
!12 = !{!"llvm.loop.parallel_accesses", !10}
-!13 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!13 = !{!"llvm.loop.vectorize.predicate.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll b/llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
index e5b88dd5219db..e42b16098776c 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
@@ -171,8 +171,8 @@ for.cond.cleanup:
attributes #0 = { optsize "target-cpu"="core-avx2" "target-features"="+avx,+avx2" }
!6 = distinct !{!6, !7, !8}
-!7 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!7 = !{!"llvm.loop.vectorize.predicate.enable"}
!8 = !{!"llvm.loop.vectorize.enable"}
!10 = distinct !{!10, !11}
-!11 = !{!"llvm.loop.vectorize.predicate.enable", i1 false}
+!11 = !{!"llvm.loop.vectorize.predicate.disable"}
diff --git a/llvm/test/Transforms/LoopVectorize/no-fold-tail-by-masking-iv-external-uses.ll b/llvm/test/Transforms/LoopVectorize/no-fold-tail-by-masking-iv-external-uses.ll
index 6a80b02aaf50e..7e6247033a875 100644
--- a/llvm/test/Transforms/LoopVectorize/no-fold-tail-by-masking-iv-external-uses.ll
+++ b/llvm/test/Transforms/LoopVectorize/no-fold-tail-by-masking-iv-external-uses.ll
@@ -128,7 +128,7 @@ done:
!0 = distinct !{!0, !1, !2, !3}
!1 = !{!"llvm.loop.unroll.disable"}
-!2 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.predicate.enable"}
!3 = !{!"llvm.loop.vectorize.enable"}
;.
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]], [[META3:![0-9]+]]}
diff --git a/llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll b/llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
index 4751570432927..2737e3accf37a 100644
--- a/llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
+++ b/llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
@@ -611,5 +611,5 @@ for.end:
}
!6 = distinct !{!6, !7, !8}
-!7 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!7 = !{!"llvm.loop.vectorize.predicate.enable"}
!8 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll b/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
index 73ce57b156952..abf0100a2440a 100644
--- a/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
+++ b/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
@@ -3138,5 +3138,5 @@ for.exit:
!6 = distinct !{!6, !7, !8}
-!7 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!7 = !{!"llvm.loop.vectorize.predicate.enable"}
!8 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll b/llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
index 5d65362df3cc2..6135464eaca14 100644
--- a/llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
+++ b/llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
@@ -244,5 +244,5 @@ end:
}
!1 = distinct !{!1, !2, !3}
-!2 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.predicate.enable"}
!3 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-predicated-early-exit.ll b/llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-predicated-early-exit.ll
index ce0da2efcab20..be0a9c5b7e7d7 100644
--- a/llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-predicated-early-exit.ll
+++ b/llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-predicated-early-exit.ll
@@ -50,5 +50,5 @@ exit:
!0 = distinct !{!0, !1, !2, !3}
!1 = !{!"llvm.loop.mustprogress"}
-!2 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.predicate.enable"}
!3 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Verifier/llvm.loop.distribute.ll b/llvm/test/Verifier/llvm.loop.distribute.ll
index 65ca27720542b..81cf6bb6b3e27 100644
--- a/llvm/test/Verifier/llvm.loop.distribute.ll
+++ b/llvm/test/Verifier/llvm.loop.distribute.ll
@@ -13,7 +13,7 @@ exit:
}
!0 = distinct !{!0, !1}
-; BAD: Expected one operand for llvm.loop.distribute metadata
+; BAD: Expecting only the metadata name
; Single-operand enable.
; RUN: cat %s > %t
diff --git a/llvm/test/Verifier/llvm.loop.vectorize.predicate.ll b/llvm/test/Verifier/llvm.loop.vectorize.predicate.ll
new file mode 100644
index 0000000000000..943efa88c22ad
--- /dev/null
+++ b/llvm/test/Verifier/llvm.loop.vectorize.predicate.ll
@@ -0,0 +1,41 @@
+; Test "llvm.loop.vectorize.predicate.enable" /
+; "llvm.loop.vectorize.predicate.disable" single-operand validation.
+
+; DEFINE: %{VERIFY} = llvm-as -disable-output %t 2>&1
+
+define void @test() {
+entry:
+ br label %body
+body:
+ br i1 0, label %body, label %exit, !llvm.loop !0
+exit:
+ ret void
+}
+!0 = distinct !{!0, !1}
+
+; BAD: Expecting only the metadata name
+
+; Single-operand enable.
+; RUN: cat %s > %t
+; RUN: echo '!1 = !{!"llvm.loop.vectorize.predicate.enable"}' >> %t
+; RUN: %{VERIFY}
+
+; Single-operand disable.
+; RUN: cat %s > %t
+; RUN: echo '!1 = !{!"llvm.loop.vectorize.predicate.disable"}' >> %t
+; RUN: %{VERIFY}
+
+; Two-operand enable with boolean false (legacy form, now rejected).
+; RUN: cat %s > %t
+; RUN: echo '!1 = !{!"llvm.loop.vectorize.predicate.enable", i1 0}' >> %t
+; RUN: not %{VERIFY} | FileCheck %s -check-prefix=BAD
+
+; Two-operand enable with boolean true (legacy form, now rejected).
+; RUN: cat %s > %t
+; RUN: echo '!1 = !{!"llvm.loop.vectorize.predicate.enable", i1 1}' >> %t
+; RUN: not %{VERIFY} | FileCheck %s -check-prefix=BAD
+
+; Two-operand disable (rejected).
+; RUN: cat %s > %t
+; RUN: echo '!1 = !{!"llvm.loop.vectorize.predicate.disable", i1 0}' >> %t
+; RUN: not %{VERIFY} | FileCheck %s -check-prefix=BAD
diff --git a/mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp b/mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp
index 7f80b5be28b0b..1bf3400614cf5 100644
--- a/mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp
+++ b/mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp
@@ -289,7 +289,8 @@ FailureOr<LoopVectorizeAttr> LoopMetadataConversion::convertVectorizeAttr() {
"llvm.loop.vectorize.enable", "llvm.loop.vectorize.disable",
/*negated=*/true);
FailureOr<BoolAttr> predicateEnable =
- lookupBoolNode("llvm.loop.vectorize.predicate.enable");
+ lookupBooleanUnitNode("llvm.loop.vectorize.predicate.enable",
+ "llvm.loop.vectorize.predicate.disable");
FailureOr<BoolAttr> scalableEnable =
lookupBoolNode("llvm.loop.vectorize.scalable.enable");
FailureOr<IntegerAttr> width = lookupIntNode("llvm.loop.vectorize.width");
diff --git a/mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp b/mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp
index 7420142957d4c..cf0e56df2c2b3 100644
--- a/mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp
+++ b/mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp
@@ -31,6 +31,8 @@ struct LoopAnnotationConversion {
void addUnitNode(StringRef name, BoolAttr attr);
void addI32NodeWithVal(StringRef name, uint32_t val);
void convertBoolNode(StringRef name, BoolAttr attr, bool negated = false);
+ void convertBooleanUnitNode(StringRef enableName, StringRef disableName,
+ BoolAttr attr, bool negated = false);
void convertI32Node(StringRef name, IntegerAttr attr);
void convertFollowupNode(StringRef name, LoopAnnotationAttr attr);
void convertLocation(FusedLoc attr);
@@ -83,6 +85,19 @@ void LoopAnnotationConversion::convertBoolNode(StringRef name, BoolAttr attr,
llvm::ConstantAsMetadata::get(cstValue)}));
}
+/// Emits the single-operand node of an enable/disable pair. As in
+/// convertBoolNode, the attribute is tri-state: a null \p attr emits no node
+/// at all, otherwise \p negated ^ the attribute value is the enable bit and
+/// selects which of the two names is emitted.
+void LoopAnnotationConversion::convertBooleanUnitNode(StringRef enableName,
+ StringRef disableName,
+ BoolAttr attr,
+ bool negated) {
+ if (!attr)
+ return;
+ addUnitNode((negated ^ attr.getValue()) ? enableName : disableName);
+}
+
void LoopAnnotationConversion::convertI32Node(StringRef name,
IntegerAttr attr) {
if (!attr)
@@ -103,14 +118,12 @@ void LoopAnnotationConversion::convertFollowupNode(StringRef name,
}
void LoopAnnotationConversion::convertLoopOptions(LoopVectorizeAttr options) {
- if (auto disable = options.getDisable()) {
- if (disable.getValue())
- addUnitNode("llvm.loop.vectorize.disable");
- else
- addUnitNode("llvm.loop.vectorize.enable");
- }
- convertBoolNode("llvm.loop.vectorize.predicate.enable",
- options.getPredicateEnable());
+ convertBooleanUnitNode("llvm.loop.vectorize.enable",
+ "llvm.loop.vectorize.disable", options.getDisable(),
+ /*negated=*/true);
+ convertBooleanUnitNode("llvm.loop.vectorize.predicate.enable",
+ "llvm.loop.vectorize.predicate.disable",
+ options.getPredicateEnable());
convertBoolNode("llvm.loop.vectorize.scalable.enable",
options.getScalableEnable());
convertI32Node("llvm.loop.vectorize.width", options.getWidth());
@@ -167,12 +180,9 @@ void LoopAnnotationConversion::convertLoopOptions(LoopLICMAttr options) {
}
void LoopAnnotationConversion::convertLoopOptions(LoopDistributeAttr options) {
- if (auto disable = options.getDisable()) {
- if (disable.getValue())
- addUnitNode("llvm.loop.distribute.disable");
- else
- addUnitNode("llvm.loop.distribute.enable");
- }
+ convertBooleanUnitNode("llvm.loop.distribute.enable",
+ "llvm.loop.distribute.disable", options.getDisable(),
+ /*negated=*/true);
convertFollowupNode("llvm.loop.distribute.followup_coincident",
options.getFollowupCoincident());
convertFollowupNode("llvm.loop.distribute.followup_sequential",
diff --git a/mlir/test/Target/LLVMIR/Import/metadata-loop.ll b/mlir/test/Target/LLVMIR/Import/metadata-loop.ll
index d64a96c1b1422..7b4a6d7fa5263 100644
--- a/mlir/test/Target/LLVMIR/Import/metadata-loop.ll
+++ b/mlir/test/Target/LLVMIR/Import/metadata-loop.ll
@@ -87,7 +87,7 @@ end:
!1 = distinct !{!1, !2, !3, !4, !5, !6, !7, !8}
!2 = !{!"llvm.loop.vectorize.enable"}
-!3 = !{!"llvm.loop.vectorize.predicate.enable", i1 1}
+!3 = !{!"llvm.loop.vectorize.predicate.enable"}
!4 = !{!"llvm.loop.vectorize.scalable.enable", i1 0}
!5 = !{!"llvm.loop.vectorize.width", i32 16}
!6 = !{!"llvm.loop.vectorize.followup_vectorized", !9}
diff --git a/mlir/test/Target/LLVMIR/loop-metadata.mlir b/mlir/test/Target/LLVMIR/loop-metadata.mlir
index ada830e103a2c..50293246d34d5 100644
--- a/mlir/test/Target/LLVMIR/loop-metadata.mlir
+++ b/mlir/test/Target/LLVMIR/loop-metadata.mlir
@@ -56,7 +56,7 @@ llvm.func @vectorizeOptions() {
// CHECK-DAG: ![[FOLLOWUP:[0-9]+]] = distinct !{![[FOLLOWUP]], ![[NON_FORCED]]}
// CHECK-DAG: ![[LOOP_NODE]] = distinct !{![[LOOP_NODE]], !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}}
// CHECK-DAG: !{{[0-9]+}} = !{!"llvm.loop.vectorize.enable"}
-// CHECK-DAG: !{{[0-9]+}} = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
+// CHECK-DAG: !{{[0-9]+}} = !{!"llvm.loop.vectorize.predicate.enable"}
// CHECK-DAG: !{{[0-9]+}} = !{!"llvm.loop.vectorize.scalable.enable", i1 false}
// CHECK-DAG: !{{[0-9]+}} = !{!"llvm.loop.vectorize.width", i32 16}
// CHECK-DAG: !{{[0-9]+}} = !{!"llvm.loop.vectorize.followup_vectorized", ![[FOLLOWUP]]}
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