[clang] 738029a - Enforce single-operand form for llvm.loop.vectorize metadata (#210932)
via cfe-commits
cfe-commits at lists.llvm.org
Sun Aug 2 23:58:35 PDT 2026
Author: Madhur Amilkanthwar
Date: 2026-08-03T06:58:28Z
New Revision: 738029a68bd265cb4e65e03f63d84c027692adaa
URL: https://github.com/llvm/llvm-project/commit/738029a68bd265cb4e65e03f63d84c027692adaa
DIFF: https://github.com/llvm/llvm-project/commit/738029a68bd265cb4e65e03f63d84c027692adaa.diff
LOG: Enforce single-operand form for llvm.loop.vectorize metadata (#210932)
This patch implements Phase 2 of the RFC "Enforce Single-Operand Format
for All .enable Metadata Nodes". Please refer to RFC:
https://discourse.llvm.org/t/rfc-enforce-single-operand-format-for-all-enable-metadata-nodes/90571/
The two-operand boolean form !{!"llvm.loop.vectorize.enable", i1 0/1} is
replaced by a single-operand enable/disable pair:
!{!"llvm.loop.vectorize.enable"} ; force vectorization
!{!"llvm.loop.vectorize.disable"} ; suppress vectorization
The Verifier rejects the two-operand form, AutoUpgrade rewrites old
bitcode (including the legacy llvm.vectorizer.enable tag), and the
readers and producers across LLVM, Clang, MLIR and Polly are updated.
Added:
llvm/test/Bitcode/upgrade-loop-vectorize-enable.ll
llvm/test/Bitcode/upgrade-loop-vectorize-enable.ll.bc
llvm/test/Verifier/llvm.loop.vectorize.ll
Modified:
clang/lib/CodeGen/CGLoopInfo.cpp
clang/test/CodeGenCXX/pragma-followup_inner.cpp
clang/test/CodeGenCXX/pragma-followup_outer.cpp
clang/test/CodeGenCXX/pragma-loop-pr27643.cpp
clang/test/CodeGenCXX/pragma-loop-predicate.cpp
clang/test/CodeGenCXX/pragma-loop-safety.cpp
clang/test/CodeGenCXX/pragma-loop.cpp
clang/test/OpenMP/for_simd_codegen.cpp
clang/test/OpenMP/for_simd_scan_codegen.cpp
clang/test/OpenMP/irbuilder_safelen.cpp
clang/test/OpenMP/irbuilder_safelen_order_concurrent.cpp
clang/test/OpenMP/irbuilder_simd.cpp
clang/test/OpenMP/irbuilder_simd_aligned.cpp
clang/test/OpenMP/irbuilder_simdlen.cpp
clang/test/OpenMP/irbuilder_simdlen_safelen.cpp
clang/test/OpenMP/master_taskloop_simd_codegen.cpp
clang/test/OpenMP/parallel_for_simd_codegen.cpp
clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp
clang/test/OpenMP/simd_codegen.cpp
clang/test/OpenMP/simd_metadata.c
clang/test/OpenMP/target_simd_codegen.cpp
clang/test/OpenMP/target_teams_distribute_simd_codegen_registration.cpp
clang/test/OpenMP/target_teams_distribute_simd_codegen_registration_naming.cpp
clang/test/OpenMP/taskloop_simd_codegen.cpp
clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp
clang/test/OpenMP/teams_distribute_simd_codegen.cpp
clang/test/PCH/delayed-template-with-pragma.cpp
clang/tools/clang-fuzzer/proto-to-llvm/loop_proto_to_llvm.cpp
flang/test/Integration/ivdep.f90
flang/test/Integration/vector-always.f90
llvm/docs/LangRef.md
llvm/docs/TransformMetadata.rst
llvm/include/llvm/IR/AutoUpgrade.h
llvm/include/llvm/Transforms/Utils/LoopUtils.h
llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
llvm/lib/IR/AutoUpgrade.cpp
llvm/lib/IR/Verifier.cpp
llvm/lib/Transforms/Utils/LoopConstrainer.cpp
llvm/lib/Transforms/Utils/LoopUtils.cpp
llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
llvm/test/Bitcode/upgrade-loop-metadata.ll
llvm/test/Transforms/IRCE/add-metadata-pre-post-loops.ll
llvm/test/Transforms/IRCE/correct-loop-info.ll
llvm/test/Transforms/IRCE/loop-guarded-bounds.ll
llvm/test/Transforms/IRCE/pre_post_loops.ll
llvm/test/Transforms/IRCE/range_intersect_miscompile.ll
llvm/test/Transforms/IRCE/unsigned_comparisons_ugt.ll
llvm/test/Transforms/IRCE/unsigned_comparisons_ult.ll
llvm/test/Transforms/Inline/dilocation-loop-metadata-update.ll
llvm/test/Transforms/InstCombine/mem-par-metadata-memcpy.ll
llvm/test/Transforms/LoopIdiom/AArch64/disable-vectorize.ll
llvm/test/Transforms/LoopRotate/vect.omp.persistence.ll
llvm/test/Transforms/LoopTransformWarning/enable_and_isvectorized.ll
llvm/test/Transforms/LoopTransformWarning/optnone.ll
llvm/test/Transforms/LoopTransformWarning/vectorization-remarks-missed.ll
llvm/test/Transforms/LoopTransformWarning/vectorizer-loop-kind-unroll-warning.ll
llvm/test/Transforms/LoopUnroll/unroll-pragmas-disabled.ll
llvm/test/Transforms/LoopUnroll/vectorizer-loop-kind-remarks.ll
llvm/test/Transforms/LoopVectorize/2016-07-27-loop-vec.ll
llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll
llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
llvm/test/Transforms/LoopVectorize/AArch64/masked-op-cost.ll
llvm/test/Transforms/LoopVectorize/AArch64/masked_ldst_sme.ll
llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll
llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll
llvm/test/Transforms/LoopVectorize/AArch64/scalable-predicate-instruction.ll
llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions-tf.ll
llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll
llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-basic-vec.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-cond-inv-loads.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-extract-last-veclane.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter-cost.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-inv-store.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-large-strides.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-masked-loadstore.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-type-conv.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-extractvalue.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
llvm/test/Transforms/LoopVectorize/AArch64/unsafe-vf-hint-remark.ll
llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll
llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
llvm/test/Transforms/LoopVectorize/AArch64/vplan-native-outer-loop-wide-type.ll
llvm/test/Transforms/LoopVectorize/AArch64/widen-gep-all-indices-invariant.ll
llvm/test/Transforms/LoopVectorize/ARM/optsize_minsize.ll
llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll
llvm/test/Transforms/LoopVectorize/ARM/tail-folding-loop-hint.ll
llvm/test/Transforms/LoopVectorize/ARM/tail-folding-prefer-flag.ll
llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll
llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cond-reduction.ll
llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-intermediate-store.ll
llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-ordered-reduction.ll
llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll
llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
llvm/test/Transforms/LoopVectorize/Sparc/no-vectorize.ll
llvm/test/Transforms/LoopVectorize/VE/disable_lv.ll
llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll
llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-reduction.ll
llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-outer-loop.ll
llvm/test/Transforms/LoopVectorize/VPlan/vplan-stress-test-no-explict-vf.ll
llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls-finite.ll
llvm/test/Transforms/LoopVectorize/X86/conditional-scalar-assignment.ll
llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
llvm/test/Transforms/LoopVectorize/X86/iv-live-outs.ll
llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls-VF2-VF8.ll
llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls-finite.ll
llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls.ll
llvm/test/Transforms/LoopVectorize/X86/no_fpmath.ll
llvm/test/Transforms/LoopVectorize/X86/no_fpmath_with_hotness.ll
llvm/test/Transforms/LoopVectorize/X86/outer-loop-non-power-of-2-type.ll
llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
llvm/test/Transforms/LoopVectorize/X86/redundant-vf2-cost.ll
llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs-max-bandwidth.ll
llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
llvm/test/Transforms/LoopVectorize/X86/svml-calls-finite.ll
llvm/test/Transforms/LoopVectorize/X86/tail_folding_and_assume_safety.ll
llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.ll
llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll
llvm/test/Transforms/LoopVectorize/alias-mask.ll
llvm/test/Transforms/LoopVectorize/dbg-outer-loop-vect.ll
llvm/test/Transforms/LoopVectorize/diag-disabled-vectorization-msgs.ll
llvm/test/Transforms/LoopVectorize/disable_nonforced_enable.ll
llvm/test/Transforms/LoopVectorize/explicit_outer_detection.ll
llvm/test/Transforms/LoopVectorize/explicit_outer_nonuniform_inner.ll
llvm/test/Transforms/LoopVectorize/explicit_outer_uniform_diverg_branch.ll
llvm/test/Transforms/LoopVectorize/make-followup-loop-id.ll
llvm/test/Transforms/LoopVectorize/memdep-fold-tail.ll
llvm/test/Transforms/LoopVectorize/nested-outer-loop-vect.ll
llvm/test/Transforms/LoopVectorize/no-fold-tail-by-masking-iv-external-uses.ll
llvm/test/Transforms/LoopVectorize/no_array_bounds.ll
llvm/test/Transforms/LoopVectorize/no_array_bounds_scalable.ll
llvm/test/Transforms/LoopVectorize/no_switch.ll
llvm/test/Transforms/LoopVectorize/no_switch_disable_vectorization.ll
llvm/test/Transforms/LoopVectorize/noalias-scope-decl-outer-loop.ll
llvm/test/Transforms/LoopVectorize/non-widenable-intrinsics-outer-loop.ll
llvm/test/Transforms/LoopVectorize/optsize.ll
llvm/test/Transforms/LoopVectorize/outer-loop-atomic.ll
llvm/test/Transforms/LoopVectorize/outer-loop-inner-latch-successors.ll
llvm/test/Transforms/LoopVectorize/outer-loop-vec-phi-predecessor-order.ll
llvm/test/Transforms/LoopVectorize/outer-loop-wide-phis.ll
llvm/test/Transforms/LoopVectorize/outer_loop_contiguous.ll
llvm/test/Transforms/LoopVectorize/outer_loop_early_exit.ll
llvm/test/Transforms/LoopVectorize/outer_loop_hcfg_construction.ll
llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll
llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
llvm/test/Transforms/LoopVectorize/remove_metadata.ll
llvm/test/Transforms/LoopVectorize/runtime-check-threshold-with-force-metadata.ll
llvm/test/Transforms/LoopVectorize/runtime-check.ll
llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
llvm/test/Transforms/LoopVectorize/unsafe-vf-hint-remark.ll
llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-predicated-early-exit.ll
llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
llvm/test/Transforms/PhaseOrdering/AArch64/Oz-and-forced-vectorize.ll
llvm/test/Transforms/PhaseOrdering/X86/loop-vectorize-metadata.ll
llvm/test/Transforms/PhaseOrdering/X86/preserve-access-group.ll
llvm/test/Transforms/SROA/mem-par-metadata-sroa.ll
llvm/test/Transforms/SimplifyCFG/X86/combine-parallel-mem-md.ll
llvm/test/Verifier/llvm.loop-cu-strip-followup.ll
mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp
mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp
mlir/test/Target/LLVMIR/Import/import-failure.ll
mlir/test/Target/LLVMIR/Import/metadata-loop.ll
mlir/test/Target/LLVMIR/loop-metadata.mlir
mlir/test/Target/LLVMIR/openmp-parallel-do-simd.mlir
mlir/test/Target/LLVMIR/openmp-simd-ordered.mlir
mlir/test/Target/LLVMIR/openmp-simd-reduction-byref.mlir
mlir/test/Target/LLVMIR/openmp-simd-reduction-simple.mlir
mlir/test/Target/LLVMIR/openmp-teams-distribute-parallel-do-simd.mlir
mlir/test/Target/LLVMIR/openmp-wsloop-simd-ordered.mlir
polly/lib/CodeGen/CodeGeneration.cpp
polly/lib/CodeGen/IRBuilder.cpp
polly/test/CodeGen/MemAccess/create_arrays.ll
polly/test/CodeGen/Metadata/basic_vec_annotate.ll
polly/test/CodeGen/Metadata/fallback_vec_annotate.ll
polly/test/CodeGen/Metadata/skip_vec_annotate_fp_dist1.ll
polly/test/CodeGen/annotated_alias_scopes.ll
polly/test/CodeGen/scev-backedgetaken.ll
polly/test/ScheduleOptimizer/pattern-matching-based-opts_14.ll
Removed:
################################################################################
diff --git a/clang/lib/CodeGen/CGLoopInfo.cpp b/clang/lib/CodeGen/CGLoopInfo.cpp
index 499e2287ae84a..93857f9aaab8d 100644
--- a/clang/lib/CodeGen/CGLoopInfo.cpp
+++ b/clang/lib/CodeGen/CGLoopInfo.cpp
@@ -209,10 +209,8 @@ clang::CodeGen::LoopInfo::createLoopVectorizeMetadata(
SmallVector<Metadata *, 4> NewLoopProperties;
if (Enabled == false) {
NewLoopProperties.append(LoopProperties.begin(), LoopProperties.end());
- NewLoopProperties.push_back(
- MDNode::get(Ctx, {MDString::get(Ctx, "llvm.loop.vectorize.enable"),
- ConstantAsMetadata::get(ConstantInt::get(
- llvm::Type::getInt1Ty(Ctx), 0))}));
+ NewLoopProperties.push_back(MDNode::get(
+ Ctx, {MDString::get(Ctx, "llvm.loop.vectorize.disable")}));
LoopProperties = NewLoopProperties;
}
return createUnrollAndJamMetadata(Attrs, LoopProperties, HasUserTransforms);
@@ -279,10 +277,10 @@ clang::CodeGen::LoopInfo::createLoopVectorizeMetadata(
(Attrs.VectorizeScalable == LoopAttributes::Disable &&
Attrs.VectorizeWidth != 1)) {
VectorizeEnabled = Attrs.VectorizeEnable != LoopAttributes::Disable;
- Args.push_back(
- MDNode::get(Ctx, {MDString::get(Ctx, "llvm.loop.vectorize.enable"),
- ConstantAsMetadata::get(ConstantInt::get(
- llvm::Type::getInt1Ty(Ctx), VectorizeEnabled))}));
+ Args.push_back(MDNode::get(
+ Ctx, {MDString::get(Ctx, VectorizeEnabled
+ ? "llvm.loop.vectorize.enable"
+ : "llvm.loop.vectorize.disable")}));
}
// Apply all loop properties to the vectorized loop.
diff --git a/clang/test/CodeGenCXX/pragma-followup_inner.cpp b/clang/test/CodeGenCXX/pragma-followup_inner.cpp
index 2cf2dba5b913d..9ab8547338832 100644
--- a/clang/test/CodeGenCXX/pragma-followup_inner.cpp
+++ b/clang/test/CodeGenCXX/pragma-followup_inner.cpp
@@ -25,7 +25,7 @@ extern "C" void followup_inner(int n, int *x) {
// CHECK-DAG: ![[DISTRIBUTE_5]] = !{!"llvm.loop.distribute.enable"}
// CHECK-DAG: ![[DISTRIBUTE_FOLLOWUP_6]] = !{!"llvm.loop.distribute.followup_all", ![[PARALLEL_ACCESSES_4]], ![[VECTORIZE_8:[0-9]+]]}
-// CHECK-DAG: ![[VECTORIZE_8]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK-DAG: ![[VECTORIZE_8]] = !{!"llvm.loop.vectorize.enable"}
// CHECK-DAG: ![[OUTERLOOP_9]] = distinct !{![[OUTERLOOP_9]], [[MP:![0-9]+]], ![[UNROLLANDJAM_COUNT_10:[0-9]+]], ![[UNROLLANDJAM_FOLLOWUPINNER_11:[0-9]+]]}
// CHECK-DAG: ![[UNROLLANDJAM_COUNT_10]] = !{!"llvm.loop.unroll_and_jam.count", i32 4}
diff --git a/clang/test/CodeGenCXX/pragma-followup_outer.cpp b/clang/test/CodeGenCXX/pragma-followup_outer.cpp
index 2e907fb814b3d..c4f8cde943be7 100644
--- a/clang/test/CodeGenCXX/pragma-followup_outer.cpp
+++ b/clang/test/CodeGenCXX/pragma-followup_outer.cpp
@@ -22,7 +22,7 @@ extern "C" void followup_outer(int n, int *x) {
// CHECK-DAG: ![[DISTRIBUTE_5:[0-9]+]] = !{!"llvm.loop.distribute.enable"}
// CHECK-DAG: ![[DISTRIBUTE_FOLLOWUP_6:[0-9]+]] = !{!"llvm.loop.distribute.followup_all", [[MP]], ![[PARALLEL_ACCESSES_4:[0-9]+]], ![[VECTORIZE_8:[0-9]+]], ![[VECTORIZE_FOLLOWUP_9:[0-9]+]]}
-// CHECK-DAG: ![[VECTORIZE_8:[0-9]+]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK-DAG: ![[VECTORIZE_8:[0-9]+]] = !{!"llvm.loop.vectorize.enable"}
// CHECK-DAG: ![[VECTORIZE_FOLLOWUP_9:[0-9]+]] = !{!"llvm.loop.vectorize.followup_all", [[MP]], ![[PARALLEL_ACCESSES_4:[0-9]+]], ![[ISVECTORIZED_11:[0-9]+]], ![[UNROLLANDJAM_12:[0-9]+]], ![[UNROLLANDJAM_FOLLOWUPOUTER_13:[0-9]+]]}
// CHECK-DAG: ![[ISVECTORIZED_11:[0-9]+]] = !{!"llvm.loop.isvectorized"}
diff --git a/clang/test/CodeGenCXX/pragma-loop-pr27643.cpp b/clang/test/CodeGenCXX/pragma-loop-pr27643.cpp
index 37e29776264b6..afab64f4c6867 100644
--- a/clang/test/CodeGenCXX/pragma-loop-pr27643.cpp
+++ b/clang/test/CodeGenCXX/pragma-loop-pr27643.cpp
@@ -43,7 +43,7 @@ void loop4(int *List, int Length) {
// CHECK: ![[LOOP1]] = distinct !{![[LOOP1]], [[MP:![0-9]+]], ![[VEC_WIDTH_1:.*]], ![[FIXED_WIDTH:.*]], ![[VEC_ENABLE:.*]]}
// CHECK: ![[VEC_WIDTH_1]] = !{!"llvm.loop.vectorize.width", i32 1}
// CHECK: ![[FIXED_WIDTH]] = !{!"llvm.loop.vectorize.scalable.enable", i1 false}
-// CHECK: ![[VEC_ENABLE]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: ![[VEC_ENABLE]] = !{!"llvm.loop.vectorize.enable"}
// CHECK: ![[LOOP2]] = distinct !{![[LOOP2]], [[MP]], ![[VEC_WIDTH_2:.*]], ![[FIXED_WIDTH:.*]], ![[VEC_ENABLE]]}
// CHECK: ![[VEC_WIDTH_2]] = !{!"llvm.loop.vectorize.width", i32 2}
diff --git a/clang/test/CodeGenCXX/pragma-loop-predicate.cpp b/clang/test/CodeGenCXX/pragma-loop-predicate.cpp
index 8a25ed8de6239..421110fd9f867 100644
--- a/clang/test/CodeGenCXX/pragma-loop-predicate.cpp
+++ b/clang/test/CodeGenCXX/pragma-loop-predicate.cpp
@@ -103,7 +103,7 @@ void test9(int *List, int Length) {
// CHECK: ![[LOOP0]] = distinct !{![[LOOP0]], [[MP:![0-9]+]], [[GEN3:![0-9]+]]}
// CHECK: [[MP]] = !{!"llvm.loop.mustprogress"}
-// CHECK-NEXT: [[GEN3]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK-NEXT: [[GEN3]] = !{!"llvm.loop.vectorize.enable"}
// CHECK-NEXT: ![[LOOP1]] = distinct !{![[LOOP1]], [[MP]], [[GEN6:![0-9]+]], [[GEN3]]}
// CHECK-NEXT: [[GEN6]] = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
diff --git a/clang/test/CodeGenCXX/pragma-loop-safety.cpp b/clang/test/CodeGenCXX/pragma-loop-safety.cpp
index db1b6769e0514..e2a7a124890a6 100644
--- a/clang/test/CodeGenCXX/pragma-loop-safety.cpp
+++ b/clang/test/CodeGenCXX/pragma-loop-safety.cpp
@@ -51,7 +51,7 @@ void interleave_test(int *List, int Length) {
// CHECK: ![[PARALLEL_ACCESSES_7]] = !{!"llvm.loop.parallel_accesses", ![[ACCESS_GROUP_2]]}
// CHECK: ![[UNROLL_DISABLE]] = !{!"llvm.loop.unroll.disable"}
// CHECK: ![[INTERLEAVE_1]] = !{!"llvm.loop.interleave.count", i32 1}
-// CHECK: ![[INTENABLE_1]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: ![[INTENABLE_1]] = !{!"llvm.loop.vectorize.enable"}
// CHECK: ![[ACCESS_GROUP_8]] = distinct !{}
// CHECK: ![[LOOP2_HINTS]] = distinct !{![[LOOP2_HINTS]], [[MP]], ![[PARALLEL_ACCESSES_11:[0-9]+]], ![[UNROLL_DISABLE]], ![[WIDTH_1:[0-9]+]], ![[INTENABLE_1]]}
// CHECK: ![[PARALLEL_ACCESSES_11]] = !{!"llvm.loop.parallel_accesses", ![[ACCESS_GROUP_8]]}
diff --git a/clang/test/CodeGenCXX/pragma-loop.cpp b/clang/test/CodeGenCXX/pragma-loop.cpp
index f9106725ad99d..68ab7b51ea833 100644
--- a/clang/test/CodeGenCXX/pragma-loop.cpp
+++ b/clang/test/CodeGenCXX/pragma-loop.cpp
@@ -256,7 +256,7 @@ void for_test_interleave_vectorize_disable_unroll(int *List, int Length) {
// CHECK-DAG: ![[INTERLEAVE_10:[0-9]+]] = !{!"llvm.loop.interleave.count", i32 10}
// CHECK-DAG: ![[INTERLEAVE_16:[0-9]+]] = !{!"llvm.loop.interleave.count", i32 16}
-// CHECK-DAG: ![[VECTORIZE_ENABLE:[0-9]+]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK-DAG: ![[VECTORIZE_ENABLE:[0-9]+]] = !{!"llvm.loop.vectorize.enable"}
// CHECK-DAG: ![[FIXED_VEC:[0-9]+]] = !{!"llvm.loop.vectorize.scalable.enable", i1 false}
// CHECK-DAG: ![[SCALABLE_VEC:[0-9]+]] = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
// CHECK-DAG: ![[WIDTH_1:[0-9]+]] = !{!"llvm.loop.vectorize.width", i32 1}
diff --git a/clang/test/OpenMP/for_simd_codegen.cpp b/clang/test/OpenMP/for_simd_codegen.cpp
index 1ac95e8943640..ae6161d03978d 100644
--- a/clang/test/OpenMP/for_simd_codegen.cpp
+++ b/clang/test/OpenMP/for_simd_codegen.cpp
@@ -802,10 +802,10 @@ void parallel_simd(float *a) {
}
// TERM_DEBUG: !{{[0-9]+}} = !DILocation(line: [[@LINE-11]],
// TERM_DEBUG-NOT: line: 0,
-// OMP45-NOT: !"llvm.loop.vectorize.enable", i1 false
+// OMP45-NOT: !"llvm.loop.vectorize.disable"
// CHECK-DAG: ![[SIMD_LOOP]] = distinct !{![[SIMD_LOOP]], {{.*}}![[VECT_LOOP:[^,]+]]}
-// CHECK-DAG: ![[VECT_LOOP]] = !{!"llvm.loop.vectorize.enable", i1 true}
-// OMP45-NOT: !"llvm.loop.vectorize.enable", i1 false
+// CHECK-DAG: ![[VECT_LOOP]] = !{!"llvm.loop.vectorize.enable"}
+// OMP45-NOT: !"llvm.loop.vectorize.disable"
// OMP50-DAG: ![[NOSIMD_LOOP]] = distinct !{![[NOSIMD_LOOP]], {{.*}}![[NOVECT_LOOP:[^,]+]]}
-// OMP50-DAG: ![[NOVECT_LOOP]] = !{!"llvm.loop.vectorize.enable", i1 false}
+// OMP50-DAG: ![[NOVECT_LOOP]] = !{!"llvm.loop.vectorize.disable"}
#endif // HEADER
diff --git a/clang/test/OpenMP/for_simd_scan_codegen.cpp b/clang/test/OpenMP/for_simd_scan_codegen.cpp
index 829f2656042fb..9ab62f8a682b2 100644
--- a/clang/test/OpenMP/for_simd_scan_codegen.cpp
+++ b/clang/test/OpenMP/for_simd_scan_codegen.cpp
@@ -300,5 +300,5 @@ void baz(int n) {
}
#endif
-// CHECK: !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: !{!"llvm.loop.vectorize.enable"}
diff --git a/clang/test/OpenMP/irbuilder_safelen.cpp b/clang/test/OpenMP/irbuilder_safelen.cpp
index 6a4266f9646a7..3090eafa6a508 100644
--- a/clang/test/OpenMP/irbuilder_safelen.cpp
+++ b/clang/test/OpenMP/irbuilder_safelen.cpp
@@ -250,7 +250,7 @@ void simple(float *a, float *b, int *c) {
// CHECK: [[META0:![0-9]+]] = !{i32 7, !"openmp", i32 45}
// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
// CHECK: [[LOOP2]] = distinct !{[[LOOP2]], [[META3:![0-9]+]], [[META4:![0-9]+]]}
-// CHECK: [[META3]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: [[META3]] = !{!"llvm.loop.vectorize.enable"}
// CHECK: [[META4]] = !{!"llvm.loop.vectorize.width", i32 3}
// CHECK: [[ACC_GRP5]] = distinct !{}
// CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META7:![0-9]+]], [[META3]]}
diff --git a/clang/test/OpenMP/irbuilder_safelen_order_concurrent.cpp b/clang/test/OpenMP/irbuilder_safelen_order_concurrent.cpp
index 210978fc6069c..215b37e4bbb5f 100644
--- a/clang/test/OpenMP/irbuilder_safelen_order_concurrent.cpp
+++ b/clang/test/OpenMP/irbuilder_safelen_order_concurrent.cpp
@@ -252,7 +252,7 @@ void simple(float *a, float *b, int *c) {
// CHECK: [[ACC_GRP2]] = distinct !{}
// CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META4:![0-9]+]], [[META5:![0-9]+]], [[META6:![0-9]+]]}
// CHECK: [[META4]] = !{!"llvm.loop.parallel_accesses", [[ACC_GRP2]]}
-// CHECK: [[META5]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: [[META5]] = !{!"llvm.loop.vectorize.enable"}
// CHECK: [[META6]] = !{!"llvm.loop.vectorize.width", i32 3}
// CHECK: [[ACC_GRP7]] = distinct !{}
// CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META9:![0-9]+]], [[META5]]}
diff --git a/clang/test/OpenMP/irbuilder_simd.cpp b/clang/test/OpenMP/irbuilder_simd.cpp
index 9c36e4ab97182..03f92d8117d45 100644
--- a/clang/test/OpenMP/irbuilder_simd.cpp
+++ b/clang/test/OpenMP/irbuilder_simd.cpp
@@ -65,7 +65,7 @@ void simple(float *a, float *b, int *c) {
// CHECK: ![[META3:[0-9]+]] = distinct !{}
// CHECK-NEXT: ![[META4]] = distinct !{![[META4]], ![[META5:[0-9]+]], ![[META6:[0-9]+]]}
// CHECK-NEXT: ![[META5]] = !{!"llvm.loop.parallel_accesses", ![[META3]]}
-// CHECK-NEXT: ![[META6]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK-NEXT: ![[META6]] = !{!"llvm.loop.vectorize.enable"}
// CHECK-NEXT: ![[META7:[0-9]+]] = distinct !{}
// CHECK-NEXT: ![[META8]] = distinct !{![[META8]], ![[META9:[0-9]+]], ![[META6]]}
// CHECK-NEXT: ![[META9]] = !{!"llvm.loop.parallel_accesses", ![[META7]]}
diff --git a/clang/test/OpenMP/irbuilder_simd_aligned.cpp b/clang/test/OpenMP/irbuilder_simd_aligned.cpp
index b5ce43c8ea6a9..bb121036b4f0c 100644
--- a/clang/test/OpenMP/irbuilder_simd_aligned.cpp
+++ b/clang/test/OpenMP/irbuilder_simd_aligned.cpp
@@ -293,7 +293,7 @@ void simple(float *a, float *b, int *c) {
// CHECK: [[ACC_GRP4]] = distinct !{}
// CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META6:![0-9]+]], [[META7:![0-9]+]]}
// CHECK: [[META6]] = !{!"llvm.loop.parallel_accesses", [[ACC_GRP4]]}
-// CHECK: [[META7]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: [[META7]] = !{!"llvm.loop.vectorize.enable"}
// CHECK: [[ACC_GRP8]] = distinct !{}
// CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META10:![0-9]+]], [[META7]]}
// CHECK: [[META10]] = !{!"llvm.loop.parallel_accesses", [[ACC_GRP8]]}
diff --git a/clang/test/OpenMP/irbuilder_simdlen.cpp b/clang/test/OpenMP/irbuilder_simdlen.cpp
index f6c26923851d0..9a7e8d5332ae0 100644
--- a/clang/test/OpenMP/irbuilder_simdlen.cpp
+++ b/clang/test/OpenMP/irbuilder_simdlen.cpp
@@ -252,7 +252,7 @@ void simple(float *a, float *b, int *c) {
// CHECK: [[ACC_GRP2]] = distinct !{}
// CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META4:![0-9]+]], [[META5:![0-9]+]], [[META6:![0-9]+]]}
// CHECK: [[META4]] = !{!"llvm.loop.parallel_accesses", [[ACC_GRP2]]}
-// CHECK: [[META5]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: [[META5]] = !{!"llvm.loop.vectorize.enable"}
// CHECK: [[META6]] = !{!"llvm.loop.vectorize.width", i32 3}
// CHECK: [[ACC_GRP7]] = distinct !{}
// CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META9:![0-9]+]], [[META5]]}
diff --git a/clang/test/OpenMP/irbuilder_simdlen_safelen.cpp b/clang/test/OpenMP/irbuilder_simdlen_safelen.cpp
index e46d5dde841b3..bb35f9341ded4 100644
--- a/clang/test/OpenMP/irbuilder_simdlen_safelen.cpp
+++ b/clang/test/OpenMP/irbuilder_simdlen_safelen.cpp
@@ -250,7 +250,7 @@ void simple(float *a, float *b, int *c) {
// CHECK: [[META0:![0-9]+]] = !{i32 7, !"openmp", i32 45}
// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
// CHECK: [[LOOP2]] = distinct !{[[LOOP2]], [[META3:![0-9]+]], [[META4:![0-9]+]]}
-// CHECK: [[META3]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: [[META3]] = !{!"llvm.loop.vectorize.enable"}
// CHECK: [[META4]] = !{!"llvm.loop.vectorize.width", i32 2}
// CHECK: [[ACC_GRP5]] = distinct !{}
// CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META7:![0-9]+]], [[META3]]}
diff --git a/clang/test/OpenMP/master_taskloop_simd_codegen.cpp b/clang/test/OpenMP/master_taskloop_simd_codegen.cpp
index d78d193e2edd1..f1eae642b613c 100644
--- a/clang/test/OpenMP/master_taskloop_simd_codegen.cpp
+++ b/clang/test/OpenMP/master_taskloop_simd_codegen.cpp
@@ -238,10 +238,10 @@ struct S {
// CHECK: br label %{{.*}}!llvm.loop
// CHECK: ret i32 0
-// OMP45-NOT: !{!"llvm.loop.vectorize.enable", i1 false}
-// CHECK-DAG: !{!"llvm.loop.vectorize.enable", i1 true}
-// OMP50-DAG: !{!"llvm.loop.vectorize.enable", i1 false}
-// OMP45-NOT: !{!"llvm.loop.vectorize.enable", i1 false}
+// OMP45-NOT: !{!"llvm.loop.vectorize.disable"}
+// CHECK-DAG: !{!"llvm.loop.vectorize.enable"}
+// OMP50-DAG: !{!"llvm.loop.vectorize.disable"}
+// OMP45-NOT: !{!"llvm.loop.vectorize.disable"}
// CHECK-DAG: !{!"llvm.loop.vectorize.width", i32 4}
// CHECK-DAG: !{!"llvm.loop.vectorize.width", i32 32}
// CHECK-DAG: !{!"llvm.loop.vectorize.width", i32 8}
diff --git a/clang/test/OpenMP/parallel_for_simd_codegen.cpp b/clang/test/OpenMP/parallel_for_simd_codegen.cpp
index 40af7069bbf7d..cc8cab706975a 100644
--- a/clang/test/OpenMP/parallel_for_simd_codegen.cpp
+++ b/clang/test/OpenMP/parallel_for_simd_codegen.cpp
@@ -798,16 +798,16 @@ for (int i = 0; i < 10; ++i);
// OMP50: omp.inner.for.body:
// OMP50: %{{[0-9]+}} = atomicrmw add ptr %{{[0-9]+}}, i32 1 monotonic, align 4, !llvm.access.group !{{[0-9]+}}
-// OMP45-NOT: !{!"llvm.loop.vectorize.enable", i1 false}
+// OMP45-NOT: !{!"llvm.loop.vectorize.disable"}
// OMP45-DAG: ![[VECT]] = distinct !{![[VECT]], ![[PA:.+]], ![[VM:.+]]}
// OMP45-DAG: ![[PA]] = !{!"llvm.loop.parallel_accesses", !{{.+}}}
-// OMP45-DAG: ![[VM]] = !{!"llvm.loop.vectorize.enable", i1 true}
-// OMP45-NOT: !{!"llvm.loop.vectorize.enable", i1 false}
+// OMP45-DAG: ![[VM]] = !{!"llvm.loop.vectorize.enable"}
+// OMP45-NOT: !{!"llvm.loop.vectorize.disable"}
// OMP50-DAG: ![[VECT]] = distinct !{![[VECT]], ![[PA:.+]], ![[VM:.+]]}
// OMP50-DAG ![[PA]] = !{!"llvm.loop.parallel_accesses", !{{.+}}}
-// OMP50-DAG: ![[VM]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// OMP50-DAG: ![[VM]] = !{!"llvm.loop.vectorize.enable"}
// OMP50-DAG: ![[NOVECT]] = distinct !{![[NOVECT]], ![[NOVM:.+]]}
-// OMP50-DAG: ![[NOVM]] = !{!"llvm.loop.vectorize.enable", i1 false}
+// OMP50-DAG: ![[NOVM]] = !{!"llvm.loop.vectorize.disable"}
// TERM_DEBUG-LABEL: bar
int bar() { extern void mayThrow(); mayThrow(); return 0; };
diff --git a/clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp b/clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp
index cac997753d480..e3810c27163a4 100644
--- a/clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp
+++ b/clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp
@@ -299,7 +299,7 @@ void baz(int n) {
}
}
-// CHECK: !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: !{!"llvm.loop.vectorize.enable"}
#endif
diff --git a/clang/test/OpenMP/simd_codegen.cpp b/clang/test/OpenMP/simd_codegen.cpp
index b96e4213e8e0e..ee8d709ba47fe 100644
--- a/clang/test/OpenMP/simd_codegen.cpp
+++ b/clang/test/OpenMP/simd_codegen.cpp
@@ -861,7 +861,7 @@ S8 s8(0);
// TERM_DEBUG-NOT: line: 0,
// TERM_DEBUG: distinct !DISubprogram(linkageName: "_GLOBAL__sub_I_simd_codegen.cpp",
-// OMP5-DAG: ![[NOVECT:.+]] = !{!"llvm.loop.vectorize.enable", i1 false}
+// OMP5-DAG: ![[NOVECT:.+]] = !{!"llvm.loop.vectorize.disable"}
// OMP5-DAG: ![[DISABLE_VECT]] = distinct !{{.*}}![[NOVECT]]{{[,}]}}
#endif // HEADER
diff --git a/clang/test/OpenMP/simd_metadata.c b/clang/test/OpenMP/simd_metadata.c
index 83bcbf6deefe2..6fc4c401135f2 100644
--- a/clang/test/OpenMP/simd_metadata.c
+++ b/clang/test/OpenMP/simd_metadata.c
@@ -109,7 +109,7 @@ void h3(float *c, float *a, float *b, int size)
// Metadata for h1:
// CHECK: [[LOOP_H1_HEADER:![0-9]+]] = distinct !{[[LOOP_H1_HEADER]], [[LOOP_WIDTH_16:![0-9]+]], [[LOOP_VEC_ENABLE:![0-9]+]]}
// CHECK: [[LOOP_WIDTH_16]] = !{!"llvm.loop.vectorize.width", i32 16}
-// CHECK: [[LOOP_VEC_ENABLE]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: [[LOOP_VEC_ENABLE]] = !{!"llvm.loop.vectorize.enable"}
// CHECK: [[LOOP_H1_HEADER:![0-9]+]] = distinct !{[[LOOP_H1_HEADER]], [[LOOP_WIDTH_8:![0-9]+]], [[LOOP_VEC_ENABLE]]}
// CHECK: [[LOOP_WIDTH_8]] = !{!"llvm.loop.vectorize.width", i32 8}
// CHECK: ![[ACCESS_GROUP_7]] = distinct !{}
diff --git a/clang/test/OpenMP/target_simd_codegen.cpp b/clang/test/OpenMP/target_simd_codegen.cpp
index 0c2dde23f6c46..59284c201bb30 100644
--- a/clang/test/OpenMP/target_simd_codegen.cpp
+++ b/clang/test/OpenMP/target_simd_codegen.cpp
@@ -702,9 +702,9 @@ int bar(int n){
// Store captures in the context.
// CHECK-DAG: [[REF_B:%.+]] = load ptr, ptr [[LOCAL_B]],
-// OMP45-NOT: !{!"llvm.loop.vectorize.enable", i1 false}
-// TOMP45-NOT: !{!"llvm.loop.vectorize.enable", i1 false}
-// OMP51: !{!"llvm.loop.vectorize.enable", i1 false}
-// TOMP51: !{!"llvm.loop.vectorize.enable", i1 false}
+// OMP45-NOT: !{!"llvm.loop.vectorize.disable"}
+// TOMP45-NOT: !{!"llvm.loop.vectorize.disable"}
+// OMP51: !{!"llvm.loop.vectorize.disable"}
+// TOMP51: !{!"llvm.loop.vectorize.disable"}
#endif
diff --git a/clang/test/OpenMP/target_teams_distribute_simd_codegen_registration.cpp b/clang/test/OpenMP/target_teams_distribute_simd_codegen_registration.cpp
index 42e8377bd22dd..fd2d0d0c18737 100644
--- a/clang/test/OpenMP/target_teams_distribute_simd_codegen_registration.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_simd_codegen_registration.cpp
@@ -455,7 +455,7 @@ int bar(int a){
// TCHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], !"_ZN2STILi100EE3fooEv", i32 {{[0-9]+}}, i32 0, i32 {{[0-9]+}}}
// TCHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], !"_ZN2SCC1Ev", i32 {{[0-9]+}}, i32 0, i32 {{[0-9]+}}}
-// TCHECK-DAG: !{!"llvm.loop.vectorize.enable", i1 true}
-// CHECK-DAG: !{!"llvm.loop.vectorize.enable", i1 true}
+// TCHECK-DAG: !{!"llvm.loop.vectorize.enable"}
+// CHECK-DAG: !{!"llvm.loop.vectorize.enable"}
#endif
diff --git a/clang/test/OpenMP/target_teams_distribute_simd_codegen_registration_naming.cpp b/clang/test/OpenMP/target_teams_distribute_simd_codegen_registration_naming.cpp
index b63f0b6caeee2..c169d4a556bf0 100644
--- a/clang/test/OpenMP/target_teams_distribute_simd_codegen_registration_naming.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_simd_codegen_registration_naming.cpp
@@ -82,6 +82,6 @@ int nested(int a){
// TCHECK-DAG: = !{i32 0, i32 {{-?[0-9]+}}, i32 {{-?[0-9]+}}, !"[[NNAME]]", i32 [[T1L]], i32 0, i32 {{[0-9]+}}}
// TCHECK-DAG: = !{i32 0, i32 {{-?[0-9]+}}, i32 {{-?[0-9]+}}, !"[[NNAME]]", i32 [[T2L]], i32 0, i32 {{[0-9]+}}}
-// CHECK-DAG: !{!"llvm.loop.vectorize.enable", i1 true}
-// TCHECK-DAG: !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK-DAG: !{!"llvm.loop.vectorize.enable"}
+// TCHECK-DAG: !{!"llvm.loop.vectorize.enable"}
#endif
diff --git a/clang/test/OpenMP/taskloop_simd_codegen.cpp b/clang/test/OpenMP/taskloop_simd_codegen.cpp
index ab34ff66e5c7a..df2df9f609a57 100644
--- a/clang/test/OpenMP/taskloop_simd_codegen.cpp
+++ b/clang/test/OpenMP/taskloop_simd_codegen.cpp
@@ -208,7 +208,7 @@ struct S {
// CHECK: br label %{{.*}}!llvm.loop
// CHECK: ret i32 0
-// CHECK: !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: !{!"llvm.loop.vectorize.enable"}
// CHECK: !{!"llvm.loop.vectorize.width", i32 4}
// CHECK: !{!"llvm.loop.vectorize.width", i32 32}
// CHECK: !{!"llvm.loop.vectorize.width", i32 8}
diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp
index 365f11cfac5c6..688849851aa4d 100644
--- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp
+++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp
@@ -46,7 +46,7 @@ int teams_template_struct(void) {
}
-// CK4: !{!"llvm.loop.vectorize.enable", i1 true}
+// CK4: !{!"llvm.loop.vectorize.enable"}
#endif // CK1
@@ -103,7 +103,7 @@ int main (int argc, char **argv) {
// discard loop variables not needed here
-// CK4: !{!"llvm.loop.vectorize.enable", i1 true}
+// CK4: !{!"llvm.loop.vectorize.enable"}
#endif // CK2
#endif // #ifndef HEADER
diff --git a/clang/test/OpenMP/teams_distribute_simd_codegen.cpp b/clang/test/OpenMP/teams_distribute_simd_codegen.cpp
index d5000a5b18a53..c2234296a059f 100644
--- a/clang/test/OpenMP/teams_distribute_simd_codegen.cpp
+++ b/clang/test/OpenMP/teams_distribute_simd_codegen.cpp
@@ -207,7 +207,7 @@ int main (int argc, char **argv) {
-// OMP5_50-DAG: !{!"llvm.loop.vectorize.enable", i1 false}
+// OMP5_50-DAG: !{!"llvm.loop.vectorize.disable"}
#endif // CK4
#endif
// CHECK1-LABEL: define {{[^@]+}}@_Z21teams_argument_globali
diff --git a/clang/test/PCH/delayed-template-with-pragma.cpp b/clang/test/PCH/delayed-template-with-pragma.cpp
index e54388456245a..124d0e5db99e8 100644
--- a/clang/test/PCH/delayed-template-with-pragma.cpp
+++ b/clang/test/PCH/delayed-template-with-pragma.cpp
@@ -27,7 +27,7 @@ void a(T t) {
// CHECK: [[LOOP1B]] = !{!"llvm.loop.unroll.count", i32 4}
// CHECK: [[LOOP2]] = distinct !{[[LOOP2]], [[LOOP2A:!.*]], [[LOOP2B:!.*]]}
// CHECK: [[LOOP2A]] = !{!"llvm.loop.parallel_accesses", [[LOOP2C:!.*]]}
-// CHECK: [[LOOP2B]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: [[LOOP2B]] = !{!"llvm.loop.vectorize.enable"}
// expected-warning at 17 {{unused variable 'zz'}}
void foo()
{
diff --git a/clang/tools/clang-fuzzer/proto-to-llvm/loop_proto_to_llvm.cpp b/clang/tools/clang-fuzzer/proto-to-llvm/loop_proto_to_llvm.cpp
index 409570c3f0fa0..d37726b74b48e 100644
--- a/clang/tools/clang-fuzzer/proto-to-llvm/loop_proto_to_llvm.cpp
+++ b/clang/tools/clang-fuzzer/proto-to-llvm/loop_proto_to_llvm.cpp
@@ -157,12 +157,13 @@ void NestedLoopToString(std::ostream &os, const LoopFunction &x) {
}
os << "%i_ct_new = add i64 %inner_ct, 1\n"
<< "%jmp_inner = icmp eq i64 %i_ct_new, %s\n"
- << "br i1 %jmp_inner, label %outer_loop, label %inner_loop, !llvm.loop !0\n"
+ << "br i1 %jmp_inner, label %outer_loop, label %inner_loop, !llvm.loop "
+ "!0\n"
<< "end:\n"
<< "ret void\n"
<< "}\n"
<< "!0 = distinct !{!0, !1, !2}\n"
- << "!1 = !{!\"llvm.loop.vectorize.enable\", i1 true}\n"
+ << "!1 = !{!\"llvm.loop.vectorize.enable\"}\n"
<< "!2 = !{!\"llvm.loop.vectorize.width\", i32 " << kArraySize << "}\n";
}
void SingleLoopToString(std::ostream &os, const LoopFunction &x) {
@@ -176,12 +177,11 @@ void SingleLoopToString(std::ostream &os, const LoopFunction &x) {
<< "ret void\n"
<< "loop:\n"
<< "%outer_ct = phi i64 [ %ctnew, %loop ], [ 0, %start ]\n"
- << x.outer_statements()
- << "%ctnew = add i64 %outer_ct, 1\n"
+ << x.outer_statements() << "%ctnew = add i64 %outer_ct, 1\n"
<< "%j = icmp eq i64 %ctnew, %s\n"
<< "br i1 %j, label %end, label %loop, !llvm.loop !0\n}\n"
<< "!0 = distinct !{!0, !1, !2}\n"
- << "!1 = !{!\"llvm.loop.vectorize.enable\", i1 true}\n"
+ << "!1 = !{!\"llvm.loop.vectorize.enable\"}\n"
<< "!2 = !{!\"llvm.loop.vectorize.width\", i32 " << kArraySize << "}\n";
}
std::ostream &operator<<(std::ostream &os, const LoopFunction &x) {
diff --git a/flang/test/Integration/ivdep.f90 b/flang/test/Integration/ivdep.f90
index 9882fe148262f..a53d46ed446de 100644
--- a/flang/test/Integration/ivdep.f90
+++ b/flang/test/Integration/ivdep.f90
@@ -120,5 +120,5 @@ end subroutine ivdep_test4
! CHECK: ![[PARALLEL_ACCESSES2]] = !{!"llvm.loop.parallel_accesses", [[DISTRINCT2]]}
! CHECK: [[DISTRINCT3:.*]] = distinct !{}
! CHECK: ![[ANNOTATION3]] = distinct !{![[ANNOTATION3]], ![[VECTORIZE:.*]], ![[PARALLEL_ACCESSES3:.*]]}
-! CHECK: ![[VECTORIZE]] = !{!"llvm.loop.vectorize.enable", i1 true}
+! CHECK: ![[VECTORIZE]] = !{!"llvm.loop.vectorize.enable"}
! CHECK: ![[PARALLEL_ACCESSES3]] = !{!"llvm.loop.parallel_accesses", [[DISTRINCT3]]}
diff --git a/flang/test/Integration/vector-always.f90 b/flang/test/Integration/vector-always.f90
index 1d8aad97bde70..5634a6a13b63f 100644
--- a/flang/test/Integration/vector-always.f90
+++ b/flang/test/Integration/vector-always.f90
@@ -25,6 +25,6 @@ subroutine no_vector
end subroutine no_vector
! CHECK: ![[ANNOTATION]] = distinct !{![[ANNOTATION]], ![[VECTORIZE:.*]]}
-! CHECK: ![[VECTORIZE]] = !{!"llvm.loop.vectorize.enable", i1 true}
+! CHECK: ![[VECTORIZE]] = !{!"llvm.loop.vectorize.enable"}
! CHECK: ![[ANNOTATION2]] = distinct !{![[ANNOTATION2]], ![[VECTORIZE2:.*]]}
-! CHECK: ![[VECTORIZE2]] = !{!"llvm.loop.vectorize.enable", i1 false}
+! CHECK: ![[VECTORIZE2]] = !{!"llvm.loop.vectorize.disable"}
diff --git a/llvm/docs/LangRef.md b/llvm/docs/LangRef.md
index 3735039b99977..1fc6ea1a7ed9d 100644
--- a/llvm/docs/LangRef.md
+++ b/llvm/docs/LangRef.md
@@ -8059,14 +8059,12 @@ then the interleave count will be determined automatically.
#### '`llvm.loop.vectorize.enable`' Metadata
-This metadata selectively enables or disables vectorization for the loop. The
-first operand is the string `llvm.loop.vectorize.enable` and the second operand
-is a bit. If the bit operand value is 1 vectorization is enabled. A value of
-0 disables vectorization:
+This metadata selectively enables or disables vectorization for the loop. Each
+node has a single operand containing the name string:
```llvm
-!0 = !{!"llvm.loop.vectorize.enable", i1 0}
-!1 = !{!"llvm.loop.vectorize.enable", i1 1}
+!0 = !{!"llvm.loop.vectorize.enable"}
+!1 = !{!"llvm.loop.vectorize.disable"}
```
#### '`llvm.loop.vectorize.predicate.enable`' Metadata
diff --git a/llvm/docs/TransformMetadata.rst b/llvm/docs/TransformMetadata.rst
index 52d64aa1bfec7..42ba63981c468 100644
--- a/llvm/docs/TransformMetadata.rst
+++ b/llvm/docs/TransformMetadata.rst
@@ -77,7 +77,7 @@ vectorized, for instance being unrolled.
br i1 %exitcond, label %for.exit, label %for.header, !llvm.loop !0
...
!0 = distinct !{!0, !1, !2}
- !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+ !1 = !{!"llvm.loop.vectorize.enable"}
!2 = !{!"llvm.loop.disable_nonforced"}
After a transformation is applied, follow-up attributes are set on the
@@ -95,7 +95,7 @@ then unrolled.
.. code-block:: llvm
!0 = distinct !{!0, !1, !2, !3}
- !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+ !1 = !{!"llvm.loop.vectorize.enable"}
!2 = !{!"llvm.loop.disable_nonforced"}
!3 = !{!"llvm.loop.vectorize.followup_vectorized", !{"llvm.loop.unroll.enable"}}
@@ -128,7 +128,7 @@ Loop Vectorization and Interleaving
Loop vectorization and interleaving is interpreted as a single
transformation. It is interpreted as forced if
-``!{"llvm.loop.vectorize.enable", i1 true}`` is set.
+``!{"llvm.loop.vectorize.enable"}`` is set.
Assuming the pre-vectorization loop is
diff --git a/llvm/include/llvm/IR/AutoUpgrade.h b/llvm/include/llvm/IR/AutoUpgrade.h
index 423fea4205a80..12aeb2793f705 100644
--- a/llvm/include/llvm/IR/AutoUpgrade.h
+++ b/llvm/include/llvm/IR/AutoUpgrade.h
@@ -112,12 +112,14 @@ namespace llvm {
/// Check whether a string looks like an old loop attachment tag.
inline bool mayBeOldLoopAttachmentTag(StringRef Name) {
- // "llvm.loop.distribute.enable" is intentionally included: the current
- // single-operand form shares the tag with the removed two-operand form
- // (!{!"llvm.loop.distribute.enable", i1 X}), so we can only decide by
- // inspecting the operands, which happens in upgradeLoopArgument().
+ // "llvm.loop.distribute.enable" and "llvm.loop.vectorize.enable" are
+ // intentionally included: the current single-operand form shares the tag
+ // with the removed two-operand form (!{!"...", i1 X}), so we can only
+ // decide by inspecting the operands, which happens in
+ // upgradeLoopArgument().
return Name.starts_with("llvm.vectorizer.") ||
- Name == "llvm.loop.distribute.enable";
+ Name == "llvm.loop.distribute.enable" ||
+ Name == "llvm.loop.vectorize.enable";
}
/// Upgrade the loop attachment metadata node.
diff --git a/llvm/include/llvm/Transforms/Utils/LoopUtils.h b/llvm/include/llvm/Transforms/Utils/LoopUtils.h
index 9fa675856ba3f..2cca26af577e1 100644
--- a/llvm/include/llvm/Transforms/Utils/LoopUtils.h
+++ b/llvm/include/llvm/Transforms/Utils/LoopUtils.h
@@ -328,6 +328,11 @@ LLVM_ABI TransformationMode hasLICMVersioningTransformation(const Loop *L);
LLVM_ABI void addStringMetadataToLoop(Loop *TheLoop, const char *MDString,
unsigned V = 0);
+/// Add a single-operand (name-only) node \p MDString to the loop metadata of
+/// \p TheLoop, keeping other values intact. If a name-only node with the same
+/// string is already present, this is a no-op.
+LLVM_ABI void addStringMetadataToLoop(Loop *TheLoop, StringRef MDString);
+
/// Return either:
/// - \c std::nullopt, if the implementation is unable to handle the loop form
/// of \p L (e.g., \p L must have a latch block that controls the loop exit).
diff --git a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
index 9704f68df4ec7..9a49f4124da5e 100644
--- a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+++ b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
@@ -7519,10 +7519,8 @@ void OpenMPIRBuilder::applySimd(CanonicalLoopInfo *CanonicalLoop,
// Use the above access group metadata to create loop level
// metadata, which should be distinct for each loop.
- ConstantAsMetadata *BoolConst =
- ConstantAsMetadata::get(ConstantInt::getTrue(Type::getInt1Ty(Ctx)));
- LoopMDList.push_back(MDNode::get(
- Ctx, {MDString::get(Ctx, "llvm.loop.vectorize.enable"), BoolConst}));
+ LoopMDList.push_back(
+ MDNode::get(Ctx, {MDString::get(Ctx, "llvm.loop.vectorize.enable")}));
if (Simdlen || Safelen) {
// If both simdlen and safelen clauses are specified, the value of the
diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp
index 4502759417c5a..f2a2ddbfc2e31 100644
--- a/llvm/lib/IR/AutoUpgrade.cpp
+++ b/llvm/lib/IR/AutoUpgrade.cpp
@@ -7023,6 +7023,27 @@ static bool isOldDistributeEnable(const MDTuple *T) {
return mdconst::hasa<ConstantInt>(T->getOperand(1));
}
+/// Old two-operand form: !{!"llvm.loop.vectorize.enable", i1 X}. The new
+/// single-operand form uses "llvm.loop.vectorize.enable" for X = true and
+/// "llvm.loop.vectorize.disable" for X = false.
+static bool isOldVectorizeEnable(const MDTuple *T) {
+ if (T->getNumOperands() != 2)
+ return false;
+ auto *Tag = dyn_cast_or_null<MDString>(T->getOperand(0));
+ if (!Tag || Tag->getString() != "llvm.loop.vectorize.enable")
+ return false;
+ return mdconst::hasa<ConstantInt>(T->getOperand(1));
+}
+
+/// Build the single-operand vectorize enable/disable node that replaces a
+/// boolean operand: nonzero -> enable, zero -> disable.
+static Metadata *makeVectorizeEnableNode(LLVMContext &C, const MDOperand &Op) {
+ bool Enable = !mdconst::extract<ConstantInt>(Op)->isZero();
+ return MDTuple::get(
+ C, {MDString::get(C, Enable ? "llvm.loop.vectorize.enable"
+ : "llvm.loop.vectorize.disable")});
+}
+
static bool isOldLoopArgument(Metadata *MD) {
auto *T = dyn_cast_or_null<MDTuple>(MD);
if (!T)
@@ -7034,7 +7055,7 @@ static bool isOldLoopArgument(Metadata *MD) {
return false;
if (S->getString().starts_with("llvm.vectorizer."))
return true;
- return isOldDistributeEnable(T);
+ return isOldDistributeEnable(T) || isOldVectorizeEnable(T);
}
static MDString *upgradeLoopTag(LLVMContext &C, StringRef OldTag) {
@@ -7069,13 +7090,26 @@ static Metadata *upgradeLoopArgument(Metadata *MD) {
: "llvm.loop.distribute.disable")});
}
+ // Rewrite the modern two-operand vectorize.enable form to the single-operand
+ // enable/disable pair.
+ if (isOldVectorizeEnable(T))
+ return makeVectorizeEnableNode(C, T->getOperand(1));
+
if (!OldTag->getString().starts_with("llvm.vectorizer."))
return MD;
// This has an old tag. Upgrade it.
+ MDString *NewTag = upgradeLoopTag(C, OldTag->getString());
+
+ // The legacy !{!"llvm.vectorizer.enable", i1 X} maps onto the single-operand
+ // vectorize.enable/disable pair, not a two-operand enable node.
+ if (NewTag->getString() == "llvm.loop.vectorize.enable" &&
+ T->getNumOperands() == 2 && mdconst::hasa<ConstantInt>(T->getOperand(1)))
+ return makeVectorizeEnableNode(C, T->getOperand(1));
+
SmallVector<Metadata *, 8> Ops;
Ops.reserve(T->getNumOperands());
- Ops.push_back(upgradeLoopTag(C, OldTag->getString()));
+ Ops.push_back(NewTag);
for (unsigned I = 1, E = T->getNumOperands(); I != E; ++I)
Ops.push_back(T->getOperand(I));
@@ -7090,14 +7124,14 @@ MDNode *llvm::upgradeInstructionLoopAttachment(MDNode &N) {
if (none_of(T->operands(), isOldLoopArgument))
return &N;
- // Fix the old two-operand llvm.loop.distribute.enable nodes in place: the
- // Verifier rejects any MDNode carrying the distribute tag with more than one
- // operand, so a leftover reference (from the distinct loop-ID) would still
- // trigger a diagnostic. In-place mutation is safe on distinct MDNodes.
+ // Fix the old two-operand distribute/vectorize.enable nodes in place: the
+ // Verifier rejects any MDNode carrying those tags with more than one operand,
+ // so a leftover reference (from the distinct loop-ID) would still trigger a
+ // diagnostic. In-place mutation is safe on distinct MDNodes.
if (T->isDistinct()) {
for (unsigned I = 0, E = T->getNumOperands(); I < E; ++I) {
auto *OpT = dyn_cast_or_null<MDTuple>(T->getOperand(I));
- if (OpT && isOldDistributeEnable(OpT))
+ if (OpT && (isOldDistributeEnable(OpT) || isOldVectorizeEnable(OpT)))
T->replaceOperandWith(I, upgradeLoopArgument(OpT));
}
if (none_of(T->operands(), isOldLoopArgument))
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index c21b8c427ea46..af5cd296bc909 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -1017,6 +1017,13 @@ void Verifier::visitMDNode(const MDNode &BaseMD,
"Expected one operand for llvm.loop.distribute metadata",
CurrentMD);
+ // Enforce the single-operand form of llvm.loop.vectorize.enable metadata.
+ if (CurrentMD->getNumOperands() > 0 &&
+ (CurrentMD->getOperand(0).equalsStr("llvm.loop.vectorize.enable") ||
+ CurrentMD->getOperand(0).equalsStr("llvm.loop.vectorize.disable")))
+ Check(CurrentMD->getNumOperands() == 1,
+ "Expecting only the metadata name", CurrentMD);
+
// Check these last, so we diagnose problems in operands first.
Check(!CurrentMD->isTemporary(), "Expected no forward declarations!",
CurrentMD);
diff --git a/llvm/lib/Transforms/Utils/LoopConstrainer.cpp b/llvm/lib/Transforms/Utils/LoopConstrainer.cpp
index ca4010dfd08ea..d1bcf77b6ff4f 100644
--- a/llvm/lib/Transforms/Utils/LoopConstrainer.cpp
+++ b/llvm/lib/Transforms/Utils/LoopConstrainer.cpp
@@ -443,11 +443,8 @@ static void DisableAllLoopOptsOnLoop(Loop &L) {
MDNode *Dummy = MDNode::get(Context, {});
MDNode *DisableUnroll = MDNode::get(
Context, {MDString::get(Context, "llvm.loop.unroll.disable")});
- Metadata *FalseVal =
- ConstantAsMetadata::get(ConstantInt::get(Type::getInt1Ty(Context), 0));
MDNode *DisableVectorize = MDNode::get(
- Context,
- {MDString::get(Context, "llvm.loop.vectorize.enable"), FalseVal});
+ Context, {MDString::get(Context, "llvm.loop.vectorize.disable")});
MDNode *DisableLICMVersioning = MDNode::get(
Context, {MDString::get(Context, "llvm.loop.licm_versioning.disable")});
MDNode *DisableDistribution = MDNode::get(
diff --git a/llvm/lib/Transforms/Utils/LoopUtils.cpp b/llvm/lib/Transforms/Utils/LoopUtils.cpp
index 51848a8e1391e..1327fb0095647 100644
--- a/llvm/lib/Transforms/Utils/LoopUtils.cpp
+++ b/llvm/lib/Transforms/Utils/LoopUtils.cpp
@@ -250,6 +250,26 @@ void llvm::addStringMetadataToLoop(Loop *TheLoop, const char *StringMD,
TheLoop->setLoopID(NewLoopID);
}
+void llvm::addStringMetadataToLoop(Loop *TheLoop, StringRef StringMD) {
+ LLVMContext &Context = TheLoop->getHeader()->getContext();
+ SmallVector<Metadata *, 4> MDs(1);
+ // Retain existing metadata, skipping a name-only node with the same string.
+ if (MDNode *LoopID = TheLoop->getLoopID())
+ for (const MDOperand &Op : drop_begin(LoopID->operands())) {
+ MDNode *Node = cast<MDNode>(Op);
+ if (Node->getNumOperands() == 1)
+ if (auto *S = dyn_cast<MDString>(Node->getOperand(0)))
+ if (S->getString() == StringMD)
+ return;
+ MDs.push_back(Node);
+ }
+ MDs.push_back(MDNode::get(Context, {MDString::get(Context, StringMD)}));
+ MDNode *NewLoopID = MDNode::get(Context, MDs);
+ // Set operand 0 to refer to the loop id itself.
+ NewLoopID->replaceOperandWith(0, NewLoopID);
+ TheLoop->setLoopID(NewLoopID);
+}
+
std::optional<ElementCount>
llvm::getOptionalElementCountLoopAttribute(const Loop *TheLoop) {
std::optional<int> Width =
@@ -405,12 +425,11 @@ TransformationMode llvm::hasUnrollAndJamTransformation(const Loop *L) {
}
TransformationMode llvm::hasVectorizeTransformation(const Loop *L) {
- std::optional<bool> Enable =
- getOptionalBoolLoopAttribute(L, "llvm.loop.vectorize.enable");
-
- if (Enable == false)
+ if (getBooleanLoopAttribute(L, "llvm.loop.vectorize.disable"))
return TM_SuppressedByUser;
+ bool Enable = getBooleanLoopAttribute(L, "llvm.loop.vectorize.enable");
+
std::optional<ElementCount> VectorizeWidth =
getOptionalElementCountLoopAttribute(L);
std::optional<int> InterleaveCount =
@@ -418,14 +437,14 @@ TransformationMode llvm::hasVectorizeTransformation(const Loop *L) {
// 'Forcing' vector width and interleave count to one effectively disables
// this tranformation.
- if (Enable == true && VectorizeWidth && VectorizeWidth->isScalar() &&
+ if (Enable && VectorizeWidth && VectorizeWidth->isScalar() &&
InterleaveCount == 1)
return TM_SuppressedByUser;
if (getBooleanLoopAttribute(L, "llvm.loop.isvectorized"))
return TM_Disable;
- if (Enable == true)
+ if (Enable)
return TM_ForcedByUser;
if ((VectorizeWidth && VectorizeWidth->isScalar()) && InterleaveCount == 1)
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
index 8d875b2b6e492..9086880599231 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
@@ -287,6 +287,14 @@ void LoopVectorizeHints::getHintsFromMetadata() {
// Check if the hint starts with the loop metadata prefix.
StringRef Name = S->getString();
+ // The single-operand enable/disable pair carries no argument.
+ if (Args.empty()) {
+ if (Name == "llvm.loop.vectorize.enable")
+ Force.Value = FK_Enabled;
+ else if (Name == "llvm.loop.vectorize.disable")
+ Force.Value = FK_Disabled;
+ continue;
+ }
if (Args.size() == 1)
setHint(Name, Args[0]);
}
diff --git a/llvm/test/Bitcode/upgrade-loop-metadata.ll b/llvm/test/Bitcode/upgrade-loop-metadata.ll
index 8dee907578760..9cd46acd26e84 100644
--- a/llvm/test/Bitcode/upgrade-loop-metadata.ll
+++ b/llvm/test/Bitcode/upgrade-loop-metadata.ll
@@ -29,7 +29,7 @@ for.end: ; preds = %for.cond
; CHECK: !{!"llvm.loop.interleave.count", i32 4}
; CHECK: !{!"llvm.loop.vectorize.width", i32 8}
-; CHECK: !{!"llvm.loop.vectorize.enable", i1 true}
+; CHECK: !{!"llvm.loop.vectorize.enable"}
!0 = metadata !{metadata !"clang version 3.5.0 (trunk 211528)"}
!1 = metadata !{metadata !1, metadata !2, metadata !3, metadata !4, metadata !4}
diff --git a/llvm/test/Bitcode/upgrade-loop-vectorize-enable.ll b/llvm/test/Bitcode/upgrade-loop-vectorize-enable.ll
new file mode 100644
index 0000000000000..b757b787ce51c
--- /dev/null
+++ b/llvm/test/Bitcode/upgrade-loop-vectorize-enable.ll
@@ -0,0 +1,37 @@
+; Test that older bitcode carrying the two-operand form of
+; "llvm.loop.vectorize.enable" is auto-upgraded to the single-operand
+; enable/disable pair on load.
+;
+; RUN: llvm-dis < %s.bc | FileCheck %s
+; RUN: verify-uselistorder < %s.bc
+
+define void @enable_true() {
+entry:
+ br label %body
+body:
+ br i1 0, label %body, label %exit, !llvm.loop !0
+exit:
+ ret void
+}
+
+define void @enable_false() {
+entry:
+ br label %body
+body:
+ br i1 0, label %body, label %exit, !llvm.loop !2
+exit:
+ ret void
+}
+
+; i1 true -> single-operand enable.
+; i1 false -> disable.
+; CHECK: !{!"llvm.loop.vectorize.enable"}
+; CHECK: !{!"llvm.loop.vectorize.disable"}
+; The old two-operand nodes must be gone from the module.
+; CHECK-NOT: llvm.loop.vectorize.enable", i1
+; CHECK-NOT: llvm.loop.vectorize.disable", i1
+
+!0 = distinct !{!0, !1}
+!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = distinct !{!2, !3}
+!3 = !{!"llvm.loop.vectorize.enable", i1 false}
diff --git a/llvm/test/Bitcode/upgrade-loop-vectorize-enable.ll.bc b/llvm/test/Bitcode/upgrade-loop-vectorize-enable.ll.bc
new file mode 100644
index 0000000000000..e51d9ed57170e
Binary files /dev/null and b/llvm/test/Bitcode/upgrade-loop-vectorize-enable.ll.bc
diff er
diff --git a/llvm/test/Transforms/IRCE/add-metadata-pre-post-loops.ll b/llvm/test/Transforms/IRCE/add-metadata-pre-post-loops.ll
index 3a360814e361e..e6f2c53e8fa6e 100644
--- a/llvm/test/Transforms/IRCE/add-metadata-pre-post-loops.ll
+++ b/llvm/test/Transforms/IRCE/add-metadata-pre-post-loops.ll
@@ -74,7 +74,7 @@ attributes #0 = { alwaysinline }
!1 = !{!"branch_weights", i32 64, i32 4}
!2 = distinct !{!2, !3, !4, !5, !6}
!3 = !{!"llvm.loop.unroll.disable"}
-!4 = !{!"llvm.loop.vectorize.enable", i1 false}
+!4 = !{!"llvm.loop.vectorize.disable"}
!5 = !{!"llvm.loop.licm_versioning.disable"}
!6 = !{!"llvm.loop.distribute.disable"}
!7 = !{}
diff --git a/llvm/test/Transforms/IRCE/correct-loop-info.ll b/llvm/test/Transforms/IRCE/correct-loop-info.ll
index bc5987ebba2e4..f1cfd0e518de9 100644
--- a/llvm/test/Transforms/IRCE/correct-loop-info.ll
+++ b/llvm/test/Transforms/IRCE/correct-loop-info.ll
@@ -176,7 +176,7 @@ declare void @pluto()
!0 = distinct !{!0, !1, !2, !3, !4}
!1 = !{!"llvm.loop.unroll.disable"}
-!2 = !{!"llvm.loop.vectorize.enable", i1 false}
+!2 = !{!"llvm.loop.vectorize.disable"}
!3 = !{!"llvm.loop.licm_versioning.disable"}
!4 = !{!"llvm.loop.distribute.disable"}
!5 = !{}
diff --git a/llvm/test/Transforms/IRCE/loop-guarded-bounds.ll b/llvm/test/Transforms/IRCE/loop-guarded-bounds.ll
index 61cfef6f1492a..027a84d546462 100644
--- a/llvm/test/Transforms/IRCE/loop-guarded-bounds.ll
+++ b/llvm/test/Transforms/IRCE/loop-guarded-bounds.ll
@@ -128,7 +128,7 @@ exit: ; preds = %guarded, %loop_, %prehead
;.
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]], [[META3:![0-9]+]], [[META4:![0-9]+]]}
; CHECK: [[META1]] = !{!"llvm.loop.unroll.disable"}
-; CHECK: [[META2]] = !{!"llvm.loop.vectorize.enable", i1 false}
+; CHECK: [[META2]] = !{!"llvm.loop.vectorize.disable"}
; CHECK: [[META3]] = !{!"llvm.loop.licm_versioning.disable"}
; CHECK: [[META4]] = !{!"llvm.loop.distribute.disable"}
; CHECK: [[META5]] = !{}
diff --git a/llvm/test/Transforms/IRCE/pre_post_loops.ll b/llvm/test/Transforms/IRCE/pre_post_loops.ll
index 2807adba35940..ec67fc7ceb7f9 100644
--- a/llvm/test/Transforms/IRCE/pre_post_loops.ll
+++ b/llvm/test/Transforms/IRCE/pre_post_loops.ll
@@ -161,7 +161,7 @@ exit:
; CHECK: [[RNG0]] = !{i32 0, i32 50}
; CHECK: [[LOOP1]] = distinct !{[[LOOP1]], [[META2:![0-9]+]], [[META3:![0-9]+]], [[META4:![0-9]+]], [[META5:![0-9]+]]}
; CHECK: [[META2]] = !{!"llvm.loop.unroll.disable"}
-; CHECK: [[META3]] = !{!"llvm.loop.vectorize.enable", i1 false}
+; CHECK: [[META3]] = !{!"llvm.loop.vectorize.disable"}
; CHECK: [[META4]] = !{!"llvm.loop.licm_versioning.disable"}
; CHECK: [[META5]] = !{!"llvm.loop.distribute.disable"}
; CHECK: [[META6]] = !{}
diff --git a/llvm/test/Transforms/IRCE/range_intersect_miscompile.ll b/llvm/test/Transforms/IRCE/range_intersect_miscompile.ll
index 2e21bb5ad0bd0..c8b77e7ddcecd 100644
--- a/llvm/test/Transforms/IRCE/range_intersect_miscompile.ll
+++ b/llvm/test/Transforms/IRCE/range_intersect_miscompile.ll
@@ -488,7 +488,7 @@ deopt: ; preds = %range_check_block
;.
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]], [[META3:![0-9]+]], [[META4:![0-9]+]]}
; CHECK: [[META1]] = !{!"llvm.loop.unroll.disable"}
-; CHECK: [[META2]] = !{!"llvm.loop.vectorize.enable", i1 false}
+; CHECK: [[META2]] = !{!"llvm.loop.vectorize.disable"}
; CHECK: [[META3]] = !{!"llvm.loop.licm_versioning.disable"}
; CHECK: [[META4]] = !{!"llvm.loop.distribute.disable"}
; CHECK: [[META5]] = !{}
diff --git a/llvm/test/Transforms/IRCE/unsigned_comparisons_ugt.ll b/llvm/test/Transforms/IRCE/unsigned_comparisons_ugt.ll
index cdd7235ac45b4..e5caf440aca3a 100644
--- a/llvm/test/Transforms/IRCE/unsigned_comparisons_ugt.ll
+++ b/llvm/test/Transforms/IRCE/unsigned_comparisons_ugt.ll
@@ -445,7 +445,7 @@ exit:
; CHECK: [[RNG0]] = !{i32 0, i32 50}
; CHECK: [[LOOP1]] = distinct !{[[LOOP1]], [[META2:![0-9]+]], [[META3:![0-9]+]], [[META4:![0-9]+]], [[META5:![0-9]+]]}
; CHECK: [[META2]] = !{!"llvm.loop.unroll.disable"}
-; CHECK: [[META3]] = !{!"llvm.loop.vectorize.enable", i1 false}
+; CHECK: [[META3]] = !{!"llvm.loop.vectorize.disable"}
; CHECK: [[META4]] = !{!"llvm.loop.licm_versioning.disable"}
; CHECK: [[META5]] = !{!"llvm.loop.distribute.disable"}
; CHECK: [[META6]] = !{}
diff --git a/llvm/test/Transforms/IRCE/unsigned_comparisons_ult.ll b/llvm/test/Transforms/IRCE/unsigned_comparisons_ult.ll
index 107a3554282ad..3fb7b46e69569 100644
--- a/llvm/test/Transforms/IRCE/unsigned_comparisons_ult.ll
+++ b/llvm/test/Transforms/IRCE/unsigned_comparisons_ult.ll
@@ -652,7 +652,7 @@ exit:
; CHECK: [[RNG0]] = !{i32 0, i32 50}
; CHECK: [[LOOP1]] = distinct !{[[LOOP1]], [[META2:![0-9]+]], [[META3:![0-9]+]], [[META4:![0-9]+]], [[META5:![0-9]+]]}
; CHECK: [[META2]] = !{!"llvm.loop.unroll.disable"}
-; CHECK: [[META3]] = !{!"llvm.loop.vectorize.enable", i1 false}
+; CHECK: [[META3]] = !{!"llvm.loop.vectorize.disable"}
; CHECK: [[META4]] = !{!"llvm.loop.licm_versioning.disable"}
; CHECK: [[META5]] = !{!"llvm.loop.distribute.disable"}
; CHECK: [[META6]] = !{}
diff --git a/llvm/test/Transforms/Inline/dilocation-loop-metadata-update.ll b/llvm/test/Transforms/Inline/dilocation-loop-metadata-update.ll
index 0d8dcfbcf2a8b..86a9d00a2b1e3 100644
--- a/llvm/test/Transforms/Inline/dilocation-loop-metadata-update.ll
+++ b/llvm/test/Transforms/Inline/dilocation-loop-metadata-update.ll
@@ -50,7 +50,7 @@ entry:
!10 = !{!"llvm.loop.distribute.enable"}
!11 = !{!"llvm.loop.distribute.followup_all", !7, !8, !9, !12, !13, !14}
!12 = !{!"llvm.loop.vectorize.width", i32 8}
-!13 = !{!"llvm.loop.vectorize.enable", i1 true}
+!13 = !{!"llvm.loop.vectorize.enable"}
!14 = !{!"llvm.loop.vectorize.followup_all", !7, !8, !9, !15, !16}
!15 = !{!"llvm.loop.isvectorized"}
!16 = !{!"llvm.loop.unroll.count", i32 1}
@@ -69,7 +69,7 @@ entry:
; CHECK: [[META10]] = !{!"llvm.loop.distribute.enable"}
; CHECK: [[META11]] = !{!"llvm.loop.distribute.followup_all", [[META7]], [[META8]], [[META9]], [[META12:![0-9]+]], [[META13:![0-9]+]], [[META14:![0-9]+]]}
; CHECK: [[META12]] = !{!"llvm.loop.vectorize.width", i32 8}
-; CHECK: [[META13]] = !{!"llvm.loop.vectorize.enable", i1 true}
+; CHECK: [[META13]] = !{!"llvm.loop.vectorize.enable"}
; CHECK: [[META14]] = !{!"llvm.loop.vectorize.followup_all", [[META7]], [[META8]], [[META9]], [[META15:![0-9]+]], [[META16:![0-9]+]]}
; CHECK: [[META15]] = !{!"llvm.loop.isvectorized"}
; CHECK: [[META16]] = !{!"llvm.loop.unroll.count", i32 1}
diff --git a/llvm/test/Transforms/InstCombine/mem-par-metadata-memcpy.ll b/llvm/test/Transforms/InstCombine/mem-par-metadata-memcpy.ll
index 644795f08ac22..ae3d76f2dce21 100644
--- a/llvm/test/Transforms/InstCombine/mem-par-metadata-memcpy.ll
+++ b/llvm/test/Transforms/InstCombine/mem-par-metadata-memcpy.ll
@@ -61,5 +61,5 @@ declare void @llvm.memcpy.p0.p0.i64(ptr nocapture writeonly, ptr nocapture reado
!1 = distinct !{!1, !2, !3, !{!"llvm.loop.parallel_accesses", !4}}
!2 = distinct !{!2, !3}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
!4 = distinct !{} ; access group
diff --git a/llvm/test/Transforms/LoopIdiom/AArch64/disable-vectorize.ll b/llvm/test/Transforms/LoopIdiom/AArch64/disable-vectorize.ll
index 875f45ebd951c..04b2ec7f9e8b3 100644
--- a/llvm/test/Transforms/LoopIdiom/AArch64/disable-vectorize.ll
+++ b/llvm/test/Transforms/LoopIdiom/AArch64/disable-vectorize.ll
@@ -379,12 +379,12 @@ exit:
!0 = distinct !{!0, !1}
!1 = !{!"llvm.loop.vectorize.width", i32 1}
!2 = distinct !{!2, !3}
-!3 = !{!"llvm.loop.vectorize.enable", i1 false}
+!3 = !{!"llvm.loop.vectorize.disable"}
attributes #0 = { "target-features"="+sve2" }
;.
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]]}
; CHECK: [[META1]] = !{!"llvm.loop.vectorize.width", i32 1}
; CHECK: [[LOOP2]] = distinct !{[[LOOP2]], [[META3:![0-9]+]]}
-; CHECK: [[META3]] = !{!"llvm.loop.vectorize.enable", i1 false}
+; CHECK: [[META3]] = !{!"llvm.loop.vectorize.disable"}
;.
diff --git a/llvm/test/Transforms/LoopRotate/vect.omp.persistence.ll b/llvm/test/Transforms/LoopRotate/vect.omp.persistence.ll
index 4465288e0f1b2..6e28973518552 100644
--- a/llvm/test/Transforms/LoopRotate/vect.omp.persistence.ll
+++ b/llvm/test/Transforms/LoopRotate/vect.omp.persistence.ll
@@ -12,7 +12,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
; CHECK-NOT: loop-inc
; CHECK: br i1 %cmp, label %return, label %loop_cond, !llvm.loop !0
; CHECK: !0 = distinct !{!0, !1}
-; CHECK: !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+; CHECK: !1 = !{!"llvm.loop.vectorize.enable"}
define i32 @foo(i32 %a) {
entry:
br label %loop_cond
@@ -31,4 +31,4 @@ return:
}
!0 = !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopTransformWarning/enable_and_isvectorized.ll b/llvm/test/Transforms/LoopTransformWarning/enable_and_isvectorized.ll
index 6fcd552d9cffa..33dad5c3a68b0 100644
--- a/llvm/test/Transforms/LoopTransformWarning/enable_and_isvectorized.ll
+++ b/llvm/test/Transforms/LoopTransformWarning/enable_and_isvectorized.ll
@@ -26,7 +26,7 @@ simd.if.end:
}
!0 = distinct !{!0, !1, !2}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
!2 = !{!"llvm.loop.isvectorized"}
diff --git a/llvm/test/Transforms/LoopTransformWarning/optnone.ll b/llvm/test/Transforms/LoopTransformWarning/optnone.ll
index 469f3ce7ffc2e..caa75266d28ee 100644
--- a/llvm/test/Transforms/LoopTransformWarning/optnone.ll
+++ b/llvm/test/Transforms/LoopTransformWarning/optnone.ll
@@ -40,7 +40,7 @@ attributes #0 = { noinline optnone }
!1 = !{!"llvm.loop.unroll.enable"}
!2 = !{!"llvm.loop.distribute.enable"}
!3 = !{!"llvm.loop.unroll_and_jam.enable"}
-!4 = !{!"llvm.loop.vectorize.enable", i1 true}
+!4 = !{!"llvm.loop.vectorize.enable"}
; CHECK-NOT: warning
diff --git a/llvm/test/Transforms/LoopTransformWarning/vectorization-remarks-missed.ll b/llvm/test/Transforms/LoopTransformWarning/vectorization-remarks-missed.ll
index fb33df0967db4..41bf5fe0dbe76 100644
--- a/llvm/test/Transforms/LoopTransformWarning/vectorization-remarks-missed.ll
+++ b/llvm/test/Transforms/LoopTransformWarning/vectorization-remarks-missed.ll
@@ -73,7 +73,7 @@ for.end:
!12 = !DILocation(line: 3, column: 8, scope: !13)
!13 = distinct !DILexicalBlock(line: 3, column: 3, file: !1, scope: !4)
!14 = !{!14, !15, !15}
-!15 = !{!"llvm.loop.vectorize.enable", i1 true}
+!15 = !{!"llvm.loop.vectorize.enable"}
!16 = !DILocation(line: 4, column: 5, scope: !17)
!17 = distinct !DILexicalBlock(line: 3, column: 36, file: !1, scope: !13)
!18 = !{!19, !19, i64 0}
diff --git a/llvm/test/Transforms/LoopTransformWarning/vectorizer-loop-kind-unroll-warning.ll b/llvm/test/Transforms/LoopTransformWarning/vectorizer-loop-kind-unroll-warning.ll
index 0168bddacca51..4fc87ac4044be 100644
--- a/llvm/test/Transforms/LoopTransformWarning/vectorizer-loop-kind-unroll-warning.ll
+++ b/llvm/test/Transforms/LoopTransformWarning/vectorizer-loop-kind-unroll-warning.ll
@@ -105,7 +105,7 @@ exit:
; (runtime unroll disabled to prevent the unroller from succeeding on this
; runtime-trip-count loop, so the hint survives to transform-warning)
!10 = distinct !{!10, !11, !12, !13}
-!11 = !{!"llvm.loop.vectorize.enable", i1 false}
+!11 = !{!"llvm.loop.vectorize.disable"}
!12 = !{!"llvm.loop.unroll.enable"}
!13 = !{!"llvm.loop.unroll.runtime.disable"}
diff --git a/llvm/test/Transforms/LoopUnroll/unroll-pragmas-disabled.ll b/llvm/test/Transforms/LoopUnroll/unroll-pragmas-disabled.ll
index 28202bb4adbd5..74f22685e6542 100644
--- a/llvm/test/Transforms/LoopUnroll/unroll-pragmas-disabled.ll
+++ b/llvm/test/Transforms/LoopUnroll/unroll-pragmas-disabled.ll
@@ -31,7 +31,7 @@ for.end: ; preds = %for.body
ret void
}
!1 = !{!1, !2, !3, !4}
-!2 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.enable"}
!3 = !{!"llvm.loop.unroll.count", i32 4}
!4 = !{!"llvm.loop.vectorize.width", i32 8}
@@ -139,7 +139,7 @@ for.inc5.1: ; preds = %for.body3.1
; CHECK: ![[LOOP_1]] = distinct !{![[LOOP_1]], ![[VEC_ENABLE:.*]], ![[WIDTH_8:.*]], ![[UNROLL_DISABLE:.*]]}
-; CHECK: ![[VEC_ENABLE]] = !{!"llvm.loop.vectorize.enable", i1 true}
+; CHECK: ![[VEC_ENABLE]] = !{!"llvm.loop.vectorize.enable"}
; CHECK: ![[WIDTH_8]] = !{!"llvm.loop.vectorize.width", i32 8}
; CHECK: ![[UNROLL_DISABLE]] = !{!"llvm.loop.unroll.disable"}
; CHECK: ![[LOOP_2]] = distinct !{![[LOOP_2]], ![[UNROLL_FULL:.*]]}
diff --git a/llvm/test/Transforms/LoopUnroll/vectorizer-loop-kind-remarks.ll b/llvm/test/Transforms/LoopUnroll/vectorizer-loop-kind-remarks.ll
index 723a0273e90a7..68913a90e8185 100644
--- a/llvm/test/Transforms/LoopUnroll/vectorizer-loop-kind-remarks.ll
+++ b/llvm/test/Transforms/LoopUnroll/vectorizer-loop-kind-remarks.ll
@@ -101,7 +101,7 @@ exit:
!99 = !DISubroutineType(types: !{})
!10 = distinct !{!10, !11}
-!11 = !{!"llvm.loop.vectorize.enable", i1 false}
+!11 = !{!"llvm.loop.vectorize.disable"}
!100 = distinct !DISubprogram(name: "plain_loop", scope: !1, file: !1, line: 1, type: !99, isLocal: false, isDefinition: true, scopeLine: 1, unit: !0)
!108 = !DILocation(line: 1, column: 1, scope: !100)
diff --git a/llvm/test/Transforms/LoopVectorize/2016-07-27-loop-vec.ll b/llvm/test/Transforms/LoopVectorize/2016-07-27-loop-vec.ll
index 0941c2367dfb8..51ce91a0b4c94 100644
--- a/llvm/test/Transforms/LoopVectorize/2016-07-27-loop-vec.ll
+++ b/llvm/test/Transforms/LoopVectorize/2016-07-27-loop-vec.ll
@@ -16,4 +16,4 @@ for.end:
}
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll b/llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
index 54dbddff5d9fd..47ec13b653a18 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
@@ -324,4 +324,4 @@ exit:
!0 = distinct !{!0, !1, !2, !3}
!1 = !{!"llvm.loop.vectorize.width", i32 2}
!2 = !{!"llvm.loop.vectorize.scalable.enable", i1 false}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll b/llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
index cc1eb9c9614f9..09852d7951c09 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
@@ -1353,4 +1353,4 @@ attributes #3 = { "target-cpu"="neoverse-v2" }
!0 = distinct !{!0, !1, !2, !3}
!1 = !{!"llvm.loop.vectorize.width", i32 8}
!2 = !{!"llvm.loop.vectorize.scalable.enable", i1 false}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll b/llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll
index f38d8897ca8ff..61ebc1e306ca5 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll
@@ -2120,4 +2120,4 @@ exit:
!1 = distinct !{!1, !2, !3}
!2 = !{!"llvm.loop.interleave.count", i32 2}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll b/llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
index d64504685fa5d..6a78f2b2bcf2b 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
@@ -1625,4 +1625,4 @@ attributes #1 = { "target-cpu"="grace" }
!0 = distinct !{!0, !1, !2}
!1 = !{!"llvm.loop.mustprogress"}
-!2 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/masked-op-cost.ll b/llvm/test/Transforms/LoopVectorize/AArch64/masked-op-cost.ll
index e007b706d3d44..f49b18c80f528 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/masked-op-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/masked-op-cost.ll
@@ -89,6 +89,6 @@ attributes #0 = { "target-features"="+neon,+sve" }
!1 = !{!"llvm.loop.mustprogress"}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
-!4 = !{!"llvm.loop.vectorize.enable", i1 true}
+!4 = !{!"llvm.loop.vectorize.enable"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.vectorize.scalable.enable", i1 false}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/masked_ldst_sme.ll b/llvm/test/Transforms/LoopVectorize/AArch64/masked_ldst_sme.ll
index 14d6ef1716bd6..127057c58db2d 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/masked_ldst_sme.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/masked_ldst_sme.ll
@@ -163,7 +163,7 @@ attributes #0 = { uwtable vscale_range(1,16) "aarch64_pstate_sm_body" "target-fe
!1 = !{!"llvm.loop.mustprogress"}
!2 = !{!"llvm.loop.vectorize.width", i32 16}
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
-!4 = !{!"llvm.loop.vectorize.enable", i1 true}
+!4 = !{!"llvm.loop.vectorize.enable"}
;.
; CHECK: [[META0]] = !{[[META1:![0-9]+]]}
; CHECK: [[META1]] = distinct !{[[META1]], [[META2:![0-9]+]]}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll b/llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
index 20aba29291dd4..047a901597675 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
@@ -779,4 +779,4 @@ for.cond.cleanup:
attributes #0 = { "target-features"="+sve" }
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll b/llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
index 860baa9e6f01f..a1f2abcca5274 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
@@ -104,4 +104,4 @@ exit:
}
!1 = distinct !{!1, !2}
-!2 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll b/llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
index d9fd4e4cb033b..9350373d2dec4 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
@@ -152,4 +152,4 @@ exit:
!1 = distinct !{!1, !2}
-!2 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
index 2f27092622192..0282a9cac5c8d 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
@@ -448,7 +448,7 @@ exit:
!7 = distinct !{!7, !8, !9, !10}
!8 = !{!"llvm.loop.mustprogress"}
!9 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
-!10 = !{!"llvm.loop.vectorize.enable", i1 true}
+!10 = !{!"llvm.loop.vectorize.enable"}
attributes #0 = { vscale_range(1,16) "target-features"="+sve" }
attributes #1 = { "target-cpu"="apple-m1" }
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
index 0985d7f052a90..339aea4551d6b 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
@@ -394,6 +394,6 @@ for.exit:
!7 = distinct !{!7, !8, !9, !10}
!8 = !{!"llvm.loop.mustprogress"}
!9 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
-!10 = !{!"llvm.loop.vectorize.enable", i1 true}
+!10 = !{!"llvm.loop.vectorize.enable"}
attributes #0 = { vscale_range(1,16) "target-features"="+sve" }
attributes #1 = { "target-features"="+neon" }
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
index f0f9e8e74b3f5..3ba46e2fd46d6 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
@@ -2395,4 +2395,4 @@ exit:
!7 = distinct !{!7, !8, !9, !10}
!8 = !{!"llvm.loop.mustprogress"}
!9 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
-!10 = !{!"llvm.loop.vectorize.enable", i1 true}
+!10 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
index 09e5959f7083c..f19db4519c09a 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
@@ -2692,6 +2692,6 @@ for.body:
!7 = distinct !{!7, !8, !9, !10}
!8 = !{!"llvm.loop.mustprogress"}
!9 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
-!10 = !{!"llvm.loop.vectorize.enable", i1 true}
+!10 = !{!"llvm.loop.vectorize.enable"}
attributes #0 = { vscale_range(1,16) "target-features"="+sve" }
attributes #1 = { vscale_range(1,16) "target-features"="+neon,+dotprod,+sve" "target-cpu"="neoverse-v2" }
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
index dd21d1994d95d..641d6db59147d 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
@@ -524,7 +524,7 @@ for.exit:
!7 = distinct !{!7, !8, !9, !10}
!8 = !{!"llvm.loop.mustprogress"}
!9 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
-!10 = !{!"llvm.loop.vectorize.enable", i1 true}
+!10 = !{!"llvm.loop.vectorize.enable"}
attributes #0 = { vscale_range(1,16) "target-features"="+sve" }
attributes #1 = { "target-cpu"="apple-m1" }
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll b/llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll
index 6bc2c098576c7..980d501954124 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll
@@ -661,6 +661,6 @@ attributes #0 = { "target-features"="+neon,+sve" vscale_range(1, 16) }
!1 = !{!"llvm.loop.mustprogress"}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
-!4 = !{!"llvm.loop.vectorize.enable", i1 true}
+!4 = !{!"llvm.loop.vectorize.enable"}
!5 = !{!"llvm.loop.interleave.count", i32 1}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll b/llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll
index 363223a66f398..3c47627e5f45f 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll
@@ -371,7 +371,7 @@ attributes #1 = { "target-cpu"="neoverse-v2" }
!0 = distinct !{!0, !1, !2, !3}
!1 = !{!"llvm.loop.mustprogress"}
!2 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
; BFI computes if is taken 20 times, and loop 32 times. Make sure we round the
; divisor up to 2 so that we don't vectorize the loop unprofitably.
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-predicate-instruction.ll b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-predicate-instruction.ll
index 13af29855be23..71e814bd4bdfd 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-predicate-instruction.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-predicate-instruction.ll
@@ -88,4 +88,4 @@ attributes #0 = { "target-features"="+sve" }
!1 = !{!"llvm.loop.vectorize.width", i32 4}
!2 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
!3 = !{!"llvm.loop.interleave.count", i32 1}
-!4 = !{!"llvm.loop.vectorize.enable", i1 true}
+!4 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions-tf.ll b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions-tf.ll
index b68c7151c3a89..25d01a2295899 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions-tf.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions-tf.ll
@@ -64,4 +64,4 @@ for.end:
!1 = !{!"llvm.loop.vectorize.width", i32 4}
!2 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
!3 = !{!"llvm.loop.interleave.count", i32 1}
-!4 = !{!"llvm.loop.vectorize.enable", i1 true}
+!4 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll
index 75e30632c5cc8..cec1dd6c359af 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll
@@ -456,4 +456,4 @@ for.end:
!1 = !{!"llvm.loop.vectorize.width", i32 8}
!2 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
!3 = !{!"llvm.loop.interleave.count", i32 2}
-!4 = !{!"llvm.loop.vectorize.enable", i1 true}
+!4 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll b/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll
index 4b2e5d051730b..b79cc7cf2bcee 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll
@@ -1416,6 +1416,6 @@ for.cond.cleanup:
!8 = !{!"llvm.loop.vectorize.width", i32 1}
!9 = !{!"llvm.loop.interleave.count", i32 1}
!10 = !{!"llvm.loop.interleave.count", i32 4}
-!11 = !{!"llvm.loop.vectorize.enable", i1 true}
+!11 = !{!"llvm.loop.vectorize.enable"}
!12 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
!13 = distinct !{!13, !6, !9, !11}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-basic-vec.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-basic-vec.ll
index e98c726e82f8e..0d5d4a42f100c 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-basic-vec.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-basic-vec.ll
@@ -95,4 +95,4 @@ for.end:
!2 = !{!"llvm.loop.vectorize.width", i32 4}
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
!4 = !{!"llvm.loop.interleave.count", i32 1}
-!5 = !{!"llvm.loop.vectorize.enable", i1 true}
+!5 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-cond-inv-loads.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-cond-inv-loads.ll
index b6c2abe3d805d..d51ae84401031 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-cond-inv-loads.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-cond-inv-loads.ll
@@ -183,4 +183,4 @@ attributes #0 = { vscale_range(1, 16) }
!2 = !{!"llvm.loop.vectorize.width", i32 4}
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
!4 = !{!"llvm.loop.interleave.count", i32 1}
-!5 = !{!"llvm.loop.vectorize.enable", i1 true}
+!5 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-extract-last-veclane.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-extract-last-veclane.ll
index 834e915d4685e..687a16cefd65b 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-extract-last-veclane.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-extract-last-veclane.ll
@@ -67,5 +67,5 @@ attributes #0 = { "target-cpu"="generic" "target-features"="+neon,+sve" }
!2 = !{!"llvm.loop.vectorize.width", i32 4}
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
!4 = !{!"llvm.loop.interleave.count", i32 1}
-!5 = !{!"llvm.loop.vectorize.enable", i1 true}
+!5 = !{!"llvm.loop.vectorize.enable"}
!6 = distinct !{!6, !1, !2, !3, !4, !5}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter-cost.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter-cost.ll
index 6fbab439e2035..eeae794f068cf 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter-cost.ll
@@ -187,4 +187,4 @@ attributes #0 = { vscale_range(1, 16) "target-features"="+sve" }
!2 = !{!"llvm.loop.vectorize.width", i32 4}
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
!4 = !{!"llvm.loop.interleave.count", i32 1}
-!5 = !{!"llvm.loop.vectorize.enable", i1 true}
+!5 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
index ba1fd71659b59..b43e2c8359525 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
@@ -271,4 +271,4 @@ attributes #0 = { vscale_range(1, 16) }
!2 = !{!"llvm.loop.vectorize.width", i32 4}
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
!4 = !{!"llvm.loop.interleave.count", i32 1}
-!5 = !{!"llvm.loop.vectorize.enable", i1 true}
+!5 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions.ll
index 4073b1055b504..eb12b7f5c1cd4 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions.ll
@@ -74,6 +74,6 @@ attributes #0 = { "target-features"="+sve" }
!0 = distinct !{!0, !1, !2, !3, !4, !5}
!1 = !{!"llvm.loop.mustprogress"}
!2 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
!4 = !{!"llvm.loop.vectorize.width", i32 4}
!5 = !{!"llvm.loop.interleave.count", i32 1}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-inv-store.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-inv-store.ll
index 8b3fa9279768e..a01188ca95678 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-inv-store.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-inv-store.ll
@@ -106,5 +106,5 @@ attributes #0 = { "target-features"="+neon,+sve" vscale_range(1, 16) }
!1 = !{!"llvm.loop.mustprogress"}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
-!4 = !{!"llvm.loop.vectorize.enable", i1 true}
+!4 = !{!"llvm.loop.vectorize.enable"}
!5 = !{!"llvm.loop.interleave.count", i32 1}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-large-strides.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-large-strides.ll
index a7c164fa7de16..561cbce0f8738 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-large-strides.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-large-strides.ll
@@ -97,6 +97,6 @@ attributes #0 = { vscale_range(1, 16) }
!2 = !{!"llvm.loop.vectorize.width", i32 4}
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
!4 = !{!"llvm.loop.interleave.count", i32 1}
-!5 = !{!"llvm.loop.vectorize.enable", i1 true}
+!5 = !{!"llvm.loop.vectorize.enable"}
!6 = distinct !{!6, !1, !7, !3, !4, !5}
!7 = !{!"llvm.loop.vectorize.width", i32 2}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-masked-loadstore.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-masked-loadstore.ll
index 826617da6f903..5ee66f493a9cd 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-masked-loadstore.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-masked-loadstore.ll
@@ -76,4 +76,4 @@ exit:
!2 = !{!"llvm.loop.vectorize.width", i32 4}
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
!4 = !{!"llvm.loop.interleave.count", i32 1}
-!5 = !{!"llvm.loop.vectorize.enable", i1 true}
+!5 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll
index fb17b9a80d09b..e80df2a09824c 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll
@@ -401,4 +401,4 @@ attributes #0 = { "target-features"="+sve" }
!1 = !{!"llvm.loop.vectorize.width", i32 4}
!2 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
!3 = !{!"llvm.loop.interleave.count", i32 1}
-!4 = !{!"llvm.loop.vectorize.enable", i1 true}
+!4 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-type-conv.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-type-conv.ll
index 78858fe512fd4..0b7782c95c417 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-type-conv.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-type-conv.ll
@@ -263,4 +263,4 @@ attributes #0 = { "target-features"="+sve" }
!2 = !{!"llvm.loop.vectorize.width", i32 8}
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
!4 = !{!"llvm.loop.interleave.count", i32 1}
-!5 = !{!"llvm.loop.vectorize.enable", i1 true}
+!5 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll
index 6d16222f25f92..91df2229db6e6 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll
@@ -101,4 +101,4 @@ attributes #0 = {"target-cpu"="generic" "target-features"="+neon,+sve"}
!1 = !{!"llvm.loop.mustprogress"}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
-!4 = !{!"llvm.loop.vectorize.enable", i1 true}
+!4 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll
index 4f53d31fd98fa..82fe12a43f842 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll
@@ -152,6 +152,6 @@ attributes #0 = { "target-cpu"="generic" "target-features"="+neon,+sve" }
!1 = !{!"llvm.loop.mustprogress"}
!2 = !{!"llvm.loop.vectorize.width", i32 8}
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
-!4 = !{!"llvm.loop.vectorize.enable", i1 true}
+!4 = !{!"llvm.loop.vectorize.enable"}
!5 = !{!"llvm.loop.interleave.count", i32 2}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-extractvalue.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-extractvalue.ll
index 1794a6ffc3ccd..0039941d2d47f 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-extractvalue.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-extractvalue.ll
@@ -58,4 +58,4 @@ attributes #0 = { "target-features"="+sve" }
!2 = !{!"llvm.loop.vectorize.width", i32 2}
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
!4 = !{!"llvm.loop.interleave.count", i32 1}
-!5 = !{!"llvm.loop.vectorize.enable", i1 true}
+!5 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
index 017982a4f8a8a..f1085e21d30f1 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
@@ -347,7 +347,7 @@ attributes #0 = { vscale_range(1, 16) }
!1 = !{!"llvm.loop.mustprogress"}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
-!4 = !{!"llvm.loop.vectorize.enable", i1 true}
+!4 = !{!"llvm.loop.vectorize.enable"}
!5 = !{!"llvm.loop.interleave.count", i32 2}
!6 = distinct !{!6, !1, !7, !3, !4, !8}
!7 = !{!"llvm.loop.vectorize.width", i32 2}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/unsafe-vf-hint-remark.ll b/llvm/test/Transforms/LoopVectorize/AArch64/unsafe-vf-hint-remark.ll
index fc20277b1d858..a354f94ba832d 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/unsafe-vf-hint-remark.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/unsafe-vf-hint-remark.ll
@@ -39,4 +39,4 @@ exit:
!0 = !{!0, !1, !2}
!1 = !{!"llvm.loop.vectorize.width", i64 32}
-!2 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll b/llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll
index 90c4ed0fb8ded..d99ab30f5ebb2 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll
@@ -119,5 +119,5 @@ attributes #0 = {"target-cpu"="generic" "target-features"="+neon,+sve" vscale_ra
!1 = !{!"llvm.loop.mustprogress"}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 false}
-!4 = !{!"llvm.loop.vectorize.enable", i1 true}
+!4 = !{!"llvm.loop.vectorize.enable"}
!5 = !{!"llvm.loop.interleave.count", i32 2}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll b/llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
index 7106be6ec78dd..cf06100f988ef 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
@@ -266,4 +266,4 @@ attributes #1 = { "target-cpu"="neoverse-v2" }
!1 = !{!"llvm.loop.mustprogress"}
!2 = !{!"llvm.loop.vectorize.width", i32 8}
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 false}
-!4 = !{!"llvm.loop.vectorize.enable", i1 true}
+!4 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/vplan-native-outer-loop-wide-type.ll b/llvm/test/Transforms/LoopVectorize/AArch64/vplan-native-outer-loop-wide-type.ll
index 3d8863368e74c..a15b377d4ef3e 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/vplan-native-outer-loop-wide-type.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/vplan-native-outer-loop-wide-type.ll
@@ -56,4 +56,4 @@ exit:
}
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/widen-gep-all-indices-invariant.ll b/llvm/test/Transforms/LoopVectorize/AArch64/widen-gep-all-indices-invariant.ll
index fbc313eddea8a..3b29335c36301 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/widen-gep-all-indices-invariant.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/widen-gep-all-indices-invariant.ll
@@ -54,7 +54,7 @@ exit:
attributes #0 = { "target-cpu"="neoverse-v2" }
!0 = distinct !{!0, !1, !2}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
!2 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
;.
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/optsize_minsize.ll b/llvm/test/Transforms/LoopVectorize/ARM/optsize_minsize.ll
index 83be0708774f1..8d8766051a5b9 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/optsize_minsize.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/optsize_minsize.ll
@@ -482,4 +482,4 @@ for.cond.cleanup:
}
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll b/llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll
index 1b5db04061631..75862d9c72e00 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll
@@ -422,7 +422,7 @@ for.body:
attributes #0 = { nofree norecurse nounwind "target-features"="+armv8.1-m.main,+mve.fp" }
!5 = distinct !{!5, !6}
-!6 = !{!"llvm.loop.vectorize.enable", i1 true}
+!6 = !{!"llvm.loop.vectorize.enable"}
!7 = distinct !{!7, !8}
!8 = !{!"llvm.loop.vectorize.predicate.enable", i1 false}
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-loop-hint.ll b/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-loop-hint.ll
index f205e21762317..3038b7fd935d3 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-loop-hint.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-loop-hint.ll
@@ -81,4 +81,4 @@ for.body:
!6 = distinct !{!6, !7, !8}
!7 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
-!8 = !{!"llvm.loop.vectorize.enable", i1 true}
+!8 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-prefer-flag.ll b/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-prefer-flag.ll
index c7af4646ccdee..a477fee265d59 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-prefer-flag.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-prefer-flag.ll
@@ -102,7 +102,7 @@ for.body:
!10 = distinct !{!10, !11, !12}
!11 = !{!"llvm.loop.vectorize.predicate.enable", i1 false}
-!12 = !{!"llvm.loop.vectorize.enable", i1 true}
+!12 = !{!"llvm.loop.vectorize.enable"}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.interleave.count", i32 4}
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll b/llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll
index 3e3c6c09050b4..2cccae4de2fa5 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll
@@ -72,7 +72,7 @@ exit:
!9 = !DILocation(line: 2, column: 27, scope: !3)
!10 = !DILocation(line: 2, column: 5, scope: !3)
!11 = distinct !{!11, !12}
-!12 = !{!"llvm.loop.vectorize.enable", i1 true}
+!12 = !{!"llvm.loop.vectorize.enable"}
;.
; CHECK: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: [[META1:![0-9]+]], producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None)
; CHECK: [[META1]] = !DIFile(filename: "{{.*}}dbg-tail-folding-by-evl.cpp", directory: {{.*}})
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll b/llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
index 7adb8b6e1b2cf..22560793e4504 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
@@ -31,4 +31,4 @@ for.end:
}
!0 = !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll b/llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
index 1c9e48fdf4aa6..100ecc172fab0 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
@@ -908,5 +908,5 @@ exit:
!0 = distinct !{!0, !1, !2, !3}
!1 = !{!"llvm.loop.vectorize.width", i32 4}
!2 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
!4 = distinct !{!4, !1, !3}
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cond-reduction.ll b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cond-reduction.ll
index dfe6a6720af27..bdae288cbe5e5 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cond-reduction.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cond-reduction.ll
@@ -768,7 +768,7 @@ for.end:
}
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
;.
; IF-EVL-OUTLOOP: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; IF-EVL-OUTLOOP: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
index 062c052b95391..43c734471537b 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
@@ -623,7 +623,7 @@ for.end:
}
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
;.
; IF-EVL: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; IF-EVL: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
index 1fad71f9f9e04..ba6af22e10718 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
@@ -1658,4 +1658,4 @@ for.end:
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
index 935e37e94c266..77808152757e8 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
@@ -757,4 +757,4 @@ exit:
}
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-intermediate-store.ll b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-intermediate-store.ll
index 8b86d42fe4377..e7631a2ddf9b5 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-intermediate-store.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-intermediate-store.ll
@@ -234,7 +234,7 @@ for.end:
}
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
;.
; IF-EVL-OUTLOOP: [[META0]] = !{[[META1:![0-9]+]]}
; IF-EVL-OUTLOOP: [[META1]] = distinct !{[[META1]], [[META2:![0-9]+]]}
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-ordered-reduction.ll b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-ordered-reduction.ll
index 85dc6b407c877..19099b43557ad 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-ordered-reduction.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-ordered-reduction.ll
@@ -91,4 +91,4 @@ for.end:
}
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll
index 1ca4b6fdb2283..7a743ea485459 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll
@@ -1680,4 +1680,4 @@ for.end:
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
index a7c3d43883b4b..c6bffa6df3533 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
@@ -59,4 +59,4 @@ exit:
!0 = distinct !{!0, !1, !2, !3}
!1 = !{!"llvm.loop.vectorize.width", i32 2}
!2 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll b/llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
index 64d412666c74f..256528c25a781 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
@@ -895,4 +895,4 @@ for.end:
!0 = distinct !{!0, !1, !2}
!1 = !{!"llvm.loop.vectorize.width", i32 4}
-!2 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/Sparc/no-vectorize.ll b/llvm/test/Transforms/LoopVectorize/Sparc/no-vectorize.ll
index c4ceb53200cce..97a3eb830213d 100644
--- a/llvm/test/Transforms/LoopVectorize/Sparc/no-vectorize.ll
+++ b/llvm/test/Transforms/LoopVectorize/Sparc/no-vectorize.ll
@@ -59,15 +59,15 @@ exit:
!1 = distinct !{!1, !2, !3}
!2 = !{!"llvm.loop.mustprogress"}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
;.
; SPARC32: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; SPARC32: [[META1]] = !{!"llvm.loop.mustprogress"}
-; SPARC32: [[META2]] = !{!"llvm.loop.vectorize.enable", i1 true}
+; SPARC32: [[META2]] = !{!"llvm.loop.vectorize.enable"}
;.
; SPARC64: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; SPARC64: [[META1]] = !{!"llvm.loop.mustprogress"}
-; SPARC64: [[META2]] = !{!"llvm.loop.vectorize.enable", i1 true}
+; SPARC64: [[META2]] = !{!"llvm.loop.vectorize.enable"}
;.
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; SPARC32: {{.*}}
diff --git a/llvm/test/Transforms/LoopVectorize/VE/disable_lv.ll b/llvm/test/Transforms/LoopVectorize/VE/disable_lv.ll
index 5058b4c85d057..4e55fcc295fe1 100644
--- a/llvm/test/Transforms/LoopVectorize/VE/disable_lv.ll
+++ b/llvm/test/Transforms/LoopVectorize/VE/disable_lv.ll
@@ -35,4 +35,4 @@ simd.if.end:
!6 = distinct !{}
!7 = distinct !{!7, !8, !9}
!8 = !{!"llvm.loop.parallel_accesses", !6}
-!9 = !{!"llvm.loop.vectorize.enable", i1 true}
+!9 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll b/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll
index 2034dedb09d7e..ed2dd44a484c8 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll
@@ -72,4 +72,4 @@ for.end:
}
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-reduction.ll b/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-reduction.ll
index fffc6779438d7..23f5de1399d52 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-reduction.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-reduction.ll
@@ -222,4 +222,4 @@ for.end:
}
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll b/llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
index 92bb9704c4fd2..4ec0ec66d4321 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
@@ -318,5 +318,5 @@ exit:
!1 = distinct !{!1, !2, !3, !4}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
!4 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-outer-loop.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-outer-loop.ll
index 6eff6d1df3523..a86a211bf1417 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-outer-loop.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-outer-loop.ll
@@ -70,4 +70,4 @@ exit:
!1 = distinct !{!1, !2, !3}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-stress-test-no-explict-vf.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-stress-test-no-explict-vf.ll
index 7f442f7d72e78..2edddc1079178 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-stress-test-no-explict-vf.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-stress-test-no-explict-vf.ll
@@ -40,4 +40,4 @@ for.end10:
}
!1 = distinct !{!1, !2}
-!2 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls-finite.ll b/llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls-finite.ll
index 7ad03ebaca7c2..985a2c693aded 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls-finite.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls-finite.ll
@@ -484,15 +484,15 @@ for.end:
!1 = distinct !{!1, !2, !3}
!2 = !{!"llvm.loop.vectorize.width", i32 2}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
!4 = distinct !{!4, !5, !6}
!5 = !{!"llvm.loop.vectorize.width", i32 4}
-!6 = !{!"llvm.loop.vectorize.enable", i1 true}
+!6 = !{!"llvm.loop.vectorize.enable"}
!7 = distinct !{!7, !8, !9}
!8 = !{!"llvm.loop.vectorize.width", i32 8}
-!9 = !{!"llvm.loop.vectorize.enable", i1 true}
+!9 = !{!"llvm.loop.vectorize.enable"}
declare float @__expf_finite(float) #0
declare double @__exp_finite(double) #0
diff --git a/llvm/test/Transforms/LoopVectorize/X86/conditional-scalar-assignment.ll b/llvm/test/Transforms/LoopVectorize/X86/conditional-scalar-assignment.ll
index 9cb7887346d3e..283aeb2a5ba21 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/conditional-scalar-assignment.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/conditional-scalar-assignment.ll
@@ -1016,4 +1016,4 @@ exit:
!1 = distinct !{!1, !2, !3}
!2 = !{!"llvm.loop.interleave.count", i32 2}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/cost-model.ll b/llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
index 941641fd688c7..b4c861e67dd38 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
@@ -1117,4 +1117,4 @@ attributes #4 = { "target-cpu"="haswell" }
!0 = distinct !{!0, !1, !2, !3}
!1 = !{!"llvm.loop.vectorize.width", i32 2}
!2 = !{!"llvm.loop.vectorize.scalable.enable", i1 false}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll b/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
index 1a5188687b508..815d13351d15d 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
@@ -642,7 +642,7 @@ exit:
!1 = distinct !{!1, !2, !3, !4}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
!4 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
define void @wide_iv_trunc_reuse(ptr %dst) {
diff --git a/llvm/test/Transforms/LoopVectorize/X86/iv-live-outs.ll b/llvm/test/Transforms/LoopVectorize/X86/iv-live-outs.ll
index 9823d18da2905..d08c1a404e6c3 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/iv-live-outs.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/iv-live-outs.ll
@@ -176,4 +176,4 @@ attributes #0 = { "target-cpu"="skylake-avx512" }
!0 = distinct !{!0, !1, !2, !3}
!1 = !{!"llvm.loop.vectorize.width", i32 2}
!2 = !{!"llvm.loop.vectorize.scalable.enable", i1 false}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls-VF2-VF8.ll b/llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls-VF2-VF8.ll
index 025e24bcbc5eb..5f7261240e3d4 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls-VF2-VF8.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls-VF2-VF8.ll
@@ -28,7 +28,7 @@ for.end:
!1 = distinct !{!1, !2, !3}
!2 = !{!"llvm.loop.vectorize.width", i32 2}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
define void @sin_f32(ptr nocapture %varray) {
@@ -56,7 +56,7 @@ for.end:
!21 = distinct !{!21, !22, !23}
!22 = !{!"llvm.loop.vectorize.width", i32 8}
-!23 = !{!"llvm.loop.vectorize.enable", i1 true}
+!23 = !{!"llvm.loop.vectorize.enable"}
define void @sin_f64_intrinsic(ptr nocapture %varray) {
; CHECK-LABEL: @sin_f64_intrinsic(
@@ -83,7 +83,7 @@ for.end:
!31 = distinct !{!31, !32, !33}
!32 = !{!"llvm.loop.vectorize.width", i32 2}
-!33 = !{!"llvm.loop.vectorize.enable", i1 true}
+!33 = !{!"llvm.loop.vectorize.enable"}
define void @sin_f32_intrinsic(ptr nocapture %varray) {
; CHECK-LABEL: @sin_f32_intrinsic(
@@ -110,7 +110,7 @@ for.end:
!41 = distinct !{!41, !42, !43}
!42 = !{!"llvm.loop.vectorize.width", i32 8}
-!43 = !{!"llvm.loop.vectorize.enable", i1 true}
+!43 = !{!"llvm.loop.vectorize.enable"}
define void @cos_f64(ptr nocapture %varray) {
; CHECK-LABEL: @cos_f64(
@@ -137,7 +137,7 @@ for.end:
!51 = distinct !{!51, !52, !53}
!52 = !{!"llvm.loop.vectorize.width", i32 2}
-!53 = !{!"llvm.loop.vectorize.enable", i1 true}
+!53 = !{!"llvm.loop.vectorize.enable"}
define void @cos_f32(ptr nocapture %varray) {
; CHECK-LABEL: @cos_f32(
@@ -164,7 +164,7 @@ for.end:
!61 = distinct !{!61, !62, !63}
!62 = !{!"llvm.loop.vectorize.width", i32 8}
-!63 = !{!"llvm.loop.vectorize.enable", i1 true}
+!63 = !{!"llvm.loop.vectorize.enable"}
define void @cos_f64_intrinsic(ptr nocapture %varray) {
; CHECK-LABEL: @cos_f64_intrinsic(
@@ -191,7 +191,7 @@ for.end:
!71 = distinct !{!71, !72, !73}
!72 = !{!"llvm.loop.vectorize.width", i32 2}
-!73 = !{!"llvm.loop.vectorize.enable", i1 true}
+!73 = !{!"llvm.loop.vectorize.enable"}
define void @cos_f32_intrinsic(ptr nocapture %varray) {
; CHECK-LABEL: @cos_f32_intrinsic(
@@ -218,7 +218,7 @@ for.end:
!81 = distinct !{!81, !82, !83}
!82 = !{!"llvm.loop.vectorize.width", i32 8}
-!83 = !{!"llvm.loop.vectorize.enable", i1 true}
+!83 = !{!"llvm.loop.vectorize.enable"}
define void @exp_f32(ptr nocapture %varray) {
@@ -245,7 +245,7 @@ for.end:
!91 = distinct !{!91, !92, !93}
!92 = !{!"llvm.loop.vectorize.width", i32 8}
-!93 = !{!"llvm.loop.vectorize.enable", i1 true}
+!93 = !{!"llvm.loop.vectorize.enable"}
define void @exp_f32_intrin(ptr nocapture %varray) {
; CHECK-LABEL: @exp_f32_intrin
@@ -271,7 +271,7 @@ for.end:
!101 = distinct !{!101, !102, !103}
!102 = !{!"llvm.loop.vectorize.width", i32 8}
-!103 = !{!"llvm.loop.vectorize.enable", i1 true}
+!103 = !{!"llvm.loop.vectorize.enable"}
define void @log_f32(ptr nocapture %varray) {
@@ -298,7 +298,7 @@ for.end:
!111 = distinct !{!111, !112, !113}
!112 = !{!"llvm.loop.vectorize.width", i32 8}
-!113 = !{!"llvm.loop.vectorize.enable", i1 true}
+!113 = !{!"llvm.loop.vectorize.enable"}
define void @pow_f32(ptr nocapture %varray, ptr nocapture readonly %exp) {
; CHECK-LABEL: @pow_f32
@@ -326,7 +326,7 @@ for.end:
!121 = distinct !{!121, !122, !123}
!122 = !{!"llvm.loop.vectorize.width", i32 8}
-!123 = !{!"llvm.loop.vectorize.enable", i1 true}
+!123 = !{!"llvm.loop.vectorize.enable"}
define void @pow_f32_intrin(ptr nocapture %varray, ptr nocapture readonly %exp) {
; CHECK-LABEL: @pow_f32_intrin
@@ -354,7 +354,7 @@ for.end:
!131 = distinct !{!131, !132, !133}
!132 = !{!"llvm.loop.vectorize.width", i32 8}
-!133 = !{!"llvm.loop.vectorize.enable", i1 true}
+!133 = !{!"llvm.loop.vectorize.enable"}
define void @tan_f64(ptr nocapture %varray) {
; CHECK-LABEL: @tan_f64(
@@ -381,7 +381,7 @@ for.end:
!141 = distinct !{!141, !142, !143}
!142 = !{!"llvm.loop.vectorize.width", i32 2}
-!143 = !{!"llvm.loop.vectorize.enable", i1 true}
+!143 = !{!"llvm.loop.vectorize.enable"}
define void @tan_f32(ptr nocapture %varray) {
@@ -409,7 +409,7 @@ for.end:
!151 = distinct !{!151, !152, !153}
!152 = !{!"llvm.loop.vectorize.width", i32 8}
-!153 = !{!"llvm.loop.vectorize.enable", i1 true}
+!153 = !{!"llvm.loop.vectorize.enable"}
define void @tan_f64_intrinsic(ptr nocapture %varray) {
; CHECK-LABEL: @tan_f64_intrinsic(
@@ -436,7 +436,7 @@ for.end:
!161 = distinct !{!161, !162, !163}
!162 = !{!"llvm.loop.vectorize.width", i32 2}
-!163 = !{!"llvm.loop.vectorize.enable", i1 true}
+!163 = !{!"llvm.loop.vectorize.enable"}
define void @tan_f32_intrinsic(ptr nocapture %varray) {
; CHECK-LABEL: @tan_f32_intrinsic(
@@ -465,7 +465,7 @@ for.end:
!171 = distinct !{!171, !172, !173}
!172 = !{!"llvm.loop.vectorize.width", i32 8}
-!173 = !{!"llvm.loop.vectorize.enable", i1 true}
+!173 = !{!"llvm.loop.vectorize.enable"}
attributes #0 = { nounwind readnone }
diff --git a/llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls-finite.ll b/llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls-finite.ll
index 95aec377738b8..176ce4e05299f 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls-finite.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls-finite.ll
@@ -27,7 +27,7 @@ for.end:
!1 = distinct !{!1, !2, !3}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
define void @exp_f64(ptr nocapture %varray) {
; CHECK-LABEL: @exp_f64
@@ -54,7 +54,7 @@ for.end:
!11 = distinct !{!11, !12, !13}
!12 = !{!"llvm.loop.vectorize.width", i32 4}
-!13 = !{!"llvm.loop.vectorize.enable", i1 true}
+!13 = !{!"llvm.loop.vectorize.enable"}
define void @log_f32(ptr nocapture %varray) {
; CHECK-LABEL: @log_f32
@@ -81,7 +81,7 @@ for.end:
!21 = distinct !{!21, !22, !23}
!22 = !{!"llvm.loop.vectorize.width", i32 4}
-!23 = !{!"llvm.loop.vectorize.enable", i1 true}
+!23 = !{!"llvm.loop.vectorize.enable"}
define void @log_f64(ptr nocapture %varray) {
; CHECK-LABEL: @log_f64
@@ -108,7 +108,7 @@ for.end:
!31 = distinct !{!31, !32, !33}
!32 = !{!"llvm.loop.vectorize.width", i32 4}
-!33 = !{!"llvm.loop.vectorize.enable", i1 true}
+!33 = !{!"llvm.loop.vectorize.enable"}
define void @pow_f32(ptr nocapture %varray, ptr nocapture readonly %exp) {
; CHECK-LABEL: @pow_f32
@@ -137,7 +137,7 @@ for.end:
!41 = distinct !{!41, !42, !43}
!42 = !{!"llvm.loop.vectorize.width", i32 4}
-!43 = !{!"llvm.loop.vectorize.enable", i1 true}
+!43 = !{!"llvm.loop.vectorize.enable"}
define void @pow_f64(ptr nocapture %varray, ptr nocapture readonly %exp) {
; CHECK-LABEL: @pow_f64
@@ -166,7 +166,7 @@ for.end:
!51 = distinct !{!51, !52, !53}
!52 = !{!"llvm.loop.vectorize.width", i32 4}
-!53 = !{!"llvm.loop.vectorize.enable", i1 true}
+!53 = !{!"llvm.loop.vectorize.enable"}
declare float @__expf_finite(float) #0
declare double @__exp_finite(double) #0
diff --git a/llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls.ll b/llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls.ll
index 25e99bce44944..be9d90a71eb33 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls.ll
@@ -28,7 +28,7 @@ for.end:
!1 = distinct !{!1, !2, !3}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
define void @sin_f32(ptr nocapture %varray) {
@@ -56,7 +56,7 @@ for.end:
!21 = distinct !{!21, !22, !23}
!22 = !{!"llvm.loop.vectorize.width", i32 4}
-!23 = !{!"llvm.loop.vectorize.enable", i1 true}
+!23 = !{!"llvm.loop.vectorize.enable"}
define void @sin_f64_intrinsic(ptr nocapture %varray) {
; CHECK-LABEL: @sin_f64_intrinsic(
@@ -83,7 +83,7 @@ for.end:
!31 = distinct !{!31, !32, !33}
!32 = !{!"llvm.loop.vectorize.width", i32 4}
-!33 = !{!"llvm.loop.vectorize.enable", i1 true}
+!33 = !{!"llvm.loop.vectorize.enable"}
define void @sin_f32_intrinsic(ptr nocapture %varray) {
; CHECK-LABEL: @sin_f32_intrinsic(
@@ -110,7 +110,7 @@ for.end:
!41 = distinct !{!41, !42, !43}
!42 = !{!"llvm.loop.vectorize.width", i32 4}
-!43 = !{!"llvm.loop.vectorize.enable", i1 true}
+!43 = !{!"llvm.loop.vectorize.enable"}
define void @cos_f64(ptr nocapture %varray) {
; CHECK-LABEL: @cos_f64(
@@ -137,7 +137,7 @@ for.end:
!51 = distinct !{!51, !52, !53}
!52 = !{!"llvm.loop.vectorize.width", i32 4}
-!53 = !{!"llvm.loop.vectorize.enable", i1 true}
+!53 = !{!"llvm.loop.vectorize.enable"}
define void @cos_f32(ptr nocapture %varray) {
; CHECK-LABEL: @cos_f32(
@@ -164,7 +164,7 @@ for.end:
!61 = distinct !{!61, !62, !63}
!62 = !{!"llvm.loop.vectorize.width", i32 4}
-!63 = !{!"llvm.loop.vectorize.enable", i1 true}
+!63 = !{!"llvm.loop.vectorize.enable"}
define void @cos_f64_intrinsic(ptr nocapture %varray) {
; CHECK-LABEL: @cos_f64_intrinsic(
@@ -191,7 +191,7 @@ for.end:
!71 = distinct !{!71, !72, !73}
!72 = !{!"llvm.loop.vectorize.width", i32 4}
-!73 = !{!"llvm.loop.vectorize.enable", i1 true}
+!73 = !{!"llvm.loop.vectorize.enable"}
define void @cos_f32_intrinsic(ptr nocapture %varray) {
; CHECK-LABEL: @cos_f32_intrinsic(
@@ -218,7 +218,7 @@ for.end:
!81 = distinct !{!81, !82, !83}
!82 = !{!"llvm.loop.vectorize.width", i32 4}
-!83 = !{!"llvm.loop.vectorize.enable", i1 true}
+!83 = !{!"llvm.loop.vectorize.enable"}
define void @exp_f32(ptr nocapture %varray) {
@@ -245,7 +245,7 @@ for.end:
!91 = distinct !{!91, !92, !93}
!92 = !{!"llvm.loop.vectorize.width", i32 4}
-!93 = !{!"llvm.loop.vectorize.enable", i1 true}
+!93 = !{!"llvm.loop.vectorize.enable"}
define void @exp_f32_intrin(ptr nocapture %varray) {
; CHECK-LABEL: @exp_f32_intrin
@@ -271,7 +271,7 @@ for.end:
!101 = distinct !{!101, !102, !103}
!102 = !{!"llvm.loop.vectorize.width", i32 4}
-!103 = !{!"llvm.loop.vectorize.enable", i1 true}
+!103 = !{!"llvm.loop.vectorize.enable"}
define void @log_f32(ptr nocapture %varray) {
@@ -298,7 +298,7 @@ for.end:
!111 = distinct !{!111, !112, !113}
!112 = !{!"llvm.loop.vectorize.width", i32 4}
-!113 = !{!"llvm.loop.vectorize.enable", i1 true}
+!113 = !{!"llvm.loop.vectorize.enable"}
define void @pow_f32(ptr nocapture %varray, ptr nocapture readonly %exp) {
; CHECK-LABEL: @pow_f32
@@ -326,7 +326,7 @@ for.end:
!121 = distinct !{!121, !122, !123}
!122 = !{!"llvm.loop.vectorize.width", i32 4}
-!123 = !{!"llvm.loop.vectorize.enable", i1 true}
+!123 = !{!"llvm.loop.vectorize.enable"}
define void @pow_f32_intrin(ptr nocapture %varray, ptr nocapture readonly %exp) {
; CHECK-LABEL: @pow_f32_intrin
@@ -354,7 +354,7 @@ for.end:
!131 = distinct !{!131, !132, !133}
!132 = !{!"llvm.loop.vectorize.width", i32 4}
-!133 = !{!"llvm.loop.vectorize.enable", i1 true}
+!133 = !{!"llvm.loop.vectorize.enable"}
attributes #0 = { nounwind readnone }
@@ -401,7 +401,7 @@ for.end:
!134 = distinct !{!134, !135, !136}
!135 = !{!"llvm.loop.vectorize.width", i32 4}
-!136 = !{!"llvm.loop.vectorize.enable", i1 true}
+!136 = !{!"llvm.loop.vectorize.enable"}
define void @erfc_f32(ptr nocapture %varray) {
; CHECK-LABEL: @erfc_f32
@@ -427,7 +427,7 @@ for.end:
!137 = distinct !{!137, !138, !139}
!138 = !{!"llvm.loop.vectorize.width", i32 4}
-!139 = !{!"llvm.loop.vectorize.enable", i1 true}
+!139 = !{!"llvm.loop.vectorize.enable"}
define void @cbrt_f32(ptr nocapture %varray) {
; CHECK-LABEL: @cbrt_f32
@@ -453,7 +453,7 @@ for.end:
!140 = distinct !{!140, !141, !142}
!141 = !{!"llvm.loop.vectorize.width", i32 4}
-!142 = !{!"llvm.loop.vectorize.enable", i1 true}
+!142 = !{!"llvm.loop.vectorize.enable"}
define void @expm1_f32(ptr nocapture %varray) {
; CHECK-LABEL: @expm1_f32
@@ -479,7 +479,7 @@ for.end:
!143 = distinct !{!143, !144, !145}
!144 = !{!"llvm.loop.vectorize.width", i32 4}
-!145 = !{!"llvm.loop.vectorize.enable", i1 true}
+!145 = !{!"llvm.loop.vectorize.enable"}
define void @log1p_f32(ptr nocapture %varray) {
; CHECK-LABEL: @log1p_f32
@@ -505,7 +505,7 @@ for.end:
!146 = distinct !{!146, !147, !148}
!147 = !{!"llvm.loop.vectorize.width", i32 4}
-!148 = !{!"llvm.loop.vectorize.enable", i1 true}
+!148 = !{!"llvm.loop.vectorize.enable"}
define void @asinh_f32(ptr nocapture %varray) {
; CHECK-LABEL: @asinh_f32
@@ -531,7 +531,7 @@ for.end:
!149 = distinct !{!149, !150, !151}
!150 = !{!"llvm.loop.vectorize.width", i32 4}
-!151 = !{!"llvm.loop.vectorize.enable", i1 true}
+!151 = !{!"llvm.loop.vectorize.enable"}
define void @acosh_f32(ptr nocapture %varray) {
; CHECK-LABEL: @acosh_f32
@@ -557,7 +557,7 @@ for.end:
!152 = distinct !{!152, !153, !154}
!153 = !{!"llvm.loop.vectorize.width", i32 4}
-!154 = !{!"llvm.loop.vectorize.enable", i1 true}
+!154 = !{!"llvm.loop.vectorize.enable"}
define void @atanh_f32(ptr nocapture %varray) {
; CHECK-LABEL: @atanh_f32
@@ -583,7 +583,7 @@ for.end:
!155 = distinct !{!155, !156, !157}
!156 = !{!"llvm.loop.vectorize.width", i32 4}
-!157 = !{!"llvm.loop.vectorize.enable", i1 true}
+!157 = !{!"llvm.loop.vectorize.enable"}
@@ -621,7 +621,7 @@ for.end:
!158 = distinct !{!158, !159, !160}
!159 = !{!"llvm.loop.vectorize.width", i32 2}
-!160 = !{!"llvm.loop.vectorize.enable", i1 true}
+!160 = !{!"llvm.loop.vectorize.enable"}
define void @erfc_f64(ptr nocapture %varray) {
; CHECK-LABEL: @erfc_f64
@@ -647,7 +647,7 @@ for.end:
!161 = distinct !{!161, !162, !163}
!162 = !{!"llvm.loop.vectorize.width", i32 2}
-!163 = !{!"llvm.loop.vectorize.enable", i1 true}
+!163 = !{!"llvm.loop.vectorize.enable"}
define void @cbrt_f64(ptr nocapture %varray) {
; CHECK-LABEL: @cbrt_f64
@@ -673,7 +673,7 @@ for.end:
!164 = distinct !{!164, !165, !166}
!165 = !{!"llvm.loop.vectorize.width", i32 2}
-!166 = !{!"llvm.loop.vectorize.enable", i1 true}
+!166 = !{!"llvm.loop.vectorize.enable"}
define void @expm1_f64(ptr nocapture %varray) {
; CHECK-LABEL: @expm1_f64
@@ -699,7 +699,7 @@ for.end:
!167 = distinct !{!167, !168, !169}
!168 = !{!"llvm.loop.vectorize.width", i32 2}
-!169 = !{!"llvm.loop.vectorize.enable", i1 true}
+!169 = !{!"llvm.loop.vectorize.enable"}
define void @log1p_f64(ptr nocapture %varray) {
; CHECK-LABEL: @log1p_f64
@@ -725,7 +725,7 @@ for.end:
!170 = distinct !{!170, !171, !172}
!171 = !{!"llvm.loop.vectorize.width", i32 2}
-!172 = !{!"llvm.loop.vectorize.enable", i1 true}
+!172 = !{!"llvm.loop.vectorize.enable"}
define void @asinh_f64(ptr nocapture %varray) {
; CHECK-LABEL: @asinh_f64
@@ -751,7 +751,7 @@ for.end:
!173 = distinct !{!173, !174, !175}
!174 = !{!"llvm.loop.vectorize.width", i32 2}
-!175 = !{!"llvm.loop.vectorize.enable", i1 true}
+!175 = !{!"llvm.loop.vectorize.enable"}
define void @acosh_f64(ptr nocapture %varray) {
; CHECK-LABEL: @acosh_f64
@@ -777,7 +777,7 @@ for.end:
!176 = distinct !{!176, !177, !178}
!177 = !{!"llvm.loop.vectorize.width", i32 2}
-!178 = !{!"llvm.loop.vectorize.enable", i1 true}
+!178 = !{!"llvm.loop.vectorize.enable"}
define void @atanh_f64(ptr nocapture %varray) {
; CHECK-LABEL: @atanh_f64
@@ -803,5 +803,5 @@ for.end:
!179 = distinct !{!179, !180, !181}
!180 = !{!"llvm.loop.vectorize.width", i32 2}
-!181 = !{!"llvm.loop.vectorize.enable", i1 true}
+!181 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/no_fpmath.ll b/llvm/test/Transforms/LoopVectorize/X86/no_fpmath.ll
index e61e22e50ff56..ae77b4270ab3e 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/no_fpmath.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/no_fpmath.ll
@@ -90,7 +90,7 @@ for.body:
!24 = !DILocation(line: 17, column: 19, scope: !20)
!25 = !DILocation(line: 17, column: 11, scope: !20)
!26 = distinct !{!26, !27}
-!27 = !{!"llvm.loop.vectorize.enable", i1 true}
+!27 = !{!"llvm.loop.vectorize.enable"}
!28 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang",
file: !5,
isOptimized: true, flags: "-O2",
diff --git a/llvm/test/Transforms/LoopVectorize/X86/no_fpmath_with_hotness.ll b/llvm/test/Transforms/LoopVectorize/X86/no_fpmath_with_hotness.ll
index a4bfbcb8ca4d2..cbedbf7fd10c0 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/no_fpmath_with_hotness.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/no_fpmath_with_hotness.ll
@@ -92,7 +92,7 @@ for.body:
!24 = !DILocation(line: 17, column: 19, scope: !20)
!25 = !DILocation(line: 17, column: 11, scope: !20)
!26 = distinct !{!26, !27, !18}
-!27 = !{!"llvm.loop.vectorize.enable", i1 true}
+!27 = !{!"llvm.loop.vectorize.enable"}
!28 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang",
file: !5,
isOptimized: true, flags: "-O2",
diff --git a/llvm/test/Transforms/LoopVectorize/X86/outer-loop-non-power-of-2-type.ll b/llvm/test/Transforms/LoopVectorize/X86/outer-loop-non-power-of-2-type.ll
index d09f42ff558db..7c4f98670719f 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/outer-loop-non-power-of-2-type.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/outer-loop-non-power-of-2-type.ll
@@ -92,4 +92,4 @@ exit:
}
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll b/llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
index d41c83d8c959e..897c1287fa18f 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
@@ -115,4 +115,4 @@ exit:
}
!1 = distinct !{!1, !2}
-!2 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/redundant-vf2-cost.ll b/llvm/test/Transforms/LoopVectorize/X86/redundant-vf2-cost.ll
index 21146e2e82216..b3f2048e81663 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/redundant-vf2-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/redundant-vf2-cost.ll
@@ -31,4 +31,4 @@ exit:
}
!0 = !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs-max-bandwidth.ll b/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs-max-bandwidth.ll
index a33874a871443..a52e2c7a0dde8 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs-max-bandwidth.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs-max-bandwidth.ll
@@ -369,7 +369,7 @@ exit:
attributes #0 = { "target-cpu"="znver2" }
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
;.
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll b/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
index 8ad4876b367bc..d9c0cea9d6f67 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
@@ -1354,4 +1354,4 @@ attributes #0 = { "target-cpu"="znver2" }
attributes #1 = { "target-cpu"="slm" }
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/svml-calls-finite.ll b/llvm/test/Transforms/LoopVectorize/X86/svml-calls-finite.ll
index 6586b08e5c294..a768a38da5593 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/svml-calls-finite.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/svml-calls-finite.ll
@@ -33,7 +33,7 @@ for.end:
!1 = distinct !{!1, !2, !3}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
declare double @__exp_finite(double) #0
@@ -62,7 +62,7 @@ for.end:
!11 = distinct !{!11, !12, !13}
!12 = !{!"llvm.loop.vectorize.width", i32 4}
-!13 = !{!"llvm.loop.vectorize.enable", i1 true}
+!13 = !{!"llvm.loop.vectorize.enable"}
@@ -93,7 +93,7 @@ for.end:
!21 = distinct !{!21, !22, !23}
!22 = !{!"llvm.loop.vectorize.width", i32 4}
-!23 = !{!"llvm.loop.vectorize.enable", i1 true}
+!23 = !{!"llvm.loop.vectorize.enable"}
declare double @__log_finite(double) #0
@@ -122,7 +122,7 @@ for.end:
!31 = distinct !{!31, !32, !33}
!32 = !{!"llvm.loop.vectorize.width", i32 4}
-!33 = !{!"llvm.loop.vectorize.enable", i1 true}
+!33 = !{!"llvm.loop.vectorize.enable"}
declare float @__powf_finite(float, float) #0
@@ -153,7 +153,7 @@ for.end:
!41 = distinct !{!41, !42, !43}
!42 = !{!"llvm.loop.vectorize.width", i32 4}
-!43 = !{!"llvm.loop.vectorize.enable", i1 true}
+!43 = !{!"llvm.loop.vectorize.enable"}
declare double @__pow_finite(double, double) #0
@@ -184,7 +184,7 @@ for.end:
!51 = distinct !{!51, !52, !53}
!52 = !{!"llvm.loop.vectorize.width", i32 4}
-!53 = !{!"llvm.loop.vectorize.enable", i1 true}
+!53 = !{!"llvm.loop.vectorize.enable"}
declare float @__exp2f_finite(float) #0
@@ -213,7 +213,7 @@ for.end:
!61 = distinct !{!61, !62, !63}
!62 = !{!"llvm.loop.vectorize.width", i32 4}
-!63 = !{!"llvm.loop.vectorize.enable", i1 true}
+!63 = !{!"llvm.loop.vectorize.enable"}
declare double @__exp2_finite(double) #0
@@ -242,7 +242,7 @@ for.end:
!71 = distinct !{!71, !72, !73}
!72 = !{!"llvm.loop.vectorize.width", i32 4}
-!73 = !{!"llvm.loop.vectorize.enable", i1 true}
+!73 = !{!"llvm.loop.vectorize.enable"}
declare float @__log2f_finite(float) #0
@@ -270,7 +270,7 @@ for.end:
!81 = distinct !{!21, !22, !23}
!82 = !{!"llvm.loop.vectorize.width", i32 4}
-!83 = !{!"llvm.loop.vectorize.enable", i1 true}
+!83 = !{!"llvm.loop.vectorize.enable"}
declare double @__log2_finite(double) #0
@@ -299,7 +299,7 @@ for.end:
!91 = distinct !{!31, !32, !33}
!92 = !{!"llvm.loop.vectorize.width", i32 4}
-!93 = !{!"llvm.loop.vectorize.enable", i1 true}
+!93 = !{!"llvm.loop.vectorize.enable"}
declare float @__log10f_finite(float) #0
@@ -327,7 +327,7 @@ for.end:
!101 = distinct !{!21, !22, !23}
!102 = !{!"llvm.loop.vectorize.width", i32 4}
-!103 = !{!"llvm.loop.vectorize.enable", i1 true}
+!103 = !{!"llvm.loop.vectorize.enable"}
declare double @__log10_finite(double) #0
@@ -356,7 +356,7 @@ for.end:
!111 = distinct !{!31, !32, !33}
!112 = !{!"llvm.loop.vectorize.width", i32 4}
-!113 = !{!"llvm.loop.vectorize.enable", i1 true}
+!113 = !{!"llvm.loop.vectorize.enable"}
declare float @__sqrtf_finite(float) #0
@@ -384,7 +384,7 @@ for.end:
!121 = distinct !{!21, !22, !23}
!122 = !{!"llvm.loop.vectorize.width", i32 4}
-!123 = !{!"llvm.loop.vectorize.enable", i1 true}
+!123 = !{!"llvm.loop.vectorize.enable"}
declare double @__sqrt_finite(double) #0
@@ -413,4 +413,4 @@ for.end:
!131 = distinct !{!31, !32, !33}
!132 = !{!"llvm.loop.vectorize.width", i32 4}
-!133 = !{!"llvm.loop.vectorize.enable", i1 true}
+!133 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/tail_folding_and_assume_safety.ll b/llvm/test/Transforms/LoopVectorize/X86/tail_folding_and_assume_safety.ll
index 52c504b090ae1..a1def726e10ed 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/tail_folding_and_assume_safety.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/tail_folding_and_assume_safety.ll
@@ -143,7 +143,7 @@ for.inc:
attributes #0 = { "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" }
!6 = distinct !{!6, !7}
-!7 = !{!"llvm.loop.vectorize.enable", i1 true}
+!7 = !{!"llvm.loop.vectorize.enable"}
!8 = distinct !{!8, !9}
!9 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll b/llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
index 90866061c4188..e5b88dd5219db 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
@@ -172,7 +172,7 @@ attributes #0 = { optsize "target-cpu"="core-avx2" "target-features"="+avx,+avx2
!6 = distinct !{!6, !7, !8}
!7 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
-!8 = !{!"llvm.loop.vectorize.enable", i1 true}
+!8 = !{!"llvm.loop.vectorize.enable"}
!10 = distinct !{!10, !11}
!11 = !{!"llvm.loop.vectorize.predicate.enable", i1 false}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.ll b/llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.ll
index dd30c045182e4..0333344025de1 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.ll
@@ -49,7 +49,7 @@ for.end:
}
!1 = !{!1, !2, !{!"llvm.loop.parallel_accesses", !11}}
-!2 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.enable"}
!11 = distinct !{}
;
diff --git a/llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll b/llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
index 78b14423578fb..98c0a3661fa1c 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
@@ -107,7 +107,7 @@ for.end:
}
!1 = !{!1, !2, !{!"llvm.loop.parallel_accesses", !11}}
-!2 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.enable"}
!11 = distinct !{}
;
diff --git a/llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll b/llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll
index 5f2a93b230995..c389765dff2d1 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll
@@ -320,7 +320,7 @@ declare i32 @foo(...)
!12 = !DILocation(line: 3, column: 8, scope: !13)
!13 = distinct !DILexicalBlock(line: 3, column: 3, file: !1, scope: !4)
!14 = !{!14, !15, !15}
-!15 = !{!"llvm.loop.vectorize.enable", i1 true}
+!15 = !{!"llvm.loop.vectorize.enable"}
!16 = !DILocation(line: 4, column: 5, scope: !17)
!17 = distinct !DILexicalBlock(line: 3, column: 36, file: !1, scope: !13)
!22 = !DILocation(line: 5, column: 9, scope: !23)
diff --git a/llvm/test/Transforms/LoopVectorize/alias-mask.ll b/llvm/test/Transforms/LoopVectorize/alias-mask.ll
index 44f962cc59ffa..47e2cd8f9f3ec 100644
--- a/llvm/test/Transforms/LoopVectorize/alias-mask.ll
+++ b/llvm/test/Transforms/LoopVectorize/alias-mask.ll
@@ -650,4 +650,4 @@ exit:
!2 = distinct !{!2, !3}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/dbg-outer-loop-vect.ll b/llvm/test/Transforms/LoopVectorize/dbg-outer-loop-vect.ll
index 45fa8d19952a4..ab61d2aa710ce 100644
--- a/llvm/test/Transforms/LoopVectorize/dbg-outer-loop-vect.ll
+++ b/llvm/test/Transforms/LoopVectorize/dbg-outer-loop-vect.ll
@@ -131,7 +131,7 @@ exit:
!30 = !DILocation(line: 10, column: 24, scope: !16)
!31 = distinct !{!31, !21, !32, !33}
!32 = !DILocation(line: 13, column: 13, scope: !12)
-!33 = !{!"llvm.loop.vectorize.enable", i1 true}
+!33 = !{!"llvm.loop.vectorize.enable"}
!34 = !DILocation(line: 10, column: 5, scope: !12)
;.
; CHECK: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C11, file: [[META1:![0-9]+]], producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None)
diff --git a/llvm/test/Transforms/LoopVectorize/diag-disabled-vectorization-msgs.ll b/llvm/test/Transforms/LoopVectorize/diag-disabled-vectorization-msgs.ll
index 31454401876b6..da41fa7a9da93 100644
--- a/llvm/test/Transforms/LoopVectorize/diag-disabled-vectorization-msgs.ll
+++ b/llvm/test/Transforms/LoopVectorize/diag-disabled-vectorization-msgs.ll
@@ -63,7 +63,7 @@ exit:
ret void
}
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 false}
+!1 = !{!"llvm.loop.vectorize.disable"}
; ALL-LABEL: 'disable_nonforced' from <stdin>
; ALL-NOT: LV: We can vectorize this loop
diff --git a/llvm/test/Transforms/LoopVectorize/disable_nonforced_enable.ll b/llvm/test/Transforms/LoopVectorize/disable_nonforced_enable.ll
index 8c4e50fdd7a61..e7622d30f5e2c 100644
--- a/llvm/test/Transforms/LoopVectorize/disable_nonforced_enable.ll
+++ b/llvm/test/Transforms/LoopVectorize/disable_nonforced_enable.ll
@@ -26,4 +26,4 @@ for.end:
ret void
}
-!0 = !{!0, !{!"llvm.loop.disable_nonforced"}, !{!"llvm.loop.vectorize.enable", i32 1}}
+!0 = !{!0, !{!"llvm.loop.disable_nonforced"}, !{!"llvm.loop.vectorize.enable"}}
diff --git a/llvm/test/Transforms/LoopVectorize/explicit_outer_detection.ll b/llvm/test/Transforms/LoopVectorize/explicit_outer_detection.ll
index a610f0669f483..7393ad8ea4dab 100644
--- a/llvm/test/Transforms/LoopVectorize/explicit_outer_detection.ll
+++ b/llvm/test/Transforms/LoopVectorize/explicit_outer_detection.ll
@@ -219,7 +219,7 @@ for.end15:
; Case 1
!6 = distinct !{!6, !7, !8}
!7 = !{!"llvm.loop.vectorize.width", i32 4}
-!8 = !{!"llvm.loop.vectorize.enable", i1 true}
+!8 = !{!"llvm.loop.vectorize.enable"}
; Case 2
!9 = distinct !{!9, !8}
; Case 3
diff --git a/llvm/test/Transforms/LoopVectorize/explicit_outer_nonuniform_inner.ll b/llvm/test/Transforms/LoopVectorize/explicit_outer_nonuniform_inner.ll
index ef6fabb11694b..9c87b9cb1e818 100644
--- a/llvm/test/Transforms/LoopVectorize/explicit_outer_nonuniform_inner.ll
+++ b/llvm/test/Transforms/LoopVectorize/explicit_outer_nonuniform_inner.ll
@@ -161,4 +161,4 @@ for.end15:
!6 = distinct !{!6, !7, !8}
!7 = !{!"llvm.loop.vectorize.width", i32 8}
-!8 = !{!"llvm.loop.vectorize.enable", i1 true}
+!8 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/explicit_outer_uniform_diverg_branch.ll b/llvm/test/Transforms/LoopVectorize/explicit_outer_uniform_diverg_branch.ll
index 2152c48c61e81..75858e626b728 100644
--- a/llvm/test/Transforms/LoopVectorize/explicit_outer_uniform_diverg_branch.ll
+++ b/llvm/test/Transforms/LoopVectorize/explicit_outer_uniform_diverg_branch.ll
@@ -124,4 +124,4 @@ for.end19:
!6 = distinct !{!6, !7, !8}
!7 = !{!"llvm.loop.vectorize.width", i32 8}
-!8 = !{!"llvm.loop.vectorize.enable", i1 true}
+!8 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/make-followup-loop-id.ll b/llvm/test/Transforms/LoopVectorize/make-followup-loop-id.ll
index 1fe802f9e1093..6e10cb0181629 100644
--- a/llvm/test/Transforms/LoopVectorize/make-followup-loop-id.ll
+++ b/llvm/test/Transforms/LoopVectorize/make-followup-loop-id.ll
@@ -108,7 +108,7 @@ exit:
ret void
}
!0 = distinct !{!0, !1, !2}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
!2 = !{!"llvm.loop.vectorize.followup_all", !3, !4}
!3 = !{!"llvm.loop.isvectorized"}
!4 = !{!"llvm.loop.unroll.count", i32 8}
diff --git a/llvm/test/Transforms/LoopVectorize/memdep-fold-tail.ll b/llvm/test/Transforms/LoopVectorize/memdep-fold-tail.ll
index 69e97069ae498..fc6cfe5942254 100644
--- a/llvm/test/Transforms/LoopVectorize/memdep-fold-tail.ll
+++ b/llvm/test/Transforms/LoopVectorize/memdep-fold-tail.ll
@@ -89,4 +89,4 @@ for.end:
}
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/nested-outer-loop-vect.ll b/llvm/test/Transforms/LoopVectorize/nested-outer-loop-vect.ll
index c6bb905988dba..2c2946448ee79 100644
--- a/llvm/test/Transforms/LoopVectorize/nested-outer-loop-vect.ll
+++ b/llvm/test/Transforms/LoopVectorize/nested-outer-loop-vect.ll
@@ -87,4 +87,4 @@ exit:
!1 = distinct !{!1, !2, !3}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/no-fold-tail-by-masking-iv-external-uses.ll b/llvm/test/Transforms/LoopVectorize/no-fold-tail-by-masking-iv-external-uses.ll
index 93c81c02d4e5d..6a80b02aaf50e 100644
--- a/llvm/test/Transforms/LoopVectorize/no-fold-tail-by-masking-iv-external-uses.ll
+++ b/llvm/test/Transforms/LoopVectorize/no-fold-tail-by-masking-iv-external-uses.ll
@@ -129,7 +129,7 @@ done:
!0 = distinct !{!0, !1, !2, !3}
!1 = !{!"llvm.loop.unroll.disable"}
!2 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
;.
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]], [[META3:![0-9]+]]}
; CHECK: [[META1]] = !{!"llvm.loop.unroll.disable"}
diff --git a/llvm/test/Transforms/LoopVectorize/no_array_bounds.ll b/llvm/test/Transforms/LoopVectorize/no_array_bounds.ll
index bfa9263bb5cf7..2f23747f44f9c 100644
--- a/llvm/test/Transforms/LoopVectorize/no_array_bounds.ll
+++ b/llvm/test/Transforms/LoopVectorize/no_array_bounds.ll
@@ -79,7 +79,7 @@ for.end15:
!10 = !DILocation(line: 4, column: 8, scope: !11)
!11 = distinct !DILexicalBlock(line: 4, column: 3, file: !1, scope: !4)
!12 = !{!12, !13}
-!13 = !{!"llvm.loop.vectorize.enable", i1 true}
+!13 = !{!"llvm.loop.vectorize.enable"}
!14 = !DILocation(line: 5, column: 5, scope: !15)
!15 = distinct !DILexicalBlock(line: 4, column: 36, file: !1, scope: !11)
!16 = !DILocation(line: 9, column: 8, scope: !17)
diff --git a/llvm/test/Transforms/LoopVectorize/no_array_bounds_scalable.ll b/llvm/test/Transforms/LoopVectorize/no_array_bounds_scalable.ll
index 2c1f485aab080..c00086ea9496e 100644
--- a/llvm/test/Transforms/LoopVectorize/no_array_bounds_scalable.ll
+++ b/llvm/test/Transforms/LoopVectorize/no_array_bounds_scalable.ll
@@ -63,7 +63,7 @@ for.end:
}
!0 = distinct !{!0, !1, !2}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
!2 = !{!"llvm.loop.vectorize.width", i32 1}
!3 = distinct !{!3, !1, !2, !4}
!4 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
diff --git a/llvm/test/Transforms/LoopVectorize/no_switch.ll b/llvm/test/Transforms/LoopVectorize/no_switch.ll
index c3662f1b4be5d..531dfd0aed5f0 100644
--- a/llvm/test/Transforms/LoopVectorize/no_switch.ll
+++ b/llvm/test/Transforms/LoopVectorize/no_switch.ll
@@ -72,7 +72,7 @@ for.end:
!10 = !DILocation(line: 3, column: 8, scope: !11)
!11 = distinct !DILexicalBlock(line: 3, column: 3, file: !1, scope: !4)
!12 = !{!12, !13, !13}
-!13 = !{!"llvm.loop.vectorize.enable", i1 true}
+!13 = !{!"llvm.loop.vectorize.enable"}
!14 = !DILocation(line: 4, column: 5, scope: !15)
!15 = distinct !DILexicalBlock(line: 3, column: 36, file: !1, scope: !11)
!16 = !{!17, !17, i64 0}
diff --git a/llvm/test/Transforms/LoopVectorize/no_switch_disable_vectorization.ll b/llvm/test/Transforms/LoopVectorize/no_switch_disable_vectorization.ll
index d73264dc01836..4c989e0b3428a 100644
--- a/llvm/test/Transforms/LoopVectorize/no_switch_disable_vectorization.ll
+++ b/llvm/test/Transforms/LoopVectorize/no_switch_disable_vectorization.ll
@@ -76,7 +76,7 @@ for.end:
!10 = !DILocation(line: 3, column: 8, scope: !11)
!11 = distinct !DILexicalBlock(line: 3, column: 3, file: !1, scope: !4)
!12 = !{!12, !13, !13}
-!13 = !{!"llvm.loop.vectorize.enable", i1 false}
+!13 = !{!"llvm.loop.vectorize.disable"}
!14 = !DILocation(line: 4, column: 5, scope: !15)
!15 = distinct !DILexicalBlock(line: 3, column: 36, file: !1, scope: !11)
!16 = !{!17, !17, i64 0}
diff --git a/llvm/test/Transforms/LoopVectorize/noalias-scope-decl-outer-loop.ll b/llvm/test/Transforms/LoopVectorize/noalias-scope-decl-outer-loop.ll
index 8020480f0dc65..efbfc49a21804 100644
--- a/llvm/test/Transforms/LoopVectorize/noalias-scope-decl-outer-loop.ll
+++ b/llvm/test/Transforms/LoopVectorize/noalias-scope-decl-outer-loop.ll
@@ -66,7 +66,7 @@ exit:
!0 = distinct !{!0, !1, !2}
!1 = !{!"llvm.loop.mustprogress"}
-!2 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.enable"}
!3 = !{!4}
!4 = distinct !{!4, !5}
!5 = distinct !{!5}
diff --git a/llvm/test/Transforms/LoopVectorize/non-widenable-intrinsics-outer-loop.ll b/llvm/test/Transforms/LoopVectorize/non-widenable-intrinsics-outer-loop.ll
index 2c46af4ccbfe2..e59e5fbfb12fb 100644
--- a/llvm/test/Transforms/LoopVectorize/non-widenable-intrinsics-outer-loop.ll
+++ b/llvm/test/Transforms/LoopVectorize/non-widenable-intrinsics-outer-loop.ll
@@ -454,4 +454,4 @@ exit:
!0 = distinct !{!0, !1, !2}
!1 = !{!"llvm.loop.mustprogress"}
-!2 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/optsize.ll b/llvm/test/Transforms/LoopVectorize/optsize.ll
index 2fe02c62c7790..294dbbbb3a5e2 100644
--- a/llvm/test/Transforms/LoopVectorize/optsize.ll
+++ b/llvm/test/Transforms/LoopVectorize/optsize.ll
@@ -1071,7 +1071,7 @@ exit:
!13 = !{i32 999999, i64 1, i32 2}
!14 = !{!"function_entry_count", i64 0}
!15 = distinct !{!15, !16}
-!16 = !{!"llvm.loop.vectorize.enable", i1 true}
+!16 = !{!"llvm.loop.vectorize.enable"}
;.
; CHECK: [[PROF14]] = !{!"function_entry_count", i64 0}
; CHECK: [[LOOP15]] = distinct !{[[LOOP15]], [[META16:![0-9]+]], [[META17:![0-9]+]]}
diff --git a/llvm/test/Transforms/LoopVectorize/outer-loop-atomic.ll b/llvm/test/Transforms/LoopVectorize/outer-loop-atomic.ll
index 6e19f71736544..2618f15665b7d 100644
--- a/llvm/test/Transforms/LoopVectorize/outer-loop-atomic.ll
+++ b/llvm/test/Transforms/LoopVectorize/outer-loop-atomic.ll
@@ -165,4 +165,4 @@ exit:
!0 = distinct !{!0, !1, !2}
!1 = !{!"llvm.loop.vectorize.width", i32 4}
-!2 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/outer-loop-inner-latch-successors.ll b/llvm/test/Transforms/LoopVectorize/outer-loop-inner-latch-successors.ll
index ef588bfda0aaf..7f17eac762fd1 100644
--- a/llvm/test/Transforms/LoopVectorize/outer-loop-inner-latch-successors.ll
+++ b/llvm/test/Transforms/LoopVectorize/outer-loop-inner-latch-successors.ll
@@ -209,4 +209,4 @@ exit:
!1 = distinct !{!1, !2, !3}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/outer-loop-vec-phi-predecessor-order.ll b/llvm/test/Transforms/LoopVectorize/outer-loop-vec-phi-predecessor-order.ll
index 4c0b5c618d7ac..045f0f58847c4 100644
--- a/llvm/test/Transforms/LoopVectorize/outer-loop-vec-phi-predecessor-order.ll
+++ b/llvm/test/Transforms/LoopVectorize/outer-loop-vec-phi-predecessor-order.ll
@@ -119,4 +119,4 @@ exit:
!0 = distinct !{!0, !1, !2}
!1 = !{!"llvm.loop.vectorize.width", i32 4}
-!2 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/outer-loop-wide-phis.ll b/llvm/test/Transforms/LoopVectorize/outer-loop-wide-phis.ll
index 47b02f17a83ce..9dcd86560c597 100644
--- a/llvm/test/Transforms/LoopVectorize/outer-loop-wide-phis.ll
+++ b/llvm/test/Transforms/LoopVectorize/outer-loop-wide-phis.ll
@@ -163,4 +163,4 @@ exit:
!1 = distinct !{!1, !2, !3}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/outer_loop_contiguous.ll b/llvm/test/Transforms/LoopVectorize/outer_loop_contiguous.ll
index 374d6348cd8f1..fce653b53e370 100644
--- a/llvm/test/Transforms/LoopVectorize/outer_loop_contiguous.ll
+++ b/llvm/test/Transforms/LoopVectorize/outer_loop_contiguous.ll
@@ -287,4 +287,4 @@ exit:
!0 = distinct !{!0, !1, !2}
!1 = !{!"llvm.loop.vectorize.width", i32 4}
-!2 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/outer_loop_early_exit.ll b/llvm/test/Transforms/LoopVectorize/outer_loop_early_exit.ll
index e0ad90d9c2bc0..a5442f4cdb7f0 100644
--- a/llvm/test/Transforms/LoopVectorize/outer_loop_early_exit.ll
+++ b/llvm/test/Transforms/LoopVectorize/outer_loop_early_exit.ll
@@ -46,4 +46,4 @@ for.end:
!1 = distinct !{!1, !2, !3}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/outer_loop_hcfg_construction.ll b/llvm/test/Transforms/LoopVectorize/outer_loop_hcfg_construction.ll
index f5bff42989a27..e80129333a4a7 100644
--- a/llvm/test/Transforms/LoopVectorize/outer_loop_hcfg_construction.ll
+++ b/llvm/test/Transforms/LoopVectorize/outer_loop_hcfg_construction.ll
@@ -318,4 +318,4 @@ innermost.loop.j1:
!3 = distinct !{!3, !4, !5, !6}
!4 = !{!"llvm.loop.vectorize.width", i32 4}
!5 = !{!"llvm.loop.vectorize.scalable.enable", i1 false}
-!6 = !{!"llvm.loop.vectorize.enable", i1 true}
+!6 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll b/llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
index 622c6bd4e09c4..511fec315dd10 100644
--- a/llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
+++ b/llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
@@ -136,6 +136,6 @@ exit:
}
!1 = distinct !{!1, !2, !3, !4}
-!2 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.enable"}
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
!4 = !{!"llvm.loop.vectorize.width", i32 4}
diff --git a/llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll b/llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll
index 624571294c278..6081725aab9d7 100644
--- a/llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll
+++ b/llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll
@@ -87,4 +87,4 @@ exit:
!1 = distinct !{!1, !2, !3}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll b/llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
index 9d82bef576638..7e07fcc0dc41d 100644
--- a/llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
+++ b/llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
@@ -157,4 +157,4 @@ exit:
!1 = distinct !{!1, !2, !3}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll b/llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
index 24c42b8b48e44..4751570432927 100644
--- a/llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
+++ b/llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
@@ -612,4 +612,4 @@ for.end:
!6 = distinct !{!6, !7, !8}
!7 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
-!8 = !{!"llvm.loop.vectorize.enable", i1 true}
+!8 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll b/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
index 241360af4fb01..73ce57b156952 100644
--- a/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
+++ b/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
@@ -3139,4 +3139,4 @@ for.exit:
!6 = distinct !{!6, !7, !8}
!7 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
-!8 = !{!"llvm.loop.vectorize.enable", i1 true}
+!8 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/remove_metadata.ll b/llvm/test/Transforms/LoopVectorize/remove_metadata.ll
index 96de172a0ea7c..de9f2467a6d3e 100644
--- a/llvm/test/Transforms/LoopVectorize/remove_metadata.ll
+++ b/llvm/test/Transforms/LoopVectorize/remove_metadata.ll
@@ -25,7 +25,7 @@ for.end:
ret void
}
-!0 = !{!0, !{!"llvm.loop.vectorize.some_property"}, !{!"llvm.loop.vectorize.enable", i32 1}}
+!0 = !{!0, !{!"llvm.loop.vectorize.some_property"}, !{!"llvm.loop.vectorize.enable"}}
; CHECK-NOT: llvm.loop.vectorize.
; CHECK: {!"llvm.loop.isvectorized", i32 1}
diff --git a/llvm/test/Transforms/LoopVectorize/runtime-check-threshold-with-force-metadata.ll b/llvm/test/Transforms/LoopVectorize/runtime-check-threshold-with-force-metadata.ll
index 5376eb86882b7..d4854fbcf9c75 100644
--- a/llvm/test/Transforms/LoopVectorize/runtime-check-threshold-with-force-metadata.ll
+++ b/llvm/test/Transforms/LoopVectorize/runtime-check-threshold-with-force-metadata.ll
@@ -79,12 +79,12 @@ exit:
!0 = distinct !{!0, !2, !3}
!1 = !{!"llvm.loop.mustprogress"}
!2 = !{!"llvm.loop.vectorize.width", i32 2}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
;.
; LIMIT0: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; LIMIT0: [[META1]] = !{!"llvm.loop.vectorize.width", i32 2}
-; LIMIT0: [[META2]] = !{!"llvm.loop.vectorize.enable", i1 true}
+; LIMIT0: [[META2]] = !{!"llvm.loop.vectorize.enable"}
;.
; LIMIT1: [[META0]] = !{[[META1:![0-9]+]]}
; LIMIT1: [[META1]] = distinct !{[[META1]], [[META2:![0-9]+]]}
diff --git a/llvm/test/Transforms/LoopVectorize/runtime-check.ll b/llvm/test/Transforms/LoopVectorize/runtime-check.ll
index 4eb806a29f018..58f8981e19401 100644
--- a/llvm/test/Transforms/LoopVectorize/runtime-check.ll
+++ b/llvm/test/Transforms/LoopVectorize/runtime-check.ll
@@ -598,4 +598,4 @@ exit:
!11 = !{i32 2, !"Debug Info Version", i32 3}
!12 = distinct !{!12, !13, !14}
!13 = !{!"llvm.loop.vectorize.width", i32 2}
-!14 = !{!"llvm.loop.vectorize.enable", i1 true}
+!14 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/scalable-inductions.ll b/llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
index 857d6dc111c0a..d8b7d21c5d086 100644
--- a/llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
+++ b/llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
@@ -308,7 +308,7 @@ exit:
!2 = !{!"llvm.loop.vectorize.width", i32 2}
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
!4 = !{!"llvm.loop.interleave.count", i32 2}
-!5 = !{!"llvm.loop.vectorize.enable", i1 true}
+!5 = !{!"llvm.loop.vectorize.enable"}
!6 = distinct !{!6, !1, !7, !3, !8, !5}
!7 = !{!"llvm.loop.vectorize.width", i32 4}
!8 = !{!"llvm.loop.interleave.count", i32 1}
diff --git a/llvm/test/Transforms/LoopVectorize/unsafe-vf-hint-remark.ll b/llvm/test/Transforms/LoopVectorize/unsafe-vf-hint-remark.ll
index 4fab0c38dd0da..fe8410adb8bae 100644
--- a/llvm/test/Transforms/LoopVectorize/unsafe-vf-hint-remark.ll
+++ b/llvm/test/Transforms/LoopVectorize/unsafe-vf-hint-remark.ll
@@ -48,4 +48,4 @@ exit:
!0 = !{!0, !1, !2}
!1 = !{!"llvm.loop.vectorize.width", i32 4}
-!2 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll b/llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
index 33a772285e423..5d65362df3cc2 100644
--- a/llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
+++ b/llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
@@ -245,4 +245,4 @@ end:
!1 = distinct !{!1, !2, !3}
!2 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll b/llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
index 2c268664ef991..eb3ad35df5bc5 100644
--- a/llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
+++ b/llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
@@ -14,7 +14,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
; CHECK-LABEL: @foo
; CHECK: !llvm.loop !0
; CHECK: !0 = distinct !{!0, !1}
-; CHECK: !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+; CHECK: !1 = !{!"llvm.loop.vectorize.enable"}
define i32 @foo(i32 %a) {
entry:
br label %loop_cond
@@ -33,4 +33,4 @@ return:
}
!0 = !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-predicated-early-exit.ll b/llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-predicated-early-exit.ll
index cd68c81f94054..ce0da2efcab20 100644
--- a/llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-predicated-early-exit.ll
+++ b/llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-predicated-early-exit.ll
@@ -51,4 +51,4 @@ exit:
!0 = distinct !{!0, !1, !2, !3}
!1 = !{!"llvm.loop.mustprogress"}
!2 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
-!3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!3 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll b/llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
index efc29b3c8a32d..358082968efe4 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
+++ b/llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
@@ -44,4 +44,4 @@ exit:
}
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll b/llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
index 3dbffd092b6cb..9db89d13c3727 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
+++ b/llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
@@ -89,7 +89,7 @@ exit:
}
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
;.
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll b/llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
index a5d367873991c..604e0a56fd81d 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
+++ b/llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
@@ -122,11 +122,11 @@ exit:
declare void @use()
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
;.
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META4:![0-9]+]]}
-; CHECK: [[META4]] = !{!"llvm.loop.vectorize.enable", i1 true}
+; CHECK: [[META4]] = !{!"llvm.loop.vectorize.enable"}
;.
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll b/llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
index 4a2952a2d95ba..caeda9e54319c 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
+++ b/llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
@@ -260,4 +260,4 @@ exit:
ret void
}
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/Oz-and-forced-vectorize.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/Oz-and-forced-vectorize.ll
index 049d1baf5c615..0ab38d96bfe4c 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/Oz-and-forced-vectorize.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/Oz-and-forced-vectorize.ll
@@ -78,4 +78,4 @@ for.cond.cleanup:
}
!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/loop-vectorize-metadata.ll b/llvm/test/Transforms/PhaseOrdering/X86/loop-vectorize-metadata.ll
index e27584bb421f1..15c4b10ec71b2 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/loop-vectorize-metadata.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/loop-vectorize-metadata.ll
@@ -1163,6 +1163,6 @@ for.end: ; preds = %for.body
}
!0 = !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable", i1 1}
+!1 = !{!"llvm.loop.vectorize.enable"}
!2 = !{!2, !3}
-!3 = !{!"llvm.loop.vectorize.enable", i1 0}
+!3 = !{!"llvm.loop.vectorize.disable"}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/preserve-access-group.ll b/llvm/test/Transforms/PhaseOrdering/X86/preserve-access-group.ll
index fe4f81a6f4749..a66528f1f12b4 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/preserve-access-group.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/preserve-access-group.ll
@@ -187,7 +187,7 @@ attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
!15 = distinct !{!15, !16, !17, !18}
!16 = !{!"llvm.loop.mustprogress"}
!17 = !{!"llvm.loop.parallel_accesses", !12}
-!18 = !{!"llvm.loop.vectorize.enable", i1 true}
+!18 = !{!"llvm.loop.vectorize.enable"}
;.
; CHECK: [[INT_TBAA0]] = !{[[META1:![0-9]+]], [[META1]], i64 0}
diff --git a/llvm/test/Transforms/SROA/mem-par-metadata-sroa.ll b/llvm/test/Transforms/SROA/mem-par-metadata-sroa.ll
index 82ebdaa900fe1..dec130bd533d6 100644
--- a/llvm/test/Transforms/SROA/mem-par-metadata-sroa.ll
+++ b/llvm/test/Transforms/SROA/mem-par-metadata-sroa.ll
@@ -113,7 +113,7 @@ declare void @llvm.memcpy.p0.p0.i64(ptr nocapture writeonly, ptr nocapture reado
!0 = !{!"clang version 4.0.0 (cfe/trunk 277751)"}
!1 = distinct !{!1, !2, !{!"llvm.loop.parallel_accesses", !11}}
-!2 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.enable"}
!3 = !{!4}
!4 = distinct !{!4, !5, !"_ZNK7ComplexplERKS_: %agg.result"}
!5 = distinct !{!5, !"_ZNK7ComplexplERKS_"}
diff --git a/llvm/test/Transforms/SimplifyCFG/X86/combine-parallel-mem-md.ll b/llvm/test/Transforms/SimplifyCFG/X86/combine-parallel-mem-md.ll
index 8c5733e5babed..d334adc2ceb6e 100644
--- a/llvm/test/Transforms/SimplifyCFG/X86/combine-parallel-mem-md.ll
+++ b/llvm/test/Transforms/SimplifyCFG/X86/combine-parallel-mem-md.ll
@@ -52,5 +52,5 @@ for.end: ; preds = %cond.end
attributes #0 = { norecurse nounwind uwtable }
!0 = distinct !{!0, !1, !{!"llvm.loop.parallel_accesses", !10}}
-!1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!1 = !{!"llvm.loop.vectorize.enable"}
!10 = distinct !{}
diff --git a/llvm/test/Verifier/llvm.loop-cu-strip-followup.ll b/llvm/test/Verifier/llvm.loop-cu-strip-followup.ll
index 25a09b15ca652..833c76276e458 100644
--- a/llvm/test/Verifier/llvm.loop-cu-strip-followup.ll
+++ b/llvm/test/Verifier/llvm.loop-cu-strip-followup.ll
@@ -23,7 +23,7 @@ define hidden void @f() {
; CHECK-NOT: DILocation
; CHECK: [[LID]] = distinct !{[[LID]], [[VE:![0-9]+]], [[VF:![0-9]+]]}
; CHECK-NOT: DILocation
-; CHECK: [[VE]] = !{!"llvm.loop.vectorize.enable", i1 true}
+; CHECK: [[VE]] = !{!"llvm.loop.vectorize.enable"}
; CHECK: [[VF]] = !{!"llvm.loop.vectorize.followup_all", [[FU:![0-9]+]]}
; CHECK: [[FU]] = distinct !{[[FU]], [[VD:![0-9]+]], [[UC:![0-9]+]]}
; CHECK: [[VD]] = !{!"llvm.loop.isvectorized"}
@@ -40,7 +40,7 @@ define hidden void @f() {
!8 = !{}
!9 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !5, isOptimized: false, runtimeVersion: 0, emissionKind: NoDebug)
!10 = !DILocation(line: 6, column: 1, scope: !4)
-!11 = !{!"llvm.loop.vectorize.enable", i1 true}
+!11 = !{!"llvm.loop.vectorize.enable"}
!12 = !{!"llvm.loop.vectorize.followup_all", !13}
!13 = distinct !{!13, !3, !10, !14, !15}
!14 = !{!"llvm.loop.isvectorized"}
diff --git a/llvm/test/Verifier/llvm.loop.vectorize.ll b/llvm/test/Verifier/llvm.loop.vectorize.ll
new file mode 100644
index 0000000000000..f1767fb66eeb1
--- /dev/null
+++ b/llvm/test/Verifier/llvm.loop.vectorize.ll
@@ -0,0 +1,41 @@
+; Test "llvm.loop.vectorize.enable" / "llvm.loop.vectorize.disable"
+; single-operand validation.
+
+; DEFINE: %{VERIFY} = llvm-as -disable-output %t 2>&1
+
+define void @test() {
+entry:
+ br label %body
+body:
+ br i1 0, label %body, label %exit, !llvm.loop !0
+exit:
+ ret void
+}
+!0 = distinct !{!0, !1}
+
+; BAD: Expecting only the metadata name
+
+; Single-operand enable.
+; RUN: cat %s > %t
+; RUN: echo '!1 = !{!"llvm.loop.vectorize.enable"}' >> %t
+; RUN: %{VERIFY}
+
+; Single-operand disable.
+; RUN: cat %s > %t
+; RUN: echo '!1 = !{!"llvm.loop.vectorize.disable"}' >> %t
+; RUN: %{VERIFY}
+
+; Two-operand enable with boolean false (legacy form, now rejected).
+; RUN: cat %s > %t
+; RUN: echo '!1 = !{!"llvm.loop.vectorize.enable", i1 0}' >> %t
+; RUN: not %{VERIFY} | FileCheck %s -check-prefix=BAD
+
+; Two-operand enable with boolean true (legacy form, now rejected).
+; RUN: cat %s > %t
+; RUN: echo '!1 = !{!"llvm.loop.vectorize.enable", i1 1}' >> %t
+; RUN: not %{VERIFY} | FileCheck %s -check-prefix=BAD
+
+; Two-operand disable (rejected).
+; RUN: cat %s > %t
+; RUN: echo '!1 = !{!"llvm.loop.vectorize.disable", i1 0}' >> %t
+; RUN: not %{VERIFY} | FileCheck %s -check-prefix=BAD
diff --git a/mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp b/mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp
index fcb11ca4629fa..7f80b5be28b0b 100644
--- a/mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp
+++ b/mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp
@@ -285,8 +285,9 @@ static T createIfNonNull(MLIRContext *ctx, const P &...args) {
}
FailureOr<LoopVectorizeAttr> LoopMetadataConversion::convertVectorizeAttr() {
- FailureOr<BoolAttr> enable =
- lookupBoolNode("llvm.loop.vectorize.enable", true);
+ FailureOr<BoolAttr> enable = lookupBooleanUnitNode(
+ "llvm.loop.vectorize.enable", "llvm.loop.vectorize.disable",
+ /*negated=*/true);
FailureOr<BoolAttr> predicateEnable =
lookupBoolNode("llvm.loop.vectorize.predicate.enable");
FailureOr<BoolAttr> scalableEnable =
diff --git a/mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp b/mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp
index 41ba31106f788..7420142957d4c 100644
--- a/mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp
+++ b/mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp
@@ -103,7 +103,12 @@ void LoopAnnotationConversion::convertFollowupNode(StringRef name,
}
void LoopAnnotationConversion::convertLoopOptions(LoopVectorizeAttr options) {
- convertBoolNode("llvm.loop.vectorize.enable", options.getDisable(), true);
+ if (auto disable = options.getDisable()) {
+ if (disable.getValue())
+ addUnitNode("llvm.loop.vectorize.disable");
+ else
+ addUnitNode("llvm.loop.vectorize.enable");
+ }
convertBoolNode("llvm.loop.vectorize.predicate.enable",
options.getPredicateEnable());
convertBoolNode("llvm.loop.vectorize.scalable.enable",
diff --git a/mlir/test/Target/LLVMIR/Import/import-failure.ll b/mlir/test/Target/LLVMIR/Import/import-failure.ll
index 564fbf4d3df68..6600e201174cc 100644
--- a/mlir/test/Target/LLVMIR/Import/import-failure.ll
+++ b/mlir/test/Target/LLVMIR/Import/import-failure.ll
@@ -160,22 +160,6 @@ end:
; // -----
-; CHECK: <unknown>
-; CHECK-SAME: warning: expected metadata node llvm.loop.vectorize.enable to hold a boolean value
-; CHECK: <unknown>
-; CHECK-SAME: warning: unhandled metadata: !0 = distinct !{!0, !1}
-define void @unsupported_loop_annotation(i64 %n, ptr %A) {
-entry:
- br label %end, !llvm.loop !0
-end:
- ret void
-}
-
-!0 = distinct !{!0, !1}
-!1 = !{!"llvm.loop.vectorize.enable"}
-
-; // -----
-
; CHECK: <unknown>
; CHECK-SAME: warning: expected metadata node llvm.loop.vectorize.width to hold an i32 value
; CHECK: <unknown>
diff --git a/mlir/test/Target/LLVMIR/Import/metadata-loop.ll b/mlir/test/Target/LLVMIR/Import/metadata-loop.ll
index 021818ded3d3c..d64a96c1b1422 100644
--- a/mlir/test/Target/LLVMIR/Import/metadata-loop.ll
+++ b/mlir/test/Target/LLVMIR/Import/metadata-loop.ll
@@ -86,7 +86,7 @@ end:
}
!1 = distinct !{!1, !2, !3, !4, !5, !6, !7, !8}
-!2 = !{!"llvm.loop.vectorize.enable", i1 1}
+!2 = !{!"llvm.loop.vectorize.enable"}
!3 = !{!"llvm.loop.vectorize.predicate.enable", i1 1}
!4 = !{!"llvm.loop.vectorize.scalable.enable", i1 0}
!5 = !{!"llvm.loop.vectorize.width", i32 16}
diff --git a/mlir/test/Target/LLVMIR/loop-metadata.mlir b/mlir/test/Target/LLVMIR/loop-metadata.mlir
index 299bcb481f67f..ada830e103a2c 100644
--- a/mlir/test/Target/LLVMIR/loop-metadata.mlir
+++ b/mlir/test/Target/LLVMIR/loop-metadata.mlir
@@ -55,7 +55,7 @@ llvm.func @vectorizeOptions() {
// CHECK-DAG: ![[NON_FORCED:[0-9]+]] = !{!"llvm.loop.disable_nonforced"}
// CHECK-DAG: ![[FOLLOWUP:[0-9]+]] = distinct !{![[FOLLOWUP]], ![[NON_FORCED]]}
// CHECK-DAG: ![[LOOP_NODE]] = distinct !{![[LOOP_NODE]], !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}}
-// CHECK-DAG: !{{[0-9]+}} = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK-DAG: !{{[0-9]+}} = !{!"llvm.loop.vectorize.enable"}
// CHECK-DAG: !{{[0-9]+}} = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
// CHECK-DAG: !{{[0-9]+}} = !{!"llvm.loop.vectorize.scalable.enable", i1 false}
// CHECK-DAG: !{{[0-9]+}} = !{!"llvm.loop.vectorize.width", i32 16}
diff --git a/mlir/test/Target/LLVMIR/openmp-parallel-do-simd.mlir b/mlir/test/Target/LLVMIR/openmp-parallel-do-simd.mlir
index bfa57b85245ca..70b5b4b0af0a8 100644
--- a/mlir/test/Target/LLVMIR/openmp-parallel-do-simd.mlir
+++ b/mlir/test/Target/LLVMIR/openmp-parallel-do-simd.mlir
@@ -12,7 +12,7 @@
// CHECK-NEXT: br label %omp_loop.header, !llvm.loop ![[LOOP_ATTR:.*]]
// CHECK: ![[LOOP_ATTR]] = distinct !{![[LOOP_ATTR]], ![[LPAR:.*]], ![[LVEC:.*]]}
// CHECK: ![[LPAR]] = !{!"llvm.loop.parallel_accesses", ![[PAR_ACC:.*]]}
-// CHECK: ![[LVEC]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: ![[LVEC]] = !{!"llvm.loop.vectorize.enable"}
llvm.func @test_parallel_do_simd() {
%0 = llvm.mlir.constant(1 : i64) : i64
diff --git a/mlir/test/Target/LLVMIR/openmp-simd-ordered.mlir b/mlir/test/Target/LLVMIR/openmp-simd-ordered.mlir
index a84c51f08daa7..5454d177295a4 100644
--- a/mlir/test/Target/LLVMIR/openmp-simd-ordered.mlir
+++ b/mlir/test/Target/LLVMIR/openmp-simd-ordered.mlir
@@ -81,5 +81,5 @@ module {
} {linear_var_types = [i32]}
llvm.return
}
- // CHECK: !{!"llvm.loop.vectorize.enable", i1 true}
+ // CHECK: !{!"llvm.loop.vectorize.enable"}
}
diff --git a/mlir/test/Target/LLVMIR/openmp-simd-reduction-byref.mlir b/mlir/test/Target/LLVMIR/openmp-simd-reduction-byref.mlir
index 3e73fd22e69ca..0f2e20cc61aa7 100644
--- a/mlir/test/Target/LLVMIR/openmp-simd-reduction-byref.mlir
+++ b/mlir/test/Target/LLVMIR/openmp-simd-reduction-byref.mlir
@@ -95,4 +95,4 @@ llvm.func @_QPsimd_reduction(%arg0: !llvm.ptr {fir.bindc_name = "a", llvm.nocapt
// CHECK: ![[ACCESS_GROUP]] = distinct !{}
// CHECK: ![[LOOP]] = distinct !{![[LOOP]], ![[PARALLEL_ACCESS:.*]], ![[VECTORIZE:.*]]}
// CHECK: ![[PARALLEL_ACCESS]] = !{!"llvm.loop.parallel_accesses", ![[ACCESS_GROUP]]}
-// CHECK: ![[VECTORIZE]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: ![[VECTORIZE]] = !{!"llvm.loop.vectorize.enable"}
diff --git a/mlir/test/Target/LLVMIR/openmp-simd-reduction-simple.mlir b/mlir/test/Target/LLVMIR/openmp-simd-reduction-simple.mlir
index ab3c87cca56ea..a712b847e8557 100644
--- a/mlir/test/Target/LLVMIR/openmp-simd-reduction-simple.mlir
+++ b/mlir/test/Target/LLVMIR/openmp-simd-reduction-simple.mlir
@@ -93,4 +93,4 @@ llvm.func @_QPsimd_reduction(%arg0: !llvm.ptr {fir.bindc_name = "a", llvm.nocapt
// CHECK: ![[ACCESS_GROUP]] = distinct !{}
// CHECK: ![[LOOP]] = distinct !{![[LOOP]], ![[PARALLEL_ACCESS:.*]], ![[VECTORIZE:.*]]}
// CHECK: ![[PARALLEL_ACCESS]] = !{!"llvm.loop.parallel_accesses", ![[ACCESS_GROUP]]}
-// CHECK: ![[VECTORIZE]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: ![[VECTORIZE]] = !{!"llvm.loop.vectorize.enable"}
diff --git a/mlir/test/Target/LLVMIR/openmp-teams-distribute-parallel-do-simd.mlir b/mlir/test/Target/LLVMIR/openmp-teams-distribute-parallel-do-simd.mlir
index 69d5d225d0515..553d56034d2c1 100644
--- a/mlir/test/Target/LLVMIR/openmp-teams-distribute-parallel-do-simd.mlir
+++ b/mlir/test/Target/LLVMIR/openmp-teams-distribute-parallel-do-simd.mlir
@@ -20,7 +20,7 @@
// CHECK: ![[LOOP_ATTR]] = distinct !{![[LOOP_ATTR]], ![[LPAR:.*]], ![[LVEC:.*]]}
// CHECK: ![[LPAR]] = !{!"llvm.loop.parallel_accesses", ![[PAR_ACC:.*]]}
-// CHECK: ![[LVEC]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: ![[LVEC]] = !{!"llvm.loop.vectorize.enable"}
omp.private {type = private} @_QFEi_private_i32 : i32
llvm.func @test_teams_distribute_parallel_do_simd() {
diff --git a/mlir/test/Target/LLVMIR/openmp-wsloop-simd-ordered.mlir b/mlir/test/Target/LLVMIR/openmp-wsloop-simd-ordered.mlir
index 8d5b89ecbd00a..907302cdf0134 100644
--- a/mlir/test/Target/LLVMIR/openmp-wsloop-simd-ordered.mlir
+++ b/mlir/test/Target/LLVMIR/openmp-wsloop-simd-ordered.mlir
@@ -84,5 +84,5 @@ module {
} {omp.composite}
llvm.return
}
- // CHECK: !{!"llvm.loop.vectorize.enable", i1 true}
+ // CHECK: !{!"llvm.loop.vectorize.enable"}
}
diff --git a/polly/lib/CodeGen/CodeGeneration.cpp b/polly/lib/CodeGen/CodeGeneration.cpp
index d9f4a7f78a322..d02a1979bed6d 100644
--- a/polly/lib/CodeGen/CodeGeneration.cpp
+++ b/polly/lib/CodeGen/CodeGeneration.cpp
@@ -284,7 +284,7 @@ static bool generateCode(Scop &S, IslAstInfo &AI, LoopInfo &LI,
if (!(CI && CI->isZero())) {
for (Loop *L : LI.getLoopsInPreorder()) {
if (S.contains(L))
- addStringMetadataToLoop(L, "llvm.loop.vectorize.enable", 0);
+ addStringMetadataToLoop(L, StringRef("llvm.loop.vectorize.disable"));
}
}
diff --git a/polly/lib/CodeGen/IRBuilder.cpp b/polly/lib/CodeGen/IRBuilder.cpp
index d326ffd8c6a2b..b461b72170c77 100644
--- a/polly/lib/CodeGen/IRBuilder.cpp
+++ b/polly/lib/CodeGen/IRBuilder.cpp
@@ -131,11 +131,10 @@ void ScopAnnotator::popLoop(bool IsParallel) {
static void addVectorizeMetadata(LLVMContext &Ctx,
SmallVector<Metadata *, 3> *Args,
bool EnableLoopVectorizer) {
- MDString *PropName = MDString::get(Ctx, "llvm.loop.vectorize.enable");
- ConstantInt *Value =
- ConstantInt::get(Type::getInt1Ty(Ctx), EnableLoopVectorizer);
- ValueAsMetadata *PropValue = ValueAsMetadata::get(Value);
- Args->push_back(MDNode::get(Ctx, {PropName, PropValue}));
+ MDString *PropName =
+ MDString::get(Ctx, EnableLoopVectorizer ? "llvm.loop.vectorize.enable"
+ : "llvm.loop.vectorize.disable");
+ Args->push_back(MDNode::get(Ctx, {PropName}));
}
void addParallelMetadata(LLVMContext &Ctx, SmallVector<Metadata *, 3> *Args,
diff --git a/polly/test/CodeGen/MemAccess/create_arrays.ll b/polly/test/CodeGen/MemAccess/create_arrays.ll
index 8443e0f7be327..29eaff8ad3fab 100644
--- a/polly/test/CodeGen/MemAccess/create_arrays.ll
+++ b/polly/test/CodeGen/MemAccess/create_arrays.ll
@@ -32,7 +32,7 @@
; CODEGEN: store double {{%.*}}, ptr %scevgep34, align 8, !alias.scope !12, !noalias !13
;
; CODEGEN: !0 = distinct !{!0, !1}
-; CODEGEN: !1 = !{!"llvm.loop.vectorize.enable", i32 0}
+; CODEGEN: !1 = !{!"llvm.loop.vectorize.disable"}
; CODEGEN: !2 = distinct !{!2, !1}
; CODEGEN: !3 = distinct !{!3, !1}
; CODEGEN: !4 = !{!5}
diff --git a/polly/test/CodeGen/Metadata/basic_vec_annotate.ll b/polly/test/CodeGen/Metadata/basic_vec_annotate.ll
index e059fea707321..7e0c1de322d16 100644
--- a/polly/test/CodeGen/Metadata/basic_vec_annotate.ll
+++ b/polly/test/CodeGen/Metadata/basic_vec_annotate.ll
@@ -13,9 +13,9 @@
; CHECK: polly.stmt.for.body:
; CHECK: br {{.*}} !llvm.loop [[POLLY_LOOP:![0-9]+]]
; CHECK: [[LOOP]] = distinct !{[[LOOP]], [[META2:![0-9]+]], [[META3:![0-9]+]]}
-; CHECK: [[META3]] = !{!"llvm.loop.vectorize.enable", i32 0}
+; CHECK: [[META3]] = !{!"llvm.loop.vectorize.disable"}
; CHECK: [[POLLY_LOOP]] = distinct !{[[POLLY_LOOP]], {{.*}}}
-; CHECK-DAG: !{!"llvm.loop.vectorize.enable", i1 true}
+; CHECK-DAG: !{!"llvm.loop.vectorize.enable"}
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
target triple = "aarch64-unknown-linux-gnu"
diff --git a/polly/test/CodeGen/Metadata/fallback_vec_annotate.ll b/polly/test/CodeGen/Metadata/fallback_vec_annotate.ll
index 8f3c4461f79aa..f232be9892781 100644
--- a/polly/test/CodeGen/Metadata/fallback_vec_annotate.ll
+++ b/polly/test/CodeGen/Metadata/fallback_vec_annotate.ll
@@ -4,7 +4,7 @@
; Verify vectorization is not disabled when RTC of Polly is false
; CHECK: attributes {{.*}} = { "polly-optimized" }
-; CHECK-NOT: {{.*}} = !{!"llvm.loop.vectorize.enable", i32 0}
+; CHECK-NOT: {{.*}} = !{!"llvm.loop.vectorize.disable"}
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
target triple = "aarch64-unknown-linux-android10000"
diff --git a/polly/test/CodeGen/Metadata/skip_vec_annotate_fp_dist1.ll b/polly/test/CodeGen/Metadata/skip_vec_annotate_fp_dist1.ll
index 6ed41b1f64cbd..1d71a96d61409 100644
--- a/polly/test/CodeGen/Metadata/skip_vec_annotate_fp_dist1.ll
+++ b/polly/test/CodeGen/Metadata/skip_vec_annotate_fp_dist1.ll
@@ -14,7 +14,7 @@
; CHECK: polly.stmt.for.body:
; CHECK: br {{.*}} !llvm.loop [[POLLY_LOOP:![0-9]+]]
; CHECK: [[POLLY_LOOP]] = distinct !{[[POLLY_LOOP]],
-; CHECK-NOT: !"llvm.loop.vectorize.enable", i1 true
+; CHECK-NOT: !"llvm.loop.vectorize.enable"
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
target triple = "aarch64-unknown-linux-gnu"
diff --git a/polly/test/CodeGen/annotated_alias_scopes.ll b/polly/test/CodeGen/annotated_alias_scopes.ll
index 7d2d9038270a9..1f3a07b5519be 100644
--- a/polly/test/CodeGen/annotated_alias_scopes.ll
+++ b/polly/test/CodeGen/annotated_alias_scopes.ll
@@ -11,7 +11,7 @@
; SCOPES: store i32 %{{[._a-zA-Z0-9]*}}, ptr %[[AIdx]], align 4, !alias.scope !10, !noalias !11
;
; SCOPES: !0 = distinct !{!0, !1}
-; SCOPES: !1 = !{!"llvm.loop.vectorize.enable", i32 0}
+; SCOPES: !1 = !{!"llvm.loop.vectorize.disable"}
; SCOPES: !2 = !{!3}
; SCOPES: !3 = distinct !{!3, !4, !"polly.alias.scope.MemRef_B"}
; SCOPES: !4 = distinct !{!4, !"polly.alias.scope.domain"}
diff --git a/polly/test/CodeGen/scev-backedgetaken.ll b/polly/test/CodeGen/scev-backedgetaken.ll
index 09fcfe3e4a09c..df416f3d6f63e 100644
--- a/polly/test/CodeGen/scev-backedgetaken.ll
+++ b/polly/test/CodeGen/scev-backedgetaken.ll
@@ -44,7 +44,7 @@ for.cond.cleanup.loopexit:
; CHECK: load i32, ptr %scevgep, align 4, !alias.scope !2, !noalias !5
; CHECK: !0 = distinct !{!0, !1}
-; CHECK: !1 = !{!"llvm.loop.vectorize.enable", i32 0}
+; CHECK: !1 = !{!"llvm.loop.vectorize.disable"}
; CHECK: !2 = !{!3}
; CHECK: !3 = distinct !{!3, !4, !"polly.alias.scope.MemRef_d"}
; CHECK: !4 = distinct !{!4, !"polly.alias.scope.domain"}
diff --git a/polly/test/ScheduleOptimizer/pattern-matching-based-opts_14.ll b/polly/test/ScheduleOptimizer/pattern-matching-based-opts_14.ll
index 3705c3fd27ed9..977dcda9b2e9a 100644
--- a/polly/test/ScheduleOptimizer/pattern-matching-based-opts_14.ll
+++ b/polly/test/ScheduleOptimizer/pattern-matching-based-opts_14.ll
@@ -2,7 +2,7 @@
;
; Check that we disable the Loop Vectorizer.
;
-; CHECK: !{!"llvm.loop.vectorize.enable", i1 false}
+; CHECK: !{!"llvm.loop.vectorize.disable"}
;
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-unknown"
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