[clang] [lld] [llvm] [ARM] Fix invalid target triples in tests (PR #213588)
via cfe-commits
cfe-commits at lists.llvm.org
Sun Aug 2 21:43:08 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-lld
@llvm/pr-subscribers-llvm-transforms
Author: Chris Copeland (chrisnc)
<details>
<summary>Changes</summary>
Update the expected codegen as-needed.
---
Patch is 34.29 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/213588.diff
39 Files Affected:
- (modified) clang/test/CodeGenCXX/bitfield-layout.cpp (+1-1)
- (modified) clang/test/Frontend/darwin-eabi.c (+1-1)
- (modified) lld/test/ELF/arm-thunk-reuse.s (+1-1)
- (modified) llvm/test/Analysis/CostModel/ARM/muls-in-smlal-patterns.ll (+2-2)
- (modified) llvm/test/Analysis/CostModel/ARM/muls-in-umull-patterns.ll (+2-2)
- (modified) llvm/test/CodeGen/ARM/ParallelDSP/squaring.ll (+1-1)
- (modified) llvm/test/CodeGen/ARM/analyze-branch-bkpt.ll (+1-1)
- (modified) llvm/test/CodeGen/ARM/cls.ll (+14-64)
- (modified) llvm/test/CodeGen/ARM/fp16-fusedMAC.ll (+12-12)
- (modified) llvm/test/CodeGen/ARM/half.ll (+4-4)
- (modified) llvm/test/CodeGen/ARM/interrupt-save-fp-attr.ll (+2-2)
- (modified) llvm/test/CodeGen/ARM/loop-align-cortex-m.ll (+1-1)
- (modified) llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll (+5-4)
- (modified) llvm/test/CodeGen/ARM/useaa.ll (+1-1)
- (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/lsr-profitable-chain.ll (+1-1)
- (modified) llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll (+1-1)
- (modified) llvm/test/CodeGen/Thumb2/inlineasm-error-t-toofewregs-mve.ll (+1-1)
- (modified) llvm/test/CodeGen/Thumb2/inlineasm-mve.ll (+9-9)
- (modified) llvm/test/CodeGen/Thumb2/unreachable-large-offset-gep.ll (+1-1)
- (modified) llvm/test/MC/ARM/ras-extension.s (+1-1)
- (modified) llvm/test/MC/Disassembler/ARM/ras-extension-thumb.txt (+1-1)
- (modified) llvm/test/Transforms/CodeGenPrepare/ARM/memory-intrinsics.ll (+1-1)
- (modified) llvm/test/Transforms/LoopStrengthReduce/ARM/vctp-chains-inseltpoison.ll (+1-1)
- (modified) llvm/test/Transforms/LoopStrengthReduce/ARM/vctp-chains.ll (+1-1)
- (modified) llvm/test/tools/llvm-mca/ARM/m4-int.s (+1-1)
- (modified) llvm/test/tools/llvm-mca/ARM/m55-fp.s (+1-1)
- (modified) llvm/test/tools/llvm-mca/ARM/m55-int.s (+1-1)
- (modified) llvm/test/tools/llvm-mca/ARM/m55-mve-fp.s (+1-1)
- (modified) llvm/test/tools/llvm-mca/ARM/m55-mve-int.s (+1-1)
- (modified) llvm/test/tools/llvm-mca/ARM/m55-mve-ldst.s (+1-1)
- (modified) llvm/test/tools/llvm-mca/ARM/m55-mve-pred.s (+1-1)
- (modified) llvm/test/tools/llvm-mca/ARM/m55-storefwd.s (+1-1)
- (modified) llvm/test/tools/llvm-mca/ARM/m7-fp.s (+1-1)
- (modified) llvm/test/tools/llvm-mca/ARM/m7-int.s (+1-1)
- (modified) llvm/test/tools/llvm-mca/ARM/m85-fp.s (+1-1)
- (modified) llvm/test/tools/llvm-mca/ARM/m85-int.s (+1-1)
- (modified) llvm/test/tools/llvm-mca/ARM/m85-mve-fp.s (+1-1)
- (modified) llvm/test/tools/llvm-mca/ARM/m85-mve-int.s (+1-1)
- (modified) llvm/test/tools/llvm-mca/ARM/m85-mve-pred.s (+1-1)
``````````diff
diff --git a/clang/test/CodeGenCXX/bitfield-layout.cpp b/clang/test/CodeGenCXX/bitfield-layout.cpp
index 66a140a966c64..c485dee980ed8 100644
--- a/clang/test/CodeGenCXX/bitfield-layout.cpp
+++ b/clang/test/CodeGenCXX/bitfield-layout.cpp
@@ -1,7 +1,7 @@
// RUN: %clang_cc1 %s -triple=x86_64-apple-darwin10 -emit-llvm -o - -O3 | FileCheck -check-prefix=CHECK -check-prefix=CHECK-LP64 %s
// RUN: %clang_cc1 %s -triple=i386-apple-darwin10 -emit-llvm -o - -O3 | FileCheck %s
// RUN: %clang_cc1 %s -triple=aarch64_be -emit-llvm -o - -O3 | FileCheck %s
-// RUN: %clang_cc1 %s -triple=thumbv7_be-none-eabi -emit-llvm -o - -O3 | FileCheck %s
+// RUN: %clang_cc1 %s -triple=thumbebv7-none-eabi -emit-llvm -o - -O3 | FileCheck %s
// RUN: %clang_cc1 %s -triple=x86_64-unknown-unknown -emit-llvm -o - -O3 -std=c++11 | FileCheck -check-prefix=CHECK -check-prefix=CHECK-LP64 %s
// CHECK-LP64: %union.Test1 = type { i32, [4 x i8] }
diff --git a/clang/test/Frontend/darwin-eabi.c b/clang/test/Frontend/darwin-eabi.c
index b94bf26e2853f..6340a01e5f5e5 100644
--- a/clang/test/Frontend/darwin-eabi.c
+++ b/clang/test/Frontend/darwin-eabi.c
@@ -5,7 +5,7 @@
// RUN: %clang --target=armv8m.main-apple-darwin -dM -E %s | FileCheck %s
// RUN: %clang --target=armv8.1m.main-apple-darwin -dM -E %s | FileCheck %s
// RUN: %clang_cc1 -triple thumbv7m-apple-unknown-macho -dM -E %s | FileCheck %s
-// RUN: %clang_cc1 -triple thumbv8m-apple-unknown-macho -dM -E %s | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8m.main-apple-unknown-macho -dM -E %s | FileCheck %s
// CHECK-NOT: __ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__
// CHECK-NOT: __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__
diff --git a/lld/test/ELF/arm-thunk-reuse.s b/lld/test/ELF/arm-thunk-reuse.s
index f6815da7af496..cde68169144ab 100644
--- a/lld/test/ELF/arm-thunk-reuse.s
+++ b/lld/test/ELF/arm-thunk-reuse.s
@@ -1,6 +1,6 @@
# REQUIRES: arm
# RUN: rm -rf %t && split-file %s %t
-# RUN: llvm-mc -filetype=obj -triple=armv7-a-none-eabi --arm-add-build-attributes %t/a.s -o %t/a.o
+# RUN: llvm-mc -filetype=obj -triple=armv7a-none-eabi --arm-add-build-attributes %t/a.s -o %t/a.o
# RUN: ld.lld -pie -T %t/lds %t/a.o -o %t/a
# RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn %t/a | FileCheck %s
# RUN: llvm-objdump -s --triple=armv7a-none-linux-gnueabi %t/a | FileCheck --check-prefix=CHECK-LE %s
diff --git a/llvm/test/Analysis/CostModel/ARM/muls-in-smlal-patterns.ll b/llvm/test/Analysis/CostModel/ARM/muls-in-smlal-patterns.ll
index 3ae02cdec5aba..cdb730929fe37 100644
--- a/llvm/test/Analysis/CostModel/ARM/muls-in-smlal-patterns.ll
+++ b/llvm/test/Analysis/CostModel/ARM/muls-in-smlal-patterns.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 5
-; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple thumbv8.1-m.main -mattr=+dsp < %s | FileCheck %s
-; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple thumbv8.1-m.main < %s | FileCheck %s --check-prefix=CHECK-NO-DSP
+; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple thumbv8.1m.main -mattr=+dsp < %s | FileCheck %s
+; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple thumbv8.1m.main < %s | FileCheck %s --check-prefix=CHECK-NO-DSP
define i64 @test(i16 %a, i16 %b) {
; CHECK-LABEL: 'test'
diff --git a/llvm/test/Analysis/CostModel/ARM/muls-in-umull-patterns.ll b/llvm/test/Analysis/CostModel/ARM/muls-in-umull-patterns.ll
index 04a952098a9c6..b904a6f9d9def 100644
--- a/llvm/test/Analysis/CostModel/ARM/muls-in-umull-patterns.ll
+++ b/llvm/test/Analysis/CostModel/ARM/muls-in-umull-patterns.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 5
-; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple thumbv8.1-m.main -mattr=+dsp < %s | FileCheck %s
-; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple thumbv8.1-m.main < %s | FileCheck %s --check-prefix=CHECK-NO-DSP
+; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple thumbv8.1m.main -mattr=+dsp < %s | FileCheck %s
+; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple thumbv8.1m.main < %s | FileCheck %s --check-prefix=CHECK-NO-DSP
define i64 @test(i16 %a, i16 %b) {
; CHECK-LABEL: 'test'
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/squaring.ll b/llvm/test/CodeGen/ARM/ParallelDSP/squaring.ll
index 5a5025d94b4da..270d848e867c8 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/squaring.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/squaring.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=armv8-a-linux-gnueabihf -arm-parallel-dsp -dce --verify %s -S -o - | FileCheck %s
+; RUN: opt -mtriple=armv8a-linux-gnueabihf -arm-parallel-dsp -dce --verify %s -S -o - | FileCheck %s
define dso_local void @a() align 2 {
; CHECK-LABEL: @a(
diff --git a/llvm/test/CodeGen/ARM/analyze-branch-bkpt.ll b/llvm/test/CodeGen/ARM/analyze-branch-bkpt.ll
index d6a2f58589c32..6cd164f2689b6 100644
--- a/llvm/test/CodeGen/ARM/analyze-branch-bkpt.ll
+++ b/llvm/test/CodeGen/ARM/analyze-branch-bkpt.ll
@@ -1,4 +1,4 @@
-; RUN: llc -o - %s -mtriple thumbv4-unknown-linux-android | FileCheck --check-prefix=V4 %s
+; RUN: llc -o - %s -mtriple thumbv4t-unknown-linux-android | FileCheck --check-prefix=V4 %s
; RUN: llc -o - %s -mtriple thumbv5-unknown-linux-android | FileCheck --check-prefix=V5 %s
; V4: udf #254
diff --git a/llvm/test/CodeGen/ARM/cls.ll b/llvm/test/CodeGen/ARM/cls.ll
index 76d787e039ed2..9cbaa55d08622 100644
--- a/llvm/test/CodeGen/ARM/cls.ll
+++ b/llvm/test/CodeGen/ARM/cls.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=armv5 %s -o - | FileCheck %s --check-prefixes=CHECKV5
-; RUN: llc -mtriple=thumbv8.1-m.main %s -o - | FileCheck %s --check-prefix=CHECKV8
+; RUN: llc -mtriple=thumbv8.1m.main %s -o - | FileCheck %s --check-prefix=CHECKV8
define i32 @cls(i32 %t) {
; CHECKV5-LABEL: cls:
@@ -13,15 +13,11 @@ define i32 @cls(i32 %t) {
;
; CHECKV8-LABEL: cls:
; CHECKV8: @ %bb.0:
-; CHECKV8-NEXT: push {r7, lr}
-; CHECKV8-NEXT: asrs r1, r0, #31
-; CHECKV8-NEXT: eors r1, r0
-; CHECKV8-NEXT: lsls r0, r1, #1
-; CHECKV8-NEXT: adds r0, r0, #1
-; CHECKV8-NEXT: bl __clzsi2
-; CHECKV8-NEXT: pop {r7}
-; CHECKV8-NEXT: pop {r1}
-; CHECKV8-NEXT: bx r1
+; CHECKV8-NEXT: eor.w r0, r0, r0, asr #31
+; CHECKV8-NEXT: lsls r0, r0, #1
+; CHECKV8-NEXT: adds r0, #1
+; CHECKV8-NEXT: clz r0, r0
+; CHECKV8-NEXT: bx lr
%cls.i = call i32 @llvm.arm.cls(i32 %t)
ret i32 %cls.i
}
@@ -42,63 +38,17 @@ define i32 @cls64(i64 %t) {
;
; CHECKV8-LABEL: cls64:
; CHECKV8: @ %bb.0:
-; CHECKV8-NEXT: push {r4, lr}
-; CHECKV8-NEXT: movs r4, r0
; CHECKV8-NEXT: cmp r1, #0
-; CHECKV8-NEXT: bpl .LBB1_2
-; CHECKV8-NEXT: @ %bb.1:
-; CHECKV8-NEXT: mvns r4, r4
-; CHECKV8-NEXT: .LBB1_2:
-; CHECKV8-NEXT: asrs r0, r1, #31
-; CHECKV8-NEXT: eors r0, r1
+; CHECKV8-NEXT: cinv r0, r0, mi
+; CHECKV8-NEXT: clz r2, r0
+; CHECKV8-NEXT: eor.w r0, r1, r1, asr #31
; CHECKV8-NEXT: lsls r0, r0, #1
-; CHECKV8-NEXT: adds r0, r0, #1
-; CHECKV8-NEXT: bl __clzsi2
+; CHECKV8-NEXT: adds r0, #1
+; CHECKV8-NEXT: clz r0, r0
; CHECKV8-NEXT: cmp r0, #31
-; CHECKV8-NEXT: bne .LBB1_4
-; CHECKV8-NEXT: @ %bb.3:
-; CHECKV8-NEXT: lsrs r0, r4, #1
-; CHECKV8-NEXT: orrs r0, r4
-; CHECKV8-NEXT: lsrs r1, r0, #2
-; CHECKV8-NEXT: orrs r1, r0
-; CHECKV8-NEXT: lsrs r0, r1, #4
-; CHECKV8-NEXT: orrs r0, r1
-; CHECKV8-NEXT: lsrs r1, r0, #8
-; CHECKV8-NEXT: orrs r1, r0
-; CHECKV8-NEXT: lsrs r0, r1, #16
-; CHECKV8-NEXT: orrs r0, r1
-; CHECKV8-NEXT: mvns r0, r0
-; CHECKV8-NEXT: lsrs r1, r0, #1
-; CHECKV8-NEXT: ldr r2, .LCPI1_0
-; CHECKV8-NEXT: ands r2, r1
-; CHECKV8-NEXT: subs r0, r0, r2
-; CHECKV8-NEXT: ldr r1, .LCPI1_1
-; CHECKV8-NEXT: lsrs r2, r0, #2
-; CHECKV8-NEXT: ands r0, r1
-; CHECKV8-NEXT: ands r2, r1
-; CHECKV8-NEXT: adds r0, r0, r2
-; CHECKV8-NEXT: lsrs r1, r0, #4
-; CHECKV8-NEXT: adds r0, r0, r1
-; CHECKV8-NEXT: ldr r1, .LCPI1_2
-; CHECKV8-NEXT: ands r1, r0
-; CHECKV8-NEXT: ldr r0, .LCPI1_3
-; CHECKV8-NEXT: muls r0, r1, r0
-; CHECKV8-NEXT: lsrs r0, r0, #24
-; CHECKV8-NEXT: adds r0, #31
-; CHECKV8-NEXT: .LBB1_4:
-; CHECKV8-NEXT: pop {r4}
-; CHECKV8-NEXT: pop {r1}
-; CHECKV8-NEXT: bx r1
-; CHECKV8-NEXT: .p2align 2
-; CHECKV8-NEXT: @ %bb.5:
-; CHECKV8-NEXT: .LCPI1_0:
-; CHECKV8-NEXT: .long 1431655765 @ 0x55555555
-; CHECKV8-NEXT: .LCPI1_1:
-; CHECKV8-NEXT: .long 858993459 @ 0x33333333
-; CHECKV8-NEXT: .LCPI1_2:
-; CHECKV8-NEXT: .long 252645135 @ 0xf0f0f0f
-; CHECKV8-NEXT: .LCPI1_3:
-; CHECKV8-NEXT: .long 16843009 @ 0x1010101
+; CHECKV8-NEXT: it eq
+; CHECKV8-NEXT: addeq.w r0, r2, #31
+; CHECKV8-NEXT: bx lr
%cls.i = call i32 @llvm.arm.cls64(i64 %t)
ret i32 %cls.i
}
diff --git a/llvm/test/CodeGen/ARM/fp16-fusedMAC.ll b/llvm/test/CodeGen/ARM/fp16-fusedMAC.ll
index 6f1f40729bd60..f354553f02c15 100644
--- a/llvm/test/CodeGen/ARM/fp16-fusedMAC.ll
+++ b/llvm/test/CodeGen/ARM/fp16-fusedMAC.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=thumbv8.1-m-none-eabi -mattr=+fullfp16 -fp-contract=fast | FileCheck %s
-; RUN: llc < %s -mtriple=thumbv8.1-m-none-eabi -mattr=+fullfp16,+slowfpvfmx -fp-contract=fast | FileCheck %s -check-prefix=DONT-FUSE
+; RUN: llc < %s -mtriple=thumbv8.1m.main-none-eabi -mattr=+fullfp16 -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv8.1m.main-none-eabi -mattr=+fullfp16,+slowfpvfmx -fp-contract=fast | FileCheck %s -check-prefix=DONT-FUSE
; Check generated fp16 fused MAC and MLS.
@@ -203,20 +203,20 @@ define arm_aapcs_vfpcc void @test_fma_const_fold(ptr %aa, ptr %bb) nounwind {
define arm_aapcs_vfpcc void @test_fma_canonicalize(ptr %aa, ptr %bb) nounwind {
; CHECK-LABEL: test_fma_canonicalize:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr.16 s0, [r0]
-; CHECK-NEXT: vldr.16 s2, [r1]
-; CHECK-NEXT: vmov.f16 s4, #2.000000e+00
-; CHECK-NEXT: vfma.f16 s2, s0, s4
-; CHECK-NEXT: vstr.16 s2, [r0]
+; CHECK-NEXT: vldr.16 s2, [r0]
+; CHECK-NEXT: vldr.16 s4, [r1]
+; CHECK-NEXT: vmov.f16 s0, #2.000000e+00
+; CHECK-NEXT: vfma.f16 s4, s2, s0
+; CHECK-NEXT: vstr.16 s4, [r0]
; CHECK-NEXT: bx lr
;
; DONT-FUSE-LABEL: test_fma_canonicalize:
; DONT-FUSE: @ %bb.0:
-; DONT-FUSE-NEXT: vldr.16 s0, [r0]
-; DONT-FUSE-NEXT: vldr.16 s2, [r1]
-; DONT-FUSE-NEXT: vmov.f16 s4, #2.000000e+00
-; DONT-FUSE-NEXT: vfma.f16 s2, s0, s4
-; DONT-FUSE-NEXT: vstr.16 s2, [r0]
+; DONT-FUSE-NEXT: vldr.16 s2, [r0]
+; DONT-FUSE-NEXT: vldr.16 s4, [r1]
+; DONT-FUSE-NEXT: vmov.f16 s0, #2.000000e+00
+; DONT-FUSE-NEXT: vfma.f16 s4, s2, s0
+; DONT-FUSE-NEXT: vstr.16 s4, [r0]
; DONT-FUSE-NEXT: bx lr
%a = load half, ptr %aa, align 2
diff --git a/llvm/test/CodeGen/ARM/half.ll b/llvm/test/CodeGen/ARM/half.ll
index 9f8c552cf8397..f12dffc857805 100644
--- a/llvm/test/CodeGen/ARM/half.ll
+++ b/llvm/test/CodeGen/ARM/half.ll
@@ -3,10 +3,10 @@
; RUN: llc < %s -mtriple=thumbv8-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8
; RUN: llc < %s -mtriple=armv8r-none-none-eabi -mattr=+neon,+fp-armv8 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8
; RUN: llc < %s -mtriple=armv8r-none-none-eabi | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8-SP
-; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+fp-armv8 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8
-; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+fp-armv8,-fp64 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8-SP
-; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+mve.fp,+fp64 | FileCheck %s --check-prefix=CHECK-V8
-; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-V8-SP
+; RUN: llc < %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+fp-armv8 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8
+; RUN: llc < %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+fp-armv8,-fp64 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8-SP
+; RUN: llc < %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 | FileCheck %s --check-prefix=CHECK-V8
+; RUN: llc < %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-V8-SP
define void @test_load_store(ptr %in, ptr %out) {
; CHECK-LABEL: test_load_store:
diff --git a/llvm/test/CodeGen/ARM/interrupt-save-fp-attr.ll b/llvm/test/CodeGen/ARM/interrupt-save-fp-attr.ll
index e96dfa4a38e12..a3d610059d00e 100644
--- a/llvm/test/CodeGen/ARM/interrupt-save-fp-attr.ll
+++ b/llvm/test/CodeGen/ARM/interrupt-save-fp-attr.ll
@@ -2,8 +2,8 @@
; RUN: llc -mtriple=thumb-ti-none-eabihf -mcpu=cortex-a15 -o - %s | FileCheck --check-prefix=CHECK-A-THUMB %s
; RUN: llc -mtriple=thumb-ti-none-eabihf -mcpu=cortex-m4 -o - %s | FileCheck --check-prefix=CHECK-M %s
; RUN: llc -mtriple=thumbv7em-ti-none-eabihf -mcpu=cortex-m4 -o - %s | FileCheck --check-prefix=CHECK-M %s
-; RUN: llc -mtriple=thumbv7r5-ti-none-eabihf -mcpu=cortex-r5 -o - %s | FileCheck --check-prefix=CHECK-R-THUMB %s
-; RUN: llc -mtriple=armv7r5-ti-none-eabihf -mcpu=cortex-r5 -o - %s | FileCheck --check-prefix=CHECK-R %s
+; RUN: llc -mtriple=thumbv7r-ti-none-eabihf -mcpu=cortex-r5 -o - %s | FileCheck --check-prefix=CHECK-R-THUMB %s
+; RUN: llc -mtriple=armv7r-ti-none-eabihf -mcpu=cortex-r5 -o - %s | FileCheck --check-prefix=CHECK-R %s
declare arm_aapcscc void @bar()
diff --git a/llvm/test/CodeGen/ARM/loop-align-cortex-m.ll b/llvm/test/CodeGen/ARM/loop-align-cortex-m.ll
index bce0bbabfdc29..8bdcc2e57899e 100644
--- a/llvm/test/CodeGen/ARM/loop-align-cortex-m.ll
+++ b/llvm/test/CodeGen/ARM/loop-align-cortex-m.ll
@@ -1,6 +1,6 @@
; RUN: llc -mtriple=thumbv7m-none-eabi %s -mcpu=cortex-m3 -o - | FileCheck %s
; RUN: llc -mtriple=thumbv7m-none-eabi %s -mcpu=cortex-m4 -o - | FileCheck %s
-; RUN: llc -mtriple=thumbv8m-none-eabi %s -mcpu=cortex-m33 -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -mcpu=cortex-m33 -o - | FileCheck %s
define void @test_loop_alignment(ptr %in, ptr %out) optsize {
; CHECK-LABEL: test_loop_alignment:
diff --git a/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll b/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
index 01cb3ba404816..a82cfcb76e159 100644
--- a/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
+++ b/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=armv7 -mattr=+neon %s -o - | FileCheck %s --check-prefix=ARMV7
; RUN: llc -mtriple=armv7 -mattr=+fp-armv8 %s -o - | FileCheck %s --check-prefix=ARMV8
; RUN: llc -mtriple=armv8.2a -mattr=+fp-armv8 %s -o - | FileCheck %s --check-prefix=ARMV8
-; RUN: llc -mtriple=armv8.1m-none-none-eabi -mattr=+mve.fp,+fp64 %s -o - | FileCheck %s --check-prefix=ARMV8M
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 %s -o - | FileCheck %s --check-prefix=ARMV8M
declare float @llvm.minnum.f32(float, float)
declare float @llvm.maxnum.f32(float, float)
@@ -999,11 +999,12 @@ define <2 x double> @fminnumv264_one_zero_intrinsic(<2 x double> %x) {
; ARMV8M-NEXT: vmov d1, r2, r3
; ARMV8M-NEXT: vldr d0, .LCPI27_0
; ARMV8M-NEXT: vcmp.f64 d1, #0
-; ARMV8M-NEXT: vmrs APSR_nzcv, fpscr
; ARMV8M-NEXT: vmov d2, r0, r1
+; ARMV8M-NEXT: vmrs APSR_nzcv, fpscr
; ARMV8M-NEXT: vmov.f64 d3, #-1.000000e+00
-; ARMV8M-NEXT: vcmp.f64 d3, d2
+; ARMV8M-NEXT: it lt
; ARMV8M-NEXT: vmovlt.f64 d0, d1
+; ARMV8M-NEXT: vcmp.f64 d3, d2
; ARMV8M-NEXT: vmrs APSR_nzcv, fpscr
; ARMV8M-NEXT: vmov r2, r3, d0
; ARMV8M-NEXT: vselgt.f64 d1, d2, d3
@@ -1312,7 +1313,7 @@ define void @pr65820(ptr %y, <4 x float> %splat) {
; ARMV8M-NEXT: vmov r1, s0
; ARMV8M-NEXT: vmov.i32 q0, #0x0
; ARMV8M-NEXT: vdup.32 q1, r1
-; ARMV8M-NEXT: vcmp.f32 gt, q1, zr
+; ARMV8M-NEXT: vpt.f32 gt, q1, zr
; ARMV8M-NEXT: vdupt.32 q0, r1
; ARMV8M-NEXT: vstrw.32 q0, [r0]
; ARMV8M-NEXT: bx lr
diff --git a/llvm/test/CodeGen/ARM/useaa.ll b/llvm/test/CodeGen/ARM/useaa.ll
index 9be0b88b35989..aca99ef83c0d4 100644
--- a/llvm/test/CodeGen/ARM/useaa.ll
+++ b/llvm/test/CodeGen/ARM/useaa.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52plus | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA
; RUN: llc < %s -mtriple=armv7m-eabi -mcpu=cortex-m4 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA
-; RUN: llc < %s -mtriple=armv8m-eabi -mcpu=cortex-m33 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA
+; RUN: llc < %s -mtriple=thumbv8m.main-eabi -mcpu=cortex-m33 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA
; Check we use AA during codegen, so can interleave these loads/stores.
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/lsr-profitable-chain.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/lsr-profitable-chain.ll
index 6d9dc46e1caa0..a7df97fc58b54 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/lsr-profitable-chain.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/lsr-profitable-chain.ll
@@ -2,7 +2,7 @@
; RUN: llc -O3 -tail-predication=enabled -mtriple=thumbv8.1m.main -mattr=+mve,+mve.fp %s -o - | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
-target triple = "thumbv8.1m-arm-none-eabi"
+target triple = "thumbv8.1m.main-arm-none-eabi"
; Tests that LSR will not interfere with the VCTP intrinsic,
; and that this loop will correctly become tail-predicated.
diff --git a/llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll b/llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll
index a0f8374e074d9..50299d3abd305 100644
--- a/llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll
+++ b/llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=thumbv8.1-m.main-none-eabi -mcpu=cortex-m55 -O3 < %s | FileCheck %s
+; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mcpu=cortex-m55 -O3 < %s | FileCheck %s
define i32 @loop(ptr nocapture readonly %x) {
; CHECK-LABEL: loop:
diff --git a/llvm/test/CodeGen/Thumb2/inlineasm-error-t-toofewregs-mve.ll b/llvm/test/CodeGen/Thumb2/inlineasm-error-t-toofewregs-mve.ll
index 419ff71c07d14..c22cb39b38b4e 100644
--- a/llvm/test/CodeGen/Thumb2/inlineasm-error-t-toofewregs-mve.ll
+++ b/llvm/test/CodeGen/Thumb2/inlineasm-error-t-toofewregs-mve.ll
@@ -1,4 +1,4 @@
-; RUN: not llc -mtriple=armv8.1-m-eabi -mattr=+mve %s -o /dev/null 2>&1 | FileCheck %s
+; RUN: not llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve %s -o /dev/null 2>&1 | FileCheck %s
; CHECK: inline assembly requires more registers than available
define arm_aapcs_vfpcc <4 x i32> @t-constraint-i32-vectors-too-few-regs(<4 x i32> %a, <4 x i32> %b) {
diff --git a/llvm/test/CodeGen/Thumb2/inlineasm-mve.ll b/llvm/test/CodeGen/Thumb2/inlineasm-mve.ll
index a8c0622b316ec..7fc9e4188248f 100644
--- a/llvm/test/CodeGen/Thumb2/inlineasm-mve.ll
+++ b/llvm/test/CodeGen/Thumb2/inlineasm-mve.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=armv8.1-m-eabi -mattr=+mve %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve %s -o - | FileCheck %s
define i32 @test1(i32 %tmp54) {
%tmp56 = tail call i32 asm "uxtb16 $0,$1", "=r,r"( i32 %tmp54 )
@@ -22,10 +22,10 @@ define arm_aapcs_vfpcc <4 x i32> @mve-t-constraint-128bit(<4 x i32>, <4 x i32>)
define i32 @even-GPR-constraint() {
entry:
; CHECK-LABEL: even-GPR-constraint
- ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #1
- ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #2
- ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #3
- ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #4
+ ; CHECK: add.w [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/213588
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