[clang] [llvm] [RISCV][MC] Add experimental Smijt, Ssijt, Smehv, and Ssehv support (PR #213431)

[Zeyi Xu via cfe-commits]

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@@ -141,6 +141,7 @@ def : SysReg<"sstatus", 0x100>;
 def : SysReg<"sie", 0x104>;
 def : SysReg<"stvec", 0x105>;
 def : SysReg<"scounteren", 0x106>;
+def : SysReg<"sijt", 0x107>;
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zeyi2 wrote:

The `sijt` address is defined [here](https://github.com/riscv/riscv-fast-interrupt/blob/6164eca8c8c9138e519ea3b8510655b2b5bb76d0/src/aclic.adoc?plain=1#L1617-L1626)

https://github.com/llvm/llvm-project/pull/213431