[clang] 037a0f4 - [RISCV][MC] Add experimental Smcsps and Sscsps support (#211712)
via cfe-commits
cfe-commits at lists.llvm.org
Fri Jul 31 20:05:30 PDT 2026
Author: Zeyi Xu
Date: 2026-08-01T11:05:22+08:00
New Revision: 037a0f40a8e40784cbb9732709aa56d0f833c713
URL: https://github.com/llvm/llvm-project/commit/037a0f40a8e40784cbb9732709aa56d0f833c713
DIFF: https://github.com/llvm/llvm-project/commit/037a0f40a8e40784cbb9732709aa56d0f833c713.diff
LOG: [RISCV][MC] Add experimental Smcsps and Sscsps support (#211712)
Add experimental v0.19 support for the `Smcsps` and `Sscsps` conditional
stack pointer swap extensions.
Added:
llvm/lib/Target/RISCV/RISCVInstrInfoSmcsps.td
llvm/test/MC/RISCV/smcsps-invalid.s
llvm/test/MC/RISCV/smcsps-valid.s
Modified:
clang/test/Driver/print-supported-extensions-riscv.c
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/docs/ReleaseNotes.md
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVSystemOperands.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/CodeGen/RISCV/features-info.ll
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/machine-csr-names.s
llvm/test/MC/RISCV/supervisor-csr-names.s
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Removed:
################################################################################
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index fa0e6802bcefa..c1abb1876d64a 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -270,7 +270,9 @@
// CHECK-NEXT: zvvmtls 0.1 'Zvvmtls' (Matrix Tile Load/Store)
// CHECK-NEXT: zvvmttls 0.1 'Zvvmttls' (Transposing Matrix Tile Load/Store)
// CHECK-NEXT: zvzip 0.1 'Zvzip' (Vector Reordering Structured Data)
+// CHECK-NEXT: smcsps 0.19 'Smcsps' (Conditional Stack Pointer Swap at Machine Level)
// CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension)
+// CHECK-NEXT: sscsps 0.19 'Sscsps' (Conditional Stack Pointer Swap at Supervisor Level)
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
// CHECK-NEXT: xqccmt 0.1 'Xqccmt' (Qualcomm 16-bit Table Jump)
// CHECK-NEXT: xsfmclic 0.1 'XSfmclic' (SiFive CLIC Machine-mode CSRs)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index bf9689d7462aa..d9423ce4baf17 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -34,6 +34,7 @@
// CHECK-NOT: __riscv_smaia {{.*$}}
// CHECK-NOT: __riscv_smcdeleg {{.*$}}
// CHECK-NOT: __riscv_smcntrpmf {{.*$}}
+// CHECK-NOT: __riscv_smcsps {{.*$}}
// CHECK-NOT: __riscv_smcsrind {{.*$}}
// CHECK-NOT: __riscv_smctr{{.*$}}
// CHECK-NOT: __riscv_smdbltrp {{.*$}}
@@ -48,6 +49,7 @@
// CHECK-NOT: __riscv_ssccptr {{.*$}}
// CHECK-NOT: __riscv_sscofpmf {{.*$}}
// CHECK-NOT: __riscv_sscounterenw {{.*$}}
+// CHECK-NOT: __riscv_sscsps {{.*$}}
// CHECK-NOT: __riscv_sscsrind {{.*$}}
// CHECK-NOT: __riscv_ssctr{{.*$}}
// CHECK-NOT: __riscv_ssdbltrp {{.*$}}
@@ -1332,6 +1334,23 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SMCNTRPMF-EXT %s
// CHECK-SMCNTRPMF-EXT: __riscv_smcntrpmf 1000000{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_smcsps0p19 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMCSPS-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_smcsps0p19 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMCSPS-EXT %s
+// CHECK-SMCSPS-EXT: __riscv_smcsps 19000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_sscsps0p19 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SSCSPS-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_sscsps0p19 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SSCSPS-EXT %s
+// CHECK-SSCSPS-EXT: __riscv_smcsps 19000{{$}}
+// CHECK-SSCSPS-EXT: __riscv_sscsps 19000{{$}}
+
// RUN: %clang --target=riscv32 \
// RUN: -march=rv32ismcsrind1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMCSRIND-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index b11ef40489d18..ab9c007505e9b 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -347,6 +347,9 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zicfilp``, ``experimental-zicfiss``
LLVM implements the `1.0 release specification <https://github.com/riscv/riscv-cfi/releases/tag/v1.0>`__.
+``experimental-smcsps``, ``experimental-sscsps``
+ LLVM implements the `0.19 release specification <https://github.com/riscv/riscv-fast-interrupt/releases/tag/v0.19>`__.
+
``experimental-zvbc32e``, ``experimental-zvkgs``
LLVM implements the `0.7 release specification <https://github.com/user-attachments/files/16450464/riscv-crypto-spec-vector-extra_v0.0.7.pdf>`__.
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index e567f4b0a37f9..10b8ede9dbdf7 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -92,6 +92,9 @@ Makes programs 10x faster by doing Special New Thing.
### Changes to the RISC-V Backend
+* Added experimental MC support for the `Smcsps` and `Sscsps`
+ conditional stack pointer swap extensions.
+
* Adds experimental assembler/CodeGen support for the `Zilx` (Indexed Integer
Load) extension.
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index 1604645520dd1..94367f95151f1 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -133,10 +133,16 @@ void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
unsigned Imm = MI->getOperand(OpNo).getImm();
auto Range = RISCVSysReg::lookupSysRegByEncoding(Imm);
+ bool PreferFeatureSpecific = llvm::any_of(Range, [&](const auto &Reg) {
+ return !Reg.IsAltName && !Reg.IsDeprecatedName &&
+ Reg.FeaturesRequired.any() &&
+ Reg.haveRequiredFeatures(STI.getFeatureBits());
+ });
for (auto &Reg : Range) {
if (Reg.IsAltName || Reg.IsDeprecatedName)
continue;
- if (Reg.haveRequiredFeatures(STI.getFeatureBits())) {
+ if (Reg.haveRequiredFeatures(STI.getFeatureBits()) &&
+ (!PreferFeatureSpecific || Reg.FeaturesRequired.any())) {
markup(O, Markup::Register) << RISCVSysReg::getSysRegStr(Reg.Name);
return;
}
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index a6e9839bc22a7..3f48aeb01c641 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1072,6 +1072,20 @@ def FeatureStdExtSsaia
def FeatureStdExtSmcntrpmf
: RISCVExtension<1, 0, "Cycle and Instret Privilege Mode Filtering">;
+def FeatureStdExtSmcsps
+ : RISCVExperimentalExtension<0, 19,
+ "Conditional Stack Pointer Swap at Machine Level">;
+def HasStdExtSmcsps : Predicate<"Subtarget->hasStdExtSmcsps()">,
+ AssemblerPredicate<(all_of FeatureStdExtSmcsps),
+ "'Smcsps' (Conditional Stack Pointer Swap at Machine Level)">;
+def FeatureStdExtSscsps
+ : RISCVExperimentalExtension<0, 19,
+ "Conditional Stack Pointer Swap at Supervisor Level",
+ [FeatureStdExtSmcsps]>;
+def HasStdExtSscsps : Predicate<"Subtarget->hasStdExtSscsps()">,
+ AssemblerPredicate<(all_of FeatureStdExtSscsps),
+ "'Sscsps' (Conditional Stack Pointer Swap at Supervisor Level)">;
+
def FeatureStdExtSmcsrind
: RISCVExtension<1, 0, "Indirect CSR Access Machine Level">;
def FeatureStdExtSscsrind
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index bfe7ac86c469c..09fa9fc0ead1b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2380,6 +2380,9 @@ include "RISCVInstrInfoZilsd.td"
include "RISCVInstrInfoZibi.td"
include "RISCVInstrInfoZilx.td"
+// Privileged
+include "RISCVInstrInfoSmcsps.td"
+
// Scalar FP
include "RISCVInstrInfoF.td"
include "RISCVInstrInfoD.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoSmcsps.td b/llvm/lib/Target/RISCV/RISCVInstrInfoSmcsps.td
new file mode 100644
index 0000000000000..adc4efd5ca2ae
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoSmcsps.td
@@ -0,0 +1,24 @@
+//===-- RISCVInstrInfoSmcsps.td ----------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
+class CSPSInst<bits<7> funct7, bits<5> funct5, string opcodestr>
+ : RVInstR<funct7, 0b000, OPC_SYSTEM, (outs SP:$rd), (ins SP:$rs1),
+ opcodestr, "$rd, $rs1">, Sched<[]> {
+ let rs2 = funct5;
+}
+
+let Predicates = [HasStdExtSmcsps] in {
+def MCSPSPUSH : CSPSInst<0b0011000, 0b01001, "mcspspush">;
+def MCSPSPOP : CSPSInst<0b0011000, 0b01100, "mcspspop">;
+}
+
+let Predicates = [HasStdExtSscsps] in {
+def SCSPSPUSH : CSPSInst<0b0001000, 0b01001, "scspspush">;
+def SCSPSPOP : CSPSInst<0b0001000, 0b01100, "scspspop">;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index c35f008b49946..6d9069dc999ec 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -165,6 +165,7 @@ def : SysReg<"scause", 0x142>;
def : SysReg<"stval", 0x143>;
def : DeprecatedSysRegName<"sbadaddr", 0x143>;
def : SysReg<"sip", 0x144>;
+def : SysReg<"sspcs", 0x149>;
def : SysReg<"siph", 0x154, RV32Only=true>;
def : SysReg<"stopei", 0x15C>;
def : SysReg<"scountovf", 0xDA0>;
@@ -376,6 +377,7 @@ def : SysReg<"mcause", 0x342>;
def : SysReg<"mtval", 0x343>;
def : DeprecatedSysRegName<"mbadaddr", 0x343>;
def : SysReg<"mip", 0x344>;
+def : SysReg<"mspcs", 0x349>;
def : SysReg<"mtinst", 0x34A>;
def : SysReg<"mtval2", 0x34B>;
def : SysReg<"miph", 0x354, RV32Only=true>;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 566786526dc7c..e5f1aa0292dd9 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -128,6 +128,8 @@
; RUN: llc -mtriple=riscv32 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s
; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s
; RUN: llc -mtriple=riscv32 -mattr=+smcntrpmf %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCNTRPMF %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-smcsps %s -o - | FileCheck --check-prefix=RV32SMCSPS %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-sscsps %s -o - | FileCheck --check-prefix=RV32SSCSPS %s
; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smpmpmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SMPMPMT %s
; RUN: llc -mtriple=riscv32 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV32SMRNMI %s
@@ -295,6 +297,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s
; RUN: llc -mtriple=riscv64 -mattr=+smcntrpmf %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCNTRPMF %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-smcsps %s -o - | FileCheck --check-prefix=RV64SMCSPS %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-sscsps %s -o - | FileCheck --check-prefix=RV64SSCSPS %s
; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smpmpmt %s -o - | FileCheck --check-prefixes=CHECK,RV64SMPMPMT %s
; RUN: llc -mtriple=riscv64 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV64SMRNMI %s
@@ -472,6 +476,8 @@
; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
; RV32SMCNTRPMF: .attribute 5, "rv32i2p1_smcntrpmf1p0"
+; RV32SMCSPS: .attribute 5, "rv32i2p1_smcsps0p19"
+; RV32SSCSPS: .attribute 5, "rv32i2p1_smcsps0p19_sscsps0p19"
; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
; RV32SMPMPMT: .attribute 5, "rv32i2p1_smpmpmt0p6"
; RV32SMRNMI: .attribute 5, "rv32i2p1_smrnmi1p0"
@@ -636,6 +642,8 @@
; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
; RV64SMCNTRPMF: .attribute 5, "rv64i2p1_smcntrpmf1p0"
+; RV64SMCSPS: .attribute 5, "rv64i2p1_smcsps0p19"
+; RV64SSCSPS: .attribute 5, "rv64i2p1_smcsps0p19_sscsps0p19"
; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
; RV64SMPMPMT: .attribute 5, "rv64i2p1_smpmpmt0p6"
; RV64SMRNMI: .attribute 5, "rv64i2p1_smrnmi1p0"
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index 679af65c8ee31..e35240b27509b 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -24,7 +24,9 @@
; CHECK-NEXT: experimental - Experimental intrinsics.
; CHECK-NEXT: experimental-p - 'P' ('Base P' (Packed SIMD)).
; CHECK-NEXT: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile.
+; CHECK-NEXT: experimental-smcsps - 'Smcsps' (Conditional Stack Pointer Swap at Machine Level).
; CHECK-NEXT: experimental-smpmpmt - 'Smpmpmt' (PMP-based Memory Types Extension).
+; CHECK-NEXT: experimental-sscsps - 'Sscsps' (Conditional Stack Pointer Swap at Supervisor Level).
; CHECK-NEXT: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses).
; CHECK-NEXT: experimental-xqccmt - 'Xqccmt' (Qualcomm 16-bit Table Jump).
; CHECK-NEXT: experimental-xsfmclic - 'XSfmclic' (SiFive CLIC Machine-mode CSRs).
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 367ec6f04d953..97ca289431a4a 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -354,6 +354,12 @@
.attribute arch, "rv32i_smcntrpmf1p0"
# CHECK: attribute 5, "rv32i2p1_smcntrpmf1p0"
+.attribute arch, "rv32i_smcsps0p19"
+# CHECK: attribute 5, "rv32i2p1_smcsps0p19"
+
+.attribute arch, "rv32i_sscsps0p19"
+# CHECK: attribute 5, "rv32i2p1_smcsps0p19_sscsps0p19"
+
.attribute arch, "rv32i_smepmp1p0"
# CHECK: attribute 5, "rv32i2p1_smepmp1p0"
diff --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s
index 016c14d6f840b..d8a3196af5d44 100644
--- a/llvm/test/MC/RISCV/machine-csr-names.s
+++ b/llvm/test/MC/RISCV/machine-csr-names.s
@@ -257,6 +257,20 @@ csrrs t1, mip, zero
# uimm12
csrrs t2, 0x344, zero
+# mspcs
+# name
+# CHECK-INST: csrrs t1, mspcs, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x90,0x34]
+# CHECK-INST-ALIAS: csrr t1, mspcs
+# uimm12
+# CHECK-INST: csrrs t2, mspcs, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x90,0x34]
+# CHECK-INST-ALIAS: csrr t2, mspcs
+# name
+csrrs t1, mspcs, zero
+# uimm12
+csrrs t2, 0x349, zero
+
# mtinst
# name
# CHECK-INST: csrrs t1, mtinst, zero
diff --git a/llvm/test/MC/RISCV/smcsps-invalid.s b/llvm/test/MC/RISCV/smcsps-invalid.s
new file mode 100644
index 0000000000000..105cd64a282f8
--- /dev/null
+++ b/llvm/test/MC/RISCV/smcsps-invalid.s
@@ -0,0 +1,31 @@
+# RUN: split-file %s %t
+# RUN: not llvm-mc -triple=riscv32 %t/no-features.s 2>&1 \
+# RUN: | FileCheck --check-prefix=NO-FEATURES %t/no-features.s
+# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-smcsps \
+# RUN: %t/no-sscsps.s 2>&1 \
+# RUN: | FileCheck --check-prefix=NO-SSCPS %t/no-sscsps.s
+# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-sscsps \
+# RUN: %t/invalid-operands.s 2>&1 \
+# RUN: | FileCheck --check-prefix=INVALID-OPERANDS %t/invalid-operands.s
+
+#--- no-features.s
+mcspspush sp, sp
+# NO-FEATURES: :[[#@LINE-1]]:1: error: instruction requires the following: 'Smcsps'
+mcspspop sp, sp
+# NO-FEATURES: :[[#@LINE-1]]:1: error: instruction requires the following: 'Smcsps'
+
+#--- no-sscsps.s
+scspspush sp, sp
+# NO-SSCPS: :[[#@LINE-1]]:1: error: instruction requires the following: 'Sscsps'
+scspspop sp, sp
+# NO-SSCPS: :[[#@LINE-1]]:1: error: instruction requires the following: 'Sscsps'
+
+#--- invalid-operands.s
+mcspspush x1, sp
+# INVALID-OPERANDS: :[[#@LINE-1]]:11: error: register must be sp (x2)
+mcspspop sp, x1
+# INVALID-OPERANDS: :[[#@LINE-1]]:14: error: register must be sp (x2)
+scspspush x1, sp
+# INVALID-OPERANDS: :[[#@LINE-1]]:11: error: register must be sp (x2)
+scspspop sp, x1
+# INVALID-OPERANDS: :[[#@LINE-1]]:14: error: register must be sp (x2)
diff --git a/llvm/test/MC/RISCV/smcsps-valid.s b/llvm/test/MC/RISCV/smcsps-valid.s
new file mode 100644
index 0000000000000..1a383771fbb28
--- /dev/null
+++ b/llvm/test/MC/RISCV/smcsps-valid.s
@@ -0,0 +1,30 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-sscsps \
+# RUN: -M no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 \
+# RUN: -mattr=+experimental-sscsps < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-sscsps -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-sscsps \
+# RUN: -M no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 \
+# RUN: -mattr=+experimental-sscsps < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-sscsps -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: mcspspush sp, sp
+# CHECK-ENC: encoding: [0x73,0x01,0x91,0x30]
+mcspspush x2, x2
+
+# CHECK-INST: mcspspop sp, sp
+# CHECK-ENC: encoding: [0x73,0x01,0xc1,0x30]
+mcspspop x2, x2
+
+# CHECK-INST: scspspush sp, sp
+# CHECK-ENC: encoding: [0x73,0x01,0x91,0x10]
+scspspush x2, x2
+
+# CHECK-INST: scspspop sp, sp
+# CHECK-ENC: encoding: [0x73,0x01,0xc1,0x10]
+scspspop x2, x2
diff --git a/llvm/test/MC/RISCV/supervisor-csr-names.s b/llvm/test/MC/RISCV/supervisor-csr-names.s
index 712ec56bb1127..bf85c7b935be7 100644
--- a/llvm/test/MC/RISCV/supervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/supervisor-csr-names.s
@@ -177,6 +177,20 @@ csrrs t1, sip, zero
# uimm12
csrrs t2, 0x144, zero
+# sspcs
+# name
+# CHECK-INST: csrrs t1, sspcs, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x90,0x14]
+# CHECK-INST-ALIAS: csrr t1, sspcs
+# uimm12
+# CHECK-INST: csrrs t2, sspcs, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x90,0x14]
+# CHECK-INST-ALIAS: csrr t2, sspcs
+# name
+csrrs t1, sspcs, zero
+# uimm12
+csrrs t2, 0x149, zero
+
#########################################
# Supervisor Protection and Translation
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 449f27fad3f54..8b10c313b29d0 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1639,7 +1639,9 @@ Experimental extensions
zvvmtls 0.1
zvvmttls 0.1
zvzip 0.1
+ smcsps 0.19
smpmpmt 0.6
+ sscsps 0.19
svukte 0.3
xqccmt 0.1
xsfmclic 0.1
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