[clang] [llvm] AMDGPU: Add missing smem-prefetch-insts to gfx12.5/gfx13 feature map (PR #213297)
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cfe-commits at lists.llvm.org
Fri Jul 31 08:48:04 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
<details>
<summary>Changes</summary>
fillAMDGCNFeatureMap omitted smem-prefetch-insts for gfx125x and gfx13,
so clang wrongly rejected __builtin_amdgcn_s_prefetch_data / _inst /
s_buffer_prefetch_data.
Co-authored-by: Claude (Claude-Opus-4.8)
---
Patch is 26.06 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/213297.diff
4 Files Affected:
- (modified) clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl (+16)
- (modified) clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl (+16)
- (modified) llvm/lib/TargetParser/AMDGPUTargetParser.cpp (+2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll (+378)
``````````diff
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
index 5da9dceaad40a..eafcf62e48ca2 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
@@ -1659,3 +1659,19 @@ void test_pk_add_min_max(global short2 *out, global ushort2 *uout, short2 a, sho
*out = __builtin_amdgcn_pk_add_min_i16(a, b, c, false);
*uout = __builtin_amdgcn_pk_add_min_u16(ua, ub, uc, true);
}
+
+// CHECK-LABEL: @test_s_prefetch_data(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[GP_ADDR:%.*]] = alloca ptr addrspace(1), align 8, addrspace(5)
+// CHECK-NEXT: [[LEN_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-NEXT: store ptr addrspace(1) [[GP:%.*]], ptr addrspace(5) [[GP_ADDR]], align 8
+// CHECK-NEXT: store i32 [[LEN:%.*]], ptr addrspace(5) [[LEN_ADDR]], align 4
+// CHECK-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr addrspace(5) [[GP_ADDR]], align 8
+// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[LEN_ADDR]], align 4
+// CHECK-NEXT: call void @llvm.amdgcn.s.prefetch.data.p1(ptr addrspace(1) [[TMP0]], i32 [[TMP1]])
+// CHECK-NEXT: ret void
+//
+void test_s_prefetch_data(global float *gp, unsigned int len)
+{
+ __builtin_amdgcn_s_prefetch_data(gp, len);
+}
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
index f5d341b31991c..de968e398d05d 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
@@ -171,3 +171,19 @@ void test_msad_u8(global unsigned int *out, unsigned int src0, unsigned int src1
*out = __builtin_amdgcn_msad_u8(src0, src1, src2);
}
+// CHECK-LABEL: @test_s_prefetch_data(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[GP_ADDR:%.*]] = alloca ptr addrspace(1), align 8, addrspace(5)
+// CHECK-NEXT: [[LEN_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-NEXT: store ptr addrspace(1) [[GP:%.*]], ptr addrspace(5) [[GP_ADDR]], align 8
+// CHECK-NEXT: store i32 [[LEN:%.*]], ptr addrspace(5) [[LEN_ADDR]], align 4
+// CHECK-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr addrspace(5) [[GP_ADDR]], align 8
+// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[LEN_ADDR]], align 4
+// CHECK-NEXT: call void @llvm.amdgcn.s.prefetch.data.p1(ptr addrspace(1) [[TMP0]], i32 [[TMP1]])
+// CHECK-NEXT: ret void
+//
+void test_s_prefetch_data(global float *gp, unsigned int len)
+{
+ __builtin_amdgcn_s_prefetch_data(gp, len);
+}
+
diff --git a/llvm/lib/TargetParser/AMDGPUTargetParser.cpp b/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
index c5df20fb6b63a..e6f467b606ceb 100644
--- a/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+++ b/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
@@ -535,6 +535,7 @@ static void fillAMDGCNFeatureMap(StringRef GPU, const Triple &T,
Features["image-insts"] = true;
Features["extended-image-insts"] = true;
Features["async-load-to-lds-insts"] = true;
+ Features["smem-prefetch-insts"] = true;
break;
case GK_GFX1251:
Features["gfx1251-gemm-insts"] = true;
@@ -598,6 +599,7 @@ static void fillAMDGCNFeatureMap(StringRef GPU, const Triple &T,
Features["async-load-to-lds-insts"] = true;
Features["async-store-from-lds-insts"] = true;
Features["asynccnt"] = true;
+ Features["smem-prefetch-insts"] = true;
break;
case GK_GFX1201:
case GK_GFX1200:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
index 35d8bff26ab12..b44d49ba57790 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
@@ -1,12 +1,42 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel=0 -mtriple=amdgpu12.00 < %s | FileCheck --check-prefixes=GCN,SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 < %s | FileCheck --check-prefixes=GCN,GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu12.50 < %s | FileCheck --check-prefixes=GFX1250-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu12.50 < %s | FileCheck --check-prefixes=GFX1250-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu13.10 < %s | FileCheck --check-prefixes=GFX1310-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu13.10 < %s | FileCheck --check-prefixes=GFX1310-GISEL %s
define amdgpu_ps void @prefetch_data_sgpr_base_sgpr_len(ptr addrspace(4) inreg %ptr, i32 inreg %len) {
; GCN-LABEL: prefetch_data_sgpr_base_sgpr_len:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_prefetch_data s[0:1], 0x0, s2, 0
; GCN-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: prefetch_data_sgpr_base_sgpr_len:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_prefetch_data s[0:1], 0x0, s2, 0
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: prefetch_data_sgpr_base_sgpr_len:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_prefetch_data s[0:1], 0x0, s2, 0
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1310-SDAG-LABEL: prefetch_data_sgpr_base_sgpr_len:
+; GFX1310-SDAG: ; %bb.0: ; %entry
+; GFX1310-SDAG-NEXT: s_prefetch_data s[0:1], 0x0, s2, 0
+; GFX1310-SDAG-NEXT: s_endpgm
+;
+; GFX1310-GISEL-LABEL: prefetch_data_sgpr_base_sgpr_len:
+; GFX1310-GISEL: ; %bb.0: ; %entry
+; GFX1310-GISEL-NEXT: s_prefetch_data s[0:1], 0x0, s2, 0
+; GFX1310-GISEL-NEXT: s_endpgm
entry:
tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %ptr, i32 %len)
ret void
@@ -17,6 +47,32 @@ define amdgpu_ps void @prefetch_data_sgpr_imm_base_sgpr_len(ptr addrspace(4) inr
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_prefetch_data s[0:1], 0x200, s2, 0
; GCN-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: prefetch_data_sgpr_imm_base_sgpr_len:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_prefetch_data s[0:1], 0x200, s2, 0
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: prefetch_data_sgpr_imm_base_sgpr_len:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_prefetch_data s[0:1], 0x200, s2, 0
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1310-SDAG-LABEL: prefetch_data_sgpr_imm_base_sgpr_len:
+; GFX1310-SDAG: ; %bb.0: ; %entry
+; GFX1310-SDAG-NEXT: s_prefetch_data s[0:1], 0x200, s2, 0
+; GFX1310-SDAG-NEXT: s_endpgm
+;
+; GFX1310-GISEL-LABEL: prefetch_data_sgpr_imm_base_sgpr_len:
+; GFX1310-GISEL: ; %bb.0: ; %entry
+; GFX1310-GISEL-NEXT: s_prefetch_data s[0:1], 0x200, s2, 0
+; GFX1310-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i32, ptr addrspace(4) %ptr, i32 128
tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %gep, i32 %len)
@@ -28,6 +84,32 @@ define amdgpu_ps void @prefetch_data_sgpr_base_imm_len(ptr addrspace(4) inreg %p
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_prefetch_data s[0:1], 0x0, null, 31
; GCN-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: prefetch_data_sgpr_base_imm_len:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_prefetch_data s[0:1], 0x0, null, 31
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: prefetch_data_sgpr_base_imm_len:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_prefetch_data s[0:1], 0x0, null, 31
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1310-SDAG-LABEL: prefetch_data_sgpr_base_imm_len:
+; GFX1310-SDAG: ; %bb.0: ; %entry
+; GFX1310-SDAG-NEXT: s_prefetch_data s[0:1], 0x0, null, 31
+; GFX1310-SDAG-NEXT: s_endpgm
+;
+; GFX1310-GISEL-LABEL: prefetch_data_sgpr_base_imm_len:
+; GFX1310-GISEL: ; %bb.0: ; %entry
+; GFX1310-GISEL-NEXT: s_prefetch_data s[0:1], 0x0, null, 31
+; GFX1310-GISEL-NEXT: s_endpgm
entry:
tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %ptr, i32 31)
ret void
@@ -38,6 +120,32 @@ define amdgpu_ps void @prefetch_data_sgpr_imm_base_imm_len(ptr addrspace(4) inre
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_prefetch_data s[0:1], 0x200, null, 31
; GCN-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: prefetch_data_sgpr_imm_base_imm_len:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_prefetch_data s[0:1], 0x200, null, 31
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: prefetch_data_sgpr_imm_base_imm_len:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_prefetch_data s[0:1], 0x200, null, 31
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1310-SDAG-LABEL: prefetch_data_sgpr_imm_base_imm_len:
+; GFX1310-SDAG: ; %bb.0: ; %entry
+; GFX1310-SDAG-NEXT: s_prefetch_data s[0:1], 0x200, null, 31
+; GFX1310-SDAG-NEXT: s_endpgm
+;
+; GFX1310-GISEL-LABEL: prefetch_data_sgpr_imm_base_imm_len:
+; GFX1310-GISEL: ; %bb.0: ; %entry
+; GFX1310-GISEL-NEXT: s_prefetch_data s[0:1], 0x200, null, 31
+; GFX1310-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i32, ptr addrspace(4) %ptr, i32 128
tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %gep, i32 31)
@@ -51,6 +159,40 @@ define amdgpu_ps void @prefetch_data_vgpr_base_sgpr_len(ptr addrspace(4) %ptr, i
; GCN-NEXT: v_readfirstlane_b32 s3, v1
; GCN-NEXT: s_prefetch_data s[2:3], 0x0, s0, 0
; GCN-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: prefetch_data_vgpr_base_sgpr_len:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1250-SDAG-NEXT: s_prefetch_data s[2:3], 0x0, s0, 0
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: prefetch_data_vgpr_base_sgpr_len:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1250-GISEL-NEXT: s_prefetch_data s[2:3], 0x0, s0, 0
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1310-SDAG-LABEL: prefetch_data_vgpr_base_sgpr_len:
+; GFX1310-SDAG: ; %bb.0: ; %entry
+; GFX1310-SDAG-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1310-SDAG-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1310-SDAG-NEXT: s_prefetch_data s[2:3], 0x0, s0, 0
+; GFX1310-SDAG-NEXT: s_endpgm
+;
+; GFX1310-GISEL-LABEL: prefetch_data_vgpr_base_sgpr_len:
+; GFX1310-GISEL: ; %bb.0: ; %entry
+; GFX1310-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1310-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1310-GISEL-NEXT: s_prefetch_data s[2:3], 0x0, s0, 0
+; GFX1310-GISEL-NEXT: s_endpgm
entry:
tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %ptr, i32 %len)
ret void
@@ -74,6 +216,48 @@ define amdgpu_ps void @prefetch_data_vgpr_imm_base_sgpr_len(ptr addrspace(4) %pt
; GISEL-NEXT: v_readfirstlane_b32 s3, v1
; GISEL-NEXT: s_prefetch_data s[2:3], 0x0, s0, 0
; GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: prefetch_data_vgpr_imm_base_sgpr_len:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1250-SDAG-NEXT: s_prefetch_data s[2:3], 0x200, s0, 0
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: prefetch_data_vgpr_imm_base_sgpr_len:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x200, v0
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1250-GISEL-NEXT: s_prefetch_data s[2:3], 0x0, s0, 0
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1310-SDAG-LABEL: prefetch_data_vgpr_imm_base_sgpr_len:
+; GFX1310-SDAG: ; %bb.0: ; %entry
+; GFX1310-SDAG-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1310-SDAG-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1310-SDAG-NEXT: s_prefetch_data s[2:3], 0x200, s0, 0
+; GFX1310-SDAG-NEXT: s_endpgm
+;
+; GFX1310-GISEL-LABEL: prefetch_data_vgpr_imm_base_sgpr_len:
+; GFX1310-GISEL: ; %bb.0: ; %entry
+; GFX1310-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x200, v0
+; GFX1310-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX1310-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1310-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1310-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1310-GISEL-NEXT: s_prefetch_data s[2:3], 0x0, s0, 0
+; GFX1310-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i32, ptr addrspace(4) %ptr, i32 128
tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %gep, i32 %len)
@@ -86,6 +270,36 @@ define amdgpu_ps void @prefetch_data_sgpr_base_vgpr_len(ptr addrspace(4) inreg %
; GCN-NEXT: v_readfirstlane_b32 s2, v0
; GCN-NEXT: s_prefetch_data s[0:1], 0x0, s2, 0
; GCN-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: prefetch_data_sgpr_base_vgpr_len:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1250-SDAG-NEXT: s_prefetch_data s[0:1], 0x0, s2, 0
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: prefetch_data_sgpr_base_vgpr_len:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1250-GISEL-NEXT: s_prefetch_data s[0:1], 0x0, s2, 0
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1310-SDAG-LABEL: prefetch_data_sgpr_base_vgpr_len:
+; GFX1310-SDAG: ; %bb.0: ; %entry
+; GFX1310-SDAG-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1310-SDAG-NEXT: s_prefetch_data s[0:1], 0x0, s2, 0
+; GFX1310-SDAG-NEXT: s_endpgm
+;
+; GFX1310-GISEL-LABEL: prefetch_data_sgpr_base_vgpr_len:
+; GFX1310-GISEL: ; %bb.0: ; %entry
+; GFX1310-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1310-GISEL-NEXT: s_prefetch_data s[0:1], 0x0, s2, 0
+; GFX1310-GISEL-NEXT: s_endpgm
entry:
tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %ptr, i32 %len)
ret void
@@ -96,6 +310,32 @@ define amdgpu_ps void @prefetch_data_sgpr_base_imm_len_global(ptr addrspace(1) i
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_prefetch_data s[0:1], 0x0, null, 31
; GCN-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: prefetch_data_sgpr_base_imm_len_global:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_prefetch_data s[0:1], 0x0, null, 31
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: prefetch_data_sgpr_base_imm_len_global:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_prefetch_data s[0:1], 0x0, null, 31
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1310-SDAG-LABEL: prefetch_data_sgpr_base_imm_len_global:
+; GFX1310-SDAG: ; %bb.0: ; %entry
+; GFX1310-SDAG-NEXT: s_prefetch_data s[0:1], 0x0, null, 31
+; GFX1310-SDAG-NEXT: s_endpgm
+;
+; GFX1310-GISEL-LABEL: prefetch_data_sgpr_base_imm_len_global:
+; GFX1310-GISEL: ; %bb.0: ; %entry
+; GFX1310-GISEL-NEXT: s_prefetch_data s[0:1], 0x0, null, 31
+; GFX1310-GISEL-NEXT: s_endpgm
entry:
tail call void @llvm.amdgcn.s.prefetch.data.p1(ptr addrspace(1) %ptr, i32 31)
ret void
@@ -106,6 +346,32 @@ define amdgpu_ps void @prefetch_data_sgpr_base_imm_len_flat(ptr inreg %ptr) {
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_prefetch_data s[0:1], 0x0, null, 31
; GCN-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: prefetch_data_sgpr_base_imm_len_flat:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_prefetch_data s[0:1], 0x0, null, 31
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: prefetch_data_sgpr_base_imm_len_flat:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_prefetch_data s[0:1], 0x0, null, 31
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1310-SDAG-LABEL: prefetch_data_sgpr_base_imm_len_flat:
+; GFX1310-SDAG: ; %bb.0: ; %entry
+; GFX1310-SDAG-NEXT: s_prefetch_data s[0:1], 0x0, null, 31
+; GFX1310-SDAG-NEXT: s_endpgm
+;
+; GFX1310-GISEL-LABEL: prefetch_data_sgpr_base_imm_len_flat:
+; GFX1310-GISEL: ; %bb.0: ; %entry
+; GFX1310-GISEL-NEXT: s_prefetch_data s[0:1], 0x0, null, 31
+; GFX1310-GISEL-NEXT: s_endpgm
entry:
tail call void @llvm.amdgcn.s.prefetch.data.p0(ptr %ptr, i32 31)
ret void
@@ -118,6 +384,40 @@ define amdgpu_ps void @prefetch_data_vgpr_base_imm_len(ptr addrspace(4) %ptr) {
; GCN-NEXT: v_readfirstlane_b32 s1, v1
; GCN-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
; GCN-NEXT: s_endpgm
+;
+...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/213297
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