[clang] [CIR][RISCV] Support Zknd builtins (PR #212947)

[via cfe-commits]

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-clangir

Author: Jianjian Guan (jacquesguan)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/212947.diff


3 Files Affected:

- (modified) clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp (+20-5) 
- (added) clang/test/CIR/CodeGenBuiltins/RISCV/riscv32-zknd.c (+23) 
- (added) clang/test/CIR/CodeGenBuiltins/RISCV/riscv64-zknd.c (+33) 


``````````diff
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
index de41c835d3eab..1ea584281bcbb 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
@@ -101,11 +101,26 @@ CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) {
     break;
   }
   // Zknd
-  case RISCV::BI__builtin_riscv_aes32dsi:
-  case RISCV::BI__builtin_riscv_aes32dsmi:
-  case RISCV::BI__builtin_riscv_aes64ds:
-  case RISCV::BI__builtin_riscv_aes64dsm:
-  case RISCV::BI__builtin_riscv_aes64im:
+  case RISCV::BI__builtin_riscv_aes32dsi: {
+    intrinsicName = "riscv.aes32dsi";
+    break;
+  }
+  case RISCV::BI__builtin_riscv_aes32dsmi: {
+    intrinsicName = "riscv.aes32dsmi";
+    break;
+  }
+  case RISCV::BI__builtin_riscv_aes64ds: {
+    intrinsicName = "riscv.aes64ds";
+    break;
+  }
+  case RISCV::BI__builtin_riscv_aes64dsm: {
+    intrinsicName = "riscv.aes64dsm";
+    break;
+  }
+  case RISCV::BI__builtin_riscv_aes64im: {
+    intrinsicName = "riscv.aes64im";
+    break;
+  }
   // Zknd & Zkne
   case RISCV::BI__builtin_riscv_aes64ks1i:
   case RISCV::BI__builtin_riscv_aes64ks2:
diff --git a/clang/test/CIR/CodeGenBuiltins/RISCV/riscv32-zknd.c b/clang/test/CIR/CodeGenBuiltins/RISCV/riscv32-zknd.c
new file mode 100644
index 0000000000000..cc27f8d956be7
--- /dev/null
+++ b/clang/test/CIR/CodeGenBuiltins/RISCV/riscv32-zknd.c
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zknd -fclangir -emit-cir %s -o - | FileCheck %s --check-prefixes=CIR
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zknd -fclangir -emit-llvm %s -o - | FileCheck %s --check-prefixes=LLVM
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zknd -emit-llvm %s -o - | FileCheck %s --check-prefixes=LLVM
+
+// CIR-LABEL: cir.func{{.*}} @test_builtin_aes32dsi(
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.aes32dsi" {{%.*}}, {{%.*}}, {{%.*}} : (!u32i, !u32i, !u32i) -> !u32i
+// CIR: cir.return
+// LLVM-LABEL: @test_builtin_aes32dsi(
+// LLVM: call i32 @llvm.riscv.aes32dsi(i32 {{%.*}}, i32 {{%.*}}, i32 3)
+// LLVM: ret i32
+unsigned int test_builtin_aes32dsi(unsigned int a, unsigned int b) {
+  return __builtin_riscv_aes32dsi(a, b, 3);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_builtin_aes32dsmi(
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.aes32dsmi" {{%.*}}, {{%.*}}, {{%.*}} : (!u32i, !u32i, !u32i) -> !u32i
+// CIR: cir.return
+// LLVM-LABEL: @test_builtin_aes32dsmi(
+// LLVM: call i32 @llvm.riscv.aes32dsmi(i32 {{%.*}}, i32 {{%.*}}, i32 3)
+// LLVM: ret i32
+unsigned int test_builtin_aes32dsmi(unsigned int a, unsigned int b) {
+  return __builtin_riscv_aes32dsmi(a, b, 3);
+}
diff --git a/clang/test/CIR/CodeGenBuiltins/RISCV/riscv64-zknd.c b/clang/test/CIR/CodeGenBuiltins/RISCV/riscv64-zknd.c
new file mode 100644
index 0000000000000..91e5a43919ca3
--- /dev/null
+++ b/clang/test/CIR/CodeGenBuiltins/RISCV/riscv64-zknd.c
@@ -0,0 +1,33 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zknd -fclangir -emit-cir %s -o - | FileCheck %s --check-prefixes=CIR
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zknd -fclangir -emit-llvm %s -o - | FileCheck %s --check-prefixes=LLVM
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zknd -emit-llvm %s -o - | FileCheck %s --check-prefixes=LLVM
+
+// CIR-LABEL: cir.func{{.*}} @test_builtin_aes64dsm(
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.aes64dsm" {{%.*}}, {{%.*}} : (!u64i, !u64i) -> !u64i
+// CIR: cir.return
+// LLVM-LABEL: @test_builtin_aes64dsm(
+// LLVM: call i64 @llvm.riscv.aes64dsm(i64 {{%.*}}, i64 {{%.*}})
+// LLVM: ret i64
+unsigned long test_builtin_aes64dsm(unsigned long a, unsigned long b) {
+  return __builtin_riscv_aes64dsm(a, b);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_builtin_aes64ds(
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.aes64ds" {{%.*}}, {{%.*}} : (!u64i, !u64i) -> !u64i
+// CIR: cir.return
+// LLVM-LABEL: @test_builtin_aes64ds(
+// LLVM: call i64 @llvm.riscv.aes64ds(i64 {{%.*}}, i64 {{%.*}})
+// LLVM: ret i64
+unsigned long test_builtin_aes64ds(unsigned long a, unsigned long b) {
+  return __builtin_riscv_aes64ds(a, b);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_builtin_aes64im(
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.aes64im" {{%.*}} : (!u64i) -> !u64i
+// CIR: cir.return
+// LLVM-LABEL: @test_builtin_aes64im(
+// LLVM: call i64 @llvm.riscv.aes64im(i64 {{%.*}})
+// LLVM: ret i64
+unsigned long test_builtin_aes64im(unsigned long a) {
+  return __builtin_riscv_aes64im(a);
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/212947