[clang] [llvm] [RISCV][MC] Support experimental Zilx extension (PR #209419)

[Pengcheng Wang via cfe-commits]

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@@ -0,0 +1,34 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+experimental-zilx %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR,CHECK-RV32-ERROR
+# RUN: not llvm-mc -triple=riscv64 --mattr=+experimental-zilx %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+# Zilx loads take three registers; the memory-operand syntax is not accepted.
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wangpc-pp wrote:

Thank folks for the asm syntax discussion!

Yes, it wasn't thought about much when writing the spec.  We are still at the very early stage so we have a lot of room to discuss it. :-)

I changed the syntax to:
> The assembly syntax for zilx instructions is:
>   mnemonic rd, (rs2), rs1
> where _rs2_, written in parentheses, is the base register and _rs1_ is the index register.

See also https://github.com/riscv/riscv-zilx/commit/9bc77361f884cec1c944f5f905403aa94c5b5fa5, please feel free to discuss here or create an issue in that repo. :-)

https://github.com/llvm/llvm-project/pull/209419