[clang] [clang][AMDGPU] Clean-up handling of named barrier type (PR #207687)

[Pierre van Houtryve via cfe-commits]

Pierre-vh wrote:

> One concern: for the AMD SPIR-V path, the device cc1 triple is still spirv64-amd-amdhsa, so it uses the SPIR/SPIR-V address-space map. Should LangAS::amdgpu_barrier also be mapped to local AS 3 there, like cuda_shared, with a CodeGen test? Otherwise a named barrier global for the AMD SPIR-V path may fall back to the default address space.

I am not sure how the SPIRV lowering path works. Do we still run the AMDGPU passes ?
This GV only works if the we can them. 

https://github.com/llvm/llvm-project/pull/207687