[clang] [llvm] [RISCV][MC] Support experimental Zilx extension (PR #209419)

[Craig Topper via cfe-commits]

================
@@ -0,0 +1,93 @@
+//===-- RISCVInstrInfoZilx.td - 'Zilx' instructions --------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// This file describes the RISC-V instructions for 'Zilx' (Indexed Integer
+/// Load).
+///
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+// Zilx indexed loads reuse the AMO major opcode. The addressing mode is
+// selected by funct5 (inst[31:27]) and the access width/signedness reuses the
+// base integer load funct3. rs1 is the index operand, rs2 is the base operand,
+// and the aq and rl bits are always 0.
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class ZilxLoad<bits<5> funct5, bits<3> funct3, string opcodestr>
+    : RVInstRAtomic<funct5, /*aq=*/0, /*rl=*/0, funct3, OPC_AMO,
+                    (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+                    opcodestr, "$rd, $rs1, $rs2">;
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZilx] in {
+// Unscaled indexed loads: address = base + index. Byte loads are not provided
+// in the unscaled mode.
+def LXH  : ZilxLoad<0b10010, 0b001, "lxh">,
+           Sched<[WriteLDH, ReadMemBase, ReadMemBase]>;
+def LXW  : ZilxLoad<0b10010, 0b010, "lxw">,
+           Sched<[WriteLDW, ReadMemBase, ReadMemBase]>;
+def LXHU : ZilxLoad<0b10010, 0b101, "lxhu">,
+           Sched<[WriteLDH, ReadMemBase, ReadMemBase]>;
+
+// Scaled indexed loads: address = base + (index << log2(access-size)). Byte
+// loads are provided only in scaled form (the byte scale factor is 1).
+def LXSB  : ZilxLoad<0b11010, 0b000, "lxsb">,
+            Sched<[WriteLDB, ReadMemBase, ReadMemBase]>;
+def LXSH  : ZilxLoad<0b11010, 0b001, "lxsh">,
+            Sched<[WriteLDH, ReadMemBase, ReadMemBase]>;
+def LXSW  : ZilxLoad<0b11010, 0b010, "lxsw">,
+            Sched<[WriteLDW, ReadMemBase, ReadMemBase]>;
+def LXSBU : ZilxLoad<0b11010, 0b100, "lxsbu">,
+            Sched<[WriteLDB, ReadMemBase, ReadMemBase]>;
+def LXSHU : ZilxLoad<0b11010, 0b101, "lxshu">,
+            Sched<[WriteLDH, ReadMemBase, ReadMemBase]>;
+} // Predicates = [HasStdExtZilx]
+
+let Predicates = [HasStdExtZilx, IsRV64] in {
----------------
topperc wrote:

Use `let append Predicates`?

https://github.com/llvm/llvm-project/pull/209419