[clang] [CIR][AArch64] Upstream store (vst[234]_*/vst[234]q_*) NEON builtins (PR #212040)
Vicky Nguyen via cfe-commits
cfe-commits at lists.llvm.org
Sat Jul 25 10:03:54 PDT 2026
https://github.com/iamvickynguyen created https://github.com/llvm/llvm-project/pull/212040
Related to https://github.com/llvm/llvm-project/issues/185382
CIR lowering for store intrinsics (`vst[234]_*`/`vst[234]q_*`) (https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#store)
Port tests:
- `clang/test/CodeGen/AArch64/neon-intrinsics.c`
- `clang/test/CodeGen/AArch64/neon-ldst-one.c`
- `clang/test/CodeGen/AArch64/poly64.c`
to `clang/test/CodeGen/AArch64/neon/store.c`
>From 746744308a876a11db7e3d2c99461fcbff60f581 Mon Sep 17 00:00:00 2001
From: Vicky Nguyen <vicky.trucviennguyen at gmail.com>
Date: Fri, 24 Jul 2026 13:42:03 -0700
Subject: [PATCH] [CIR][AArch64] Upstream store (vst[234]_*/vst[234]q_*) NEON
builtins
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 72 +-
clang/test/CodeGen/AArch64/neon-intrinsics.c | 1515 -----------
clang/test/CodeGen/AArch64/neon-ldst-one.c | 1628 ------------
clang/test/CodeGen/AArch64/neon/store.c | 2340 +++++++++++++++++
clang/test/CodeGen/AArch64/poly64.c | 114 -
5 files changed, 2402 insertions(+), 3267 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 969ed724d7f73..5c786ee754d64 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -2467,6 +2467,18 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
case NEON::BI__builtin_neon_vst1q_v:
case NEON::BI__builtin_neon_vst1_lane_v:
case NEON::BI__builtin_neon_vst1q_lane_v:
+ case NEON::BI__builtin_neon_vst2_v:
+ case NEON::BI__builtin_neon_vst2q_v:
+ case NEON::BI__builtin_neon_vst2_lane_v:
+ case NEON::BI__builtin_neon_vst2q_lane_v:
+ case NEON::BI__builtin_neon_vst3_v:
+ case NEON::BI__builtin_neon_vst3q_v:
+ case NEON::BI__builtin_neon_vst3_lane_v:
+ case NEON::BI__builtin_neon_vst3q_lane_v:
+ case NEON::BI__builtin_neon_vst4_v:
+ case NEON::BI__builtin_neon_vst4q_v:
+ case NEON::BI__builtin_neon_vst4_lane_v:
+ case NEON::BI__builtin_neon_vst4q_lane_v:
// Get the alignment for the argument in addition to the value;
// we'll use it later.
ptrOp0 = emitPointerWithAlignment(expr->getArg(0));
@@ -3360,22 +3372,62 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
case NEON::BI__builtin_neon_vld3q_lane_v:
case NEON::BI__builtin_neon_vld4_lane_v:
case NEON::BI__builtin_neon_vld4q_lane_v:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vst2_v:
- case NEON::BI__builtin_neon_vst2q_v:
+ case NEON::BI__builtin_neon_vst2q_v: {
+ // The builtin call has the pointer last, but the AArch64 st2 intrinsic
+ // takes the vector operands first and the pointer last.
+ std::rotate(ops.begin(), ops.begin() + 1, ops.end());
+ llvm::SmallVector<mlir::Type> argTypes = {ty, ty, builder.getVoidPtrTy()};
+ return emitNeonCall(cgm, builder, argTypes, ops, "aarch64.neon.st2",
+ cgm.voidTy, loc);
+ }
case NEON::BI__builtin_neon_vst2_lane_v:
- case NEON::BI__builtin_neon_vst2q_lane_v:
+ case NEON::BI__builtin_neon_vst2q_lane_v: {
+ std::rotate(ops.begin(), ops.begin() + 1, ops.end());
+ ops[2] = builder.createIntCast(ops[2], sInt64Ty);
+ llvm::SmallVector<mlir::Type> argTypes = {ty, ty, sInt64Ty,
+ builder.getVoidPtrTy()};
+ return emitNeonCall(cgm, builder, argTypes, ops, "aarch64.neon.st2lane",
+ cgm.voidTy, loc);
+ }
case NEON::BI__builtin_neon_vst3_v:
- case NEON::BI__builtin_neon_vst3q_v:
+ case NEON::BI__builtin_neon_vst3q_v: {
+ std::rotate(ops.begin(), ops.begin() + 1, ops.end());
+ llvm::SmallVector<mlir::Type> argTypes = {ty, ty, ty,
+ builder.getVoidPtrTy()};
+ return emitNeonCall(cgm, builder, argTypes, ops, "aarch64.neon.st3",
+ cgm.voidTy, loc);
+ }
case NEON::BI__builtin_neon_vst3_lane_v:
- case NEON::BI__builtin_neon_vst3q_lane_v:
+ case NEON::BI__builtin_neon_vst3q_lane_v: {
+ std::rotate(ops.begin(), ops.begin() + 1, ops.end());
+ ops[3] = builder.createIntCast(ops[3], sInt64Ty);
+ llvm::SmallVector<mlir::Type> argTypes = {ty, ty, ty, sInt64Ty,
+ builder.getVoidPtrTy()};
+ return emitNeonCall(cgm, builder, argTypes, ops, "aarch64.neon.st3lane",
+ cgm.voidTy, loc);
+ }
case NEON::BI__builtin_neon_vst4_v:
- case NEON::BI__builtin_neon_vst4q_v:
+ case NEON::BI__builtin_neon_vst4q_v: {
+ std::rotate(ops.begin(), ops.begin() + 1, ops.end());
+ llvm::SmallVector<mlir::Type> argTypes = {ty, ty, ty, ty,
+ builder.getVoidPtrTy()};
+ return emitNeonCall(cgm, builder, argTypes, ops, "aarch64.neon.st4",
+ cgm.voidTy, loc);
+ }
case NEON::BI__builtin_neon_vst4_lane_v:
- case NEON::BI__builtin_neon_vst4q_lane_v:
- cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented AArch64 builtin call: ") +
- getContext().BuiltinInfo.getName(builtinID));
- return mlir::Value{};
+ case NEON::BI__builtin_neon_vst4q_lane_v: {
+ std::rotate(ops.begin(), ops.begin() + 1, ops.end());
+ ops[4] = builder.createIntCast(ops[4], sInt64Ty);
+ llvm::SmallVector<mlir::Type> argTypes = {
+ ty, ty, ty, ty, sInt64Ty, builder.getVoidPtrTy()};
+ return emitNeonCall(cgm, builder, argTypes, ops, "aarch64.neon.st4lane",
+ cgm.voidTy, loc);
+ }
case NEON::BI__builtin_neon_vtrn_v:
case NEON::BI__builtin_neon_vtrnq_v: {
ops[1] = builder.createBitcast(ops[1], ty);
diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c
index 88c85668435b3..08000cde4d85f 100644
--- a/clang/test/CodeGen/AArch64/neon-intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c
@@ -7794,1521 +7794,6 @@ poly16x4x4_t test_vld4_p16(poly16_t const *a) {
return vld4_p16(a);
}
-// CHECK-LABEL: define dso_local void @test_vst2q_u8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_u8(uint8_t *a, uint8x16x2_t b) {
- vst2q_u8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_u16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <8 x i16>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <8 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <8 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v8i16.p0(<8 x i16> [[TMP2]], <8 x i16> [[TMP3]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_u16(uint16_t *a, uint16x8x2_t b) {
- vst2q_u16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_u32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <4 x i32>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> [[TMP2]], <4 x i32> [[TMP3]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_u32(uint32_t *a, uint32x4x2_t b) {
- vst2q_u32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_u64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <2 x i64>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <2 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <2 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v2i64.p0(<2 x i64> [[TMP2]], <2 x i64> [[TMP3]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_u64(uint64_t *a, uint64x2x2_t b) {
- vst2q_u64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_s8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_s8(int8_t *a, int8x16x2_t b) {
- vst2q_s8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_s16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <8 x i16>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <8 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <8 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v8i16.p0(<8 x i16> [[TMP2]], <8 x i16> [[TMP3]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_s16(int16_t *a, int16x8x2_t b) {
- vst2q_s16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_s32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <4 x i32>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> [[TMP2]], <4 x i32> [[TMP3]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_s32(int32_t *a, int32x4x2_t b) {
- vst2q_s32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_s64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <2 x i64>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <2 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <2 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v2i64.p0(<2 x i64> [[TMP2]], <2 x i64> [[TMP3]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_s64(int64_t *a, int64x2x2_t b) {
- vst2q_s64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_mf8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_mf8(mfloat8_t *a, mfloat8x16x2_t b) {
- vst2q_mf8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_f16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <8 x half>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <8 x half>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <8 x half>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i16>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP3]] to <8 x half>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v8f16.p0(<8 x half> [[TMP4]], <8 x half> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_f16(float16_t *a, float16x8x2_t b) {
- vst2q_f16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_f32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <4 x float>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x float>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[B_COERCE_FCA_0_EXTRACT]] to <4 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x float>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B_COERCE_FCA_1_EXTRACT]] to <4 x i32>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x float>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v4f32.p0(<4 x float> [[TMP4]], <4 x float> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_f32(float32_t *a, float32x4x2_t b) {
- vst2q_f32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_f64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <2 x double>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <2 x double>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_0_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <2 x double>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_1_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x double>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x double>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v2f64.p0(<2 x double> [[TMP4]], <2 x double> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_f64(float64_t *a, float64x2x2_t b) {
- vst2q_f64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_p8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_p8(poly8_t *a, poly8x16x2_t b) {
- vst2q_p8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_p16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <8 x i16>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <8 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <8 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v8i16.p0(<8 x i16> [[TMP2]], <8 x i16> [[TMP3]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_p16(poly16_t *a, poly16x8x2_t b) {
- vst2q_p16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_u8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_u8(uint8_t *a, uint8x8x2_t b) {
- vst2_u8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_u16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <4 x i16>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v4i16.p0(<4 x i16> [[TMP2]], <4 x i16> [[TMP3]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_u16(uint16_t *a, uint16x4x2_t b) {
- vst2_u16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_u32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <2 x i32>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <2 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <2 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v2i32.p0(<2 x i32> [[TMP2]], <2 x i32> [[TMP3]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_u32(uint32_t *a, uint32x2x2_t b) {
- vst2_u32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_u64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <1 x i64>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <1 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <1 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v1i64.p0(<1 x i64> [[TMP2]], <1 x i64> [[TMP3]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_u64(uint64_t *a, uint64x1x2_t b) {
- vst2_u64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_s8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_s8(int8_t *a, int8x8x2_t b) {
- vst2_s8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_s16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <4 x i16>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v4i16.p0(<4 x i16> [[TMP2]], <4 x i16> [[TMP3]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_s16(int16_t *a, int16x4x2_t b) {
- vst2_s16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_s32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <2 x i32>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <2 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <2 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v2i32.p0(<2 x i32> [[TMP2]], <2 x i32> [[TMP3]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_s32(int32_t *a, int32x2x2_t b) {
- vst2_s32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_s64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <1 x i64>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <1 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <1 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v1i64.p0(<1 x i64> [[TMP2]], <1 x i64> [[TMP3]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_s64(int64_t *a, int64x1x2_t b) {
- vst2_s64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_mf8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_mf8(mfloat8_t *a, mfloat8x8x2_t b) {
- vst2_mf8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_f16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <4 x half>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x half>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[B_COERCE_FCA_0_EXTRACT]] to <4 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x half>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x half> [[B_COERCE_FCA_1_EXTRACT]] to <4 x i16>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP1]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x half>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v4f16.p0(<4 x half> [[TMP4]], <4 x half> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_f16(float16_t *a, float16x4x2_t b) {
- vst2_f16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_f32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <2 x float>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <2 x float>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[B_COERCE_FCA_0_EXTRACT]] to <2 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <2 x float>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B_COERCE_FCA_1_EXTRACT]] to <2 x i32>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v2f32.p0(<2 x float> [[TMP4]], <2 x float> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_f32(float32_t *a, float32x2x2_t b) {
- vst2_f32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_f64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <1 x double>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <1 x double>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_0_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <1 x double>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_1_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_2_8_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP1]], i64 0
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[B_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[B_SROA_2_8_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP3]] to <1 x double>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v1f64.p0(<1 x double> [[TMP4]], <1 x double> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_f64(float64_t *a, float64x1x2_t b) {
- vst2_f64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_p8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_p8(poly8_t *a, poly8x8x2_t b) {
- vst2_p8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_p16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <4 x i16>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v4i16.p0(<4 x i16> [[TMP2]], <4 x i16> [[TMP3]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_p16(poly16_t *a, poly16x4x2_t b) {
- vst2_p16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_u8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], <16 x i8> [[B_COERCE_FCA_2_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_u8(uint8_t *a, uint8x16x3_t b) {
- vst3q_u8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_u16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <8 x i16>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <8 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <8 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <8 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v8i16.p0(<8 x i16> [[TMP3]], <8 x i16> [[TMP4]], <8 x i16> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_u16(uint16_t *a, uint16x8x3_t b) {
- vst3q_u16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_u32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <4 x i32>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <4 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <4 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <4 x i32>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v4i32.p0(<4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_u32(uint32_t *a, uint32x4x3_t b) {
- vst3q_u32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_u64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <2 x i64>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v2i64.p0(<2 x i64> [[TMP3]], <2 x i64> [[TMP4]], <2 x i64> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_u64(uint64_t *a, uint64x2x3_t b) {
- vst3q_u64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_s8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], <16 x i8> [[B_COERCE_FCA_2_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_s8(int8_t *a, int8x16x3_t b) {
- vst3q_s8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_s16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <8 x i16>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <8 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <8 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <8 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v8i16.p0(<8 x i16> [[TMP3]], <8 x i16> [[TMP4]], <8 x i16> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_s16(int16_t *a, int16x8x3_t b) {
- vst3q_s16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_s32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <4 x i32>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <4 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <4 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <4 x i32>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v4i32.p0(<4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_s32(int32_t *a, int32x4x3_t b) {
- vst3q_s32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_s64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <2 x i64>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v2i64.p0(<2 x i64> [[TMP3]], <2 x i64> [[TMP4]], <2 x i64> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_s64(int64_t *a, int64x2x3_t b) {
- vst3q_s64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_mf8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], <16 x i8> [[B_COERCE_FCA_2_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_mf8(mfloat8_t *a, mfloat8x16x3_t b) {
- vst3q_mf8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_f16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <8 x half>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <8 x half>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <8 x half>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <8 x half>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x half> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to <16 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP3]] to <8 x half>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP5]] to <8 x half>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v8f16.p0(<8 x half> [[TMP6]], <8 x half> [[TMP7]], <8 x half> [[TMP8]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_f16(float16_t *a, float16x8x3_t b) {
- vst3q_f16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_f32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <4 x float>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <4 x float>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[B_COERCE_FCA_0_EXTRACT]] to <4 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <4 x float>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B_COERCE_FCA_1_EXTRACT]] to <4 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <4 x float>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x float> [[B_COERCE_FCA_2_EXTRACT]] to <4 x i32>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to <16 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x float>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <4 x float>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v4f32.p0(<4 x float> [[TMP6]], <4 x float> [[TMP7]], <4 x float> [[TMP8]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_f32(float32_t *a, float32x4x3_t b) {
- vst3q_f32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_f64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <2 x double>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <2 x double>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_0_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <2 x double>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_1_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <2 x double>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_2_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to <16 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x double>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <2 x double>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v2f64.p0(<2 x double> [[TMP6]], <2 x double> [[TMP7]], <2 x double> [[TMP8]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_f64(float64_t *a, float64x2x3_t b) {
- vst3q_f64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_p8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], <16 x i8> [[B_COERCE_FCA_2_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_p8(poly8_t *a, poly8x16x3_t b) {
- vst3q_p8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_p16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <8 x i16>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <8 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <8 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <8 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v8i16.p0(<8 x i16> [[TMP3]], <8 x i16> [[TMP4]], <8 x i16> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_p16(poly16_t *a, poly16x8x3_t b) {
- vst3q_p16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_u8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], <8 x i8> [[B_COERCE_FCA_2_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_u8(uint8_t *a, uint8x8x3_t b) {
- vst3_u8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_u16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <4 x i16>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <4 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <4 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <4 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v4i16.p0(<4 x i16> [[TMP3]], <4 x i16> [[TMP4]], <4 x i16> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_u16(uint16_t *a, uint16x4x3_t b) {
- vst3_u16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_u32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <2 x i32>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <2 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <2 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <2 x i32>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v2i32.p0(<2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_u32(uint32_t *a, uint32x2x3_t b) {
- vst3_u32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_u64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <1 x i64>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v1i64.p0(<1 x i64> [[TMP3]], <1 x i64> [[TMP4]], <1 x i64> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_u64(uint64_t *a, uint64x1x3_t b) {
- vst3_u64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_s8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], <8 x i8> [[B_COERCE_FCA_2_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_s8(int8_t *a, int8x8x3_t b) {
- vst3_s8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_s16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <4 x i16>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <4 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <4 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <4 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v4i16.p0(<4 x i16> [[TMP3]], <4 x i16> [[TMP4]], <4 x i16> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_s16(int16_t *a, int16x4x3_t b) {
- vst3_s16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_s32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <2 x i32>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <2 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <2 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <2 x i32>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v2i32.p0(<2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_s32(int32_t *a, int32x2x3_t b) {
- vst3_s32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_s64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <1 x i64>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v1i64.p0(<1 x i64> [[TMP3]], <1 x i64> [[TMP4]], <1 x i64> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_s64(int64_t *a, int64x1x3_t b) {
- vst3_s64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_mf8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], <8 x i8> [[B_COERCE_FCA_2_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_mf8(mfloat8_t *a, mfloat8x8x3_t b) {
- vst3_mf8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_f16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <4 x half>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <4 x half>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[B_COERCE_FCA_0_EXTRACT]] to <4 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <4 x half>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x half> [[B_COERCE_FCA_1_EXTRACT]] to <4 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <4 x half>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x half> [[B_COERCE_FCA_2_EXTRACT]] to <4 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP1]] to <8 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP2]] to <8 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x half>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x half>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v4f16.p0(<4 x half> [[TMP6]], <4 x half> [[TMP7]], <4 x half> [[TMP8]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_f16(float16_t *a, float16x4x3_t b) {
- vst3_f16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_f32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <2 x float>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <2 x float>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[B_COERCE_FCA_0_EXTRACT]] to <2 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <2 x float>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B_COERCE_FCA_1_EXTRACT]] to <2 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <2 x float>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[B_COERCE_FCA_2_EXTRACT]] to <2 x i32>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP2]] to <8 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <2 x float>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP5]] to <2 x float>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v2f32.p0(<2 x float> [[TMP6]], <2 x float> [[TMP7]], <2 x float> [[TMP8]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_f32(float32_t *a, float32x2x3_t b) {
- vst3_f32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_f64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <1 x double>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <1 x double>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_0_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <1 x double>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_1_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_2_8_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP1]], i64 0
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <1 x double>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_2_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_4_16_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i64 0
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[B_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[B_SROA_2_8_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[B_SROA_4_16_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP3]] to <1 x double>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <1 x double>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP5]] to <1 x double>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v1f64.p0(<1 x double> [[TMP6]], <1 x double> [[TMP7]], <1 x double> [[TMP8]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_f64(float64_t *a, float64x1x3_t b) {
- vst3_f64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_p8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], <8 x i8> [[B_COERCE_FCA_2_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_p8(poly8_t *a, poly8x8x3_t b) {
- vst3_p8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_p16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <4 x i16>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <4 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <4 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <4 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v4i16.p0(<4 x i16> [[TMP3]], <4 x i16> [[TMP4]], <4 x i16> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_p16(poly16_t *a, poly16x4x3_t b) {
- vst3_p16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_u8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 3
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], <16 x i8> [[B_COERCE_FCA_2_EXTRACT]], <16 x i8> [[B_COERCE_FCA_3_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_u8(uint8_t *a, uint8x16x4_t b) {
- vst4q_u8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_u16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <8 x i16>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_3_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <8 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v8i16.p0(<8 x i16> [[TMP4]], <8 x i16> [[TMP5]], <8 x i16> [[TMP6]], <8 x i16> [[TMP7]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_u16(uint16_t *a, uint16x8x4_t b) {
- vst4q_u16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_u32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <4 x i32>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <4 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <4 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <4 x i32>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <4 x i32>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_3_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x i32>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v4i32.p0(<4 x i32> [[TMP4]], <4 x i32> [[TMP5]], <4 x i32> [[TMP6]], <4 x i32> [[TMP7]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_u32(uint32_t *a, uint32x4x4_t b) {
- vst4q_u32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_u64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <2 x i64>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_3_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v2i64.p0(<2 x i64> [[TMP4]], <2 x i64> [[TMP5]], <2 x i64> [[TMP6]], <2 x i64> [[TMP7]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_u64(uint64_t *a, uint64x2x4_t b) {
- vst4q_u64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_s8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 3
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], <16 x i8> [[B_COERCE_FCA_2_EXTRACT]], <16 x i8> [[B_COERCE_FCA_3_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_s8(int8_t *a, int8x16x4_t b) {
- vst4q_s8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_s16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <8 x i16>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_3_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <8 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v8i16.p0(<8 x i16> [[TMP4]], <8 x i16> [[TMP5]], <8 x i16> [[TMP6]], <8 x i16> [[TMP7]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_s16(int16_t *a, int16x8x4_t b) {
- vst4q_s16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_s32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <4 x i32>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <4 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <4 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <4 x i32>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <4 x i32>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_3_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x i32>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v4i32.p0(<4 x i32> [[TMP4]], <4 x i32> [[TMP5]], <4 x i32> [[TMP6]], <4 x i32> [[TMP7]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_s32(int32_t *a, int32x4x4_t b) {
- vst4q_s32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_s64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <2 x i64>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_3_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v2i64.p0(<2 x i64> [[TMP4]], <2 x i64> [[TMP5]], <2 x i64> [[TMP6]], <2 x i64> [[TMP7]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_s64(int64_t *a, int64x2x4_t b) {
- vst4q_s64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_mf8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 3
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], <16 x i8> [[B_COERCE_FCA_2_EXTRACT]], <16 x i8> [[B_COERCE_FCA_3_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_mf8(mfloat8_t *a, mfloat8x16x4_t b) {
- vst4q_mf8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_f16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <8 x half>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <8 x half>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <8 x half>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <8 x half>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x half> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <8 x half>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x half> [[B_COERCE_FCA_3_EXTRACT]] to <8 x i16>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP2]] to <16 x i8>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i16> [[TMP3]] to <16 x i8>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half>
-// CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP5]] to <8 x half>
-// CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x half>
-// CHECK-NEXT: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP7]] to <8 x half>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v8f16.p0(<8 x half> [[TMP8]], <8 x half> [[TMP9]], <8 x half> [[TMP10]], <8 x half> [[TMP11]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_f16(float16_t *a, float16x8x4_t b) {
- vst4q_f16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_f32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <4 x float>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <4 x float>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[B_COERCE_FCA_0_EXTRACT]] to <4 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <4 x float>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B_COERCE_FCA_1_EXTRACT]] to <4 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <4 x float>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x float> [[B_COERCE_FCA_2_EXTRACT]] to <4 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <4 x float>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x float> [[B_COERCE_FCA_3_EXTRACT]] to <4 x i32>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP2]] to <16 x i8>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to <16 x i8>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP4]] to <4 x float>
-// CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float>
-// CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <4 x float>
-// CHECK-NEXT: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x float>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v4f32.p0(<4 x float> [[TMP8]], <4 x float> [[TMP9]], <4 x float> [[TMP10]], <4 x float> [[TMP11]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_f32(float32_t *a, float32x4x4_t b) {
- vst4q_f32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_f64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <2 x double>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <2 x double>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_0_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <2 x double>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_1_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <2 x double>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_2_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <2 x double>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_3_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to <16 x i8>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to <16 x i8>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP4]] to <2 x double>
-// CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double>
-// CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <2 x double>
-// CHECK-NEXT: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP7]] to <2 x double>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v2f64.p0(<2 x double> [[TMP8]], <2 x double> [[TMP9]], <2 x double> [[TMP10]], <2 x double> [[TMP11]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_f64(float64_t *a, float64x2x4_t b) {
- vst4q_f64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_p8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 3
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], <16 x i8> [[B_COERCE_FCA_2_EXTRACT]], <16 x i8> [[B_COERCE_FCA_3_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_p8(poly8_t *a, poly8x16x4_t b) {
- vst4q_p8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_p16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <8 x i16>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_3_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <8 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v8i16.p0(<8 x i16> [[TMP4]], <8 x i16> [[TMP5]], <8 x i16> [[TMP6]], <8 x i16> [[TMP7]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_p16(poly16_t *a, poly16x8x4_t b) {
- vst4q_p16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_u8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 3
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], <8 x i8> [[B_COERCE_FCA_2_EXTRACT]], <8 x i8> [[B_COERCE_FCA_3_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_u8(uint8_t *a, uint8x8x4_t b) {
- vst4_u8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_u16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <4 x i16>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_3_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v4i16.p0(<4 x i16> [[TMP4]], <4 x i16> [[TMP5]], <4 x i16> [[TMP6]], <4 x i16> [[TMP7]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_u16(uint16_t *a, uint16x4x4_t b) {
- vst4_u16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_u32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <2 x i32>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <2 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <2 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <2 x i32>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <2 x i32>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_3_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v2i32.p0(<2 x i32> [[TMP4]], <2 x i32> [[TMP5]], <2 x i32> [[TMP6]], <2 x i32> [[TMP7]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_u32(uint32_t *a, uint32x2x4_t b) {
- vst4_u32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_u64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <1 x i64>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_3_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x i64>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP3]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v1i64.p0(<1 x i64> [[TMP4]], <1 x i64> [[TMP5]], <1 x i64> [[TMP6]], <1 x i64> [[TMP7]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_u64(uint64_t *a, uint64x1x4_t b) {
- vst4_u64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_s8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 3
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], <8 x i8> [[B_COERCE_FCA_2_EXTRACT]], <8 x i8> [[B_COERCE_FCA_3_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_s8(int8_t *a, int8x8x4_t b) {
- vst4_s8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_s16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <4 x i16>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_3_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v4i16.p0(<4 x i16> [[TMP4]], <4 x i16> [[TMP5]], <4 x i16> [[TMP6]], <4 x i16> [[TMP7]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_s16(int16_t *a, int16x4x4_t b) {
- vst4_s16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_s32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <2 x i32>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <2 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <2 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <2 x i32>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <2 x i32>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_3_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v2i32.p0(<2 x i32> [[TMP4]], <2 x i32> [[TMP5]], <2 x i32> [[TMP6]], <2 x i32> [[TMP7]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_s32(int32_t *a, int32x2x4_t b) {
- vst4_s32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_s64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <1 x i64>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_3_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x i64>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP3]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v1i64.p0(<1 x i64> [[TMP4]], <1 x i64> [[TMP5]], <1 x i64> [[TMP6]], <1 x i64> [[TMP7]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_s64(int64_t *a, int64x1x4_t b) {
- vst4_s64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_mf8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 3
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], <8 x i8> [[B_COERCE_FCA_2_EXTRACT]], <8 x i8> [[B_COERCE_FCA_3_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_mf8(mfloat8_t *a, mfloat8x8x4_t b) {
- vst4_mf8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_f16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <4 x half>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <4 x half>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[B_COERCE_FCA_0_EXTRACT]] to <4 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <4 x half>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x half> [[B_COERCE_FCA_1_EXTRACT]] to <4 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <4 x half>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x half> [[B_COERCE_FCA_2_EXTRACT]] to <4 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <4 x half>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x half> [[B_COERCE_FCA_3_EXTRACT]] to <4 x i16>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP1]] to <8 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP2]] to <8 x i8>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP3]] to <8 x i8>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half>
-// CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x half>
-// CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half>
-// CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP7]] to <4 x half>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v4f16.p0(<4 x half> [[TMP8]], <4 x half> [[TMP9]], <4 x half> [[TMP10]], <4 x half> [[TMP11]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_f16(float16_t *a, float16x4x4_t b) {
- vst4_f16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_f32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <2 x float>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <2 x float>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[B_COERCE_FCA_0_EXTRACT]] to <2 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <2 x float>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B_COERCE_FCA_1_EXTRACT]] to <2 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <2 x float>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[B_COERCE_FCA_2_EXTRACT]] to <2 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <2 x float>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x float> [[B_COERCE_FCA_3_EXTRACT]] to <2 x i32>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP2]] to <8 x i8>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP3]] to <8 x i8>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP4]] to <2 x float>
-// CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP5]] to <2 x float>
-// CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <2 x float>
-// CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP7]] to <2 x float>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v2f32.p0(<2 x float> [[TMP8]], <2 x float> [[TMP9]], <2 x float> [[TMP10]], <2 x float> [[TMP11]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_f32(float32_t *a, float32x2x4_t b) {
- vst4_f32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_f64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <1 x double>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <1 x double>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_0_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <1 x double>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_1_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_2_8_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP1]], i64 0
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <1 x double>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_2_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_4_16_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i64 0
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <1 x double>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_3_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_6_24_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP3]], i64 0
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[B_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[B_SROA_2_8_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[B_SROA_4_16_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[B_SROA_6_24_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP4]] to <1 x double>
-// CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP5]] to <1 x double>
-// CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <1 x double>
-// CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP7]] to <1 x double>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v1f64.p0(<1 x double> [[TMP8]], <1 x double> [[TMP9]], <1 x double> [[TMP10]], <1 x double> [[TMP11]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_f64(float64_t *a, float64x1x4_t b) {
- vst4_f64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_p8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 3
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], <8 x i8> [[B_COERCE_FCA_2_EXTRACT]], <8 x i8> [[B_COERCE_FCA_3_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_p8(poly8_t *a, poly8x8x4_t b) {
- vst4_p8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_p16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <4 x i16>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_3_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v4i16.p0(<4 x i16> [[TMP4]], <4 x i16> [[TMP5]], <4 x i16> [[TMP6]], <4 x i16> [[TMP7]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_p16(poly16_t *a, poly16x4x4_t b) {
- vst4_p16(a, b);
-}
-
// CHECK-LABEL: define dso_local %struct.float64x2x2_t @test_vld1q_f64_x2(
// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
diff --git a/clang/test/CodeGen/AArch64/neon-ldst-one.c b/clang/test/CodeGen/AArch64/neon-ldst-one.c
index 915788867a94c..d84d41e1b9f83 100644
--- a/clang/test/CodeGen/AArch64/neon-ldst-one.c
+++ b/clang/test/CodeGen/AArch64/neon-ldst-one.c
@@ -3308,1631 +3308,3 @@ poly64x1x4_t test_vld4_lane_p64(poly64_t *a, poly64x1x4_t b) {
return vld4_lane_p64(a, b, 0);
}
-// CHECK-LABEL: define dso_local void @test_vst2q_lane_u8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], i64 15, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_lane_u8(uint8_t *a, uint8x16x2_t b) {
- vst2q_lane_u8(a, b, 15);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_lane_u16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <8 x i16>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <8 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <8 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v8i16.p0(<8 x i16> [[TMP2]], <8 x i16> [[TMP3]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_lane_u16(uint16_t *a, uint16x8x2_t b) {
- vst2q_lane_u16(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_lane_u32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <4 x i32>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v4i32.p0(<4 x i32> [[TMP2]], <4 x i32> [[TMP3]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_lane_u32(uint32_t *a, uint32x4x2_t b) {
- vst2q_lane_u32(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_lane_u64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <2 x i64>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <2 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <2 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v2i64.p0(<2 x i64> [[TMP2]], <2 x i64> [[TMP3]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_lane_u64(uint64_t *a, uint64x2x2_t b) {
- vst2q_lane_u64(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_lane_s8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], i64 15, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_lane_s8(int8_t *a, int8x16x2_t b) {
- vst2q_lane_s8(a, b, 15);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_lane_s16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <8 x i16>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <8 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <8 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v8i16.p0(<8 x i16> [[TMP2]], <8 x i16> [[TMP3]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_lane_s16(int16_t *a, int16x8x2_t b) {
- vst2q_lane_s16(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_lane_s32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <4 x i32>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v4i32.p0(<4 x i32> [[TMP2]], <4 x i32> [[TMP3]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_lane_s32(int32_t *a, int32x4x2_t b) {
- vst2q_lane_s32(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_lane_s64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <2 x i64>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <2 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <2 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v2i64.p0(<2 x i64> [[TMP2]], <2 x i64> [[TMP3]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_lane_s64(int64_t *a, int64x2x2_t b) {
- vst2q_lane_s64(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_lane_mf8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], i64 15, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_lane_mf8(mfloat8_t *a, mfloat8x16x2_t b) {
- vst2q_lane_mf8(a, b, 15);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_lane_f16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <8 x half>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <8 x half>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <8 x half>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i16>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP3]] to <8 x half>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v8f16.p0(<8 x half> [[TMP4]], <8 x half> [[TMP5]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_lane_f16(float16_t *a, float16x8x2_t b) {
- vst2q_lane_f16(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_lane_f32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <4 x float>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x float>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[B_COERCE_FCA_0_EXTRACT]] to <4 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x float>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B_COERCE_FCA_1_EXTRACT]] to <4 x i32>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x float>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v4f32.p0(<4 x float> [[TMP4]], <4 x float> [[TMP5]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_lane_f32(float32_t *a, float32x4x2_t b) {
- vst2q_lane_f32(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_lane_f64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <2 x double>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <2 x double>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_0_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <2 x double>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_1_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x double>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x double>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v2f64.p0(<2 x double> [[TMP4]], <2 x double> [[TMP5]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_lane_f64(float64_t *a, float64x2x2_t b) {
- vst2q_lane_f64(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_lane_p8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], i64 15, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_lane_p8(poly8_t *a, poly8x16x2_t b) {
- vst2q_lane_p8(a, b, 15);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_lane_p16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <8 x i16>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <8 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <8 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v8i16.p0(<8 x i16> [[TMP2]], <8 x i16> [[TMP3]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_lane_p16(poly16_t *a, poly16x8x2_t b) {
- vst2q_lane_p16(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_lane_p64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <2 x i64>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <2 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <2 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v2i64.p0(<2 x i64> [[TMP2]], <2 x i64> [[TMP3]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_lane_p64(poly64_t *a, poly64x2x2_t b) {
- vst2q_lane_p64(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_lane_u8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_lane_u8(uint8_t *a, uint8x8x2_t b) {
- vst2_lane_u8(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_lane_u16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <4 x i16>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v4i16.p0(<4 x i16> [[TMP2]], <4 x i16> [[TMP3]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_lane_u16(uint16_t *a, uint16x4x2_t b) {
- vst2_lane_u16(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_lane_u32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <2 x i32>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <2 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <2 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v2i32.p0(<2 x i32> [[TMP2]], <2 x i32> [[TMP3]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_lane_u32(uint32_t *a, uint32x2x2_t b) {
- vst2_lane_u32(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_lane_u64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <1 x i64>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <1 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <1 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v1i64.p0(<1 x i64> [[TMP2]], <1 x i64> [[TMP3]], i64 0, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_lane_u64(uint64_t *a, uint64x1x2_t b) {
- vst2_lane_u64(a, b, 0);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_lane_s8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_lane_s8(int8_t *a, int8x8x2_t b) {
- vst2_lane_s8(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_lane_s16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <4 x i16>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v4i16.p0(<4 x i16> [[TMP2]], <4 x i16> [[TMP3]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_lane_s16(int16_t *a, int16x4x2_t b) {
- vst2_lane_s16(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_lane_s32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <2 x i32>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <2 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <2 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v2i32.p0(<2 x i32> [[TMP2]], <2 x i32> [[TMP3]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_lane_s32(int32_t *a, int32x2x2_t b) {
- vst2_lane_s32(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_lane_s64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <1 x i64>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <1 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <1 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v1i64.p0(<1 x i64> [[TMP2]], <1 x i64> [[TMP3]], i64 0, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_lane_s64(int64_t *a, int64x1x2_t b) {
- vst2_lane_s64(a, b, 0);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_lane_mf8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_lane_mf8(mfloat8_t *a, mfloat8x8x2_t b) {
- vst2_lane_mf8(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_lane_f16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <4 x half>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x half>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[B_COERCE_FCA_0_EXTRACT]] to <4 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x half>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x half> [[B_COERCE_FCA_1_EXTRACT]] to <4 x i16>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP1]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x half>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v4f16.p0(<4 x half> [[TMP4]], <4 x half> [[TMP5]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_lane_f16(float16_t *a, float16x4x2_t b) {
- vst2_lane_f16(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_lane_f32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <2 x float>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <2 x float>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[B_COERCE_FCA_0_EXTRACT]] to <2 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <2 x float>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B_COERCE_FCA_1_EXTRACT]] to <2 x i32>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v2f32.p0(<2 x float> [[TMP4]], <2 x float> [[TMP5]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_lane_f32(float32_t *a, float32x2x2_t b) {
- vst2_lane_f32(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_lane_f64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <1 x double>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <1 x double>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_0_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <1 x double>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_1_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_2_8_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP1]], i64 0
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[B_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[B_SROA_2_8_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP3]] to <1 x double>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v1f64.p0(<1 x double> [[TMP4]], <1 x double> [[TMP5]], i64 0, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_lane_f64(float64_t *a, float64x1x2_t b) {
- vst2_lane_f64(a, b, 0);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_lane_p8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_lane_p8(poly8_t *a, poly8x8x2_t b) {
- vst2_lane_p8(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_lane_p16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <4 x i16>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v4i16.p0(<4 x i16> [[TMP2]], <4 x i16> [[TMP3]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_lane_p16(poly16_t *a, poly16x4x2_t b) {
- vst2_lane_p16(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2_lane_p64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <1 x i64>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <1 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <1 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2lane.v1i64.p0(<1 x i64> [[TMP2]], <1 x i64> [[TMP3]], i64 0, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_lane_p64(poly64_t *a, poly64x1x2_t b) {
- vst2_lane_p64(a, b, 0);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_lane_u8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], <16 x i8> [[B_COERCE_FCA_2_EXTRACT]], i64 15, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_lane_u8(uint8_t *a, uint8x16x3_t b) {
- vst3q_lane_u8(a, b, 15);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_lane_u16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <8 x i16>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <8 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <8 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <8 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v8i16.p0(<8 x i16> [[TMP3]], <8 x i16> [[TMP4]], <8 x i16> [[TMP5]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_lane_u16(uint16_t *a, uint16x8x3_t b) {
- vst3q_lane_u16(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_lane_u32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <4 x i32>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <4 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <4 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <4 x i32>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v4i32.p0(<4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> [[TMP5]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_lane_u32(uint32_t *a, uint32x4x3_t b) {
- vst3q_lane_u32(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_lane_u64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <2 x i64>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v2i64.p0(<2 x i64> [[TMP3]], <2 x i64> [[TMP4]], <2 x i64> [[TMP5]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_lane_u64(uint64_t *a, uint64x2x3_t b) {
- vst3q_lane_u64(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_lane_s8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], <16 x i8> [[B_COERCE_FCA_2_EXTRACT]], i64 15, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_lane_s8(int8_t *a, int8x16x3_t b) {
- vst3q_lane_s8(a, b, 15);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_lane_s16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <8 x i16>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <8 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <8 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <8 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v8i16.p0(<8 x i16> [[TMP3]], <8 x i16> [[TMP4]], <8 x i16> [[TMP5]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_lane_s16(int16_t *a, int16x8x3_t b) {
- vst3q_lane_s16(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_lane_s32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <4 x i32>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <4 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <4 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <4 x i32>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v4i32.p0(<4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> [[TMP5]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_lane_s32(int32_t *a, int32x4x3_t b) {
- vst3q_lane_s32(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_lane_s64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <2 x i64>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v2i64.p0(<2 x i64> [[TMP3]], <2 x i64> [[TMP4]], <2 x i64> [[TMP5]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_lane_s64(int64_t *a, int64x2x3_t b) {
- vst3q_lane_s64(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_lane_mf8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], <16 x i8> [[B_COERCE_FCA_2_EXTRACT]], i64 15, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_lane_mf8(mfloat8_t *a, mfloat8x16x3_t b) {
- vst3q_lane_mf8(a, b, 15);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_lane_f16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <8 x half>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <8 x half>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <8 x half>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <8 x half>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x half> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to <16 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP3]] to <8 x half>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP5]] to <8 x half>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v8f16.p0(<8 x half> [[TMP6]], <8 x half> [[TMP7]], <8 x half> [[TMP8]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_lane_f16(float16_t *a, float16x8x3_t b) {
- vst3q_lane_f16(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_lane_f32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <4 x float>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <4 x float>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[B_COERCE_FCA_0_EXTRACT]] to <4 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <4 x float>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B_COERCE_FCA_1_EXTRACT]] to <4 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <4 x float>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x float> [[B_COERCE_FCA_2_EXTRACT]] to <4 x i32>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to <16 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x float>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <4 x float>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v4f32.p0(<4 x float> [[TMP6]], <4 x float> [[TMP7]], <4 x float> [[TMP8]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_lane_f32(float32_t *a, float32x4x3_t b) {
- vst3q_lane_f32(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_lane_f64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <2 x double>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <2 x double>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_0_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <2 x double>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_1_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <2 x double>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_2_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to <16 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x double>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <2 x double>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v2f64.p0(<2 x double> [[TMP6]], <2 x double> [[TMP7]], <2 x double> [[TMP8]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_lane_f64(float64_t *a, float64x2x3_t b) {
- vst3q_lane_f64(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_lane_p8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], <16 x i8> [[B_COERCE_FCA_2_EXTRACT]], i64 15, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_lane_p8(poly8_t *a, poly8x16x3_t b) {
- vst3q_lane_p8(a, b, 15);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_lane_p16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <8 x i16>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <8 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <8 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <8 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v8i16.p0(<8 x i16> [[TMP3]], <8 x i16> [[TMP4]], <8 x i16> [[TMP5]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_lane_p16(poly16_t *a, poly16x8x3_t b) {
- vst3q_lane_p16(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_lane_p64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <2 x i64>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v2i64.p0(<2 x i64> [[TMP3]], <2 x i64> [[TMP4]], <2 x i64> [[TMP5]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_lane_p64(poly64_t *a, poly64x2x3_t b) {
- vst3q_lane_p64(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_lane_u8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], <8 x i8> [[B_COERCE_FCA_2_EXTRACT]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_lane_u8(uint8_t *a, uint8x8x3_t b) {
- vst3_lane_u8(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_lane_u16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <4 x i16>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <4 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <4 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <4 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v4i16.p0(<4 x i16> [[TMP3]], <4 x i16> [[TMP4]], <4 x i16> [[TMP5]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_lane_u16(uint16_t *a, uint16x4x3_t b) {
- vst3_lane_u16(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_lane_u32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <2 x i32>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <2 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <2 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <2 x i32>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v2i32.p0(<2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32> [[TMP5]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_lane_u32(uint32_t *a, uint32x2x3_t b) {
- vst3_lane_u32(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_lane_u64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <1 x i64>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v1i64.p0(<1 x i64> [[TMP3]], <1 x i64> [[TMP4]], <1 x i64> [[TMP5]], i64 0, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_lane_u64(uint64_t *a, uint64x1x3_t b) {
- vst3_lane_u64(a, b, 0);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_lane_s8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], <8 x i8> [[B_COERCE_FCA_2_EXTRACT]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_lane_s8(int8_t *a, int8x8x3_t b) {
- vst3_lane_s8(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_lane_s16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <4 x i16>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <4 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <4 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <4 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v4i16.p0(<4 x i16> [[TMP3]], <4 x i16> [[TMP4]], <4 x i16> [[TMP5]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_lane_s16(int16_t *a, int16x4x3_t b) {
- vst3_lane_s16(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_lane_s32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <2 x i32>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <2 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <2 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <2 x i32>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v2i32.p0(<2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32> [[TMP5]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_lane_s32(int32_t *a, int32x2x3_t b) {
- vst3_lane_s32(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_lane_s64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <1 x i64>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v1i64.p0(<1 x i64> [[TMP3]], <1 x i64> [[TMP4]], <1 x i64> [[TMP5]], i64 0, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_lane_s64(int64_t *a, int64x1x3_t b) {
- vst3_lane_s64(a, b, 0);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_lane_mf8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], <8 x i8> [[B_COERCE_FCA_2_EXTRACT]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_lane_mf8(mfloat8_t *a, mfloat8x8x3_t b) {
- vst3_lane_mf8(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_lane_f16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <4 x half>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <4 x half>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[B_COERCE_FCA_0_EXTRACT]] to <4 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <4 x half>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x half> [[B_COERCE_FCA_1_EXTRACT]] to <4 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <4 x half>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x half> [[B_COERCE_FCA_2_EXTRACT]] to <4 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP1]] to <8 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP2]] to <8 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x half>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x half>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v4f16.p0(<4 x half> [[TMP6]], <4 x half> [[TMP7]], <4 x half> [[TMP8]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_lane_f16(float16_t *a, float16x4x3_t b) {
- vst3_lane_f16(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_lane_f32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <2 x float>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <2 x float>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[B_COERCE_FCA_0_EXTRACT]] to <2 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <2 x float>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B_COERCE_FCA_1_EXTRACT]] to <2 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <2 x float>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[B_COERCE_FCA_2_EXTRACT]] to <2 x i32>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP2]] to <8 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <2 x float>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP5]] to <2 x float>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v2f32.p0(<2 x float> [[TMP6]], <2 x float> [[TMP7]], <2 x float> [[TMP8]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_lane_f32(float32_t *a, float32x2x3_t b) {
- vst3_lane_f32(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_lane_f64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <1 x double>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <1 x double>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_0_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <1 x double>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_1_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_2_8_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP1]], i64 0
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <1 x double>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_2_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_4_16_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i64 0
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[B_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[B_SROA_2_8_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[B_SROA_4_16_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP3]] to <1 x double>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <1 x double>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP5]] to <1 x double>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v1f64.p0(<1 x double> [[TMP6]], <1 x double> [[TMP7]], <1 x double> [[TMP8]], i64 0, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_lane_f64(float64_t *a, float64x1x3_t b) {
- vst3_lane_f64(a, b, 0);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_lane_p8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], <8 x i8> [[B_COERCE_FCA_2_EXTRACT]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_lane_p8(poly8_t *a, poly8x8x3_t b) {
- vst3_lane_p8(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_lane_p16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <4 x i16>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <4 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <4 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <4 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v4i16.p0(<4 x i16> [[TMP3]], <4 x i16> [[TMP4]], <4 x i16> [[TMP5]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_lane_p16(poly16_t *a, poly16x4x3_t b) {
- vst3_lane_p16(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_lane_p64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <1 x i64>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3lane.v1i64.p0(<1 x i64> [[TMP3]], <1 x i64> [[TMP4]], <1 x i64> [[TMP5]], i64 0, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_lane_p64(poly64_t *a, poly64x1x3_t b) {
- vst3_lane_p64(a, b, 0);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_lane_u8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 3
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], <16 x i8> [[B_COERCE_FCA_2_EXTRACT]], <16 x i8> [[B_COERCE_FCA_3_EXTRACT]], i64 15, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_lane_u8(uint8_t *a, uint8x16x4_t b) {
- vst4q_lane_u8(a, b, 15);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_lane_u16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <8 x i16>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_3_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <8 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v8i16.p0(<8 x i16> [[TMP4]], <8 x i16> [[TMP5]], <8 x i16> [[TMP6]], <8 x i16> [[TMP7]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_lane_u16(uint16_t *a, uint16x8x4_t b) {
- vst4q_lane_u16(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_lane_u32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <4 x i32>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <4 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <4 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <4 x i32>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <4 x i32>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_3_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x i32>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v4i32.p0(<4 x i32> [[TMP4]], <4 x i32> [[TMP5]], <4 x i32> [[TMP6]], <4 x i32> [[TMP7]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_lane_u32(uint32_t *a, uint32x4x4_t b) {
- vst4q_lane_u32(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_lane_u64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <2 x i64>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_3_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v2i64.p0(<2 x i64> [[TMP4]], <2 x i64> [[TMP5]], <2 x i64> [[TMP6]], <2 x i64> [[TMP7]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_lane_u64(uint64_t *a, uint64x2x4_t b) {
- vst4q_lane_u64(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_lane_s8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 3
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], <16 x i8> [[B_COERCE_FCA_2_EXTRACT]], <16 x i8> [[B_COERCE_FCA_3_EXTRACT]], i64 15, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_lane_s8(int8_t *a, int8x16x4_t b) {
- vst4q_lane_s8(a, b, 15);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_lane_s16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <8 x i16>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_3_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <8 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v8i16.p0(<8 x i16> [[TMP4]], <8 x i16> [[TMP5]], <8 x i16> [[TMP6]], <8 x i16> [[TMP7]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_lane_s16(int16_t *a, int16x8x4_t b) {
- vst4q_lane_s16(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_lane_s32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <4 x i32>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <4 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <4 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <4 x i32>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <4 x i32>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[B_COERCE_FCA_3_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x i32>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v4i32.p0(<4 x i32> [[TMP4]], <4 x i32> [[TMP5]], <4 x i32> [[TMP6]], <4 x i32> [[TMP7]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_lane_s32(int32_t *a, int32x4x4_t b) {
- vst4q_lane_s32(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_lane_s64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <2 x i64>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_3_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v2i64.p0(<2 x i64> [[TMP4]], <2 x i64> [[TMP5]], <2 x i64> [[TMP6]], <2 x i64> [[TMP7]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_lane_s64(int64_t *a, int64x2x4_t b) {
- vst4q_lane_s64(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_lane_mf8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 3
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], <16 x i8> [[B_COERCE_FCA_2_EXTRACT]], <16 x i8> [[B_COERCE_FCA_3_EXTRACT]], i64 15, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_lane_mf8(mfloat8_t *a, mfloat8x16x4_t b) {
- vst4q_lane_mf8(a, b, 15);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_lane_f16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <8 x half>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <8 x half>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <8 x half>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <8 x half>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x half> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <8 x half>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x half> [[B_COERCE_FCA_3_EXTRACT]] to <8 x i16>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP2]] to <16 x i8>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i16> [[TMP3]] to <16 x i8>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half>
-// CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP5]] to <8 x half>
-// CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x half>
-// CHECK-NEXT: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP7]] to <8 x half>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v8f16.p0(<8 x half> [[TMP8]], <8 x half> [[TMP9]], <8 x half> [[TMP10]], <8 x half> [[TMP11]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_lane_f16(float16_t *a, float16x8x4_t b) {
- vst4q_lane_f16(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_lane_f32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <4 x float>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <4 x float>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[B_COERCE_FCA_0_EXTRACT]] to <4 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <4 x float>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B_COERCE_FCA_1_EXTRACT]] to <4 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <4 x float>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x float> [[B_COERCE_FCA_2_EXTRACT]] to <4 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <4 x float>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x float> [[B_COERCE_FCA_3_EXTRACT]] to <4 x i32>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP2]] to <16 x i8>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP3]] to <16 x i8>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP4]] to <4 x float>
-// CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float>
-// CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <4 x float>
-// CHECK-NEXT: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x float>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v4f32.p0(<4 x float> [[TMP8]], <4 x float> [[TMP9]], <4 x float> [[TMP10]], <4 x float> [[TMP11]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_lane_f32(float32_t *a, float32x4x4_t b) {
- vst4q_lane_f32(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_lane_f64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <2 x double>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <2 x double>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_0_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <2 x double>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_1_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <2 x double>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_2_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <2 x double>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_3_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to <16 x i8>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to <16 x i8>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP4]] to <2 x double>
-// CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double>
-// CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <2 x double>
-// CHECK-NEXT: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP7]] to <2 x double>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v2f64.p0(<2 x double> [[TMP8]], <2 x double> [[TMP9]], <2 x double> [[TMP10]], <2 x double> [[TMP11]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_lane_f64(float64_t *a, float64x2x4_t b) {
- vst4q_lane_f64(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_lane_p8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 3
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], <16 x i8> [[B_COERCE_FCA_2_EXTRACT]], <16 x i8> [[B_COERCE_FCA_3_EXTRACT]], i64 15, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_lane_p8(poly8_t *a, poly8x16x4_t b) {
- vst4q_lane_p8(a, b, 15);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_lane_p16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <8 x i16>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <8 x i16>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[B_COERCE_FCA_3_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <8 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v8i16.p0(<8 x i16> [[TMP4]], <8 x i16> [[TMP5]], <8 x i16> [[TMP6]], <8 x i16> [[TMP7]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_lane_p16(poly16_t *a, poly16x8x4_t b) {
- vst4q_lane_p16(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_lane_p64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <2 x i64>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_3_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v2i64.p0(<2 x i64> [[TMP4]], <2 x i64> [[TMP5]], <2 x i64> [[TMP6]], <2 x i64> [[TMP7]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_lane_p64(poly64_t *a, poly64x2x4_t b) {
- vst4q_lane_p64(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_lane_u8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 3
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], <8 x i8> [[B_COERCE_FCA_2_EXTRACT]], <8 x i8> [[B_COERCE_FCA_3_EXTRACT]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_lane_u8(uint8_t *a, uint8x8x4_t b) {
- vst4_lane_u8(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_lane_u16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <4 x i16>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_3_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v4i16.p0(<4 x i16> [[TMP4]], <4 x i16> [[TMP5]], <4 x i16> [[TMP6]], <4 x i16> [[TMP7]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_lane_u16(uint16_t *a, uint16x4x4_t b) {
- vst4_lane_u16(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_lane_u32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <2 x i32>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <2 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <2 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <2 x i32>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <2 x i32>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_3_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v2i32.p0(<2 x i32> [[TMP4]], <2 x i32> [[TMP5]], <2 x i32> [[TMP6]], <2 x i32> [[TMP7]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_lane_u32(uint32_t *a, uint32x2x4_t b) {
- vst4_lane_u32(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_lane_u64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <1 x i64>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_3_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x i64>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP3]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v1i64.p0(<1 x i64> [[TMP4]], <1 x i64> [[TMP5]], <1 x i64> [[TMP6]], <1 x i64> [[TMP7]], i64 0, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_lane_u64(uint64_t *a, uint64x1x4_t b) {
- vst4_lane_u64(a, b, 0);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_lane_s8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 3
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], <8 x i8> [[B_COERCE_FCA_2_EXTRACT]], <8 x i8> [[B_COERCE_FCA_3_EXTRACT]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_lane_s8(int8_t *a, int8x8x4_t b) {
- vst4_lane_s8(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_lane_s16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <4 x i16>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_3_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v4i16.p0(<4 x i16> [[TMP4]], <4 x i16> [[TMP5]], <4 x i16> [[TMP6]], <4 x i16> [[TMP7]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_lane_s16(int16_t *a, int16x4x4_t b) {
- vst4_lane_s16(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_lane_s32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <2 x i32>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <2 x i32>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <2 x i32>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <2 x i32>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <2 x i32>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[B_COERCE_FCA_3_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v2i32.p0(<2 x i32> [[TMP4]], <2 x i32> [[TMP5]], <2 x i32> [[TMP6]], <2 x i32> [[TMP7]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_lane_s32(int32_t *a, int32x2x4_t b) {
- vst4_lane_s32(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_lane_s64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <1 x i64>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_3_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x i64>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP3]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v1i64.p0(<1 x i64> [[TMP4]], <1 x i64> [[TMP5]], <1 x i64> [[TMP6]], <1 x i64> [[TMP7]], i64 0, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_lane_s64(int64_t *a, int64x1x4_t b) {
- vst4_lane_s64(a, b, 0);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_lane_mf8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 3
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], <8 x i8> [[B_COERCE_FCA_2_EXTRACT]], <8 x i8> [[B_COERCE_FCA_3_EXTRACT]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_lane_mf8(mfloat8_t *a, mfloat8x8x4_t b) {
- vst4_lane_mf8(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_lane_f16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <4 x half>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <4 x half>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[B_COERCE_FCA_0_EXTRACT]] to <4 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <4 x half>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x half> [[B_COERCE_FCA_1_EXTRACT]] to <4 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <4 x half>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x half> [[B_COERCE_FCA_2_EXTRACT]] to <4 x i16>
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <4 x half>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x half> [[B_COERCE_FCA_3_EXTRACT]] to <4 x i16>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP1]] to <8 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP2]] to <8 x i8>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP3]] to <8 x i8>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half>
-// CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x half>
-// CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half>
-// CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP7]] to <4 x half>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v4f16.p0(<4 x half> [[TMP8]], <4 x half> [[TMP9]], <4 x half> [[TMP10]], <4 x half> [[TMP11]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_lane_f16(float16_t *a, float16x4x4_t b) {
- vst4_lane_f16(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_lane_f32(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <2 x float>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <2 x float>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[B_COERCE_FCA_0_EXTRACT]] to <2 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <2 x float>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B_COERCE_FCA_1_EXTRACT]] to <2 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <2 x float>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[B_COERCE_FCA_2_EXTRACT]] to <2 x i32>
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <2 x float>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x float> [[B_COERCE_FCA_3_EXTRACT]] to <2 x i32>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP2]] to <8 x i8>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP3]] to <8 x i8>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP4]] to <2 x float>
-// CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP5]] to <2 x float>
-// CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <2 x float>
-// CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP7]] to <2 x float>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v2f32.p0(<2 x float> [[TMP8]], <2 x float> [[TMP9]], <2 x float> [[TMP10]], <2 x float> [[TMP11]], i64 1, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_lane_f32(float32_t *a, float32x2x4_t b) {
- vst4_lane_f32(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_lane_f64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <1 x double>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <1 x double>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_0_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <1 x double>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_1_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_2_8_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP1]], i64 0
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <1 x double>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_2_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_4_16_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i64 0
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <1 x double>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_3_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_6_24_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP3]], i64 0
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[B_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[B_SROA_2_8_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[B_SROA_4_16_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[B_SROA_6_24_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP4]] to <1 x double>
-// CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP5]] to <1 x double>
-// CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <1 x double>
-// CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP7]] to <1 x double>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v1f64.p0(<1 x double> [[TMP8]], <1 x double> [[TMP9]], <1 x double> [[TMP10]], <1 x double> [[TMP11]], i64 0, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_lane_f64(float64_t *a, float64x1x4_t b) {
- vst4_lane_f64(a, b, 0);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_lane_p8(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 3
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], <8 x i8> [[B_COERCE_FCA_2_EXTRACT]], <8 x i8> [[B_COERCE_FCA_3_EXTRACT]], i64 7, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_lane_p8(poly8_t *a, poly8x8x4_t b) {
- vst4_lane_p8(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_lane_p16(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <4 x i16>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <4 x i16>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[B_COERCE_FCA_3_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v4i16.p0(<4 x i16> [[TMP4]], <4 x i16> [[TMP5]], <4 x i16> [[TMP6]], <4 x i16> [[TMP7]], i64 3, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_lane_p16(poly16_t *a, poly16x4x4_t b) {
- vst4_lane_p16(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_lane_p64(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <1 x i64>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_3_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x i64>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP3]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4lane.v1i64.p0(<1 x i64> [[TMP4]], <1 x i64> [[TMP5]], <1 x i64> [[TMP6]], <1 x i64> [[TMP7]], i64 0, ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_lane_p64(poly64_t *a, poly64x1x4_t b) {
- vst4_lane_p64(a, b, 0);
-}
diff --git a/clang/test/CodeGen/AArch64/neon/store.c b/clang/test/CodeGen/AArch64/neon/store.c
index 5579bf27ad00d..0eaa79e02ca74 100644
--- a/clang/test/CodeGen/AArch64/neon/store.c
+++ b/clang/test/CodeGen/AArch64/neon/store.c
@@ -1484,3 +1484,2343 @@ void test_vst1q_u8_x4(uint8_t *a, uint8x16x4_t b) {
// LLVM: ret void
vst1q_u8_x4(a, b);
}
+
+// ALL-LABEL: @test_vst2_f16(
+void test_vst2_f16(float16_t *a, float16x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v4f16.p0(<4 x half> [[V0]], <4 x half> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2_f16(a, b);
+}
+
+// ALL-LABEL: @test_vst2_f32(
+void test_vst2_f32(float32_t *a, float32x2x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<2 x !cir.float>, !cir.vector<2 x !cir.float>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v2f32.p0(<2 x float> [[V0]], <2 x float> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2_f32(a, b);
+}
+
+// ALL-LABEL: @test_vst2_f64(
+void test_vst2_f64(float64_t *a, float64x1x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<1 x !cir.double>, !cir.vector<1 x !cir.double>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v1f64.p0(<1 x double> [[V0]], <1 x double> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2_f64(a, b);
+}
+
+// ALL-LABEL: @test_vst2_mf8(
+void test_vst2_mf8(mfloat8_t *a, mfloat8x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2_mf8(a, b);
+}
+
+// ALL-LABEL: @test_vst2_p16(
+void test_vst2_p16(poly16_t *a, poly16x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v4i16.p0(<4 x i16> [[V0]], <4 x i16> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2_p16(a, b);
+}
+
+// ALL-LABEL: @test_vst2_p64(
+void test_vst2_p64(poly64_t * ptr, poly64x1x2_t val) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v1i64.p0(<1 x i64> [[V0]], <1 x i64> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2_p64(ptr, val);
+}
+
+// ALL-LABEL: @test_vst2_p8(
+void test_vst2_p8(poly8_t *a, poly8x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2_p8(a, b);
+}
+
+// ALL-LABEL: @test_vst2_s16(
+void test_vst2_s16(int16_t *a, int16x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v4i16.p0(<4 x i16> [[V0]], <4 x i16> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2_s16(a, b);
+}
+
+// ALL-LABEL: @test_vst2_s32(
+void test_vst2_s32(int32_t *a, int32x2x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v2i32.p0(<2 x i32> [[V0]], <2 x i32> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2_s32(a, b);
+}
+
+// ALL-LABEL: @test_vst2_s64(
+void test_vst2_s64(int64_t *a, int64x1x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v1i64.p0(<1 x i64> [[V0]], <1 x i64> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2_s64(a, b);
+}
+
+// ALL-LABEL: @test_vst2_s8(
+void test_vst2_s8(int8_t *a, int8x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2_s8(a, b);
+}
+
+// ALL-LABEL: @test_vst2_u16(
+void test_vst2_u16(uint16_t *a, uint16x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v4i16.p0(<4 x i16> [[V0]], <4 x i16> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2_u16(a, b);
+}
+
+// ALL-LABEL: @test_vst2_u32(
+void test_vst2_u32(uint32_t *a, uint32x2x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v2i32.p0(<2 x i32> [[V0]], <2 x i32> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2_u32(a, b);
+}
+
+// ALL-LABEL: @test_vst2_u64(
+void test_vst2_u64(uint64_t *a, uint64x1x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v1i64.p0(<1 x i64> [[V0]], <1 x i64> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2_u64(a, b);
+}
+
+// ALL-LABEL: @test_vst2_u8(
+void test_vst2_u8(uint8_t *a, uint8x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2_u8(a, b);
+}
+
+// ALL-LABEL: @test_vst2q_f16(
+void test_vst2q_f16(float16_t *a, float16x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v8f16.p0(<8 x half> [[V0]], <8 x half> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2q_f16(a, b);
+}
+
+// ALL-LABEL: @test_vst2q_f32(
+void test_vst2q_f32(float32_t *a, float32x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<4 x !cir.float>, !cir.vector<4 x !cir.float>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v4f32.p0(<4 x float> [[V0]], <4 x float> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2q_f32(a, b);
+}
+
+// ALL-LABEL: @test_vst2q_f64(
+void test_vst2q_f64(float64_t *a, float64x2x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<2 x !cir.double>, !cir.vector<2 x !cir.double>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v2f64.p0(<2 x double> [[V0]], <2 x double> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2q_f64(a, b);
+}
+
+// ALL-LABEL: @test_vst2q_mf8(
+void test_vst2q_mf8(mfloat8_t *a, mfloat8x16x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2q_mf8(a, b);
+}
+
+// ALL-LABEL: @test_vst2q_p16(
+void test_vst2q_p16(poly16_t *a, poly16x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v8i16.p0(<8 x i16> [[V0]], <8 x i16> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2q_p16(a, b);
+}
+
+// ALL-LABEL: @test_vst2q_p64(
+void test_vst2q_p64(poly64_t * ptr, poly64x2x2_t val) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v2i64.p0(<2 x i64> [[V0]], <2 x i64> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2q_p64(ptr, val);
+}
+
+// ALL-LABEL: @test_vst2q_p8(
+void test_vst2q_p8(poly8_t *a, poly8x16x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2q_p8(a, b);
+}
+
+// ALL-LABEL: @test_vst2q_s16(
+void test_vst2q_s16(int16_t *a, int16x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v8i16.p0(<8 x i16> [[V0]], <8 x i16> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2q_s16(a, b);
+}
+
+// ALL-LABEL: @test_vst2q_s32(
+void test_vst2q_s32(int32_t *a, int32x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> [[V0]], <4 x i32> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2q_s32(a, b);
+}
+
+// ALL-LABEL: @test_vst2q_s64(
+void test_vst2q_s64(int64_t *a, int64x2x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v2i64.p0(<2 x i64> [[V0]], <2 x i64> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2q_s64(a, b);
+}
+
+// ALL-LABEL: @test_vst2q_s8(
+void test_vst2q_s8(int8_t *a, int8x16x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2q_s8(a, b);
+}
+
+// ALL-LABEL: @test_vst2q_u16(
+void test_vst2q_u16(uint16_t *a, uint16x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v8i16.p0(<8 x i16> [[V0]], <8 x i16> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2q_u16(a, b);
+}
+
+// ALL-LABEL: @test_vst2q_u32(
+void test_vst2q_u32(uint32_t *a, uint32x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> [[V0]], <4 x i32> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2q_u32(a, b);
+}
+
+// ALL-LABEL: @test_vst2q_u64(
+void test_vst2q_u64(uint64_t *a, uint64x2x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v2i64.p0(<2 x i64> [[V0]], <2 x i64> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2q_u64(a, b);
+}
+
+// ALL-LABEL: @test_vst2q_u8(
+void test_vst2q_u8(uint8_t *a, uint8x16x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2" {{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], ptr [[A]])
+// LLVM: ret void
+ vst2q_u8(a, b);
+}
+
+// ALL-LABEL: @test_vst2_lane_f16(
+void test_vst2_lane_f16(float16_t *a, float16x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v4f16.p0(<4 x half> [[V0]], <4 x half> [[V1]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst2_lane_f16(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst2_lane_f32(
+void test_vst2_lane_f32(float32_t *a, float32x2x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<2 x !cir.float>, !cir.vector<2 x !cir.float>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v2f32.p0(<2 x float> [[V0]], <2 x float> [[V1]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst2_lane_f32(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst2_lane_f64(
+void test_vst2_lane_f64(float64_t *a, float64x1x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<1 x !cir.double>, !cir.vector<1 x !cir.double>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v1f64.p0(<1 x double> [[V0]], <1 x double> [[V1]], i64 0, ptr [[A]])
+// LLVM: ret void
+ vst2_lane_f64(a, b, 0);
+}
+
+// ALL-LABEL: @test_vst2_lane_mf8(
+void test_vst2_lane_mf8(mfloat8_t *a, mfloat8x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst2_lane_mf8(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst2_lane_p16(
+void test_vst2_lane_p16(poly16_t *a, poly16x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v4i16.p0(<4 x i16> [[V0]], <4 x i16> [[V1]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst2_lane_p16(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst2_lane_p64(
+void test_vst2_lane_p64(poly64_t *a, poly64x1x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v1i64.p0(<1 x i64> [[V0]], <1 x i64> [[V1]], i64 0, ptr [[A]])
+// LLVM: ret void
+ vst2_lane_p64(a, b, 0);
+}
+
+// ALL-LABEL: @test_vst2_lane_p8(
+void test_vst2_lane_p8(poly8_t *a, poly8x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst2_lane_p8(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst2_lane_s16(
+void test_vst2_lane_s16(int16_t *a, int16x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v4i16.p0(<4 x i16> [[V0]], <4 x i16> [[V1]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst2_lane_s16(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst2_lane_s32(
+void test_vst2_lane_s32(int32_t *a, int32x2x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v2i32.p0(<2 x i32> [[V0]], <2 x i32> [[V1]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst2_lane_s32(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst2_lane_s64(
+void test_vst2_lane_s64(int64_t *a, int64x1x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v1i64.p0(<1 x i64> [[V0]], <1 x i64> [[V1]], i64 0, ptr [[A]])
+// LLVM: ret void
+ vst2_lane_s64(a, b, 0);
+}
+
+// ALL-LABEL: @test_vst2_lane_s8(
+void test_vst2_lane_s8(int8_t *a, int8x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst2_lane_s8(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst2_lane_u16(
+void test_vst2_lane_u16(uint16_t *a, uint16x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v4i16.p0(<4 x i16> [[V0]], <4 x i16> [[V1]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst2_lane_u16(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst2_lane_u32(
+void test_vst2_lane_u32(uint32_t *a, uint32x2x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v2i32.p0(<2 x i32> [[V0]], <2 x i32> [[V1]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst2_lane_u32(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst2_lane_u64(
+void test_vst2_lane_u64(uint64_t *a, uint64x1x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v1i64.p0(<1 x i64> [[V0]], <1 x i64> [[V1]], i64 0, ptr [[A]])
+// LLVM: ret void
+ vst2_lane_u64(a, b, 0);
+}
+
+// ALL-LABEL: @test_vst2_lane_u8(
+void test_vst2_lane_u8(uint8_t *a, uint8x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst2_lane_u8(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst2q_lane_f16(
+void test_vst2q_lane_f16(float16_t *a, float16x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v8f16.p0(<8 x half> [[V0]], <8 x half> [[V1]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst2q_lane_f16(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst2q_lane_f32(
+void test_vst2q_lane_f32(float32_t *a, float32x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<4 x !cir.float>, !cir.vector<4 x !cir.float>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v4f32.p0(<4 x float> [[V0]], <4 x float> [[V1]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst2q_lane_f32(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst2q_lane_f64(
+void test_vst2q_lane_f64(float64_t *a, float64x2x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<2 x !cir.double>, !cir.vector<2 x !cir.double>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v2f64.p0(<2 x double> [[V0]], <2 x double> [[V1]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst2q_lane_f64(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst2q_lane_mf8(
+void test_vst2q_lane_mf8(mfloat8_t *a, mfloat8x16x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], i64 15, ptr [[A]])
+// LLVM: ret void
+ vst2q_lane_mf8(a, b, 15);
+}
+
+// ALL-LABEL: @test_vst2q_lane_p16(
+void test_vst2q_lane_p16(poly16_t *a, poly16x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v8i16.p0(<8 x i16> [[V0]], <8 x i16> [[V1]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst2q_lane_p16(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst2q_lane_p64(
+void test_vst2q_lane_p64(poly64_t *a, poly64x2x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v2i64.p0(<2 x i64> [[V0]], <2 x i64> [[V1]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst2q_lane_p64(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst2q_lane_p8(
+void test_vst2q_lane_p8(poly8_t *a, poly8x16x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], i64 15, ptr [[A]])
+// LLVM: ret void
+ vst2q_lane_p8(a, b, 15);
+}
+
+// ALL-LABEL: @test_vst2q_lane_s16(
+void test_vst2q_lane_s16(int16_t *a, int16x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v8i16.p0(<8 x i16> [[V0]], <8 x i16> [[V1]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst2q_lane_s16(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst2q_lane_s32(
+void test_vst2q_lane_s32(int32_t *a, int32x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v4i32.p0(<4 x i32> [[V0]], <4 x i32> [[V1]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst2q_lane_s32(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst2q_lane_s64(
+void test_vst2q_lane_s64(int64_t *a, int64x2x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v2i64.p0(<2 x i64> [[V0]], <2 x i64> [[V1]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst2q_lane_s64(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst2q_lane_s8(
+void test_vst2q_lane_s8(int8_t *a, int8x16x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], i64 15, ptr [[A]])
+// LLVM: ret void
+ vst2q_lane_s8(a, b, 15);
+}
+
+// ALL-LABEL: @test_vst2q_lane_u16(
+void test_vst2q_lane_u16(uint16_t *a, uint16x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v8i16.p0(<8 x i16> [[V0]], <8 x i16> [[V1]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst2q_lane_u16(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst2q_lane_u32(
+void test_vst2q_lane_u32(uint32_t *a, uint32x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v4i32.p0(<4 x i32> [[V0]], <4 x i32> [[V1]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst2q_lane_u32(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst2q_lane_u64(
+void test_vst2q_lane_u64(uint64_t *a, uint64x2x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v2i64.p0(<2 x i64> [[V0]], <2 x i64> [[V1]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst2q_lane_u64(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst2q_lane_u8(
+void test_vst2q_lane_u8(uint8_t *a, uint8x16x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st2lane" {{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM: call void @llvm.aarch64.neon.st2lane.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], i64 15, ptr [[A]])
+// LLVM: ret void
+ vst2q_lane_u8(a, b, 15);
+}
+
+// ALL-LABEL: @test_vst3_f16(
+void test_vst3_f16(float16_t *a, float16x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v4f16.p0(<4 x half> [[V0]], <4 x half> [[V1]], <4 x half> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3_f16(a, b);
+}
+
+// ALL-LABEL: @test_vst3_f32(
+void test_vst3_f32(float32_t *a, float32x2x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<2 x !cir.float>, !cir.vector<2 x !cir.float>, !cir.vector<2 x !cir.float>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v2f32.p0(<2 x float> [[V0]], <2 x float> [[V1]], <2 x float> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3_f32(a, b);
+}
+
+// ALL-LABEL: @test_vst3_f64(
+void test_vst3_f64(float64_t *a, float64x1x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<1 x !cir.double>, !cir.vector<1 x !cir.double>, !cir.vector<1 x !cir.double>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v1f64.p0(<1 x double> [[V0]], <1 x double> [[V1]], <1 x double> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3_f64(a, b);
+}
+
+// ALL-LABEL: @test_vst3_mf8(
+void test_vst3_mf8(mfloat8_t *a, mfloat8x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], <8 x i8> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3_mf8(a, b);
+}
+
+// ALL-LABEL: @test_vst3_p16(
+void test_vst3_p16(poly16_t *a, poly16x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v4i16.p0(<4 x i16> [[V0]], <4 x i16> [[V1]], <4 x i16> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3_p16(a, b);
+}
+
+// ALL-LABEL: @test_vst3_p64(
+void test_vst3_p64(poly64_t * ptr, poly64x1x3_t val) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v1i64.p0(<1 x i64> [[V0]], <1 x i64> [[V1]], <1 x i64> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3_p64(ptr, val);
+}
+
+// ALL-LABEL: @test_vst3_p8(
+void test_vst3_p8(poly8_t *a, poly8x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], <8 x i8> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3_p8(a, b);
+}
+
+// ALL-LABEL: @test_vst3_s16(
+void test_vst3_s16(int16_t *a, int16x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v4i16.p0(<4 x i16> [[V0]], <4 x i16> [[V1]], <4 x i16> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3_s16(a, b);
+}
+
+// ALL-LABEL: @test_vst3_s32(
+void test_vst3_s32(int32_t *a, int32x2x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v2i32.p0(<2 x i32> [[V0]], <2 x i32> [[V1]], <2 x i32> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3_s32(a, b);
+}
+
+// ALL-LABEL: @test_vst3_s64(
+void test_vst3_s64(int64_t *a, int64x1x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v1i64.p0(<1 x i64> [[V0]], <1 x i64> [[V1]], <1 x i64> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3_s64(a, b);
+}
+
+// ALL-LABEL: @test_vst3_s8(
+void test_vst3_s8(int8_t *a, int8x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], <8 x i8> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3_s8(a, b);
+}
+
+// ALL-LABEL: @test_vst3_u16(
+void test_vst3_u16(uint16_t *a, uint16x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v4i16.p0(<4 x i16> [[V0]], <4 x i16> [[V1]], <4 x i16> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3_u16(a, b);
+}
+
+// ALL-LABEL: @test_vst3_u32(
+void test_vst3_u32(uint32_t *a, uint32x2x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v2i32.p0(<2 x i32> [[V0]], <2 x i32> [[V1]], <2 x i32> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3_u32(a, b);
+}
+
+// ALL-LABEL: @test_vst3_u64(
+void test_vst3_u64(uint64_t *a, uint64x1x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v1i64.p0(<1 x i64> [[V0]], <1 x i64> [[V1]], <1 x i64> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3_u64(a, b);
+}
+
+// ALL-LABEL: @test_vst3_u8(
+void test_vst3_u8(uint8_t *a, uint8x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], <8 x i8> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3_u8(a, b);
+}
+
+// ALL-LABEL: @test_vst3q_f16(
+void test_vst3q_f16(float16_t *a, float16x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v8f16.p0(<8 x half> [[V0]], <8 x half> [[V1]], <8 x half> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3q_f16(a, b);
+}
+
+// ALL-LABEL: @test_vst3q_f32(
+void test_vst3q_f32(float32_t *a, float32x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<4 x !cir.float>, !cir.vector<4 x !cir.float>, !cir.vector<4 x !cir.float>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v4f32.p0(<4 x float> [[V0]], <4 x float> [[V1]], <4 x float> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3q_f32(a, b);
+}
+
+// ALL-LABEL: @test_vst3q_f64(
+void test_vst3q_f64(float64_t *a, float64x2x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<2 x !cir.double>, !cir.vector<2 x !cir.double>, !cir.vector<2 x !cir.double>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v2f64.p0(<2 x double> [[V0]], <2 x double> [[V1]], <2 x double> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3q_f64(a, b);
+}
+
+// ALL-LABEL: @test_vst3q_mf8(
+void test_vst3q_mf8(mfloat8_t *a, mfloat8x16x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], <16 x i8> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3q_mf8(a, b);
+}
+
+// ALL-LABEL: @test_vst3q_p16(
+void test_vst3q_p16(poly16_t *a, poly16x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v8i16.p0(<8 x i16> [[V0]], <8 x i16> [[V1]], <8 x i16> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3q_p16(a, b);
+}
+
+// ALL-LABEL: @test_vst3q_p64(
+void test_vst3q_p64(poly64_t * ptr, poly64x2x3_t val) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v2i64.p0(<2 x i64> [[V0]], <2 x i64> [[V1]], <2 x i64> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3q_p64(ptr, val);
+}
+
+// ALL-LABEL: @test_vst3q_p8(
+void test_vst3q_p8(poly8_t *a, poly8x16x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], <16 x i8> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3q_p8(a, b);
+}
+
+// ALL-LABEL: @test_vst3q_s16(
+void test_vst3q_s16(int16_t *a, int16x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v8i16.p0(<8 x i16> [[V0]], <8 x i16> [[V1]], <8 x i16> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3q_s16(a, b);
+}
+
+// ALL-LABEL: @test_vst3q_s32(
+void test_vst3q_s32(int32_t *a, int32x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v4i32.p0(<4 x i32> [[V0]], <4 x i32> [[V1]], <4 x i32> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3q_s32(a, b);
+}
+
+// ALL-LABEL: @test_vst3q_s64(
+void test_vst3q_s64(int64_t *a, int64x2x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v2i64.p0(<2 x i64> [[V0]], <2 x i64> [[V1]], <2 x i64> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3q_s64(a, b);
+}
+
+// ALL-LABEL: @test_vst3q_s8(
+void test_vst3q_s8(int8_t *a, int8x16x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], <16 x i8> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3q_s8(a, b);
+}
+
+// ALL-LABEL: @test_vst3q_u16(
+void test_vst3q_u16(uint16_t *a, uint16x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v8i16.p0(<8 x i16> [[V0]], <8 x i16> [[V1]], <8 x i16> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3q_u16(a, b);
+}
+
+// ALL-LABEL: @test_vst3q_u32(
+void test_vst3q_u32(uint32_t *a, uint32x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v4i32.p0(<4 x i32> [[V0]], <4 x i32> [[V1]], <4 x i32> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3q_u32(a, b);
+}
+
+// ALL-LABEL: @test_vst3q_u64(
+void test_vst3q_u64(uint64_t *a, uint64x2x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v2i64.p0(<2 x i64> [[V0]], <2 x i64> [[V1]], <2 x i64> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3q_u64(a, b);
+}
+
+// ALL-LABEL: @test_vst3q_u8(
+void test_vst3q_u8(uint8_t *a, uint8x16x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3" {{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], <16 x i8> [[V2]], ptr [[A]])
+// LLVM: ret void
+ vst3q_u8(a, b);
+}
+
+// ALL-LABEL: @test_vst3_lane_f16(
+void test_vst3_lane_f16(float16_t *a, float16x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v4f16.p0(<4 x half> [[V0]], <4 x half> [[V1]], <4 x half> [[V2]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst3_lane_f16(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst3_lane_f32(
+void test_vst3_lane_f32(float32_t *a, float32x2x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<2 x !cir.float>, !cir.vector<2 x !cir.float>, !cir.vector<2 x !cir.float>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v2f32.p0(<2 x float> [[V0]], <2 x float> [[V1]], <2 x float> [[V2]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst3_lane_f32(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst3_lane_f64(
+void test_vst3_lane_f64(float64_t *a, float64x1x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<1 x !cir.double>, !cir.vector<1 x !cir.double>, !cir.vector<1 x !cir.double>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v1f64.p0(<1 x double> [[V0]], <1 x double> [[V1]], <1 x double> [[V2]], i64 0, ptr [[A]])
+// LLVM: ret void
+ vst3_lane_f64(a, b, 0);
+}
+
+// ALL-LABEL: @test_vst3_lane_mf8(
+void test_vst3_lane_mf8(mfloat8_t *a, mfloat8x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], <8 x i8> [[V2]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst3_lane_mf8(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst3_lane_p16(
+void test_vst3_lane_p16(poly16_t *a, poly16x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v4i16.p0(<4 x i16> [[V0]], <4 x i16> [[V1]], <4 x i16> [[V2]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst3_lane_p16(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst3_lane_p64(
+void test_vst3_lane_p64(poly64_t *a, poly64x1x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v1i64.p0(<1 x i64> [[V0]], <1 x i64> [[V1]], <1 x i64> [[V2]], i64 0, ptr [[A]])
+// LLVM: ret void
+ vst3_lane_p64(a, b, 0);
+}
+
+// ALL-LABEL: @test_vst3_lane_p8(
+void test_vst3_lane_p8(poly8_t *a, poly8x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], <8 x i8> [[V2]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst3_lane_p8(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst3_lane_s16(
+void test_vst3_lane_s16(int16_t *a, int16x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v4i16.p0(<4 x i16> [[V0]], <4 x i16> [[V1]], <4 x i16> [[V2]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst3_lane_s16(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst3_lane_s32(
+void test_vst3_lane_s32(int32_t *a, int32x2x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v2i32.p0(<2 x i32> [[V0]], <2 x i32> [[V1]], <2 x i32> [[V2]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst3_lane_s32(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst3_lane_s64(
+void test_vst3_lane_s64(int64_t *a, int64x1x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v1i64.p0(<1 x i64> [[V0]], <1 x i64> [[V1]], <1 x i64> [[V2]], i64 0, ptr [[A]])
+// LLVM: ret void
+ vst3_lane_s64(a, b, 0);
+}
+
+// ALL-LABEL: @test_vst3_lane_s8(
+void test_vst3_lane_s8(int8_t *a, int8x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], <8 x i8> [[V2]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst3_lane_s8(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst3_lane_u16(
+void test_vst3_lane_u16(uint16_t *a, uint16x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v4i16.p0(<4 x i16> [[V0]], <4 x i16> [[V1]], <4 x i16> [[V2]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst3_lane_u16(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst3_lane_u32(
+void test_vst3_lane_u32(uint32_t *a, uint32x2x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v2i32.p0(<2 x i32> [[V0]], <2 x i32> [[V1]], <2 x i32> [[V2]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst3_lane_u32(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst3_lane_u64(
+void test_vst3_lane_u64(uint64_t *a, uint64x1x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v1i64.p0(<1 x i64> [[V0]], <1 x i64> [[V1]], <1 x i64> [[V2]], i64 0, ptr [[A]])
+// LLVM: ret void
+ vst3_lane_u64(a, b, 0);
+}
+
+// ALL-LABEL: @test_vst3_lane_u8(
+void test_vst3_lane_u8(uint8_t *a, uint8x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], <8 x i8> [[V2]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst3_lane_u8(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst3q_lane_f16(
+void test_vst3q_lane_f16(float16_t *a, float16x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v8f16.p0(<8 x half> [[V0]], <8 x half> [[V1]], <8 x half> [[V2]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst3q_lane_f16(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst3q_lane_f32(
+void test_vst3q_lane_f32(float32_t *a, float32x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<4 x !cir.float>, !cir.vector<4 x !cir.float>, !cir.vector<4 x !cir.float>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v4f32.p0(<4 x float> [[V0]], <4 x float> [[V1]], <4 x float> [[V2]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst3q_lane_f32(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst3q_lane_f64(
+void test_vst3q_lane_f64(float64_t *a, float64x2x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<2 x !cir.double>, !cir.vector<2 x !cir.double>, !cir.vector<2 x !cir.double>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v2f64.p0(<2 x double> [[V0]], <2 x double> [[V1]], <2 x double> [[V2]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst3q_lane_f64(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst3q_lane_mf8(
+void test_vst3q_lane_mf8(mfloat8_t *a, mfloat8x16x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], <16 x i8> [[V2]], i64 15, ptr [[A]])
+// LLVM: ret void
+ vst3q_lane_mf8(a, b, 15);
+}
+
+// ALL-LABEL: @test_vst3q_lane_p16(
+void test_vst3q_lane_p16(poly16_t *a, poly16x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v8i16.p0(<8 x i16> [[V0]], <8 x i16> [[V1]], <8 x i16> [[V2]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst3q_lane_p16(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst3q_lane_p64(
+void test_vst3q_lane_p64(poly64_t *a, poly64x2x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v2i64.p0(<2 x i64> [[V0]], <2 x i64> [[V1]], <2 x i64> [[V2]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst3q_lane_p64(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst3q_lane_p8(
+void test_vst3q_lane_p8(poly8_t *a, poly8x16x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], <16 x i8> [[V2]], i64 15, ptr [[A]])
+// LLVM: ret void
+ vst3q_lane_p8(a, b, 15);
+}
+
+// ALL-LABEL: @test_vst3q_lane_s16(
+void test_vst3q_lane_s16(int16_t *a, int16x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v8i16.p0(<8 x i16> [[V0]], <8 x i16> [[V1]], <8 x i16> [[V2]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst3q_lane_s16(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst3q_lane_s32(
+void test_vst3q_lane_s32(int32_t *a, int32x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v4i32.p0(<4 x i32> [[V0]], <4 x i32> [[V1]], <4 x i32> [[V2]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst3q_lane_s32(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst3q_lane_s64(
+void test_vst3q_lane_s64(int64_t *a, int64x2x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v2i64.p0(<2 x i64> [[V0]], <2 x i64> [[V1]], <2 x i64> [[V2]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst3q_lane_s64(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst3q_lane_s8(
+void test_vst3q_lane_s8(int8_t *a, int8x16x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], <16 x i8> [[V2]], i64 15, ptr [[A]])
+// LLVM: ret void
+ vst3q_lane_s8(a, b, 15);
+}
+
+// ALL-LABEL: @test_vst3q_lane_u16(
+void test_vst3q_lane_u16(uint16_t *a, uint16x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v8i16.p0(<8 x i16> [[V0]], <8 x i16> [[V1]], <8 x i16> [[V2]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst3q_lane_u16(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst3q_lane_u32(
+void test_vst3q_lane_u32(uint32_t *a, uint32x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v4i32.p0(<4 x i32> [[V0]], <4 x i32> [[V1]], <4 x i32> [[V2]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst3q_lane_u32(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst3q_lane_u64(
+void test_vst3q_lane_u64(uint64_t *a, uint64x2x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v2i64.p0(<2 x i64> [[V0]], <2 x i64> [[V1]], <2 x i64> [[V2]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst3q_lane_u64(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst3q_lane_u8(
+void test_vst3q_lane_u8(uint8_t *a, uint8x16x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st3lane" {{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM: call void @llvm.aarch64.neon.st3lane.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], <16 x i8> [[V2]], i64 15, ptr [[A]])
+// LLVM: ret void
+ vst3q_lane_u8(a, b, 15);
+}
+
+// ALL-LABEL: @test_vst4_f16(
+void test_vst4_f16(float16_t *a, float16x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v4f16.p0(<4 x half> [[V0]], <4 x half> [[V1]], <4 x half> [[V2]], <4 x half> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4_f16(a, b);
+}
+
+// ALL-LABEL: @test_vst4_f32(
+void test_vst4_f32(float32_t *a, float32x2x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<2 x !cir.float>, !cir.vector<2 x !cir.float>, !cir.vector<2 x !cir.float>, !cir.vector<2 x !cir.float>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v2f32.p0(<2 x float> [[V0]], <2 x float> [[V1]], <2 x float> [[V2]], <2 x float> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4_f32(a, b);
+}
+
+// ALL-LABEL: @test_vst4_f64(
+void test_vst4_f64(float64_t *a, float64x1x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<1 x !cir.double>, !cir.vector<1 x !cir.double>, !cir.vector<1 x !cir.double>, !cir.vector<1 x !cir.double>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v1f64.p0(<1 x double> [[V0]], <1 x double> [[V1]], <1 x double> [[V2]], <1 x double> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4_f64(a, b);
+}
+
+// ALL-LABEL: @test_vst4_mf8(
+void test_vst4_mf8(mfloat8_t *a, mfloat8x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], <8 x i8> [[V2]], <8 x i8> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4_mf8(a, b);
+}
+
+// ALL-LABEL: @test_vst4_p16(
+void test_vst4_p16(poly16_t *a, poly16x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v4i16.p0(<4 x i16> [[V0]], <4 x i16> [[V1]], <4 x i16> [[V2]], <4 x i16> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4_p16(a, b);
+}
+
+// ALL-LABEL: @test_vst4_p64(
+void test_vst4_p64(poly64_t * ptr, poly64x1x4_t val) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v1i64.p0(<1 x i64> [[V0]], <1 x i64> [[V1]], <1 x i64> [[V2]], <1 x i64> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4_p64(ptr, val);
+}
+
+// ALL-LABEL: @test_vst4_p8(
+void test_vst4_p8(poly8_t *a, poly8x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], <8 x i8> [[V2]], <8 x i8> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4_p8(a, b);
+}
+
+// ALL-LABEL: @test_vst4_s16(
+void test_vst4_s16(int16_t *a, int16x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v4i16.p0(<4 x i16> [[V0]], <4 x i16> [[V1]], <4 x i16> [[V2]], <4 x i16> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4_s16(a, b);
+}
+
+// ALL-LABEL: @test_vst4_s32(
+void test_vst4_s32(int32_t *a, int32x2x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v2i32.p0(<2 x i32> [[V0]], <2 x i32> [[V1]], <2 x i32> [[V2]], <2 x i32> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4_s32(a, b);
+}
+
+// ALL-LABEL: @test_vst4_s64(
+void test_vst4_s64(int64_t *a, int64x1x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v1i64.p0(<1 x i64> [[V0]], <1 x i64> [[V1]], <1 x i64> [[V2]], <1 x i64> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4_s64(a, b);
+}
+
+// ALL-LABEL: @test_vst4_s8(
+void test_vst4_s8(int8_t *a, int8x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], <8 x i8> [[V2]], <8 x i8> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4_s8(a, b);
+}
+
+// ALL-LABEL: @test_vst4_u16(
+void test_vst4_u16(uint16_t *a, uint16x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v4i16.p0(<4 x i16> [[V0]], <4 x i16> [[V1]], <4 x i16> [[V2]], <4 x i16> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4_u16(a, b);
+}
+
+// ALL-LABEL: @test_vst4_u32(
+void test_vst4_u32(uint32_t *a, uint32x2x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v2i32.p0(<2 x i32> [[V0]], <2 x i32> [[V1]], <2 x i32> [[V2]], <2 x i32> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4_u32(a, b);
+}
+
+// ALL-LABEL: @test_vst4_u64(
+void test_vst4_u64(uint64_t *a, uint64x1x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v1i64.p0(<1 x i64> [[V0]], <1 x i64> [[V1]], <1 x i64> [[V2]], <1 x i64> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4_u64(a, b);
+}
+
+// ALL-LABEL: @test_vst4_u8(
+void test_vst4_u8(uint8_t *a, uint8x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], <8 x i8> [[V2]], <8 x i8> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4_u8(a, b);
+}
+
+// ALL-LABEL: @test_vst4q_f16(
+void test_vst4q_f16(float16_t *a, float16x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v8f16.p0(<8 x half> [[V0]], <8 x half> [[V1]], <8 x half> [[V2]], <8 x half> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4q_f16(a, b);
+}
+
+// ALL-LABEL: @test_vst4q_f32(
+void test_vst4q_f32(float32_t *a, float32x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<4 x !cir.float>, !cir.vector<4 x !cir.float>, !cir.vector<4 x !cir.float>, !cir.vector<4 x !cir.float>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v4f32.p0(<4 x float> [[V0]], <4 x float> [[V1]], <4 x float> [[V2]], <4 x float> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4q_f32(a, b);
+}
+
+// ALL-LABEL: @test_vst4q_f64(
+void test_vst4q_f64(float64_t *a, float64x2x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<2 x !cir.double>, !cir.vector<2 x !cir.double>, !cir.vector<2 x !cir.double>, !cir.vector<2 x !cir.double>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v2f64.p0(<2 x double> [[V0]], <2 x double> [[V1]], <2 x double> [[V2]], <2 x double> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4q_f64(a, b);
+}
+
+// ALL-LABEL: @test_vst4q_mf8(
+void test_vst4q_mf8(mfloat8_t *a, mfloat8x16x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], <16 x i8> [[V2]], <16 x i8> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4q_mf8(a, b);
+}
+
+// ALL-LABEL: @test_vst4q_p16(
+void test_vst4q_p16(poly16_t *a, poly16x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v8i16.p0(<8 x i16> [[V0]], <8 x i16> [[V1]], <8 x i16> [[V2]], <8 x i16> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4q_p16(a, b);
+}
+
+// ALL-LABEL: @test_vst4q_p64(
+void test_vst4q_p64(poly64_t * ptr, poly64x2x4_t val) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v2i64.p0(<2 x i64> [[V0]], <2 x i64> [[V1]], <2 x i64> [[V2]], <2 x i64> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4q_p64(ptr, val);
+}
+
+// ALL-LABEL: @test_vst4q_p8(
+void test_vst4q_p8(poly8_t *a, poly8x16x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], <16 x i8> [[V2]], <16 x i8> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4q_p8(a, b);
+}
+
+// ALL-LABEL: @test_vst4q_s16(
+void test_vst4q_s16(int16_t *a, int16x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v8i16.p0(<8 x i16> [[V0]], <8 x i16> [[V1]], <8 x i16> [[V2]], <8 x i16> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4q_s16(a, b);
+}
+
+// ALL-LABEL: @test_vst4q_s32(
+void test_vst4q_s32(int32_t *a, int32x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v4i32.p0(<4 x i32> [[V0]], <4 x i32> [[V1]], <4 x i32> [[V2]], <4 x i32> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4q_s32(a, b);
+}
+
+// ALL-LABEL: @test_vst4q_s64(
+void test_vst4q_s64(int64_t *a, int64x2x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v2i64.p0(<2 x i64> [[V0]], <2 x i64> [[V1]], <2 x i64> [[V2]], <2 x i64> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4q_s64(a, b);
+}
+
+// ALL-LABEL: @test_vst4q_s8(
+void test_vst4q_s8(int8_t *a, int8x16x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], <16 x i8> [[V2]], <16 x i8> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4q_s8(a, b);
+}
+
+// ALL-LABEL: @test_vst4q_u16(
+void test_vst4q_u16(uint16_t *a, uint16x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v8i16.p0(<8 x i16> [[V0]], <8 x i16> [[V1]], <8 x i16> [[V2]], <8 x i16> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4q_u16(a, b);
+}
+
+// ALL-LABEL: @test_vst4q_u32(
+void test_vst4q_u32(uint32_t *a, uint32x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v4i32.p0(<4 x i32> [[V0]], <4 x i32> [[V1]], <4 x i32> [[V2]], <4 x i32> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4q_u32(a, b);
+}
+
+// ALL-LABEL: @test_vst4q_u64(
+void test_vst4q_u64(uint64_t *a, uint64x2x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v2i64.p0(<2 x i64> [[V0]], <2 x i64> [[V1]], <2 x i64> [[V2]], <2 x i64> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4q_u64(a, b);
+}
+
+// ALL-LABEL: @test_vst4q_u8(
+void test_vst4q_u8(uint8_t *a, uint8x16x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4" {{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], <16 x i8> [[V2]], <16 x i8> [[V3]], ptr [[A]])
+// LLVM: ret void
+ vst4q_u8(a, b);
+}
+
+// ALL-LABEL: @test_vst4_lane_f16(
+void test_vst4_lane_f16(float16_t *a, float16x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v4f16.p0(<4 x half> [[V0]], <4 x half> [[V1]], <4 x half> [[V2]], <4 x half> [[V3]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst4_lane_f16(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst4_lane_f32(
+void test_vst4_lane_f32(float32_t *a, float32x2x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<2 x !cir.float>, !cir.vector<2 x !cir.float>, !cir.vector<2 x !cir.float>, !cir.vector<2 x !cir.float>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v2f32.p0(<2 x float> [[V0]], <2 x float> [[V1]], <2 x float> [[V2]], <2 x float> [[V3]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst4_lane_f32(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst4_lane_f64(
+void test_vst4_lane_f64(float64_t *a, float64x1x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<1 x !cir.double>, !cir.vector<1 x !cir.double>, !cir.vector<1 x !cir.double>, !cir.vector<1 x !cir.double>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v1f64.p0(<1 x double> [[V0]], <1 x double> [[V1]], <1 x double> [[V2]], <1 x double> [[V3]], i64 0, ptr [[A]])
+// LLVM: ret void
+ vst4_lane_f64(a, b, 0);
+}
+
+// ALL-LABEL: @test_vst4_lane_mf8(
+void test_vst4_lane_mf8(mfloat8_t *a, mfloat8x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], <8 x i8> [[V2]], <8 x i8> [[V3]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst4_lane_mf8(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst4_lane_p16(
+void test_vst4_lane_p16(poly16_t *a, poly16x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v4i16.p0(<4 x i16> [[V0]], <4 x i16> [[V1]], <4 x i16> [[V2]], <4 x i16> [[V3]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst4_lane_p16(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst4_lane_p64(
+void test_vst4_lane_p64(poly64_t *a, poly64x1x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v1i64.p0(<1 x i64> [[V0]], <1 x i64> [[V1]], <1 x i64> [[V2]], <1 x i64> [[V3]], i64 0, ptr [[A]])
+// LLVM: ret void
+ vst4_lane_p64(a, b, 0);
+}
+
+// ALL-LABEL: @test_vst4_lane_p8(
+void test_vst4_lane_p8(poly8_t *a, poly8x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], <8 x i8> [[V2]], <8 x i8> [[V3]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst4_lane_p8(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst4_lane_s16(
+void test_vst4_lane_s16(int16_t *a, int16x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v4i16.p0(<4 x i16> [[V0]], <4 x i16> [[V1]], <4 x i16> [[V2]], <4 x i16> [[V3]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst4_lane_s16(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst4_lane_s32(
+void test_vst4_lane_s32(int32_t *a, int32x2x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v2i32.p0(<2 x i32> [[V0]], <2 x i32> [[V1]], <2 x i32> [[V2]], <2 x i32> [[V3]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst4_lane_s32(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst4_lane_s64(
+void test_vst4_lane_s64(int64_t *a, int64x1x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v1i64.p0(<1 x i64> [[V0]], <1 x i64> [[V1]], <1 x i64> [[V2]], <1 x i64> [[V3]], i64 0, ptr [[A]])
+// LLVM: ret void
+ vst4_lane_s64(a, b, 0);
+}
+
+// ALL-LABEL: @test_vst4_lane_s8(
+void test_vst4_lane_s8(int8_t *a, int8x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], <8 x i8> [[V2]], <8 x i8> [[V3]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst4_lane_s8(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst4_lane_u16(
+void test_vst4_lane_u16(uint16_t *a, uint16x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v4i16.p0(<4 x i16> [[V0]], <4 x i16> [[V1]], <4 x i16> [[V2]], <4 x i16> [[V3]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst4_lane_u16(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst4_lane_u32(
+void test_vst4_lane_u32(uint32_t *a, uint32x2x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v2i32.p0(<2 x i32> [[V0]], <2 x i32> [[V1]], <2 x i32> [[V2]], <2 x i32> [[V3]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst4_lane_u32(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst4_lane_u64(
+void test_vst4_lane_u64(uint64_t *a, uint64x1x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v1i64.p0(<1 x i64> [[V0]], <1 x i64> [[V1]], <1 x i64> [[V2]], <1 x i64> [[V3]], i64 0, ptr [[A]])
+// LLVM: ret void
+ vst4_lane_u64(a, b, 0);
+}
+
+// ALL-LABEL: @test_vst4_lane_u8(
+void test_vst4_lane_u8(uint8_t *a, uint8x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v8i8.p0(<8 x i8> [[V0]], <8 x i8> [[V1]], <8 x i8> [[V2]], <8 x i8> [[V3]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst4_lane_u8(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst4q_lane_f16(
+void test_vst4q_lane_f16(float16_t *a, float16x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v8f16.p0(<8 x half> [[V0]], <8 x half> [[V1]], <8 x half> [[V2]], <8 x half> [[V3]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst4q_lane_f16(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst4q_lane_f32(
+void test_vst4q_lane_f32(float32_t *a, float32x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<4 x !cir.float>, !cir.vector<4 x !cir.float>, !cir.vector<4 x !cir.float>, !cir.vector<4 x !cir.float>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v4f32.p0(<4 x float> [[V0]], <4 x float> [[V1]], <4 x float> [[V2]], <4 x float> [[V3]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst4q_lane_f32(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst4q_lane_f64(
+void test_vst4q_lane_f64(float64_t *a, float64x2x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<2 x !cir.double>, !cir.vector<2 x !cir.double>, !cir.vector<2 x !cir.double>, !cir.vector<2 x !cir.double>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v2f64.p0(<2 x double> [[V0]], <2 x double> [[V1]], <2 x double> [[V2]], <2 x double> [[V3]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst4q_lane_f64(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst4q_lane_mf8(
+void test_vst4q_lane_mf8(mfloat8_t *a, mfloat8x16x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], <16 x i8> [[V2]], <16 x i8> [[V3]], i64 15, ptr [[A]])
+// LLVM: ret void
+ vst4q_lane_mf8(a, b, 15);
+}
+
+// ALL-LABEL: @test_vst4q_lane_p16(
+void test_vst4q_lane_p16(poly16_t *a, poly16x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v8i16.p0(<8 x i16> [[V0]], <8 x i16> [[V1]], <8 x i16> [[V2]], <8 x i16> [[V3]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst4q_lane_p16(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst4q_lane_p64(
+void test_vst4q_lane_p64(poly64_t *a, poly64x2x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v2i64.p0(<2 x i64> [[V0]], <2 x i64> [[V1]], <2 x i64> [[V2]], <2 x i64> [[V3]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst4q_lane_p64(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst4q_lane_p8(
+void test_vst4q_lane_p8(poly8_t *a, poly8x16x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], <16 x i8> [[V2]], <16 x i8> [[V3]], i64 15, ptr [[A]])
+// LLVM: ret void
+ vst4q_lane_p8(a, b, 15);
+}
+
+// ALL-LABEL: @test_vst4q_lane_s16(
+void test_vst4q_lane_s16(int16_t *a, int16x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v8i16.p0(<8 x i16> [[V0]], <8 x i16> [[V1]], <8 x i16> [[V2]], <8 x i16> [[V3]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst4q_lane_s16(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst4q_lane_s32(
+void test_vst4q_lane_s32(int32_t *a, int32x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v4i32.p0(<4 x i32> [[V0]], <4 x i32> [[V1]], <4 x i32> [[V2]], <4 x i32> [[V3]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst4q_lane_s32(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst4q_lane_s64(
+void test_vst4q_lane_s64(int64_t *a, int64x2x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v2i64.p0(<2 x i64> [[V0]], <2 x i64> [[V1]], <2 x i64> [[V2]], <2 x i64> [[V3]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst4q_lane_s64(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst4q_lane_s8(
+void test_vst4q_lane_s8(int8_t *a, int8x16x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], <16 x i8> [[V2]], <16 x i8> [[V3]], i64 15, ptr [[A]])
+// LLVM: ret void
+ vst4q_lane_s8(a, b, 15);
+}
+
+// ALL-LABEL: @test_vst4q_lane_u16(
+void test_vst4q_lane_u16(uint16_t *a, uint16x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v8i16.p0(<8 x i16> [[V0]], <8 x i16> [[V1]], <8 x i16> [[V2]], <8 x i16> [[V3]], i64 7, ptr [[A]])
+// LLVM: ret void
+ vst4q_lane_u16(a, b, 7);
+}
+
+// ALL-LABEL: @test_vst4q_lane_u32(
+void test_vst4q_lane_u32(uint32_t *a, uint32x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v4i32.p0(<4 x i32> [[V0]], <4 x i32> [[V1]], <4 x i32> [[V2]], <4 x i32> [[V3]], i64 3, ptr [[A]])
+// LLVM: ret void
+ vst4q_lane_u32(a, b, 3);
+}
+
+// ALL-LABEL: @test_vst4q_lane_u64(
+void test_vst4q_lane_u64(uint64_t *a, uint64x2x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v2i64.p0(<2 x i64> [[V0]], <2 x i64> [[V1]], <2 x i64> [[V2]], <2 x i64> [[V3]], i64 1, ptr [[A]])
+// LLVM: ret void
+ vst4q_lane_u64(a, b, 1);
+}
+
+// ALL-LABEL: @test_vst4q_lane_u8(
+void test_vst4q_lane_u8(uint8_t *a, uint8x16x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st4lane" {{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !s64i, !cir.ptr<!void>) -> !void
+
+// LLVM-SAME: ptr {{[a-z ]*}}[[A:%[a-z0-9_.]+]],
+// LLVM-DAG: [[V0:%.*]] = extractvalue {{.*}} [[B:%[a-z0-9_.]+]],{{( 0,)?}} 0{{$}}
+// LLVM-DAG: [[V1:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 1{{$}}
+// LLVM-DAG: [[V2:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 2{{$}}
+// LLVM-DAG: [[V3:%.*]] = extractvalue {{.*}} [[B]],{{( 0,)?}} 3{{$}}
+// LLVM: call void @llvm.aarch64.neon.st4lane.v16i8.p0(<16 x i8> [[V0]], <16 x i8> [[V1]], <16 x i8> [[V2]], <16 x i8> [[V3]], i64 15, ptr [[A]])
+// LLVM: ret void
+ vst4q_lane_u8(a, b, 15);
+}
diff --git a/clang/test/CodeGen/AArch64/poly64.c b/clang/test/CodeGen/AArch64/poly64.c
index f422a82f65138..410b5aecf3567 100644
--- a/clang/test/CodeGen/AArch64/poly64.c
+++ b/clang/test/CodeGen/AArch64/poly64.c
@@ -328,120 +328,6 @@ poly64x2x4_t test_vld4q_p64(poly64_t const * ptr) {
return vld4q_p64(ptr);
}
-// CHECK-LABEL: define dso_local void @test_vst2_p64(
-// CHECK-SAME: ptr noundef [[PTR:%.*]], [2 x <1 x i64>] alignstack(8) [[VAL_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VAL_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <1 x i64>] [[VAL_COERCE]], 0
-// CHECK-NEXT: [[VAL_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <1 x i64>] [[VAL_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[VAL_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[VAL_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v1i64.p0(<1 x i64> [[TMP2]], <1 x i64> [[TMP3]], ptr [[PTR]])
-// CHECK-NEXT: ret void
-//
-void test_vst2_p64(poly64_t * ptr, poly64x1x2_t val) {
- return vst2_p64(ptr, val);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst2q_p64(
-// CHECK-SAME: ptr noundef [[PTR:%.*]], [2 x <2 x i64>] alignstack(16) [[VAL_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VAL_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <2 x i64>] [[VAL_COERCE]], 0
-// CHECK-NEXT: [[VAL_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <2 x i64>] [[VAL_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[VAL_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[VAL_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st2.v2i64.p0(<2 x i64> [[TMP2]], <2 x i64> [[TMP3]], ptr [[PTR]])
-// CHECK-NEXT: ret void
-//
-void test_vst2q_p64(poly64_t * ptr, poly64x2x2_t val) {
- return vst2q_p64(ptr, val);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3_p64(
-// CHECK-SAME: ptr noundef [[PTR:%.*]], [3 x <1 x i64>] alignstack(8) [[VAL_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VAL_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[VAL_COERCE]], 0
-// CHECK-NEXT: [[VAL_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[VAL_COERCE]], 1
-// CHECK-NEXT: [[VAL_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[VAL_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[VAL_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[VAL_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[VAL_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v1i64.p0(<1 x i64> [[TMP3]], <1 x i64> [[TMP4]], <1 x i64> [[TMP5]], ptr [[PTR]])
-// CHECK-NEXT: ret void
-//
-void test_vst3_p64(poly64_t * ptr, poly64x1x3_t val) {
- return vst3_p64(ptr, val);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst3q_p64(
-// CHECK-SAME: ptr noundef [[PTR:%.*]], [3 x <2 x i64>] alignstack(16) [[VAL_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VAL_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[VAL_COERCE]], 0
-// CHECK-NEXT: [[VAL_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[VAL_COERCE]], 1
-// CHECK-NEXT: [[VAL_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[VAL_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[VAL_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[VAL_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[VAL_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st3.v2i64.p0(<2 x i64> [[TMP3]], <2 x i64> [[TMP4]], <2 x i64> [[TMP5]], ptr [[PTR]])
-// CHECK-NEXT: ret void
-//
-void test_vst3q_p64(poly64_t * ptr, poly64x2x3_t val) {
- return vst3q_p64(ptr, val);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4_p64(
-// CHECK-SAME: ptr noundef [[PTR:%.*]], [4 x <1 x i64>] alignstack(8) [[VAL_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VAL_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[VAL_COERCE]], 0
-// CHECK-NEXT: [[VAL_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[VAL_COERCE]], 1
-// CHECK-NEXT: [[VAL_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[VAL_COERCE]], 2
-// CHECK-NEXT: [[VAL_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[VAL_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[VAL_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[VAL_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[VAL_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[VAL_COERCE_FCA_3_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x i64>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP3]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v1i64.p0(<1 x i64> [[TMP4]], <1 x i64> [[TMP5]], <1 x i64> [[TMP6]], <1 x i64> [[TMP7]], ptr [[PTR]])
-// CHECK-NEXT: ret void
-//
-void test_vst4_p64(poly64_t * ptr, poly64x1x4_t val) {
- return vst4_p64(ptr, val);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst4q_p64(
-// CHECK-SAME: ptr noundef [[PTR:%.*]], [4 x <2 x i64>] alignstack(16) [[VAL_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VAL_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[VAL_COERCE]], 0
-// CHECK-NEXT: [[VAL_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[VAL_COERCE]], 1
-// CHECK-NEXT: [[VAL_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[VAL_COERCE]], 2
-// CHECK-NEXT: [[VAL_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[VAL_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[VAL_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[VAL_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[VAL_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[VAL_COERCE_FCA_3_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st4.v2i64.p0(<2 x i64> [[TMP4]], <2 x i64> [[TMP5]], <2 x i64> [[TMP6]], <2 x i64> [[TMP7]], ptr [[PTR]])
-// CHECK-NEXT: ret void
-//
-void test_vst4q_p64(poly64_t * ptr, poly64x2x4_t val) {
- return vst4q_p64(ptr, val);
-}
-
// CHECK-LABEL: define dso_local <1 x i64> @test_vext_p64(
// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
More information about the cfe-commits
mailing list